A B C D E

1 1

2 DBQ01 Rev0.1 Schematics Document 2

Intel Prescott uFCPGA-478 / P4 Northwood

with Springdale / ICH5 / nVIDIA NV34M/31M chipset

2003/07/01
3 3

4 4

Compal Electronics, Inc.

Title

Cover Sheet
Size Document Number R ev
B 0.1
LA-2041
D ate: ¬P 期三, 七月 09, 2003 Sheet 1 of 56
A B C D E
 A B C D E

Compal Confidential
Desktop Prescott uFCPGA-478 CPU
File Name : DBQ01 Fan Control Desktop Northwood uFCPGA-478 CPU Thermal Sensor Clock Generator
page 45
ADM1032AR ICS 952623
page 4,5,6
1
page 5 page 15 1

CRT Connector PSB

H_A#(3..31) 400/533/667/800MHz H_D#(0..63)
page 22

Memory BUS(DDR)
VGA AGP BUS(8X) DDR-SO-DIMM X2
LVDS Interface NV31M/34M
Intel Springdale MCH BANK 0, 1, 2, 3page 12,13,14
page 22
FCBGA-932
page 16,17, 2.5V DDR- 200/266
PIRQA# 18,19 page 7,8,9,10,11
TV OUT Connector
(4Pin Reverse)
page 22
USB2.0
USB Conn *4
page 37

VRAM DDR
32MB/64MB (FBGA) Hub-Link MDC & BT Conn
2
page 20,21 page 38 2

AC97 Codec HW EQ CKT

3.3V 33 MHz ALC202
PCI BUS page 32
page 31
IDSEL: AD18
IDSEL: AD16 PIRQC#, PIRQD# IDSEL: AD17 IDSEL: AD20 Intel ICH5 AC-LINK
PIRQA#, GNT0#, REQ0# GNT1#, REQ1# PIRQB#, GNT3#, REQ3# PIRQB#, SIRQ, GNT2#, REQ2#
ATA-100
CardBus Controller mBGA-460 Primary IDE Audio AMP
IEEE 1394 Mini PCI LAN page 32
Secondary IDE
TSB43AB21 socket RTL 8101L Toshiba TC6385XB page 23,24,25 master HDD
ATA-100
page 30 page 29 page 26 page 27,28 Connector
page 35

RTC CKT. master/slave

RJ45/11 CONN Slot 0,1 SD Conn.
page 26 page 28 page 27
3 3
LPC BUS Audio DJ
OZ-168
page 34

Power OK CKT. SMsC LPC47N227

EC NS87591L
page 41 Super I/O
page 39 page 36
Module Conn. Module Conn.
(Main Module) (2nd Module)
Power On/Off CKT. Touch Pad Int.KBD PARALLEL
page 35 page 35

page 44 page 39
page 38 Floppy

EC I/O Buffer BIOS (1MB)

DC/DC Interface CKT. page 40 page 40 FIR
page 37

4 4

Power Circuit DC/DC

Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-2041
Date: 星期三, 七月 09, 2003 Sheet 2 of 56
A B C D E
 A B C D E

Voltage Rails
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
VIN Adapter power supply (19V) N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
1 B+ AC or battery power rail for power circuit. N/A N/A N/A 1

+CPU_CORE Core voltage for CPU ON OFF OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+CPU_VID 1.2V switched power rail for CPU AGTL Bus ON OFF OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+VTT_GMCH +1.225V (Prescott) / +1.45V (Northwood) ON OFF OFF
+VGA_CORE 1.3V switched power rail for VGA chip ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.25VS 1.25V switched power rail ON OFF OFF
+1.5VS AGP 4X/8X ON OFF OFF
+2.5V 2.5V power rail ON ON OFF
+2.5VS 2.5V switched power rail ON OFF OFF Board ID Table for AD channel
+3VALW 3.3V always on power rail ON ON ON*
+3V 3.3V power rail ON ON OFF
Vcc 3.3V +/- 5%
+3VS 3.3V switched power rail ON OFF OFF
Ra 100K +/- 5%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max
+5VALW 5V always on power rail ON ON ON*
+5V 5V power rail ON ON OFF
0 0 0 V 0 V 0 V
+5VS 5V switched power rail ON OFF OFF
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
2 2
+12VALW 12V always on power rail ON ON ON*
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+RTCVCC RTC power ON ON ON
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. 7 NC 2.500 V 3.300 V 3.300 V
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
VGA PIRQA
C ardB us AD20 2 PIRQA/PIRQB
Board ID PCB Revision
LAN A D17 3 PI RQB
0 0.1
Mini-PCI AD18 1/4 PIRQC/PIRQD
1
1 3 94 AD16 0 PIRQA
2
SD AD22
3
3 4 3

5
6
EC SM Bus1 address EC SM Bus2 address 7
Device Address Device Address
Smart Battery 0001 011X b ADM1032 1001 110X b
EEPROM(24C16/02) 1010 000X b OZ168 0011 0100 b
(24C04) 1011 000Xb

ICH5 SM Bus address

Device Address
4 4
Clock Generator 1101 001Xb
( ICS 952623)

DDR DIMM0 1001 000Xb

DDR DIMM2 1001 001Xb Compal Electronics, Inc.
Title
Notes
Size Document Number R ev
B 0.1
LA-2041
D ate: ¬P 期三, 七月 09, 2003 Sheet 3 of 56
A B C D E
 5 4 3 2 1

+ CPU_CORE

D D

AC10
AC12
AC14
AC16
AC18

AD11
AD13
AD15
AD17
AD19
AA10
AA12
AA14
AA16
AA18

AB11
AB13
AB15
AB17
AB19

AE10
AE12
AE14
AE16
AE18
AE20

AF11
AF13
AF15
AF17
AF19

AF21
AC8

AD7
AD9
AA8

AB7
AB9

AE6
AE8

AF2

AF5
AF7
AF9

C10
C12
C14
C16
C18
C20

D11
D13
D15
D17
D19
A10
A12
A14
A16
A18
A20

B11
B13
B15
B17
B19

E10
C8

D7
D9
A8

B7
B9
J C PU1A

VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
7 H_A#[3..31] H_D#[0..63] 7
H_A#3 K2 B21 H _D#0
H_A#4 A#3 D#0 H _D#1
K4 B22
H_A#5 A#4 D#1 H _D#2
L6 A23
H_A#6 A#5 D#2 H _D#3
K1 A25
H_A#7 A#6 D#3 H _D#4
L3 C21
H_A#8 A#7 D#4 H _D#5
M6 D22
H_A#9 A#8 D#5 H _D#6
L2 B24
H_A#10 A#9 D#6 H _D#7
M3 C23
H_A#11 A#10 D#7 H _D#8
M4 C24
H_A#12 A#11 D#8 H _D#9
N1 B25
H_A#13 A#12 D#9 H_D#10
M1 G22
H_A#14 A#13 D#10 H_D#11
N2 H21
H_A#15 A#14 D#11 H_D#12
N4 C26
H_A#16 A#15 D#12 H_D#13
N5 D23
H_A#17 A#16 D#13 H_D#14
T1 J21
H_A#18 A#17 D#14 H_D#15
R2 D25
H_A#19 A#18 D#15 H_D#16
P3 H22
H_A#20 A#19 D#16 H_D#17
P4 E24
H_A#21 A#20 D#17 H_D#18
R3 G23
H_A#22 A#21 D#18 H_D#19
T2 F23
H_A#23 A#22 D#19 H_D#20
U1 F24
H_A#24 A#23 D#20 H_D#21
P6 E25
H_A#25 A#24 D#21 H_D#22
U3 F26
H_A#26 A#25 D#22 H_D#23
T4 D26
H_A#27 A#26 D#23 H_D#24
V2 L21
H_A#28 A#27 D#24 H_D#25
R6 G26
H_A#29 A#28 D#25 H_D#26
W1 H24
H_A#30 A#29 D#26 H_D#27
T5 M21
H_A#31 A#30 D#27 H_D#28
U4 L22
A#31 D#28 H_D#29
V3 J24

C
W2
Y1
AB1
A#32
A#33
A#34
Prescott D#29
D#30
D#31
K23
H25
M23
H_D#30
H_D#31
H_D#32
C

A#35 D#32 H_D#33

N22
D#33 H_D#34
P21
7 H_REQ#[0..4] H_REQ#0 D#34 H_D#35
J1 M24
H_REQ#1 REQ#0 D#35 H_D#36
K5 N23
H_REQ#2 REQ#1 D#36 H_D#37
J4 M26
H_REQ#3 REQ#2 D#37 H_D#38
J3 N26
H_REQ#4 REQ#3 D#38 H_D#39
H3 N25
REQ#4 D#39 H_D#40
G1 R21
7 H _ADS# ADS# D#40 H_D#41
P24
D#41 H_D#42
R25
D#42 H_D#43
AC1 R24
AP#0 D#43 H_D#44
V5 T26
R 43 @62_0402_5% AP#1 D#44 H_D#45
AA3 T25
H _ IERR# BINIT# D#45 H_D#46
+ CPU_CORE 1 2 AC3 T22
IERR# D#46 H_D#47
+ CPU_CORE 1 2 T23
R103 200_0402_5% D#47 H_D#48
U26
D#48 H_D#49
H6 U24
7 H_BR0# BR0# D#49 H_D#50
D2 U23
7 H _BPRI# BPRI# D#50 H_D#51
G2 V25
7 H _ BNR# BNR# D#51 H_D#52
G4 U21
7 H_LOCK# LOCK# D#52 H_D#53
V22
D#53 H_D#54
V24
CLK_BC LK D#54 H_D#55
15 CLK_BCLK AF22 W26
CLK_BC LK# BCLK0 D#55 H_D#56
15 CLK_BCLK# AF23 Y26
BCLK1 D#56 H_D#57
W25
D#57 H_D#58
Y23
D#58 H_D#59
Y24
D#59 H_D#60
F3 Y21
7 H_HIT# HIT# D#60 H_D#61
E3 AA25

BOOTSELECT
7 H_HITM# HITM# D#61 H_D#62
E2 AA22
7 H _DEFER# DEFER# D#62 H_D#63
AA24
D#63

VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
H1
H4
H23
H26
A11
A13
A15
A17
A19
A21
A24
A26
A3
A9
AA1
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AD4
AD8

AD1

F13
F15
F17
F19
F9
F11
E8
E20
E18
E16
E14
E12
B B
AMP_3-1565030-1_Prescott

+CPU_CORE

1 2 BOOTSEL 1 2
53 BOOTSELECT
R 33 R 34
0_0402_5% R_C 0_0402_5%

Reference Intel document Pop: Northwood

Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0 Depop: Prescott
Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5
Pin number Northwood Commend Prescott Commend
Pin name Pin name Northwood Prescott

B6 FERR# Pull-up 62ohm FERR#/PBE# Pull-up 62ohm

to +VCC_CORE to +VCC_CORE P op P op

AA20 ITPCLKOUT0 Pull-up56ohm TESTHI6 Pull-up 62ohm

to +VCC_CORE to +VCC_CORE P op P op
AB22 ITPCLKOUT1 Pull-up 56ohm TESTHI7 Pull-up 62ohm
to +VCC_CORE to +VCC_CORE P op P op
A D2 NC float VIDPWRGD Pull-up 8.2Kohm
to +VCCVID Depop P op
A D3 NC float VID5 Pull-up1Kohm to
A +3VRUN & connect Depop P op A
to PWRIC
A F3 NC float VCCVIDLB Connect to +VCCVID Depop P op
AD20 VCCA Connect to CPU VCCIOPLL Connect to CPU
Filter Filter
AF23 VCCIOPLL Connect to CPU VCCA Connect to CPU
Filter Filter
A D1 V SS Connect to GND BOOTSELECT CPU determine P op Depop
Title
Compal Electronics, Inc.
AE26 V SS Connect to GND OPTIMIZED/ float
COMPAT# P op Depop Prescott Processor in uFCPGA478 (1/2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2041
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期 T, 七月 09, 2003 Sheet 4 of 56
5 4 3 2 1
 5 4 3 2 1

+ CPU_CORE

Place near ICH

1 2 H _ FERR# R 17
R255 62_0402_5%
1 2

AE11
AE13
AE15
AE17
AE19
AE22
AE24

AF10
AF12
AF14
AF16
AF18
AF20

AF26
0_0402_5%

AE7
AE9
AF1

AF6
AF8

C11
C13
C15
C17
C19

C22
C25

D10
D12
D14
D16
D18
D20
D21
D24
B10
B12
B14
B16
B18
B20
B23
B26

E11
E13
E15
E17
E19
E23
E26

F10
F12
F14
F16
F18

F22
F25
C2

C5
C7
C9

D3
D6
D8
B4
B8

E1

E4
E7
E9
J C PU1B

F2

F5
Place near CPU

VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128

SKTOCC#
1 2 H_PROCHOT#
R147 130_0402_5%
7 H_RS#[0..2]
1 2 H _P WRGOOD H_RS#0 F1 J26
D
R 64 300_0402_5% H_RS#1 RS#0 DP#0 D
G5 K25
H_RS#2 RS#1 DP#1 +CPU_GTLREF
F4 K26
RS#2 DP#2
1 2 H_RESET# AB2 L25
R 63 62_0402_5% RSP# DP#3
J6
7 H _ TRDY# TRDY#
AA21 Pop: Northwood
GTLREF0
AA6 Depop: Prescott
GTLREF1
F20
GTLREF2
23 H_A20M#
C6
A20M# GTLREF3
F6 R_G
H _ FERR# B6 R 18 0_0402_5%
23 H _ FERR# FERR#
B2 AE26 1 2
23 H _IGNNE# IGNNE# OPTIMIZED/COMPAT# +CPU_CORE
B5
23 H_SMI# H _P WRGOOD SMI#
AB23
23 H _P WRGOOD PWRGOOD H_T ESTHI0 R 21
Y4 AD24 1 2 62_0402_5%
23 H_STPCLK# STPCLK# TESTHI0 H_T ESTHI1 R 65
AA2 1 2 62_0402_5%
TESTHI1
D1 AC21
23 H_INTR LINT0 TESTHI2
E5 AC20
23 H_NMI LINT1 TESTHI3 H_T ESTHI2_7 R 20
W5 AC24 1 2 62_0402_5%
23 H_INIT# H_RESET# INIT# TESTHI4
AB25 AC23

2
7 H_RESET# RESET# TESTHI5
AA20
TESTHI6 R150
AB22
TESTHI7 H_T ESTHI8 R 52 62_0402_5%
H5 U6 1 2
7 H _D BSY# DBSY# TESTHI8 H_T ESTHI9 R 57 62_0402_5% @300_0402_5%
H2 W4 1 2
7 H _D R D Y# DRDY# TESTHI9 H_T ESTHI10 R 61 62_0402_5%
AD6 Y3 1 2

1
15 CPU_CLKSEL0 BSEL0 TESTHI10 H_T ESTHI11 R149 62_0402_5%
AD5 A6 1 2
15 CPU_CLKSEL1 BSEL1 TESTHI11 H_T ESTHI12 R 22 62_0402_5%
AD25 1 2
TESTHI12
H_THER MDA B3 R1481 2 @0_0402_5%
THERMDA H _ CPUPERF# 24
H_THERM DC C4 R 23 1 2 @0_0402_5%
THERMDC H_DPSLP# 23
E22
+ CPU_CORE 24 H_THERMTRIP# A2
THERMTRIP# Prescott DSTBN#0
DSTBN#1
DSTBN#2
K22
R22
W22
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
7
7
7 Pop: P4 Protability
Depop: Prescott/Northwood
DSTBN#3 H_DSTBN#3 7
R 305 1 2 62_0402_5% I TP_BPM#0 AC6
R 307 62_0402_5% I TP_BPM#1 BPM#0
1 2 AB5
R 308 62_0402_5% I TP_BPM#2 BPM#1
1 2 AC4 F21 H_DSTBP#0 7
R 306 62_0402_5% I TP_BPM#3 BPM#2 DSTBP#0
1 2 Y6 J23 H_DSTBP#1 7
R 309 62_0402_5% I TP_BPM#4 BPM#3 DSTBP#1
1 2 AA5 P23 H_DSTBP#2 7
R 310 62_0402_5% I TP_BPM#5 BPM#4 DSTBP#2
C 1 2 AB4 W23 H_DSTBP#3 7
C
BPM#5 DSTBP#3
Note: Please change to 10uH, DC current
of 100mA parts and close to cap I TP_TCK D4 L5
TCK ADSTB#0 H_ADSTB#0 7
I TP_TDI C1 R5
TDI ADSTB#1 H_ADSTB#1 7
+ CPU_CORE D5
ITP_TMS TDO
F7
ITP_TRST# TMS
E6 E21 H _DINV#0 7
L9 LQG21F4R7N00_0805 TRST# DBI#0
G25 H _DINV#1 7
DBI#1
1 2 AD20 P26 H _DINV#2 7
H _ VCCA VCCIOPLL DBI#2
AE23 V21 H _DINV#3 7
VCCA DBI#3

53 V CCSENSE A5 AE25
VCCSENSE DBR#
53 VSSSENSE A4
VSSSENSE
C 22 + CPUVID 1 2 V CCVIDLB AF3
@0_0402_5% VCCVIDLB H_PROCHOT#
R 28 C3 H_PROCHOT# 7,52
PROCHOT#
2 Trace >= 25mils H_VSSA
+

1 2 1 AD22 V6
VSSA MCERR#
AB26 H_CPUSLP# 23
L8 LQG21F4R7N00_0805 SLP#
33U_D2_8M_R35 CLK_ITP AC26 A22
15 CLK_ITP CLK_ITP# AD26 ITP_CLK0 NC1
A7 1 2 + CPU_CORE
15 CLK_ITP# ITP_CLK1 NC2 R 66
Pop: Prescott NC3
AF25
PLL Layout note : Depop: Northwood COM P0 L24 AF24 62_0402_5%
COM P1 COMP0 NC4
P1 AE21

VIDPWRGD
COMP1 NC5
1.Place cap within 600 mils of
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181

VCCVID
the VCCA and VSSA pins.
1

VID0
VID1
VID2
VID3
VID4
VID5
2.H_VCCIOPLL,HVCCA,HVSSA trace wide R106 R 94
12 mils(min) 61.9_0603_1% 61.9_0603_1%
F8
G21
G24
G3
G6
J2
J22
J25
J5
K21
K24
K3
K6
L1
L23
L26
L4
M2
M22
M25
M5
N21
N24
N3
N6
P2
P22
P25
P5
R1
R23
R26
R4
T21
T24
T3
T6
U2
U22
U25
U5
V1
V23
V26
V4
W21
W24
W3
W6
Y2
Y22
Y25
Y5

AE5
AE4
AE3
AE2
AE1
AD3

AD2

AF4
+3VS
2

AMP_3-1565030-1_Prescott Trace >= 25mils

+ CPUVID
1 RE H _VID5 1 2
Pop: Prescott R 24 1K_0402_5%
C4 H _VID4 1 2
Depop: Northwood R 27 1K_0402_5%
B 2
0.1U_0402_10V6K R_E B

+ CPUVID R P5
H _VID3 5 4
H _VID0 R 19 H _VID2 6 3
53 H_VID0
H _VID1 @2.43K_0603_1% H _VID1 7 2
53 H_VID1
H _VID2 1 2 H _VID0 8 1
53 H_VID2
H _VID3
53 H_VID3
H _VID4 H _V ID_PWRGD 1K_8P4R_1206_5%
53 H_VID4
H _VID5
53 H_VID5

+3V

1
R 654
10K_0402_5%

+3VS

2
VI D _PWRGD 53
1 2 E NLL 50,53
R 655 0_0402_5%
GTL Reference Voltage 1

4
U 51B C 73

1
Layout note :

OE#
H _V ID_PWRGD 6 5 0.1U_0402_16V4Z
O I 2 R 77
1. +CPU_GTLREF Trace wide
12mils(min),Space 15mils 1 @10K_0402_5%
+CPU_GMCH_GTLREF +CPU_CORE C 83

2
SN74LVC125APWLE_TSSOP14 U1
2. Place R_A and R_B near CPU.
3. Place decoupling cap 220PF near CPU. +3V POWER 2200P_0402_50V7K H_THER MDA 2 1
R P88 2 D+ VDD1
1

+CPU_GMCH_GTLREF trace H_THERM DC 3 6

ITP_TMS R 51 D- ALERT#
1 8 wide 12mils(min),Space
ITP_TRST# +CPU_GTLREF
2 7 15mils R_A 34,39 EC_SMB_CK2 8
SCLK THERM#
4
3 6 I TP_TCK 200_0603_1%
A 4 5 I TP_TDI 7 5 A
2

34,39 EC_SMB_DA2 SDATA GND

2 1
1K_8P4R_1206_5%
R 37 ADM1032ARM_RM8
1

2 0_0603_5% 1
R 38 C8
R_B C7
169_0603_1% 0.1U_0402_10V6K 220P_0402_50V8K
1 2
2

Close to the CPU Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Prescott Processor in uFCPGA478 (2/2)
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 0 .1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2041
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期 T, 七月 09, 2003 Sheet 5 of 56
5 4 3 2 1
 5 4 3 2 1

Place 11 North of Socket(Stuff 8)

+CPU_CORE

1 1 1 1 1 1 1 1 1 1 1
C448 C 451 C466 C 86 C103 C 69 C 45 C116 C134 C141 C124
22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z
2 2 2 2 2 2 2 2 2 2 2

D D

Place 12 Inside Socket(Stuff all)

+CPU_CORE

1 1 1 1 1 1 1 1 1 1
C483 C 482 C481 C480 C491 C494 C 493 C492 C488 C487
22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z
2 2 2 2 2 2 2 2 2 2

+CPU_CORE

1 1
(H_1.78)
C513 C 514
22U_1206_16V4Z 22U_1206_16V4Z 22uF depop reference
2 2
Springdale Customer Schematic R1.2 page82

C C
Place 9 South of Socket(Unstuff all)

+CPU_CORE

1 1 1 1 1 1 1 1 1
C158 C 164 C 33 C 93 C 18 C 94 C 34 C 95 C 35
22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z 22U_1206_16V4Z
2 2 2 2 2 2 2 2 2

B B

470uF _ERS10m ohm* 15, ESR=0.5m ohm

+ CPU_CORE

1 1 1 1 1 1
+ C 204 + C203 + C205 + C206 + C210 + C 208
470U_D4_2.5VM 470U_D4_2.5VM 470U_D4_2.5VM @470U_D4_2.5VM 470U_D4_2.5VM 470U_D4_2.5VM
2 2 2 2 2 2

+ CPU_CORE

1 1 1 1 1 1
+ C 207 + C209 + C202 + C518 + C187 + C 188
470U_D4_2.5VM 470U_D4_2.5VM 470U_D4_2.5VM 470U_D4_2.5VM @470U_D4_2.5VM @470U_D4_2.5VM
2 2 2 2 2 2

+CPU_CORE

Decoupling Reference Document:

A A
1 1 1
Springdale Chipset Platform Design guide Rev1.11
+ + +
(12474)page239
C218 C517 C524
@470U_D4_2.5VM 470U_D4_2.5VM @470U_D4_2.5VM
2 2 2 Decoupling Reference Requirement:
560uF Polymer, ESR:5m ohm(each) * 10
22uF X5R * 32

Title
Compal Electronics, Inc.
CPU Decoupling
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2041
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 星期 T, 七月 09, 2003 Sheet 6 of 56
5 4 3 2 1
 5 4 3 2 1

U36A U36F U36G

4 H_A#[3..31] H_D#[0..63] 4
AR32 VSS VSS AE11 L31 VSS VSS F16
+VTT_GMCH H_A#3 D26 B23 H _D#0 AR29 AE10 L26 F14
H_A#4 HA3# HD0# H _D#1 VSS VSS VSS VSS
Trace width 10mils,Space D30 HA4# HD1# E22 AR27 VSS VSS AE4 L25 VSS VSS F12
7mils H_A#5 L23 B21 H _D#2 AR25 AE1 L24 F10
HA5# HD2# VSS VSS VSS VSS

1
H_A#6 E29 D20 H _D#3 AR23 AD33 K33 F8
R365 H_A#7 HA6# HD3# H _D#4 VSS VSS VSS VSS
B32 HA7# HD4# B22 AR20 VSS VSS AD30 K29 VSS VSS F5
301_0603_1% H_A#8 K23 D22 H _D#5 AR16 AD28 K27 F3
H_A#9 HA8# HD5# H _D#6 VSS VSS VSS VSS
C30 HA9# HD6# B20 AR13 VSS VSS AD10 K25 VSS VSS F1
H_A#10 C31 C21 H _D#7 AR11 AD9 K22 E3
2

HD_S W ING H_A#11 HA10# HD7# H _D#8 VSS VSS VSS VSS
D J25 HA11# HD8# E18 AR9 VSS VSS AD8 K20 VSS VSS E1 D
H_A#12 B31 E20 H _D#9 AN32 AD6 K18 D35
HA12# HD9# VSS VSS VSS VSS
1

1 H_A#13 E30 B16 H_D#10 AN30 AD3 K16 D33

R369 C159 H_A#14 HA13# HD10# H_D#11 VSS VSS VSS VSS
B33 HA14# HD11# D16 AN28 VSS VSS AC35 K14 VSS VSS D31
102_0603_1% H_A#15 J24 B18 H_D#12 AN26 AC32 K12 D29
0.01U_0402_16V7K H_A#16 HA15# HD12# H_D#13 VSS VSS VSS VSS
F25 HA16# HD13# B17 AN24 VSS VSS AC4 K11 VSS VSS D27
2 H_A#17 H_D#14
D34 E16 AN22 AC1 J35 D25
2

H_A#18 HA17# HD14# H_D#15 VSS VSS VSS VSS

C32 HA18# HD15# D18 AN20 VSS VSS AB33 J32 VSS VSS D23
H_A#19 F28 G20 H_D#16 AN18 AB30 J28 D21
H_A#20 HA19# HD16# H_D#17 VSS VSS VSS VSS
C34 HA20# HD17# F17 AN16 VSS VSS AB28 J22 VSS VSS D19
H_A#21 J27 E19 H_D#18 AN14 AB27 J20 D17
H_A#22 HA21# HD18# H_D#19 VSS VSS VSS VSS
G27 HA22# HD19# F19 AN12 VSS VSS AB26 J18 VSS VSS D15
H_A#23 F29 J17 H_D#20 AN10 AB10 J16 D13
H_A#24 HA23# HD20# H_D#21 VSS VSS VSS VSS
E28 L18 AM35 AB9 J14 D11

GND
H_A#25 HA24# HD21# H_D#22 VSS VSS VSS VSS
H27 HA25# HD22# G16 AM29 VSS VSS AB8 J12 VSS VSS D9
H_A#26 K24 G18 H_D#23 AM27 AB6 J10 D1
H_A#27 HA26# HD23# H_D#24 VSS VSS VSS VSS
E32 HA27# HD24# F21 AM25 VSS VSS AB3 H33 VSS VSS C28
HDR COMP H_A#28 F31 F15 H_D#25 AM23 AA32 H30 C26
H_A#29 HA28# HD25# H_D#26 VSS VSS VSS VSS
G30 HA29# HD26# E15 AM21 VSS VSS AA4 H26 VSS VSS C24
H_A#30 J26 E21 H_D#27 AM19 AA1 H24 C22
HA30# HD27# VSS VSS VSS VSS
1

H_A#31 G26 J19 H_D#28 AM17 Y35 H22 C20

R362 HA31# HD28# H_D#29 VSS VSS VSS VSS
HD29# G14 AM15 VSS VSS Y33 H20 VSS VSS C18
24.9_0603_1% E17 H_D#30 AM13 Y30 H18 C16
4 H_REQ#[0..4] H_REQ#0 HD30# H_D#31 VSS VSS VSS VSS
B29 HREQ0# HD31# K17 AM11 VSS VSS Y28 H16 VSS VSS C14
H_REQ#1 J23 J15 H_D#32 AM9 Y27 H14 C12
2

H_REQ#2 HREQ1# HD32# H_D#33 VSS VSS VSS VSS

L22 HREQ2# HD33# L16 AL32 VSS VSS Y26 H12 VSS VSS C10
H_REQ#3 C29 J13 H_D#34 AL1 Y10 H9 C8
H_REQ#4 HREQ3# HD34# H_D#35 VSS VSS VSS VSS
J21 HREQ4# HD35# F13 AK28 VSS VSS Y9 H8 VSS VSS C4
B30 F11 H_D#36 AK26 Y8 H5 A32
C 5 H_ADSTB#0 HADSTB0# HD36# H_D#37 VSS VSS VSS VSS C
D28 E13 AK24 Y6 H2 A29

FSB
5 H_ADSTB#1 HADSTB1# HD37# H_D#38 VSS VSS VSS VSS
HD38# K15 AK22 VSS VSS Y3 G35 VSS VSS A27
B7 G12 H_D#39 AK20 W32 G31 A25
15 CLK_HCLK HCLKP HD39# H_D#40 VSS VSS VSS VSS
C7 G10 AK18 W18 G28 A23

GND
15 CLK_HCLK# HCLKN HD40# H_D#41 VSS VSS VSS VSS
HD41# L15 AK16 VSS VSS W17 F26 VSS VSS A20
B19 E11 H_D#42 AK14 W4 F24 A16
5 H_DSTBP#0 HDSTBP0# HD42# H_D#43 VSS VSS VSS VSS
5 H_DSTBN#0 C19 HDSTBN0# HD43# K13 AK12 VSS VSS V33 F22 VSS VSS A13
C17 J11 H_D#44 AK10 V30 F20 A11
5 H_DINV#0 DINV0# HD44# H_D#45 VSS VSS VSS VSS
5 H_DSTBP#1 L19 HDSTBP1# HD45# H10 AK8 VSS VSS V28 F18 VSS VSS A9
K19 G8 H_D#46 AK3 V27 A7
5 H_DSTBN#1 HDSTBN1# HD46# H_D#47 VSS VSS VSS
5 H_DINV#1 L17 DINV1# HD47# E9 AJ35 VSS VSS V26
G9 B13 H_D#48 AJ32 V19
+VTT_GMCH 5 H_DSTBP#2 HDSTBP2# HD48# H_D#49 VSS VSS SPRINGDALE_UFCBGA932
5 H_DSTBN#2 F9 HDSTBN2# HD49# E14 AJ9 VSS VSS V17
L14 B14 H_D#50 AJ4 V10
5 H_DINV#2 DINV2# HD50# H_D#51 VSS VSS
5 H_DSTBP#3 D12 HDSTBP3# HD51# B12 AJ1 VSS VSS V9
+GMCH_GTLREF E12 B15 H_D#52 AH33 V8
5 H_DSTBN#3 HDSTBN3# HD52# VSS VSS
1

+CPU_GMCH_GTLREF H_D#53
5 H_DINV#3 C15 DINV3# HD53# D14 AH30 VSS VSS V6
R359 C13 H_D#54 AH24 V3
HD54# H_D#55 VSS VSS
4 H_ADS# F27 ADS# HD55# B11 AH22 VSS VSS U32
200_0603_1% D24 D10 H_D#56 AH20 U19
5 H_TRDY# HTRDY# HD56# VSS VSS
G24 C11 H_D#57 AH18 U18
2

5 H _ D R DY# DRDY# HD57# H_D#58 VSS VSS

4 H_DEFER# L21 DEFER# HD58# E10 AH16 VSS VSS U4
1 2 E23 B10 H_D#59 AH14 T35
4 H_HITM# HITM# HD59# H_D#60 VSS VSS
1 4 H_HIT# K21 HIT# HD60# C9 AH12 VSS VSS T33
R647 0_0603_5% E25 B9 H_D#61 AH10 T30
C160 4 H_LOCK# HLOCK# HD61# H_D#62 VSS VSS
B24 D8 AH6 T28
GTL Reference Voltage 220P_0402_50V8K 4 H_BR0#
B28
BREQ0# HD62#
B8 H_D#63 AH3
VSS VSS
T27
2 4 H_BNR# BNR# HD63# VSS VSS
Layout note : 4 H_BPRI# B26 BPRI# AG35 VSS VSS T26
5 H_DBSY# E27 DBSY# AG32 VSS VSS T10
B H_RS#0 H_PROCHOT# B
1. +GMCH_GTLREF Trace wide G22 RS0# PROCHOT# L20 H_PROCHOT# 5,52 AG28 VSS VSS T9
H_RS#1 C27 AG26 T8
12mils (min),Space 15mils. H_RS#2 RS1# VSS VSS
B27 RS2# AG24 VSS VSS T6
2. Place decoupling cap 220PF near GMCH. 5 H_RS#[0..2] 5 H_RESET# E8 CPURST# BSEL0 L13 MCH_CLKSEL0 15 AG22 VSS VSS T3
24,42 SYS_PW ROK AE14 PWROK# BSEL1 L12 MCH_CLKSEL1 15 AG20 VSS VSS T1
AG18 VSS VSS R32
HDR COMP E24 AG16 R4
HD_S W ING HDRCOMP VSS VSS
C25 HDSWING AG14 VSS VSS R1
+GMCH_GTLREF F23 HDVREF AG8 VSS VSS P33
AG4 VSS VSS P30
AF33 VSS VSS P28
SPRINGDALE_UFCBGA932 AF30 P27
VSS VSS
AF25 VSS VSS P26
AF24 VSS VSS P9
AF22 VSS VSS P8
AF20 VSS VSS P6
AF18 VSS VSS P3
AF16 VSS VSS N35
AF14 VSS VSS N32
AF11 VSS VSS N4
AF9 VSS VSS N1
AF6 VSS VSS M33
AF3 VSS VSS M30
AE35 VSS VSS M28
AE32 VSS VSS M27
AE26 VSS VSS M26
AE25 VSS VSS M6
AE13 VSS VSS M3
A AE12 VSS VSS L35 A

SPRINGDALE_UFCBGA932

Compal Electronics, Inc.

Title
Springdale-Host/GND (1/4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2041
D ate: ¬P 期三, 七月 09, 2003 Sheet 7 of 56
5 4 3 2 1
 5 4 3 2 1

DDR A_SMA[0..12] U36B

12,14 DDRA_SMA[0..12]
DDRA_SMA0 AJ34 AN11 DDRA_SD Q[0..63]
SMAA_A0 SDQS_A0 DDRA_SDQS0 12,14 DDRA_SDQ[0..63] 12,14
DDRA_SMA1 AL33 AP12
SMAA_A1 SDM_A0 DDRA_SDM0 12,14
DDRA_SMA2 AK29 AP10 DD RA_SDQ0
DDRA_SMA3 SMAA_A2 SDQ_A0 DD RA_SDQ1
AN31 SMAA_A3 SDQ_A1 AP11
DDRA_SMA4 AL30 AM12 DD RA_SDQ2
DDRA_SMA5 SMAA_A4 SDQ_A2 DD RA_SDQ3
AL26 SMAA_A5 SDQ_A3 AN13
D DDRA_SMA6 AL28 AM10 DD RA_SDQ4 D
DDRA_SMA7 SMAA_A6 SDQ_A4 DD RA_SDQ5
AN25 SMAA_A7 SDQ_A5 AL10
DDRA_SMA8 AP26 AL12 DD RA_SDQ6
DDRA_SMA9 SMAA_A8 SDQ_A6 DD RA_SDQ7
AP24 SMAA_A9 SDQ_A7 AP13
DDRA_SMA10 AJ33
DDRA_SMA11 SMAA_A10
AN23 SMAA_A11 SDQS_A1 AP15 DDRA_SDQS1 12,14
DDRA_SMA12 AN21 AP16 DDRA_SDM1 12,14
Trace width of 12mils and space
SMAA_A12 SDM_A1 +2.5V 10mils(min)
AL34 AP14 DD RA_SDQ8
SMAB_A1 SDQ_A8 DD RA_SDQ9
AM34 SMAB_A2 SDQ_A9 AM14
AP32 AL18 D DRA_SDQ10
SMAB_A3 SDQ_A10 D DRA_SDQ11
AP31 SMAB_A4 SDQ_A11 AP19
AM26 AL14 D DRA_SDQ12 2
SMAB_A5 SDQ_A12

1
AN15 D DRA_SDQ13

DDR Channel A
SDQ_A13 D DRA_SDQ14 R390
12,14 DDRA_SW E# AB34 SWE_A# SDQ_A14 AP18 2
Y34 AM18 D DRA_SDQ15 C523 C777 10K_0603_1%
12,14 DDRA_SCAS# SCAS_A# SDQ_A15 1
12,14 DDRA_SRAS# AC33 SRAS_A#
AP23 2.2U_0805_16V4Z 0.1U_0402_16V4Z
DDRA_SDQS2 12,14

2
SDQS_A2 1 SMXRCOMPVOH
12,14 DDRA_SBS0 AE33 SBA_A0 SDM_A2 AM24 DDRA_SDM2 12,14
12,14 DDRA_SBS1 AH34 SBA_A1
AP22 D DRA_SDQ16 1
SDQ_A16

1
D DRA_SCS#0 AA34 AM22 D DRA_SDQ17 1
12,14 DDRA_SCS#0 SCS_A0# SDQ_A17
D DRA_SCS#1 Y31 AL24 D DRA_SDQ18 C533 R391
12,14 DDRA_SCS#1 SCS_A1# SDQ_A18 1U_0603_10V6K
Y32 AN27 D DRA_SDQ19 30.9K_0603_1% C196
SCS_A2# SDQ_A19 2
W34 SCS_A3# SDQ_A20 AP21 D DRA_SDQ20 * 0.01U_0402_16V7K
D DRA_SDQ21 2
AL22

2
DD RA_CKE0 SDQ_A21 D DRA_SDQ22
12,14 DDRA_CKE0 AL20 SCKE_A0 SDQ_A22 AP25
12,14 DDRA_CKE1
DD RA_CKE1 AN19 AP27 D DRA_SDQ23 Close to Pin AN9
SCKE_A1 SDQ_A23
AM20 SCKE_A2
C AP20 SCKE_A3 SDQS_A3 AM30 DDRA_SDQS3 12,14
Close to GMCH <1" C

SDM_A3 AP30 DDRA_SDM3 12,14

AK32 * Change to 31.12K
SCMDCLK_A0 D DRA_SDQ24
AK31 SCMDCLK_A0# SDQ_A24 AP28
AP17 AP29 D DRA_SDQ25
12 DDRA_CLK1 SCMDCLK_A1 SDQ_A25
AN17 AP33 D DRA_SDQ26
12 DDRA_CLK1# SCMDCLK_A1# SDQ_A26
N33 AM33 D DRA_SDQ27
12 DDRA_CLK2 SCMDCLK_A2 SDQ_A27
N34 AM28 D DRA_SDQ28 Follow Intel design guide
12 DDRA_CLK2# SCMDCLK_A2# SDQ_A28
AK33 AN29 D DRA_SDQ29 R1.11(12474) page124,125
SCMDCLK_A3 SDQ_A29 D DRA_SDQ30
AK34 SCMDCLK_A3# SDQ_A30 AM31
AM16 AN34 D DRA_SDQ31
SCMDCLK_A4 SDQ_A31
+SM_VREF_A AL16 SCMDCLK_A4#
+SM_VREF_A trace width of 12mils and space P31 SCMDCLK_A5 SDQS_A4 AF34 DDRA_SDQS4 12,14
12mils(min) P32 SCMDCLK_A5# SDM_A4 AF31 DDRA_SDM4 12,14
E34 AH32 D DRA_SDQ32
SMVREF_A SDQ_A32 D DRA_SDQ33
SDQ_A33 AG34
SMXRCOMP AK9 AF32 D DRA_SDQ34
SMXRCOMP SDQ_A34 D DRA_SDQ35
2 2 SDQ_A35 AD32
C528 C522 SMXRCOMPVOH AN9 AH31 D DRA_SDQ36
SMXRCOMPVOH SDQ_A36 D DRA_SDQ37
SDQ_A37 AG33
2.2U_0805_16V4Z 0.1U_0402_16V4Z SMXRCOMPVOL AL9 AE34 D DRA_SDQ38
1 1 SMXRCOMPVOL SDQ_A38 D DRA_SDQ39
SDQ_A39 AD34

SDQS_A5 V34 DDRA_SDQS5 12,14

Close to GMCH(E34) W33 DDRA_SDM5 12,14
SDM_A5
AC34 D DRA_SDQ40
SDQ_A40 D DRA_SDQ41
SDQ_A41 AB31
B D DRA_SDQ42 B
SDQ_A42 V32
V31 D DRA_SDQ43
SDQ_A43 D DRA_SDQ44 +2.5V
SDQ_A44 AD31
AB32 D DRA_SDQ45
SDQ_A45 D DRA_SDQ46
SDQ_A46 U34
U33 D DRA_SDQ47
SDQ_A47 Trace width of 12mils and space
2
+2.5V M32 C217 10mils(min)
SDQS_A6 DDRA_SDQS6 12,14

1
SDM_A6 M34 DDRA_SDM6 12,14
Trace width of 12mils and space 2.2U_0805_16V4Z R153
D DRA_SDQ48 1 30.9K_0603_1%
10mils(min) SDQ_A48 T34
SDQ_A49 T32 D DRA_SDQ49 *
K34 D DRA_SDQ50

2
SDQ_A50
1

K32 D DRA_SDQ51 SMXRCOMPVOL

R151 SDQ_A51 D DRA_SDQ52
SDQ_A52 T31
40.2_0603_1% P34 D DRA_SDQ53 1
SDQ_A53

1
L34 D DRA_SDQ54 1
SDQ_A54 D DRA_SDQ55 C220 R154
Change to 42.2_1% L33
2

SDQ_A55 1U_0603_10V6K 10K_0603_1% C190

SMXRCOMP 2
SDQS_A7 H31 DDRA_SDQS7 12,14 0.01U_0402_16V7K
2
2 H32 DDRA_SDM7 12,14

2
SDM_A7
C201 Close to Pin AL9
Place resistors within J33 D DRA_SDQ56
SDQ_A56
1

2.2U_0805_16V4Z 1.0 inch of GMCH (AK9) SDQ_A57 H34 D DRA_SDQ57 Close to GMCH <1"
1 R152 D DRA_SDQ58
SDQ_A58 E33
40.2_0603_1% F33 D DRA_SDQ59
SDQ_A59 D DRA_SDQ60
Change to 42.2_1% SDQ_A60 K31
J34 D DRA_SDQ61
2

SDQ_A61 D DRA_SDQ62
A SDQ_A62 G34 A
F34 D DRA_SDQ63
SDQ_A63

SPRINGDALE_UFCBGA932

Title
Compal Electronics, Inc.
Springdale-DDR Interface-A(2/5)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-2041
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: ¬P 期三, 七月 09, 2003 Sheet 8 of 56
5 4 3 2 1
 5 4 3 2 1

DDR B_SMA[0..12] U36C

13,14 DDRB_SMA[0..12]
DDRB_SMA0 AG31 AF15
SMAA_B0 SDQS_B0 DDRB_SDQS0 13,14
DDRB_SMA1 AJ31 AG11
SMAA_B1 SDM_B0 DDRB_SDM0 13,14
DDRB_SMA2 AD27 AJ10 DD RB_SDQ0
DDRB_SMA3 SMAA_B2 SDQ_B0 DD RB_SDQ1 DDRB_SD Q[0..63]
AE24 SMAA_B3 SDQ_B1 AE15 DDRB_SDQ[0..63] 13,14
DDRB_SMA4 AK27 AL11 DD RB_SDQ2
DDRB_SMA5 AG25 SMAA_B4 SDQ_B2 DD RB_SDQ3
SMAA_B5 SDQ_B3 AE16
DDRB_SMA6 AL25 AL8 DD RB_SDQ4
DDRB_SMA7 SMAA_B6 SDQ_B4 DD RB_SDQ5
D AF21 SMAA_B7 SDQ_B5 AF12 D
DDRB_SMA8 AL23 AK11 DD RB_SDQ6
DDRB_SMA9 SMAA_B8 SDQ_B6 DD RB_SDQ7
AJ22 SMAA_B9 SDQ_B7 AG12
DDRB_SMA10 AF29
DDRB_SMA11 AL21 SMAA_B10
SMAA_B11 SDQS_B1 AG13 DDRB_SDQS1 13,14
DDRB_SMA12 AJ20 AG15
SMAA_B12 SDM_B1 DDRB_SDM1 13,14
AE27 AE17 DD RB_SDQ8
SMAB_B1 SDQ_B8 DD RB_SDQ9
AD26 SMAB_B2 SDQ_B9 AL13
AL29 AK17 D DRB_SDQ10
SMAB_B3 SDQ_B10 D DRB_SDQ11
AL27 SMAB_B4 SDQ_B11 AL17
AE23 AK13 D DRB_SDQ12

DDR Channel B
SMAB_B5 SDQ_B12 D DRB_SDQ13
SDQ_B13 AJ14
W27 AJ16 D DRB_SDQ14
13,14 DDRB_SW E# SWE_B# SDQ_B14
W31 AJ18 D DRB_SDQ15 +2.5V
13,14 DDRB_SCAS# SCAS_B# SDQ_B15
13,14 DDRB_SRAS# W26 SRAS_B#
SDQS_B2 AG21 DDRB_SDQS2 13,14
SDM_B2 AE21 DDRB_SDM2 13,14
13,14 DDRB_SBS0 Y25 SBA_B0
Trace width of 12mils and space
AA25 AE19 D DRB_SDQ16 2 2 10mils(min)
13,14 DDRB_SBS1 SBA_B1 SDQ_B16

1
AE20 D DRB_SDQ17 C541 C778
D DRB_SCS#0 SDQ_B17 D DRB_SDQ18 R394
13,14 DDRB_SCS#0 U26 SCS_B0# SDQ_B18 AG23
D DRB_SCS#1 T29 AK23 D DRB_SDQ19 2.2U_0805_16V4Z 0.1U_0402_16V4Z 10K_0603_1%
13,14 DDRB_SCS#1 SCS_B1# SDQ_B19 1 1
V25 AL19 D DRB_SDQ20
SCS_B2# SDQ_B20 D DRB_SDQ21
W25 AK21

2
SCS_B3# SDQ_B21 D DRB_SDQ22 SM YRCOMPVOH
SDQ_B22 AJ24
DD RB_CKE0 AK19 AE22 D DRB_SDQ23
13,14 DDRB_CKE0 SCKE_B0 SDQ_B23
DD RB_CKE1 AF19 1
13,14 DDRB_CKE1 SCKE_B1

1
AG19 SCKE_B2 SDQS_B3 AH27 DDRB_SDQS3 13,14 1
C AE18 AJ28 C546 R398 C213 C
SCKE_B3 SDM_B3 DDRB_SDM3 13,14 1U_0603_10V6K 30.9K_0603_1%
D DRB_SDQ24 2 0.01U_0402_50V7K
AG29 SCMDCLK_B0 SDQ_B24 AK25
D DRB_SDQ25 2
AG30 AH26

2
SCMDCLK_B0# SDQ_B25 D DRB_SDQ26 Close to Pin R14
13 DDRB_CLK1 AF17 SCMDCLK_B1 SDQ_B26 AG27
AG17 AF27 D DRB_SDQ27
13 DDRB_CLK1# SCMDCLK_B1# SDQ_B27
13 DDRB_CLK2 N27 SCMDCLK_B2 SDQ_B28 AJ26 D DRB_SDQ28 Close to GMCH <1"
N26 AJ27 D DRB_SDQ29
13 DDRB_CLK2# SCMDCLK_B2# SDQ_B29
SM_VREF_B and SM_VREF_A AJ30 AD25 D DRB_SDQ30
SCMDCLK_B3 SDQ_B30 D DRB_SDQ31
are connected inside GMCH. AH29 SCMDCLK_B3# SDQ_B31 AF28
+SM_VREF_B AK15 SCMDCLK_B4
+2.5V AL15 AD29
SCMDCLK_B4# SDQS_B4 DDRB_SDQS4 13,14
+SM_VREF_B trace width of N31 SCMDCLK_B5 SDM_B4 AC31 DDRB_SDM4 13,14
12mils and space N30 SCMDCLK_B5#
AE30 D DRB_SDQ32
12mils(min) SDQ_B32 D DRB_SDQ33
2 AP9 SMVREF_B SDQ_B33 AC27
C539 AC30 D DRB_SDQ34
SM YRCOMP SDQ_B34 D DRB_SDQ35
AA33 SMYRCOMP SDQ_B35 Y29
1

2.2U_0805_16V4Z AE31 D DRB_SDQ36

R392 1 SM YRCOMPVOH SDQ_B36 D DRB_SDQ37
R34 SMYRCOMPVOH SDQ_B37 AB29
AA26 D DRB_SDQ38
150_0603_1% SMYRCOMPVOL SDQ_B38 D DRB_SDQ39
R33 SMYRCOMPVOL SDQ_B39 AA27
2

SDQS_B5 U30 DDRB_SDQS5 13,14

SDM_B5 U31 DDRB_SDM5 13,14
+2.5V
2 2 AA30 D DRB_SDQ40
SDQ_B40
1

C547 C200 W30 D DRB_SDQ41

SDQ_B41
R396
SDQ_B42 U27 D DRB_SDQ42 Trace width of 12mils and space
B 2.2U_0805_16V4Z 0.1U_0402_16V4Z D DRB_SDQ43 B
SDQ_B43 T25 10mils(min)

1
150_0603_1% 1 1 D DRB_SDQ44
SDQ_B44 AA31 2
V29 D DRB_SDQ45 C219 R163
2

SDQ_B45 D DRB_SDQ46 30.9K_0603_1%

SDQ_B46 U25
Close to GMCH(AP9) R27 D DRB_SDQ47 2.2U_0805_16V4Z
SDQ_B47 1

2
SDQS_B6 L27 DDRB_SDQS6 13,14
M29 SMYRCOMPVOL
SDM_B6 DDRB_SDM6 13,14
+2.5V P29 D DRB_SDQ48
SDQ_B48

1
R30 D DRB_SDQ49 1 1
SDQ_B49 D DRB_SDQ50 R164 C211
SDQ_B50 K28
L30 D DRB_SDQ51 C223 10K_0603_1%
SDQ_B51 D DRB_SDQ52 1U_0603_10V6K 0.01U_0402_50V7K
2 SDQ_B52 R31
C553 D DRB_SDQ53 2 2
R26

2
SDQ_B53
1

P25 D DRB_SDQ54 Close to Pin R33

R399 2.2U_0805_16V4Z SDQ_B54 D DRB_SDQ55
SDQ_B55 L32
Change to 42.2_1% 40.2_0603_1% 1

SDQS_B7 J30 DDRB_SDQS7 13,14

Close to GMCH <1"
J31 DDRB_SDM7 13,14
2

SDM_B7
Trace width of 12mils
SM YRCOMP and space 10mils(min) K30 D DRB_SDQ56
SDQ_B56 D DRB_SDQ57
SDQ_B57 H29
F32 D DRB_SDQ58
SDQ_B58 D DRB_SDQ59
SDQ_B59 G33
1

Change to 42.2_1% N25 D DRB_SDQ60

R400 SDQ_B60 D DRB_SDQ61
SDQ_B61 M25
40.2_0603_1% J29 D DRB_SDQ62
SDQ_B62 D DRB_SDQ63
A SDQ_B63 G32 A
Place resistors within
2

1.0 inch of GMCH (AA33)

SPRINGDALE_UFCBGA932

Title
Compal Electronics, Inc.
Springdale-DDR Interface-B(3/5)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2041
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: ¬P 期三, 七月 09, 2003 Sheet 9 of 56
5 4 3 2 1
 5 4 3 2 1

+1.5VS +1.5VS
Change to 43.2_1% Change to 52.3_1% +1.5VS
U36D
16 AGP_C/BE#[0..3]
AGP_C/BE#0 Y7 AC6
GCBE0 GADSTBF0 AGP_AD_STBF0 16
1

2
? AGP_C/BE#1 W5 AC5
GCBE1 GADSTBS0# AGP_AD_STBS0 16
R123 R116 R121 AGP_C/BE#2 AA3
43_0402_5% AGP_C/BE#3 GCBE2 AGP_AD0
U2 GCBE3 GAD0 AE6
51.1_0603_1% @10K_0402_5% AC11 AGP_AD1
GAD1 AGP_AD2
16 AGP_FRAME# U6 AD5
2

1
CLK_MCH_66M H4 GFRAME GAD2 AGP_AD3
D 15 CLK_MCH_66M GCLKIN GAD3 AE5 D
GRCOMP HI_RCOMP_MCH AGP_PAR AB4 AA10 AGP_AD4
16 AGP_DEVSEL# GDEVSEL GAD4 AGP_AD5
16 AGP_IRDY# V11 GIRDY GAD5 AC9
AGP_AD6
1: External AGP
16 AGP_TRDY# AB5
W11
GTRDY AGP GAD6 AB11
AB7 AGP_AD7
16 AGP_STOP# GSTOP GAD7 AGP_AD[0..31] 16
AGP_PAR AB2 AA9 AGP_AD8
0: Internal Graphics 16 AGP_PAR
N6
GPAR/ADD_DETECT GAD8
AA6 AGP_AD9
16 AGP_REQ# GREQ GAD9
M7 AA5 AGP_AD10
+1.5VS 16 AGP_GNT# GGNT GAD10
W10 AGP_AD11
GAD11
Note: GRCOMP AC2 GRCOMP/DVOBCGCOMP GAD12 AA11 AGP_AD12
HI_SWING_MCH, HI_VREF_MCH AGP_SW ING AC3 W6 AGP_AD13
GVSWING GAD13
1

trace width of 10mils and +AGP_VREF +AGP_VREF AD2 W9 AGP_AD14

R353 GVREF GAD14 AGP_AD15
space 7mils GAD15 V7
16 AGP_RBF# R10 GRBF
226_0603_1% R9 V4
16 AGP_WBF# GWBF GADSTBF1 AGP_AD_STBF1 16
16 AGP_DBIHI M4 V5 AGP_AD_STBS1 16
2

HI_SW ING_MCH DBI_HI GADSTBS1#

16 AGP_DBILO M5 DBI_LO
AA2 AGP_AD16
16 AGP_ST[0..2] GAD16
1

1 1 Close to GMCH(AE3) AGP_ST0 N3 GST0 GAD17 Y4 AGP_AD17

R368 C499 AGP_ST1 N5 Y2 AGP_AD18
C498 AGP_ST2 GST1 GAD18 AGP_AD19
N2 GST2 GAD19 W2
147_0603_1% 0.01U_0402_16V7K Y5 AGP_AD20
2 0.1U_0402_16V4Z 2 23 HUB_HL[0..10] GAD20
H UB_HL0 AF5 V2 AGP_AD21
2

HI0 GAD21
Close to GMCH ball <250mils H UB_HL1 AG3 HI1 GAD22 W3 AGP_AD22
H UB_HL2 AK2 U3 AGP_AD23
H UB_HL3 HI2 GAD23 AGP_AD24
AG5 HI3 GAD24 T2

HUB
HI_V REF_MCH H UB_HL4 AK5 T4 AGP_AD25
H UB_HL5 HI4 GAD25 AGP_AD26
AL3 HI5 GAD26 T5
1

1 1 Close to GMCH(AE2) H UB_HL6 AL2 R2 AGP_AD27

C R372 C500 H UB_HL7 HI6 GAD27 AGP_AD28 C
AL4 HI7 GAD28 P2
C503 H UB_HL8 AJ2 P5 AGP_AD29
113_0603_1% 0.1U_0402_16V4Z H UB_HL9 HI8 GAD29 AGP_AD30
0.01U_0402_16V7K AH2 HI9 GAD30 P4
2 2 HUB_HL10 AGP_AD31
AJ3 M2
2

Close to GMCH ball <250mils HI10 GAD31

23 HUB_HLSTRF AH5 HISTRF
CLK_MCH_66M AH4 U11
23 HUB_HLSTRS HISTRS GSBSTBF AGP_SB_STBF 16
GSBSTBS# T11 AGP_SB_STBS 16

1
HI_RCOMP_MCH AD4
+1.5VS HI_RCOMP AGP_SBA[0..7] 16
Note: R337 HI_SW ING_MCH AE3 R6 AGP_SBA0
@10_0402_5% HI_V REF_MCH HI_SWING GSBA0# AGP_SBA1
CI_SWING_MCH, CI_VREF_MCH AE2 HI_VREF GSBA1# P7
trace width of 10mils and R3 AGP_SBA2
GSBA2#
1

AK7 R5 AGP_SBA3
space 20mils
2
R122 CI0 GSBA3# AGP_SBA4
1 AH7 CI1 GSBA4# U9
AD11 U10 AGP_SBA5
226_0603_1% 0.8V C486 CI2 GSBA5# AGP_SBA6
AF7 CI3 GSBA6# U5
@10P_0402_50V8K AD7 T7 AGP_SBA7
2

CI_S W ING_GMCH 2 CI4 GSBA7#

AC10 CI5

CSA
AF8 H3 R88 2 1 0_0402_5%
CI6 DDCA_DATA
1

1 1 Close to GMCH(AF2) AG7 CI7 DDCA_CLK F2 R84 2 1 0_0402_5%

C147 R127 AE9
C155 CI8 R91 2
AH9 CI9 RED F4 1 0_0402_5%
0.1U_0402_16V4Z 147_0603_1% 0.01U_0402_16V7K change to 52.3_1% AG6 E4
2 2 CI10 RED# R1012
AJ6 H6 1 0_0402_5%

VGA
2

CISTRF GREEN
Close to GMCH ball <250mils AJ5 CISTRS GREEN# G5
H7 R1042 1 0_0402_5%
CI_V REF_GMCH R375 54.9_0603_1% BLUE
+1.5VS 1 2 AG2 CI_RCOMP BLUE# G6
0.35V CI_S W ING_GMCH AF2 CI_SWING
1

1 1 Close to GMCH(AF4) CI_V REF_GMCH AF4 CI_VREF HSYNC G3

C166 R130 E2
B C165 R92 0_0402_5% VSYNC B
2 1 G4 DREFCLK
0.1U_0402_16V4Z 113_0603_1% 0.01U_0402_16V7K +3VS 1 2 AP8 D2 R3222 1 0_0402_5%
2 2 R692 10K_0402_5% EXTTS# REFSET
24 IC H _ SYNC# AJ8
2

ICH_SYNC#
13,23,26,27,29,30,36,39 PCIRST# 2 1 AK4 RSTIN# NC_1 A3
R134 0_0402_5% A33
Close to GMCH ball <250mils NC_2
AG10 RESERVED_1 NC_3 A35 Analog RGB/CRT guidelines for Springdale-P
AG9 RESERVED_2 NC_4 AF13
AN35 RESERVED_3 NC_5 AF23
+1.5VS AP34 AJ12
RESERVED_4 NC_6
AR1 RESERVED_5 NC_7 AN1
NC_8 AP2
1

NC_9 AR3
R31 AR33
NC_10
Close GMCH ball (AC3) less than 250mils NC_11 AR35
60.4_0603_1% B2
NC_12
B25
2

AGP_SW ING NC_13

NC_14 B34
1 1 NC_15 C1
1

C9 C113 C23
R32 NC_16
NC_17 C35
39.2_0603_1% 0.1U_0402_16V4Z 0.01U_0402_16V7K E26
2 2 NC_18
NC_19 M31
R25
2

NC_20
+AGP_VREF = 0.3535 Follow Springdale Chipset Platform Design guide Rev1.11(12474)
1 2 +AGP_VREF SPRINGDALE_UFCBGA932
R56 Note:
1

44.2_0603_1% R55 1 Springdale Customer Schematic R1.2 page18

A
C127 AGP_SWING only had 0.1u cap ; But Springdale A

0.01U_0402_16V7K Chipset Platform Design guide Rev1.11(12474)

100_0603_1% 2 page138 had a 0.01uf cap. need confirm with
2

Intel.
Close GMCH ball (AD2)
less than 250mils
Title
Springdale-AGP/HUB/VGA/CSA (4/5)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B LA-2041 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 七月 09, 2003 Sheet 10 of 56
5 4 3 2 1
 5 4 3 2 1

+2.5V

1 2 1 1 1 1 1 1 1
C174 C186 C169 C238 C191 C198 C172 C195 C199
Note:
22U_1206_10V4Z 4.7U_0805_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
Placed less than 100 mils from ball 2 1 2 2 2 2 2 2 2
Route to GMCH ball without via +1.5VS

U36E
D VTT_DCAP1 A15 J6 +2.5V +1.5VS D
VTT_DCAP2 VTT VCC
A21 VTT VCC J7
1 1 A4 VTT VCC J8
C490 C496 A5 J9 1 1 1 1 1
VTT VCC C189 C185 C222 C175 C99
A6 VTT VCC K6
0.47U_0603_16V7K 0.47U_0603_16V7K B5 K7
2 2 VTT VCC 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
B6 VTT VCC K8
2 2 2 2 2
C5 VTT VCC K9
C6 VTT VCC L6
D5 VTT VCC L7
D6 VTT VCC L9
+VTT_GMCH D7 VTT VCC L10
E6 L11 +1.5VS
VTT VCC
E7 VTT VCC M8
F7 VTT VCC M9
VCC M10 1 1 1 1 1 1 1 1 1
AA35 M11 C171 C112 C135 C125 C106 C181 C167 C143 C184
VCC_DDR VCC
2 +2.5V AL6 VCC_DDR VCC N9
AL7 N10 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
C535 VCC_DDR VCC 2 2 2 2 2 2 2 2 2
AM1 VCC_DDR VCC N11
0.1U_0402_10V6K AM2 VCC_DDR VCC P10
1
AM3 VCC_DDR VCC P11
AM5 VCC_DDR VCC R11
AM6 VCC_DDR VCC T16
AM7 T17 +1.5VS +VTT_GMCH
VCC_DDR VCC
AM8 VCC_DDR VCC T18
AN2 VCC_DDR VCC T19
AN4 T20 1 2 1 2 2 2 1 1

POWER
VCC_DDR VCC C157 C156 C70 C47 C60 C42 C26
AN5 VCC_DDR VCC U16
C AN6 U17 + C72 + C28 C
VCC_DDR VCC 4.7U_0805_10V4Z 10U_1206_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 1U_0603_6.3V6M 0.47U_0603_16V4Z
AN7 VCC_DDR VCC U20
470U_D4_2.5VM 1 470U_D4_2.5VM 1 1 1 2 2
AN8 VCC_DDR VCC V16
2 2
AP3 VCC_DDR VCC V18
AP4 VCC_DDR VCC V20
AP5 VCC_DDR VCC W16 Place at the output of the 1.5V VR
C548 AP6 W19
0.1U_0402_10V6K VCC_DDR VCC
AP7 VCC_DDR VCC W20 +1.5VS
2 1 VCC_D DR_DCAP5 AR15 Y16 +VTT_GMCH +2.5V
VCC_D DR_DCAP4 VCC_DDR VCC
2 1 AR21 VCC_DDR VCC Y17
C552 0.22U_0603_10V7K * AR31 Y18 1 1 1
VCC_DDR VCC
AR4 VCC_DDR VCC Y19
C520 AR5 Y20 C92 C126 C183
0.47U_0603_16V7K VCC_DDR VCC 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
AR7 VCC_DDR
VCC_D DR_DCAP1 2 2 Place near ball 2
2 1 E35 VCC_DDR
2 1 R35 VCC_DDR VCC_AGP J1 Y11,routing trace Place near GMCH
C532 0.22U_0603_10V7K J2 Place near GMCH
VCC_AGP from cap to ball
+3VS G1 VCC_DAC VCC_AGP J3
C163 G2 J4
VCC_DAC VCC_AGP
Trace 14mils 0.1U_0402_10V6K
VCC_AGP J5
2 1 VCC_AGP_DCAP2 AG1 K2 Note: Please change to 0.82uH, DC current
VCCA_AGP VCC_AGP
+1.5VS Y11 VCCA_AGP VCC_AGP K3 of 30mA parts and close to cap
VCC_AGP K4
2 1 VTT_DCAP3 A31 K5
C168 0.1U_0402_10V6K V CCA_FSB VCCA_FSB VCC_AGP +1.5VS
B4 VCCA_FSB VCC_AGP L1
R321 2 1 0_0402_5% VCCA_DPLL B3 L2
VCC A_DAC VCCA_DPLL VCC_AGP Trace 14mils L21 Trace 14mils
2 1 C2 VCCA_DAC VCC_AGP L3
R316 0_0402_5% L4
VCC_D DR_DCAP2 VCC_AGP VCCA_FSB1 V CCA_FSB
1 2 AL35 VCCA_DDR VCC_AGP L5 2 1 1 2
B C242 0.1U_0402_10V6K VCC_AGP_DCAP1 R315 B
AB25 VCCA_DDR VCC_AGP Y1 1 2

1
AC25 0_0603_5% LQG21F4R7N00_0805 2
VCCA1P5_DDR_SM VCCA_DDR C117 C32 C475
AC26 VCCA_DDR VSSA_DAC D3 +
(1A) 0.1U_0402_10V6K
SPRINGDALE_UFCBGA932 150U_D2_6.3VM 0.1U_0402_16V4Z

2
1
Close to GMCH
Note:
Placed less than 100 mils from ball
Route to GMCH ball without via Note: Please change to 1uH(0.54uH-D-IN), DC current
of 1000mA parts and close to cap
Decoupling Reference Document: Trace 50mils
Springdale Chipset Platform Design guide Rev1.11 Trace 35mils (under GMCH ball field)
+1.5VS
(12474)page246,248
Trace 35mils
2 1 VCCA_ DDR 1 2 VCCA1P5_DDR_SM
R144 0_0603_5% L16 0_0603_5%
(1A) 1 (1A) 2
Decoupling Reference Document: C212
C197
Springdale Customer Schematic R1.2 page84 22U_1206_16V4Z 0.1U_0402_16V4Z
2 1
Close to GMCH

A A

Compal Electronics, Inc.

Title
Springdale-Decoupling (5/5)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2041
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: ¬P 期三, 七月 09, 2003 Sheet 11 of 56
5 4 3 2 1
 5 4 3 2 1

+2.5V +2.5V DDRA_VREF trace width of

12mils and space 12mils(min)
JP26
1 2 DDRA _VREF +2.5V
VREF VREF
3 VSS VSS 4 1
DD RA_SDQ0 5 6 DD RA_SDQ5 C305 DDRA_SD Q[0..63]
DQ0 DQ4 8,14 DDRA_SDQ[0..63]

1
DD RA_SDQ1 7 8 DD RA_SDQ4
DQ1 DQ5 0.1U_0402_16V4Z R204 DDRA_SD QS[0..7]
9 VDD VDD 10 8,14 DDRA_SDQS[0..7]
DD RA_SDQS0 DDRA_SDM0 2
11 DQS0 DM0 12
DD RA_SDQ6 13 14 DD RA_SDQ7 Close to SO-DIMM 75_0603_1% DDR A_SMA[0..12]
DQ2 DQ6 8,14 DDRA_SMA[0..12]
15 16

2
DD RA_SDQ2 VSS VSS DD RA_SDQ3 DDRA_S DM[0..7]
17 DQ3 DQ7 18 8,14 DDRA_SDM[0..7]
D D DRA_SDQ12 19 20 DD RA_SDQ9 D
DQ8 DQ12

1
21 VDD VDD 22
DD RA_SDQ8 23 24 D DRA_SDQ13 R203
DD RA_SDQS1 DQ9 DQ13 DDRA_SDM1
25 DQS1 DM1 26
27 28 75_0603_1%
D DRA_SDQ10 VSS VSS D DRA_SDQ14
29 30

2
D DRA_SDQ15 DQ10 DQ14 D DRA_SDQ11
31 DQ11 DQ15 32
33 VDD VDD 34
8 DDRA_CLK1 35 CK0 VDD 36
8 DDRA_CLK1# 37 CK0# VSS 38
39 VSS VSS 40

D DRA_SDQ20 41 42 D DRA_SDQ21
D DRA_SDQ16 43
DQ16
DQ17
DQ20
DQ21 44 D DRA_SDQ17
+2.5V
System Memory Decoupling caps
45 VDD VDD 46
DD RA_SDQS2 47 48 DDRA_SDM2
D DRA_SDQ18 DQS2 DM2 D DRA_SDQ22
49 DQ18 DQ22 50
51 VSS VSS 52 1 1 1 1 1 1 1
D DRA_SDQ19 53 54 D DRA_SDQ23 C331 C314 C339 C312 C337 C311 C336
D DRA_SDQ28 DQ19 DQ23 D DRA_SDQ24
55 DQ24 DQ28 56
57 58 22U_1206_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
D DRA_SDQ29 VDD VDD D DRA_SDQ25 2 2 2 2 2 2 2
59 DQ25 DQ29 60
DD RA_SDQS3 61 62 DDRA_SDM3
DQS3 DM3
63 VSS VSS 64
D DRA_SDQ30 65 66 D DRA_SDQ26
D DRA_SDQ27 DQ26 DQ30 D DRA_SDQ31
67 DQ27 DQ31 68
69 VDD VDD 70
71 72 +2.5V
C CB0 CB4 C
73 CB1 CB5 74
75 VSS VSS 76
77 DQS8 DM8 78 1 1 1 1 1 1 1 1
79 80 C310 C335 C334 C308 C333 C307 C332 C306
CB2 CB6
81 VDD VDD 82
83 84 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
CB3 CB7 2 2 2 2 2 2 2 2
85 DU DU/RESET# 86
87 VSS VSS 88
89 CK2 VSS 90
91 CK2# VDD 92
93 VDD VDD 94
DD RA_CKE1 95 96 DD RA_CKE0
8,14 DDRA_CKE1 CKE1 CKE0 DDRA_CKE0 8,14
97 DU/A13 DU/BA2 98
DDRA_SMA12 99 100 DDRA_SMA11
DDRA_SMA9 A12 A11 DDRA_SMA8
101 A9 A8 102
103 VSS VSS 104
DDRA_SMA7 105 106 DDRA_SMA6
DDRA_SMA5 A7 A6 DDRA_SMA4
107 A5 A4 108
DDRA_SMA3 109 110 DDRA_SMA2
DDRA_SMA1 A3 A2 DDRA_SMA0
111 A1 A0 112
113 VDD VDD 114
DDRA_SMA10 115 116 DDRA_SBS1
A10/AP BA1 DDRA_SBS1 8,14
DDRA_SBS0 117 118 D DRA_SRAS#
8,14 DDRA_SBS0 BA0 RAS# DDRA_SRAS# 8,14
DDRA_SW E# 119 120 D DRA_SCAS# Decoupling Reference Document:
8,14 DDRA_SW E# WE# CAS# DDRA_SCAS# 8,14
D DRA_SCS#0 121 122 D DRA_SCS#1
8,14 DDRA_SCS#0
123
S0# S1#
124
DDRA_SCS#1 8,14 Springdale Customer Schematic R1.2 page22
DU DU
125 VSS VSS 126 each Channel(two DIMMs) requirement 22uF*1 ; 0.1uF*14
D DRA_SDQ36 127 128 D DRA_SDQ32
D DRA_SDQ37 DQ32 DQ36 D DRA_SDQ33
129 DQ33 DQ37 130
B B
131 VDD VDD 132
DD RA_SDQS4 133 134 DDRA_SDM4
D DRA_SDQ34 DQS4 DM4 D DRA_SDQ38
135 DQ34 DQ38 136 Decoupling Reference Document:
137 138
D DRA_SDQ35 139
VSS VSS
140 D DRA_SDQ39 Springdale Chipset Platform Design guide Rev1.11
DQ35 DQ39
D DRA_SDQ44 141 DQ40 DQ44 142 D DRA_SDQ40 (12474)pag 271 each DIMM(two) requirement 0.1uF*42
143 VDD VDD 144
D DRA_SDQ41 145 146 D DRA_SDQ45
DD RA_SDQS5 DQ41 DQ45 DDRA_SDM5
147 DQS5 DM5 148
149 VSS VSS 150
D DRA_SDQ43 151 152 D DRA_SDQ42
D DRA_SDQ46 DQ42 DQ46 D DRA_SDQ47
153 DQ43 DQ47 154
155 VDD VDD 156
157 VDD CK1# 158 DDRA_CLK2# 8
159 VSS CK1 160 DDRA_CLK2 8
161 VSS VSS 162
D DRA_SDQ48 163 164 D DRA_SDQ49
D DRA_SDQ53 DQ48 DQ52 D DRA_SDQ52
165 DQ49 DQ53 166
167 VDD VDD 168
DD RA_SDQS6 169 170 DDRA_SDM6
D DRA_SDQ54 DQS6 DM6 D DRA_SDQ51
171 DQ50 DQ54 172
173 VSS VSS 174
D DRA_SDQ55 175 176 D DRA_SDQ50
D DRA_SDQ60 DQ51 DQ55 D DRA_SDQ56
177 DQ56 DQ60 178
179 VDD VDD 180
D DRA_SDQ61 181 182 D DRA_SDQ57
DD RA_SDQS7 DQ57 DQ61 DDRA_SDM7
183 DQS7 DM7 184
185 VSS VSS 186
A
D DRA_SDQ62 187 188 D DRA_SDQ63 A
D DRA_SDQ59 DQ58 DQ62 D DRA_SDQ58
189 DQ59 DQ63 190
191 VDD VDD 192
13,15,23 ICH_SMB_DATA 193 SDA SA0 194
13,15,23 ICH_SMB_CLK 195 SCL SA1 196
197 198
+3VS 199
VDD_SPD
VDD_ID
SA2
DU 200 SO-DIMM 0 Compal Electronics, Inc.
KEYLINK_5762-3-111
REVERSE Title
H = 5.2mm DDR-SODIMM SLOT1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2041
D ate: ¬P 期三, 七月 09, 2003 Sheet 12 of 56
5 4 3 2 1
 5 4 3 2 1

+2.5V +2.5V DDRB_VREF trace width of +2.5V

DDRB_SD Q[0..63]
12mils and space 12mils(min) 9,14 DDRB_SDQ[0..63]
JP24
1 2 DDRB _VREF DDRB_SD QS[0..7]
VREF VREF 9,14 DDRB_SDQS[0..7]

1
3 VSS VSS 4
DD RB_SDQ4 5 6 DD RB_SDQ2 2 R197 DDR B_SMA[0..12]
DD RB_SDQ0 DQ0 DQ4 DD RB_SDQ6 9,14 DDRB_SMA[0..12]
7 DQ1 DQ5 8
9 10 C300 75_0603_1% DDRB_S DM[0..7]
DD RB_SDQS0 VDD VDD DDRB_SDM0 0.1U_0402_16V4Z 9,14 DDRB_SDM[0..7]
11 12

2
DD RB_SDQ7 DQS0 DM0 DD RB_SDQ1 1
13 DQ2 DQ6 14
15 VSS VSS 16

1
D DD RB_SDQ5 17 18 DD RB_SDQ3 D
DD RB_SDQ9 DQ3 DQ7 D DRB_SDQ13 R196
19 DQ8 DQ12 20
21 VDD VDD 22
D DRB_SDQ12 23 24 D DRB_SDQ11 75_0603_1%
DD RB_SDQS1 DQ9 DQ13 DDRB_SDM1
25 26

2
DQS1 DM1
27 VSS VSS 28
D DRB_SDQ10 29 30 D DRB_SDQ15
D DRB_SDQ14 DQ10 DQ14 DD RB_SDQ8
31 DQ11 DQ15 32
33 VDD VDD 34
35 36
9 DDRB_CLK1
9 DDRB_CLK1# 37
CK0
CK0#
VDD
VSS 38 System Memory Decoupling caps
39 VSS VSS 40
+2.5V

D DRB_SDQ20 41 42 D DRB_SDQ19
D DRB_SDQ21 DQ16 DQ20 D DRB_SDQ16
43 DQ17 DQ21 44 1 1 1 1 1 1 1 1
45 46 C299 C270 C298 C269 C297 C267 C296 C266
DD RB_SDQS2 VDD VDD DDRB_SDM2
47 DQS2 DM2 48
D DRB_SDQ22 49 50 D DRB_SDQ18 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
DQ18 DQ22 2 2 2 2 2 2 2 2
51 VSS VSS 52
D DRB_SDQ17 53 54 D DRB_SDQ23
D DRB_SDQ24 DQ19 DQ23 D DRB_SDQ28
55 DQ24 DQ28 56
57 VDD VDD 58
D DRB_SDQ25 59 60 D DRB_SDQ29
DD RB_SDQS3 DQ25 DQ29 DDRB_SDM3
61 DQS3 DM3 62 Decoupling Reference Document:
63 64
D DRB_SDQ26 65
VSS VSS
66 D DRB_SDQ27 Springdale Customer Schematic R1.2 page26
DQ26 DQ30
D DRB_SDQ30 67 DQ27 DQ31 68 D DRB_SDQ31 each Channel(two DIMMs) requirement 0.1uF*24
69 VDD VDD 70
C R_LAD0 71 72 +2.5V C
R_LAD1 CB0 CB4
73 CB1 CB5 74
75 VSS VSS 76
R_LFRAME# 77 78 R _PCIRST# 1 1 1 1 1 1 1 1
R_LAD2 DQS8 DM8 C294 C292 C264 C263 C291 C262 C290 C261
79 CB2 CB6 80
81 VDD VDD 82
R_LAD3 83 84 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
CB3 CB7 2 2 2 2 2 2 2 2
85 DU DU/RESET# 86
87 VSS VSS 88
R_PCLK_80H 89 90
CK2 VSS
91 CK2# VDD 92
93 94 +2.5V
DD RB_CKE1 VDD VDD DD RB_CKE0
9,14 DDRB_CKE1 95 CKE1 CKE0 96 DDRB_CKE0 9,14
97 DU/A13 DU/BA2 98
DDRB_SMA12 99 100 DDRB_SMA11 1 1 1 1 1 1 1 1
DDRB_SMA9 A12 A11 DDRB_SMA8 C338 C313 C295 C265 C271 C309 C293 C268
101 A9 A8 102
103 VSS VSS 104
DDRB_SMA7 105 106 DDRB_SMA6 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
DDRB_SMA5 A7 A6 DDRB_SMA4 2 2 2 2 2 2 2 2
107 A5 A4 108
DDRB_SMA3 109 110 DDRB_SMA2
DDRB_SMA1 A3 A2 DDRB_SMA0
111 A1 A0 112
113 VDD VDD 114
DDRB_SMA10 115 116 DDRB_SBS1
A10/AP BA1 DDRB_SBS1 9,14
DDRB_SBS0 117 118 D DRB_SRAS#
9,14 DDRB_SBS0 BA0 RAS# DDRB_SRAS# 9,14
DDRB_SW E# 119 120 D DRB_SCAS#
9,14 DDRB_SW E# WE# CAS# DDRB_SCAS# 9,14
D DRB_SCS#0 121 122 D DRB_SCS#1 LAD2 1 8 R_LAD2
9,14 DDRB_SCS#0 S0# S1# DDRB_SCS#1 9,14 24,36,39 LPC_AD2
123 124 LAD3 2 7 R_LAD3
DU DU 24,36,39 LPC_AD3 PCLK_80H R_PCLK_80H
125 VSS VSS 126 15 CLK_80H 3 6
D DRB_SDQ33 127 128 D DRB_SDQ32 P CIRST# 4 5 R _PCIRST#
B D DRB_SDQ34 DQ32 DQ36 D DRB_SDQ36 10,23,26,27,29,30,36,39 PCIRST# B
129 DQ33 DQ37 130
131 132 RP147 @0_1206_8P4R_5%
DD RB_SDQS4 VDD VDD DDRB_SDM4
133 DQS4 DM4 134
D DRB_SDQ37 135 136 D DRB_SDQ39 LAD0 1 8 R_LAD0
DQ34 DQ38 24,36,39 LPC_AD0 LAD1 R_LAD1
137 VSS VSS 138 24,36,39 LPC_AD1 2 7
D DRB_SDQ38 139 140 D DRB_SDQ35 LFRAME# 3 6 R_LFRAME#
D DRB_SDQ40 DQ35 DQ39 D DRB_SDQ46 24,36,39 LPC_FRAME#
141 DQ40 DQ44 142 4 5
143 VDD VDD 144
D DRB_SDQ44 145 146 D DRB_SDQ45 RP148 @0_1206_8P4R_5%
DD RB_SDQS5 DQ41 DQ45 DDRB_SDM5
147 DQS5 DM5 148
149 VSS VSS 150
D DRB_SDQ43 151 152 D DRB_SDQ41
D DRB_SDQ42 DQ42 DQ46 D DRB_SDQ47 JP36
153 DQ43 DQ47 154
155 156 P CIRST# 1
VDD VDD 1
157 VDD CK1# 158 DDRB_CLK2# 9 2 2
159 160 LFRAME# 3
VSS CK1 DDRB_CLK2 9 3
161 162 LAD3 4
D DRB_SDQ52 VSS VSS D DRB_SDQ48 LAD2 4
163 DQ48 DQ52 164 5 5
D DRB_SDQ49 165 166 D DRB_SDQ53 LAD1 6
DQ49 DQ53 LAD0 6
167 VDD VDD 168 7 7
DD RB_SDQS6 169 170 DDRB_SDM6 8
D DRB_SDQ55 DQS6 DM6 D DRB_SDQ51 PCLK_80H 8
171 DQ50 DQ54 172 9 9
173 VSS VSS 174 +3VS 10 10
D DRB_SDQ50 175 176 D DRB_SDQ54
D DRB_SDQ60 DQ51 DQ55 D DRB_SDQ62 E&T_96212-1011S
177 DQ56 DQ60 178
179 VDD VDD 180
D DRB_SDQ56 181 182 D DRB_SDQ61
DD RB_SDQS7 183
DQ57
DQS7
DQ61
DM7 184 DDRB_SDM7 DEBUG PORT
A 185 VSS VSS 186 A
D DRB_SDQ58 187 188 D DRB_SDQ59
D DRB_SDQ57 DQ58 DQ62 D DRB_SDQ63
189 DQ59 DQ63 190
191 VDD VDD 192
12,15,23 ICH_SMB_DATA 193 SDA SA0 194
12,15,23 ICH_SMB_CLK 195 SCL SA1 196 +3VS
197 198
+3VS 199
VDD_SPD SA2
200
Compal Electronics, Inc.
VDD_ID DU SO-DIMM 2 REVERSE Title

KLINK_5746-3-111 DDR-SODIMM SLOT2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H= 9.2mm Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-2041
D ate: ¬P 期三, 七月 09, 2003 Sheet 13 of 56
5 4 3 2 1
 5 4 3 2 1

Channel A(DIMM0) Termination resistors & Decoupling caps Channel B(DIMM1) Termination resistors & Decoupling caps
+1.25VS +1.25VS
+1.25VS +1.25VS

RP77 RP121 RP80 RP92 RP45 RP37

DD RA_SDQ5 1 4 4 1 D DRA_SDQ28 1 4 D DRA_SCS#0 DD RB_SDQ2 1 4 4 1 DD RB_SDQS3 4 1 D DRB_SCS#0
DDRA_SCS#0 8,12 DDRB_SCS#0 9,13
DD RA_SDQ4 2 3 3 2 D DRA_SDQ19 2 3 D DRA_SCS#1 DD RB_SDQ6 2 3 3 2 D DRB_SDQ25 3 2 DDRB_SW E#
DDRA_SCS#1 8,12 DDRB_SW E# 9,13
56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5%
RP114 RP68 RP66 RP52 RP44 RP38
DD RA_SDQ1 1 4 4 1 D DRA_SDQ26 4 1 DDRA_SMA8 DD RB_SDQ0 1 4 4 1 D DRB_SDQ30 4 1 DDRB_SMA10
D DD RA_SDQ0 2 3 3 2 D DRA_SDQ31 3 2 DDRA_SMA6 DDRA_SD Q[0..63] DD RB_SDQ4 2 3 3 2 D DRB_SDQ26 3 2 DDRB_SBS0 D
8,12 DDRA_SDQ[0..63] DDRB_SBS0 9,13
56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% DDRA_SD QS[0..7] 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5%
8,12 DDRA_SDQS[0..7] DDRB_SD Q[0..63]
RP115 RP132 RP67 RP51 RP24 RP41
DD RA_SDQ6 1 DDR A_SMA[0..12] 9,13 DDRB_SDQ[0..63]
4 4 1 D DRA_SDQ53 4 1 DDRA_SMA12 8,12 DDRA_SMA[0..12]
DD RB_SDQ7 1 4 4 1 D DRB_SDQ62 4 1 DDRB_SMA12
DD RA_SDQS0 2 3 3 2 D DRA_SDQ48 3 2 DDRA_SMA11 DD RB_SDQS0 2 3 3 2 D DRB_SDQ59 3 2 DDRB_SMA9 DDRB_SD QS[0..7]
DDRA_S DM[0..7] 9,13 DDRB_SDQS[0..7]
56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 8,12 DDRA_SDM[0..7] 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% DDR B_SMA[0..12]
9,13 DDRB_SMA[0..12]
RP76 RP79 RP125 RP93 RP30 RP89
DDRA_SDM0 1 4 4 1 D DRA_SDQ57 4 1 DDRA_SMA3 DDRB_SDM0 1 4 4 1 D DRB_SDQ55 1 4 DDRB_SMA8 DDRB_S DM[0..7]
DD RA_SDQ7 9,13 DDRB_SDM[0..7]
2 3 3 2 DDRA_SDM7 3 2 DDRA_SMA5 DD RB_SDQ1 2 3 3 2 DD RB_SDQS6 2 3 DDRB_SMA11

56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5%

RP74 RP78 RP126 RP94 RP25 RP39
D DRA_SDQ13 1 4 4 1 D DRA_SDQ63 4 1 DDRA_SMA10 DD RB_SDQ3 1 4 4 1 D DRB_SDQ63 4 1 DDRB_SMA1
DDRA_SDM1 2 3 3 2 D DRA_SDQ58 3 2 DDRA_SMA1 D DRB_SDQ13 2 3 3 2 D DRB_SDQ61 3 2 DDRB_SMA3

56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5%

RP75 RP135 RP65 RP96 RP29 RP91
DD RA_SDQ3 1 4 4 1 DD RA_SDQS7 4 1 DDRA_SMA4 D DRB_SDQ15 1 4 4 1 D DRB_SDQ60 4 1 DDRB_SMA6
DD RA_SDQ9 2 3 3 2 D DRA_SDQ61 3 2 DDRA_SMA2 DD RB_SDQ8 2 3 3 2 D DRB_SDQ50 3 2 DDRB_SMA4

56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5%

RP73 RP133 RP124 RP50 RP43 RP40
D DRA_SDQ14 1 4 4 1 D DRA_SDQ54 4 1 DDRA_SMA7 DD RB_SDQ9 1 4 4 1 D DRB_SDQ14 4 1 DDRB_SMA5
D DRA_SDQ11 2 3 3 2 DD RA_SDQS6 3 2 DDRA_SMA9 DD RB_SDQ5 2 3 3 2 D DRB_SDQ10 3 2 DDRB_SMA7

56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5%

RP116 RP62 RP64 RP95 RP35 RP102
C D DRA_SDQ12 1 4 4 1 D DRA_SDQ32 4 1 DDRA_SMA0 D DRB_SDQ11 1 4 4 1 D DRB_SDQ37 4 1 DDRB_SMA2 C
DD RA_SDQ2 2 3 3 2 D DRA_SDQ33 3 2 DDRA_SBS1 DDRB_SDM1 2 3 3 2 DD RB_SDQS4 3 2 DDRB_SMA0
DDRA_SBS1 8,12
56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5%
RP117 RP61 RP63 RP49 RP104 RP42
DD RA_SDQS1 1 4 4 1 DDRA_SDM4 4 1 D DRA_SRAS# DD RB_SDQS1 1 4 4 1 DDRB_SDM4 4 1 DD RB_CKE1
DDRA_SRAS# 8,12 DDRB_CKE1 9,13
DD RA_SDQ8 2 3 3 2 D DRA_SDQ38 3 2 D DRA_SCAS# D DRB_SDQ12 2 3 3 2 D DRB_SDQ39 3 2 DD RB_CKE0
DDRA_SCAS# 8,12 DDRB_CKE0 9,13
56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5%
RP118 RP127 RP81 RP97 RP36 RP110
D DRA_SDQ15 1 4 4 1 D DRA_SDQ37 1 4 DD RA_CKE0 D DRB_SDQ19 1 4 4 1 D DRB_SDQ34 4 1 D DRB_SCAS#
DDRA_CKE0 8,12 DDRB_SCAS# 9,13
D DRA_SDQ10 2 3 3 2 D DRA_SDQ36 2 3 DD RA_CKE1 D DRB_SDQ16 2 3 3 2 D DRB_SDQ33 3 2 D DRB_SCS#1
DDRA_CKE1 8,12 DDRB_SCS#1 9,13
56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5%
RP119 RP128 RP137 RP48 RP105 RP90
D DRA_SDQ16 1 4 4 1 D DRA_SDQ34 1 4 DDRA_SBS0 D DRB_SDQ21 1 4 4 1 D DRB_SDQ35 1 4 D DRB_SRAS#
DDRA_SBS0 8,12 DDRB_SRAS# 9,13
D DRA_SDQ20 2 3 3 2 DD RA_SDQS4 2 3 DDRA_SW E# D DRB_SDQ20 2 3 3 2 D DRB_SDQ46 2 3 DDRB_SBS1
DDRA_SW E# 8,12 DDRB_SBS1 9,13
56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5%
RP72 RP59 RP100 RP106
D DRA_SDQ21 1 4 4 1 D DRA_SDQ45 +1.25VS D DRB_SDQ29 1 4 4 1 D DRB_SDQ45 +1.25VS
D DRA_SDQ17 2 3 3 2 DDRA_SDM5 DDRB_SDM3 2 3 3 2 DDRB_SDM5
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
56_0404_4P2R_5% 56_0404_4P2R_5% 1 1 1 1 1 1 56_0404_4P2R_5% 56_0404_4P2R_5% 1 1 1 1 1 1 1
RP120 RP60 C621 C630 C631 C629 C632 C633 RP47 RP108 C284 C283 C282 C281 C280 C279 C278
D DRA_SDQ18 1 4 4 1 D DRA_SDQ39 D DRB_SDQ22 1 4 4 1 D DRB_SDQ48
DD RA_SDQS2 2 3 3 2 D DRA_SDQ40 DD RB_SDQS2 2 3 3 2 D DRB_SDQ53
2 2 2 2 2 2 2 2 2 2 2 2 2
56_0404_4P2R_5% 56_0404_4P2R_5% 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 56_0404_4P2R_5% 56_0404_4P2R_5% 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
B +1.25VS +1.25VS B
RP71 RP58 RP46 RP34
DDRA_SDM2 1 4 4 1 D DRA_SDQ42 D DRB_SDQ24 1 4 4 1 D DRB_SDQ40
D DRA_SDQ22 2 3 3 2 D DRA_SDQ47 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K D DRB_SDQ17 2 3 3 2 D DRB_SDQ38 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
1 1 1 1 1 1 1 1 1 1 1 1 1
56_0404_4P2R_5% 56_0404_4P2R_5% C634 C622 C327 C564 C624 C625 56_0404_4P2R_5% 56_0404_4P2R_5% C277 C276 C275 C274 C273 C272 C562
RP70 RP129 RP99 RP107
D DRA_SDQ23 1 4 4 1 D DRA_SDQ44 D DRB_SDQ23 1 4 4 1 D DRB_SDQ41
D DRA_SDQ24 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 2 D DRA_SDQ35 D DRB_SDQ28 2 3 3 2 D DRB_SDQ47
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
56_0404_4P2R_5% 56_0404_4P2R_5% +1.25VS 56_0404_4P2R_5% 56_0404_4P2R_5% +1.25VS
RP69 RP57 RP98 RP33
D DRA_SDQ25 1 4 4 1 D DRA_SDQ49 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K DDRB_SDM2 1 4 4 1 DD RB_SDQS5 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
DDRA_SDM3 2 3 3 2 D DRA_SDQ52 1 1 1 1 1 1 D DRB_SDQ18 2 3 3 2 D DRB_SDQ44 1 1 1 1 1 1 1
C626 C627 C628 C316 C321 C328 C563 C623 C565 C566 C567 C568 C569
56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5%
RP130 RP122 RP109 RP103
DD RA_SDQS5 1 2 2 2 2 2 2 2 2 2 2 2 2 2
4 4 1 DD RA_SDQS3 DDRB_SDM6 1 4 4 1 D DRB_SDQ32
D DRA_SDQ41 2 3 3 2 D DRA_SDQ29 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K D DRB_SDQ51 2 3 3 2 D DRB_SDQ36 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
+1.25VS +1.25VS
56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5%
RP56 RP123 0.1U_0402_10V6K 0.1U_0402_10V6K 4.7U_0805_10V4Z RP32 RP101 4.7U_0805_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K
DDRA_SDM6 1 4 4 1 D DRA_SDQ27 1 1 1 1 1 1 D DRB_SDQ42 1 4 4 1 D DRB_SDQ27 1 1 1 1 1 1
D DRA_SDQ51 2 3 3 2 D DRA_SDQ30 C326 C329 C325 C324 C619 C618 D DRB_SDQ43 2 3 3 2 D DRB_SDQ31 C570 C572 C573 C571 C259 C258

56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5%

RP131 RP136 2 2 2 2 2 2 RP26 RP28 2 2 2 2 2 2
D DRA_SDQ46 1 4 4 1 D DRA_SDQ59 0.1U_0402_10V6K 0.1U_0402_10V6K 4.7U_0805_10V4Z DDRB_SDM7 1 4 4 1 DD RB_SDQS7 0.1U_0402_10V6K 4.7U_0805_10V4Z 0.1U_0402_10V6K
D DRA_SDQ43 2 3 3 2 D DRA_SDQ62 +1.25VS D DRB_SDQ54 2 3 3 2 D DRB_SDQ56
A Decoupling Reference Document: A
56_0404_4P2R_5% 56_0404_4P2R_5% 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 56_0404_4P2R_5% 56_0404_4P2R_5%
RP55 RP134 1 1 1 1 1 1 RP31 RP27 Springdale Customer Schematic R1.2 page26
D DRA_SDQ50 1 4 4 1 D DRA_SDQ60 C323 C322 C320 C318 C319 C317 D DRB_SDQ49 1 4 4 1 D DRB_SDQ57 each Channel(two DIMMs) requirement 4.7u*2 ; 0.1uF*26
D DRA_SDQ56 2 3 3 2 D DRA_SDQ55 D DRB_SDQ52 2 3 3 2 D DRB_SDQ58

56_0404_4P2R_5% 56_0404_4P2R_5% 2 2 2 2 2 2 56_0404_4P2R_5% 56_0404_4P2R_5%

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
Title
Decoupling Reference Document: DDR Termination Resistors
Springdale Customer Schematic R1.2 page22 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B 0.1
each Channel(two DIMMs) requirement 4.7u*2 ; 0.1uF*28 LA-2041
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: ¬P 期三, 七月 09, 2003 Sheet 14 of 56
5 4 3 2 1
 5 4 3 2 1

SEL0 SEL1 CPU 3V66[0..3] REF0 REF1 SRC USB/Dot Place near each pin
+3VS +3VS_CLK
0 0 100 66 14.3 14.3 100/200 48 W>40 mil
L29 Trace wide=40 mils
0 MID REF REF REF REF REF REF 1 2
BLM21A601SPT_0805
L28 1 1 1 1 1 1 1 1
D 0 1 200 66 14.3 14.3 100/200 48 1 2 C583 C582 C597 C596 C595 C594 C580 D
BLM21A601SPT_0805 C591
10U_1206_6.3V7K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2 2 2
1 0 133 66 14.3 14.3 100/200 48

1 1 166 66 14.3 14.3 100/200 48

1 MID Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

1 1
C581 C592

0.1U_0402_10V6K 4.7U_0805_10V4Z
2 2

24 CLK_ICH_14M 2 1
R450 33_0402_5%

10
16
24

34
36

42
48
3
2 1 U42
36 CLK_14M_SIO
R451 33_0402_5%

VDD_3V66

VDD_48
VDD_SRC

VDD_CPU
VDD_CPU
VDD_PCI
VDD_PCI
VDD_REF
C LKREF1 1
C LKREF0 REF_0
2 REF_1
C602 45
@10P_0402_50V8K VSS_CPU
2 1 CLK_XTAL_IN 4 XTAL_IN C LK_CPU2 C LK_HCLK
CPUCLKT2 47 1 2 CLK_HCLK 7
R428 33_0402_5%

1
X3 1 2
49.9_0603_1% R413
C C
C603 14.31818MHz_20P_1BX14318CC1A~L 1 2

2
@10P_0402_50V8K 49.9_0603_1% R414
2 1 CLK_XTAL_OUT 5 46 CLK_CPU2# 1 2 CLK_HCLK#
XTAL_OUT CPU_CLKC2 CLK_HCLK# 7
R429 33_0402_5%
44 C LK_CPU1 1 2 CLK_ITP
CPUCLKT1 CLK_ITP 5
Place crystal within R430 33_0402_5%
R462 2 1 @0_0402_5% SLP_S1# 1 2
24 PM_SLP_S1#
R425 2
500 mils of CK409
1 @0_0402_5% STPPCI# CLKSEL0 51 49.9_0603_1% R415
24 STP_PCI#
24,53 STP_CPU#
R424 2 1 @0_0402_5% STPCPU# CLKSEL1 56 SEL0
SEL1
CK409
1 2
49.9_0603_1% R416
43 CLK_CPU1# 1 2 CLK_ITP#
CPUCLKC1 CLK_ITP# 5
+3VS R463 1 2 1K_0402_5% SLP_S1# 21 R431 33_0402_5%
R412 1 PWRDWN#
2 1K_0402_5% STPPCI# 49 PCI_STP# CPUCLKT0 41 C LK_CPU0 1 2 CLK_BCLK
CLK_BCLK 4
R411 1 2 1K_0402_5% STPCPU# 50 R432 33_0402_5%
CPU_STP#
1 2
49.9_0603_1% R417
52 CK409_PW RGD#
CLK_VTT_PG# 35 VTT_PWRGD#
Place near CK409
1 2
+3VS 49.9_0603_1% R418
40 CLK_CPU0# 1 2 CLK_BCLK#
CPUCLKC0 CLK_BCLK# 4
CK_SCLK 28 R433 33_0402_5%
12,13,23 ICH_SMB_CLK SCLK
CK_SDATA 30 29
12,13,23 ICH_SMB_DATA SDATA 48/66MHZ_OUT/3V66_4
1

R421 R444 27 CLK66M_OUT3 1 2

66MHZ_OUT3/3V66_3 CLK_AGP_66M 16
R457 33_0402_5%
1K_0603_1% 1K_0603_1% 37 26
R187 2 SRCLKN_100MHZ 66MHZ_OUT2/3V66_2
1 @0_0402_5%
2

B CLK66M_OUT1 B
66MHZ_OUT1/3V66_1 23 1 2 CLK_MCH_66M 10
CLKSEL0 R186 2 1 0_0402_5% R456 33_0402_5%
CPU_CLKSEL0 5
22 CLK66M_OUT0 1 2
66MHZ_OUT0/3V66_0 CLK_ICH_66M 23
CLKSEL1 R188 2 1 0_0402_5% R455 33_0402_5%
CPU_CLKSEL1 5
38 9 PCICLK_F2 1 2
SRCLKP_100MHZ PCICLK_F2 CLK_PCI_ICH 23
1

R189 2 1 @0_0402_5% R452 33_0402_5%

R420 R443 8
2K_0603_1% PCICLK_F1
2K_0603_1% 2 1 CLK48M_OUT0 31 7
24 CLK_ICH_48M USB_48MHZ PCICLK_F0
R438 33_0402_5%
2

MCH_CLKSEL0 7
MCH_CLKSEL1 7 32 DOT_48MHZ
20 PCICLK6 1 2
PCICLK6 CLK_PCI_MINI 29
1

R461 33_0402_5%
R185 R190 19 PCICLK5 1 2
PCICLK5 CLK_PCI_PCM 27
2.49K_0603_1% 1 2 52 R460 33_0402_5%
2.49K_0603_1% Check SPEC (250mA,300 ohm) R437 475_0603_1% IREF PCICLK4
PCICLK4 18 1 2 CLK_PCI_LPC 39
R454 33_0402_5%
2

L27 15 PCICLK3 1 2
PCICLK3 CLK_PCI_1394 30
BLM11A601S_0603 R459 33_0402_5%
1 2 CLK_VDD_PLL 55 14 PCICLK2 1 2
+3VS VDD_PLL PCICLK2 CLK_PCI_LAN 26
R458 33_0402_5%
1 1 13 PCICLK1 1 2
PCICLK1 CLK_PCI_SIO 36
C578 C579 R453 33_0402_5%
VSS_3V66

VSS_IREF

PCICLK0
VSS_SRC
VSS_REF

12 1 2
VSS_PCI
VSS_PCI

PCICLK0 CLK_80H 13
VSS_48

10U_1206_6.3V7K 0.1U_0402_16V4Z 54 R708 33_0402_5%

2 2 VSS_PLL

A A
ICS952623BG_TSSOP56
6
11
17
25
33

39
53

Compal Electronics, Inc.

Title
Clock Generator
Size Document Number R ev
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL 0.1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D LA-2041
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D ate: ¬P 期三, 七月 09, 2003 Sheet 15 of 56
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS U35A

AGP_AD0 AJ28 G5 VGA_GPIO0 2 1 SPREAD_RATE DV ODE 1 2
Place close AGP_AD1 AK28
AD0
AD1 nVIDIA GPIO0
GPIO1 F4 R132 0_0402_5% R691 @10K_0402_5%

1
AGP_AD2 AH27 G4 ENBKL ONLY FOR NV18M
to pin AD2 GPIO2 ENBKL 22,39
R128 R124 AGP_AD3 AK27 H5 ENVDD ENBKL 1 2
H2 & H3 AD3 GPIO3 ENVDD 22
2.2K_0402_5% @2.2K_0402_5%
AGP_AD4
AGP_AD5
AGP_AD6
AJ27
AH26
AJ26
AD4
AD5
NV31/34 GPIO4
GPIO5
H4
J4
J5
VGA_GPIO5
VAG_GPIO6
R374 2
R129 2
1 @0_0402_5%
1 10K_0402_5% (SUS_STAT#) +3VS POW ER_SEL 1
R682 10K_0402_5%

2
@2200P_0402_50V7K +3VS AGP_AD7 AD6 GPIO6 POW ER_SEL_F R701 2
AH25 AD7 GPIO7 J6 1 0_0402_5% POW ER_SEL 51
R683 @10K_0402_5%
1 AGP_AD8 AH23 K4 NV_THERCTL#
C145 U33 AGP_AD9 AD8 GPIO8 Only for R133 2
AJ23 AD9 GPIO9 K6 1 @10K_0402_5% +3VS
NV_THERMDA 2 1 AGP_AD10 AH22 NV34MU, NV31
D+ VDD1 AGP_AD11 AD10 Power Mizer
AJ22 M2

ZV PORT / EXT TMDS / GPIO / ROM

2 1 AD11 FPBCLKOUT#
D NV_THERMDC 3 6 NV_THERCTL# C148 AGP_AD12 AJ21 M3 D
D- ALERT# AGP_AD13 AD12 FPBCLKOUT +3VS
I2CC _SCL AGP_AD14
AK21 AD13 ROMA14
1 PCI_AD_SWAP: 0-RVSERSED 1-NORMAL
8 SCLK THERM# 4 AH20 AD14 ROMA14 R2
2 AGP_AD15 ROMA15 STRAP0 R377 2
AJ20 AD15 ROMA15 R1 1 10K_0402_5%
I2CC _SDA 7 5 AGP_AD16 AG26 AF2
SDATA GND AGP_AD17
AGP_AD18
AE24
AG25
AD16
AD17 PCI/AGP ROMCS#
L4
2 SUB_VENDOR: 0-SYSTEM BIOS 1-ADAPTER BIOS
@0.1U_0402_16V4Z AGP_AD19 AD18 VIPPCLK V IPHCTL R376 2
@ADM1032ARM_RM8 AG24 AD19 VIPHCTL M4 1 10K_0402_5% STRAP1
AGP_AD20 AF24 M5
AGP_AD21 AD20 VIPHCLK
AG P_AD[0..31] AGP_AD22
AG23 AD21 3 RAM_CFG[3:0]
10 AGP_AD[0..31] AE22 AD22 VIPHAD0 P3
AGP_AD23 AF22 P2 (1101 = 4Mx32 DDR,0000 =8Mx32 DDR Samsung, 0001 =8Mx32 DDR Hynix, DQS per byte)
AGP_AD24 AD23 VIPHAD1
AE21 AD24
AGP_SBA[0..7] AGP_AD25 AG20 J3 Low R378 2 1 @10K_0402_5% STRAP2 R379 2 1 @10K_0402_5%
10 AGP_SBA[0..7] AD25 VIPD0
AGP_AD26 AG19 J2 0 NV18M
AGP_AD27 AD26 VIPD1 VIPD2 R334 2
AF19 AD27 VIPD2 K2 1 @10K_0402_5% D VOD2 R335 2 1 10K_0402_5%
AGP _C/BE#[0..3] AGP_AD28 AE19 K1 VIPD3 NV31M:NV34M
10 AGP_C/BE#[0..3] AD28 VIPD3
AGP_AD29 AF18 L3 VIPD4
AGP_AD30 AD29 VIPD4 VIPD5
AG18 AD30 VIPD5 L2 4
AGP_ST[0..2] AGP_AD31 AE18 N2 VIPD6 R380 2 1 @10K_0402_5% STRAP3 R381 2 1 @10K_0402_5%
10 AGP_ST[0..2] AD31 VIPD6
N1 VIPD7 1 NV18M
C16 R68 AGP_C/BE#0 VIPD7 R329 2
AJ24 C/BE#0 1 10K_0402_5% D VOD3 R330 2 1 @10K_0402_5%
1 2 1 2 AGP_C/BE#1 AH19 AG2 NV31M:NV34M
AGP_C/BE#2 C/BE#1 DVOD0
AF25 C/BE#2 DVOD1 AH1 5
+3VS @10P_0402_50V8K @10_0402_5% AGP_C/BE#3 AG22 AG3 D VOD2 2 R49 2 1 @10K_0402_5% DACA_VSYNC R29 2 1 10K_0402_5%
C/BE#3 DVOD2 D VOD3
DVOD3 AJ1
R35 CLK_AGP_66M AG12 AH2 3 R50 2 1 @10K_0402_5% D ACA_HSYNC R30 2 1 10K_0402_5%
15 CLK_AGP_66M PCICLK DVOD4 High
10K_0402_5% B_PCIRST# AF15 AK1
23,35 B_PCIRST# PCIRST# DVOD5
1 2 STP_AGP# AGP_REQ# AF13 AJ3 CRYSTAL: (10)-27MHz
C 1 2 AG P_BUSY#
10 AGP_REQ#
AGP_GNT# AE15
PCIREQ# DVOD6
AK3
6 C
10 AGP_GNT# PCIGNT# DVOD7 Low
R36 10K_0402_5% AGP_PAR AK18 AH4 D VOD8 0 R373 2 1 10K_0402_5% VIPD2
10 AGP_PAR PCIPAR DVOD8
AGP_STOP# AH17 AK4 D VOD9
10 AGP_STOP# PCISTOP# DVOD9 High
AGP_DEVSEL# AJ16 AJ4 1 VIPD6 R357 2 1 10K_0402_5%
10 AGP_DEVSEL# AG P_TRDY# PCIDEVSEL# DVOD10
10 AGP_TRDY# AJ17 PCITRDY# DVOD11 AH5
AGP_IRDY# AG16 TVMODE: (01)-NTSC
+SVDD +3VS 10 AGP_IRDY#
AGP_FRAME# AK16
PCIIRDY#
AD5 D VO_HSYNC
7
L10 10 AGP_FRAME# PCIFRAME# DVOHSYNC Low
PCI_ PIRQA# AG15 AD6 0 DACB_VSYNC R340 2 1 10K_0402_5%
23,27,30 PCI_PIRQA# PCIINTA# DVOVSYNC
0.1U_0402_10V6K 4.7U_0805_10V4Z 1 2 AE10 AE4 DV ODE
FCM2012C-800_0805 NC DVODE +3VS R339 2
AJ2 1 1 10K_0402_5% D ACB_HSYNC
10 AGP_WBF#
AGP_WBF# AG17 AGP4X/8X
AGPWBF#
DVOCLKOUT
DVOCLKOUT# AK2 High
1

C479 C30 C31 C478 AGP_RBF# AG14 AG6 I2CC _SCL 2 1 AGP8X/4X: (0)-8X / (1)-4X
10 AGP_RBF#
AJ18
AGPRBF# I2CC_SCL
AG7 I2CC _SDA R693 2 12.2K_0402_5%
8
10 AGP_DBIHI AGPPIPE/ DBI_HI I2CC_SDA
0.1U_0402_10V6K AJ19 B1 R694 2.2K_0402_5% R48 2 1 10K_0402_5% D VOD9
10 AGP_DBILO
2

NC/ DBI_LO BUFRST#

DVOCLKIN AG1
4.7U_0805_10V4Z AGP_SB_STBF AK13 AGP_SIDEBAND: (0)-ENABLE
10 AGP_SB_STBF
AGP_SB_STBS AJ13
AGPSB_STB/ ADSTBF
G1 STRAP0
9
10 AGP_SB_STBS AGPSB_STB#/ ADSTBS STRAP0
AGP_AD_STBF0 AK24 G2 STRAP1 R360 2 1 10K_0402_5% VIPD7 R361 2 1 @10K_0402_5%
10 AGP_AD_STBF0 AGPADSTB0/ ADSTBF0 STRAP1
AGP_AD_STBS0 AJ25 F2 STRAP2
10 AGP_AD_STBS0 AGPADSTB0#/ADSTBS0 STRAP2
AGP_AD_STBS0 AGP_AD_STBF1 STRAP3
1
R67
2
220K_0402_5%
10 AGP_AD_STBF1
AGP_AD_STBS1
AG21
AF21
AGPADSTB1/ ADSTBF1 STRAP3 F3 10 AGP_FASTWRITE: (0)-ENABLE
10 AGP_AD_STBS1 AGPADSTB1#/ADSTBS1
1 2 AGP_AD_STBS1 T4 TXOUT0- R319 2 1 10K_0402_5% D VOD8 R320 2 1 @10K_0402_5%
IFPATXDO# TXOUT0- 22
R69 220K_0402_5% AGP_SBA0 AJ11 U4 TXOUT0+
AGPSBA0 IFPATXDO TXOUT0+ 22
AGP_SBA1 TXOUT1-
AGP_SBA2
AH11
AJ12
AGPSBA1 IFPATXD1# AA1
Y2 TXOUT1+
TXOUT1- 22 11 PCI_DEVID[3:0] (0100 NV34M 0101 NV34MU 1010 NV31M)
AGPSBA2 IFPATXD1 TXOUT1+ 22 Low
AGP_SBA3 AH12 W3 TXOUT2- 0 R366 2 1 @10K_0402_5% VIPD4 R367 2 1 10K_0402_5%
AGPSBA3 IFPATXD2# TXOUT2- 22
AGP_SBA4 AJ14 V3 TXOUT2+
AGPSBA4 IFPATXD2 TXOUT2+ 22
Selection Table For W180 AGP_SBA5 AH14 V4 TXOUT3- 1 R363 2 1 10K_0402_5% VIPD5 R364 2 1 @10K_0402_5%
AGPSBA5 IFPATXD3# TXOUT3- 22
AGP_SBA6 AJ15 U5 TXOUT3+
B AGPSBA6 IFPATXD3 TXOUT3+ 22 B
AGP_SBA7 AH15 V1 TXCLK- 2 R370 2 1 @10K_0402_5% VIPD3 R371 2 1 10K_0402_5%
AGPSBA7 IFPATXC# TXCLK- 22
Modulation AGP_ST0 AG13 W2 TXCLK+
SST

LVDS
AGPST0 IFPATXC TXCLK+ 22 High
Setting Close VGA ball (AK29) AGP_ST1 AE16 AGPST1 IFPBTXD4# V5 TZOUT0-
TZOUT0- 22 3 R346 2 1 10K_0402_5% D VO_HSYNC R347 2 1 @10K_0402_5%
Ratio less than 250mils AGP_ST2 AE13 AGPST2 IFPBTXD4 W4 TZOUT0+
TZOUT1-
TZOUT0+ 22
SS% +AGP_REF AK29
IFPBTXD5# AB2
AB3 TZOUT1+
TZOUT1- 22 12 BUS_TYPE: (1)-AGP V IPHCTL R126 2 1 10K_0402_5%
+AGP_VREF AGPVREF IFPBTXD5 TZOUT1+ 22
0 1.25% R42 2 1 10K_0402_5% AF16 W6 TZOUT2-
NC/AGPMBDET# IFPBTXD6# TZOUT2- 22
1 AG P_BUSY# AF12 Y6 TZOUT2+
AGP_BUSY# IFPBTXD6 TZOUT2+ 22
1 3.75% C13 STP_AGP# AG11 AC2 TZOUT3- ROM TYPE: (00)-PARALLEL
STP_AGP# IFPBTXD7# TZOUT3- 22
0.1U_0402_10V6K AC3 TZOUT3+
IFPBTXD7 TZOUT3+ 22 Low
CRMA AE2 Y3 TZCLK- 0 R354 2 1 10K_0402_5% ROMA14 R355 2 1 @10K_0402_5%
2 22 CRMA DACB_RED/CHROMA IFPBTXC# TZCLK- 22
LUMA AD2 AA2 TZCLK+
22 LUMA DACB_GREEN/LUMA IFPBTXC TZCLK+ 22 High
COMPS AD1 1 R351 2 1 10K_0402_5% ROMA15 R352 2 1 @10K_0402_5%
22 COMPS D ACB_HSYNC DACB_BLUE/COMPOSITE R
AF3 DACB_HSYNC DACA_RED AK10 R 22
DACB_VSYNC AE3 AJ10 G
DACB_VSYNC DACA_GREEN G 22
1 2 DACB_RSET AD3 AJ9 B
DACB_RSET DACA_BLUE B 22
+SVDD R70 63.4_0603_1% AE7 AH9 D ACA_HSYNC
DAC2

I2CB_SCL DACA_HSYNC D ACA_HSYNC 22

PLACE COLSE TO VGA AF6 AJ8 DACA_VSYNC
DAC1

I2CB_SDA DACA_VSYNC DACA_VSYNC 22

2 1 AD4 Y2
Pin AJ5, AJ7, +3VS SWAPRDY_B
6

U31 R343 10K_0402_5% Y5 AG8 DACA_RSET 1 2 XTALIN 1 2 XTALOUT

STEREO DACA_RSET R39 130_0603_1%
SWAPRDY_B AC4
VDD

DACB_IDUMP DDC_ CLK 27MHZ_16PF

NV31,NV34 use. I2CA_SCL AG5 DDC_CLK 22
XTALIN AJ6 AF7 D DC_DATA 1 2
NV18 not use. XTALIN I2CA_SDA DDC_DATA 22
XTALOUTBUFF 1 5 1 2 XTALSSIN XTALOUT AH6 AF9 2 1 +3VS R311 @2M_0402_5%
+3VS R318 X1/CLK CLKOUT R323 22_0402_5% XTALOUT SWAPRDY_A R41 10K_0402_5%
DACA_IDUMP AG10 1 1
1K_0402_5% XTALSSIN AJ7 C468 C469
XTALOUTBUFF XTALSSIN
1 2 7 FS1 X2 2 AJ5 XTALOUTBUFF IFPCTXD0# T2 SWAPRDY_A
NV_THERMDA H2 R3 NV31,NV34 use. 22P_0402_50V8J 22P_0402_50V8J
THERMDA IFPCTXD0 2 2
1 2 8 4SPREAD_RATE 1 2 NV_THERMDC H3 T3
CLK

A FS2 SS% +SVDD THERMDC IFPCTXD1# NV18 not use. A

R317 R341 C2 U2
TMDS
GND

JTAG[0] IFPCTXD1
2

1K_0402_5% @1K_0402_5% C1 V2
JTAG[1] IFPCTXD2#
SSC

R345 D1 U3
W180-01GT_SO8 JTAG[2] IFPCTXD2
E2 P4
3

10K_0402_5% JTAG[3] IFPCTXC#

D2 JTAG[4] IFPCTXC P5
Compal Electronics, Inc.
1

NV34M_EPBGA701
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND nVIDIA NV31M (AGP BUS)
PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE 0.1
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-2041
D ate: ¬P 期四, 七月 10, 2003 Sheet 16 of 56
5 4 3 2 1
 5 4 3 2 1

R_NDQ MA[0..7] R_NDQ MB[0..7]

20 R_NDQMA[0..7] 21 R_NDQMB[0..7]
R_NDQS A[0..7] R_NDQS B[0..7]
20 R_NDQSA[0..7] 21 R_NDQSB[0..7]
NM AA[0..11] NM AB[0..11]
20 NMAA[0..11] 21 NMAB[0..11]
D D
R_NM DA[0..63] R_NM DB[0..63]
20 R_NMDA[0..63] 21 R_NMDB[0..63]
U35C
U35B
R_NMDB0 F13 A18 NMAB0
R_NMDA0 NMAA0 R_NMDB1 FBCD0 FBCA0 NMAB1
N25 FBAD0 FBAA0 V30 D13 FBCD1 FBCA1 C17
R_NMDA1 N27 U28 NMAA1 R_NMDB2 E13 B17 NMAB2
R_NMDA2 FBAD1 FBAA1 NMAA2 R_NMDB3 FBCD2 FBCA2 NMAB3
N26 FBAD2 FBAA2 U29 F12 FBCD3 FBCA3 C16
R_NMDA3 M25 T28 NMAA3 R_NMDB4 E10 B16 NMAB4
R_NMDA4 FBAD3 FBAA3 NMAA4 R_NMDB5 FBCD4 FBCA4 NMAB5
K26 FBAD4 FBAA4 T29 D10 FBCD5 FBCA5 D16
R_NMDA5 K27 T27 NMAA5 R_NMDB6 D9 A16 NMAB6
R_NMDA6 FBAD5 FBAA5 NMAA6 R_NMDB7 FBCD6 FBCA6 NMAB7
J27 FBAD6 FBAA6 T30 D8 FBCD7 FBCA7 E16
R_NMDA7 H27 T26 NMAA7 R_NMDB8 B13 F16 NMAB8
R_NMDA8 FBAD7 FBAA7 NMAA8 R_NMDB9 FBCD8 FBCA8 NMAB9
N29 FBAD8 FBAA8 T25 B12 FBCD9 FBCA9 D15
R_NMDA9 M29 R27 NMAA9 R_NMDB10 C12 F15 NMAB10
R_NMDA10 FBAD9 FBAA9 NMAA10 R_NMDB11 FBCD10 FBCA10 NMAB11
M28 FBAD10 FBAA10 R25 B11 FBCD11 FBCA11 A15
R_NMDA11 L29 R30 NMAA11 R_NMDB12 B9 G17
R_NMDA12 FBAD11 FBAA11 R_NMDB13 FBCD12 FBCA12
J29 FBAD12 FBAA12 U24 C9 FBCD13
R_NMDA13 J28 R_NMDB14 B8
R_NMDA14 FBAD13 R_NMDB15 FBCD14 R_NDQMB0
H29 FBAD14 A7 FBCD15 FBCDQM0 D11
R_NMDA15 G30 R_NMDB16 F10 B10 R_NDQMB1
R_NMDA16 FBAD15 R_NMDB17 FBCD16 FBCDQM1 R_NDQMB2
K25 FBAD16 E9 FBCD17 FBCDQM2 D7
R_NMDA17 J26 L27 R_NDQMA0 R_NMDB18 F9 C5 R_NDQMB3
R_NMDA18 FBAD17 FBADQM0 R_NDQMA1 R_NMDB19 FBCD18 FBCDQM3 R_NDQMB4
J25 FBAD18 FBADQM1 K29 F7 FBCD19 FBCDQM4 C26
R_NMDA19 G26 G25 R_NDQMA2 R_NMDB20 C6 F24 R_NDQMB5
R_NMDA20 FBAD19 FBADQM2 R_NDQMA3 R_NMDB21 FBCD20 FBCDQM5 R_NDQMB6
F28 E28 E6 B21

MEMORY INTERFACE B
R_NMDA21 FBAD20 FBADQM3 R_NDQMA4 R_NMDB22 FBCD21 FBCDQM6 R_NDQMB7
F26 FBAD21 FBADQM4 AF28 D5 FBCD22 FBCDQM7 D20
R_NMDA22 E27
MEMORY INTERFACE AD27 R_NDQMA5 R_NMDB23 C4
C R_NMDA23 FBAD22 FBADQM5 R_NDQMA6 R_NMDB24 FBCD23 C
D27 FBAD23 FBADQM6 AA30 C8 FBCD24
R_NMDA24 H28 Y27 R_NDQMA7 R_NMDB25 B7 D12 R _NDQSB0
R_NMDA25 FBAD24 FBADQM7 R_NMDB26 FBCD25 FBCDQS0 R _NDQSB1
G29 FBAD25 B6 FBCD26 FBCDQS1 A10
R_NMDA26 F29 R_NMDB27 B5 E7 R _NDQSB2
R_NMDA27 FBAD26 R _NDQSA0 R_NMDB28 FBCD27 FBCDQS2 R _NDQSB3
E29 FBAD27 FBADQS0 M27 A3 FBCD28 FBCDQS3 A4
R_NMDA28 C30 K30 R _NDQSA1 R_NMDB29 B3 A27 R _NDQSB4
R_NMDA29 FBAD28 FBADQS1 R _NDQSA2 R_NMDB30 FBCD29 FBCDQS4 R _NDQSB5
C29 FBAD29 FBADQS2 G27 A2 FBCD30 FBCDQS5 D24
R_NMDA30 B30 D30 R _NDQSA3 R_NMDB31 B2 A21 R _NDQSB6
R_NMDA31 FBAD30 FBADQS3 R _NDQSA4 R_NMDB32 FBCD31 FBCDQS6 R _NDQSB7
A30 FBAD31 FBADQS4 AG30 B29 FBCD32 FBCDQS7 D19
R_NMDA32 AJ29 AD26 R _NDQSA5 R_NMDB33 A29
R_NMDA33 FBAD32 FBADQS5 R _NDQSA6 R_NMDB34 FBCD33
AJ30 FBAD33 FBADQS6 AA29 B28 FBCD34
R_NMDA34 AH29 W27 R _NDQSA7 R_NMDB35 A28
R_NMDA35 FBAD34 FBADQS7 R_NMDB36 FBCD35 NMRASB#
AH30 FBAD35 B26 FBCD36 FBCRAS# C14 NMRASB# 21
R_NMDA36 AF29 R_NMDB37 B25
R_NMDA37 FBAD36 NMRASA# R_NMDB38 FBCD37 NMCASB#
AE29 FBAD37 FBARAS# P28 NMRASA# 20 B24 FBCD38 FBCCAS# B14 NMCASB# 21
A

R_NMDA38 AD29 R_NMDB39 C23

R_NMDA39 FBAD38 NMCASA# R_NMDB40 FBCD39 NMWEB#
AC28 FBAD39 FBACAS# P29 NMCASA# 20 E26 FBCD40 FBCWE# C15 NMWEB# 21
R_NMDA40 AG28 R_NMDB41 D26
R_NMDA41 FBAD40 NMWEA# R_NMDB42 FBCD41 NMCSB0#
AF27 FBAD41 FBAWE# R28 NMWEA# 20 E25 FBCD42 FBCCS0# D17 NMCSB0# 21
R_NMDA42 AE26 R_NMDB43 C25
R_NMDA43 FBAD42 NMCSA0# R_NMDB44 FBCD43 NMCSB1#
AE28 FBAD43 FBACS0# U27 NMCSA0# 20 E24 FBCD44 FBCCS1# D14 NMCSB1# 21 NMCLKB0 21

1
R_NMDA44 AD25 R_NMDB45 F22
R_NMDA45 FBAD44 NMCSA1# R_NMDB46 FBCD45 NMCKEB R111
AB25 FBAD45 FBACS1# P27 NMCSA1# 20 NMCLKA0 20 E22 FBCD46 FBCCKE A13 NMCKEB 21

1
R_NMDA46 AB26 R_NMDB47 F21 @120_0402_5%
R_NMDA47 FBAD46 NMCKEA R89 R_NMDB48 FBCD47 NMCLKB0
AA25 FBAD47 FBACKE N30 NMCKEA 20 A24 FBCD48 FBCCLK0 K18
R_NMDA48 AD30 @120_0402_5% R_NMDB49 B23 K17 NMCLKB0#
NMCLKB0# 21

2
R_NMDA49 FBAD48 NMCLKA0 R_NMDB50 FBCD49 FBCCLK0#
AC29 FBAD49 FBACLK0 U21 C22 FBCD50
R_NMDA50 AB28 V21 NMCLKA0# R_NMDB51 B22
NMCLKA0# 20

2
R_NMDA51 FBAD50 FBACLK0# R_NMDB52 FBCD51 NMCLKB1
AB29 FBAD51 B20 FBCD52 FBCCLK1 K13 NMCLKB1 21

1
B R_NMDA52 NMCLKA1 R_NMDB53 NMCLKB1# B
Y29 FBAD52 FBACLK1 N21 NMCLKA1 20 C19 FBCD53 FBCCLK1# K14

1
R_NMDA53 W28 P21 NMCLKA1# R_NMDB54 B19 R110
R_NMDA54 FBAD53 FBACLK1# R105 R_NMDB55 FBCD54 @120_0402_5%
W29 FBAD54 B18 FBCD55
R_NMDA55 V29 @120_0402_5% R_NMDB56 D23
R_NMDA56 FBAD55 R_NMDB57 FBCD56 NMB_BA0
AC27 D22 E15 NMB_BA0 21 NMCLKB1# 21

2
R_NMDA57 FBAD56 NMA_BA0 R_NMDB58 FBCD57 FBCBA0 NMB_BA1
AB27 FBAD57 FBABA0 R26 NMA_BA0 20 2 NMCLKA1# 20 D21 FBCD58 FBCBA1 B15 NMB_BA1 21
R_NMDA58 AA27 R29 NMA_BA1 R_NMDB59 E21
FBAD58 FBABA1 NMA_BA1 20 +2.5VS FBCD59
R_NMDA59 AA26 R_NMDB60 F19
R_NMDA60 FBAD59 R_NMDB61 FBCD60
W25 FBAD60 E18 FBCD61
R_NMDA61 V26 C28 A _REF R_NMDB62 D18
FBAD61 FB_VREF FBCD62
1

R_NMDA62 V27 (10 mil) R_NMDB63 F18

R_NMDA63 FBAD62 R138 FBCD63
V25 FBAD63
1K_0603_1% NV34M_EPBGA701
NV34M_EPBGA701
2
1

1
C173 R135

0.1U_0402_10V6K 1K_0603_1%
2
2

1 2 NMCKEA
R358 1K_0402_5%

1 2 NMCKEB
A
R389 1K_0402_5% A

Title
Compal Electronics, Inc.
nVIDIA NV31M (DDR)
Size Document Number R ev
LA-2041 0.1

D ate: ¬P 期三, 七月 09, 2003 Sheet 17 of 56

5 4 3 2 1
 5 4 3 2 1

U35D
C44 0.1U_0402_10V6K +1.5VS +5VS
+1.5VS AD11 AA4 IFABVPROBE 1 2
AGPVDDQ IFPABVPROBE IFPABREST
AD14 AGPVDDQ IFPABRSET V6 1 2
AD17 R109 1K_0402_5%
AGPVDDQ +IFPABPLLVDD
AD20 AGPVDDQ IFPABPLLVDD U10 1 1 1 1 1 1 1
AD23 V10 C61 C36 C40 C39 C49 C41 C110
AGPVDDQ IFPABPLLGND
D AE11 AGPVDDQ D
AE14 T5 +IFP ABIOVDD 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.022U_0402_16V7K 0.022U_0402_16V7K 0.022U_0402_16V7K 0.1U_0402_10V6K 0.1U_0402_10V6K
AGPVDDQ IFPAIOVDD 2 2 2 2 2 2 2
AE17 AGPVDDQ IFPAIOGND T6
AE20 AGPVDDQ
AE23 AGPVDDQ IFPBIOVDD Y4
IFPBIOGND W5
C55 0.1U_0402_10V6K
+VGA_CORE L11 AA3 IFP CVPROBE 1 2
VDD IFPCVPROBE
L13 VDD IFPCRSET R4 1 2
L14 R112 1K_0402_5%
VDD +IF PCPLLVDD
L17 VDD IFPCPLLVDD P10 1 2
L18 N10 R107 10K_0402_5%
VDD IFPCPLLGND
L20 VDD
1 2AGP_VDD1 N6 VDD IFPCIOVDD R5 +IFPCIO VDD 1 2 +3VS
R108 0_0402_5% N11 R6 R114 10K_0402_5% L11
VDD IFPCIOGND +DA CA/BVDD
N20 VDD 1 2
P11 1 1 1 KC FBM-L11-201209-221LMAT_0805
VDD C53 C65 C24
P20 VDD
U11 L6 +VIP/DVOVDDQ
VDD VIPVDDQ 4.7U_0805_10V4Z 4700P_0402_25V7K 470P_0402_50V8J
U20 VDD VIPVDDQ L7
NV31 use only. 2 2 2
V11 VDD VIPVDDQ M7
V20 VDD NV18,NV34 not use.
Y11 VDD
Y13 P6 VIPCAL_1 R120 2 1 @49.9_0603_1%
VDD VIPCAL_PD_VDDQ VIPCAL_2 R125 1 @49.9_0603_1%
Y14 VDD VIPCAL_PU_GND P7 2
Y17 VDD
Y18 +3VS
VDD L20
Y20 VDD
AA17 AD8 +PLLVDD 1 2
VDD DVOVDDQ
C AA18 VDD DVOVDDQ AD9 1 C472 1 1 KC FBM-L11-201209-221LMAT_0805 C
AE8 C474 C15
DVOVDDQ
NV31 use only.
+3VS G14 NV18,NV34 not use. +VIP/DVOVDDQ 4.7U_0805_10V4Z 4700P_0402_25V7K 470P_0402_50V8J
VDD33 2 2 2
H6 VDD33

1
H7 VDD33
1 2AGP_VDD2 M6 VDD33 DVOCAL_PD_VDDQ AB6 DVOCAL_1 R349 1 2 @49.9_0603_1% R76
R113 0_0402_5% P24 AB7 DVOCAL_2 R348 1 2 @49.9_0603_1%
VDD33 DVOCAL_PU_GND 1K_0603_1%
U6 VDD33 DVO_VREF AF4
I/O POWER

U7

2
VDD33 +DVO_VREF +3VS
AC6 VDD33
AC7 L13
VDD33

1
AD12 AE5 R342 1 2 10K_0402_5% 1 +IFPABPLLVDD 2 1
VDD33 TESTMODE C23 R71 KC FBM-L11-201209-221LMAT_0805
AD15 VDD33 TESTMECLK G24 1 1
AD19 R117 1 2 10K_0402_5% C87 C88
VDD33 0.1U_0402_10V6K 1K_0603_1%
AD22 VDD33
TESTMECLK
2 470P_0402_50V8J 4700P_0402_25V7K
AD16 NV31,NV34 use.

2
VDD33 2 2
+DA CA/BVDD NV18 not use.
DACB_VDD AB4
+1.5VS N4 AB5 DAC AVREF
+5VS VD50CLAMP0 DACB_VREF
R40 49.9_0603_1% AE9 1
AGPCALPD_VDDQ AA13 VD50CLAMP1 DAC BVREF C67
1 2 AGPCALPD_VDDQ
1 2 AGPCALPU_GND AA14 AG9 1
R82 49.9_0603_1% +AGP_PLLVDD AGPCALPU_GND DACA_VDD C10 0.01U_0402_50V7K
AE12 AGP_PLLVDD DACA_VREF AH8
2
0.01U_0603_50V7K +3VS +3VS
2 +2.5VS L14 L12
+2.5VS F8 FBVDDQ
F11 +IFP ABIOVDD 2 1 +VIP/DVOVDDQ 1 2
FBVDDQ 49.9_0603_1% R136 KC FBM-L11-201209-221LMAT_0805 KC FBM-L11-201209-221LMAT_0805
F14 FBVDDQ FBCAL_PD_VDDQ F5 2 1 1 1 1 1 1
B 49.9_0603_1% R139 C100 C62 C131 C50 C114 B
F17 FBVDDQ FBCAL_PU_GND E4 2 1
F20 D3 @0_0402_5% 2 1 R385
FBVDDQ FBCAL_TERM_GND @549_0603_1% R137 470P_0402_50V8J 4700P_0402_25V7K 4.7U_0805_10V4Z 470P_0402_50V8J 4700P_0402_25V7K
F23 FBVDDQ FBCAL_CLK_GND E3 2 1
2 2 2 2 2
G8 FBVDDQ
FBCAL_PD_VDDQ G11 FBVDDQ
NV31,NV34 use. G20 FBVDDQ
G23 C27 +FB_DLLVDD
NV18 not use. FBVDDQ FB_DLLVDD +PLLVDD
H24 FBVDDQ PLLVDD AK7
H25 FBVDDQ
FBCAL_PUK_GND L24 FBVDDQ NC B4
NV31,NV34 use. L25 FBVDDQ NC B27
NV18 not use. P25 FBVDDQ NC C11
U25 FBVDDQ NC C20
Y24 FBVDDQ NC D6
FBCAL_TERM_GND Y25 FBVDDQ NC D25
NV31 use (tie to GND). AC24 FBVDDQ NC D29
NV18,NV34 not use. AC25 FBVDDQ NC E12
+3VS +3VS
NC E19
F27 L15 L19
NC +FB_DLLVDD +AGP_PLLVDD
FBCAL_CLK_GND AA6 NC NC L28 1 2 1 2
NV31 use. AC5 M26 1 1 KC FBM-L11-201209-221LMAT_0805 1 1 KC FBM-L11-201209-221LMAT_0805
NC NC C176 C182 C471 C37 C43
NV18,NV34 not use. AF10 NC NC N5
AG29 NC NC W7
AE27 W26 4700P_0402_25V7K 470P_0402_50V8J 4.7U_0805_10V4Z 4700P_0402_25V7K 470P_0402_50V8J
NC NC 2 2 2 2
G9 NC NC Y7 +AGP_PLLVDD
Y28 NC
+FB_DLLVDD NV31,NV34 use.
NV31,NV34 use. NV18 not use.
NV34M_EPBGA701 NV18 not use.
A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
nVIDIA NV31M POWER)
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2041
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: ¬P 期三, 七月 09, 2003 Sheet 18 of 56
5 4 3 2 1
 5 4 3 2 1

+VGA_CORE
U35E

A9 GND T_GND M12 1 1 1 1 1 1 1 1 1 1 1

A12 M13 C129 C75 C71 C74 C130 C102 C96 C115 C111 C84 C123
GND T_GND
A19 GND T_GND M14
A22 M15 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 1U_0603_10V6K 1U_0603_10V6K 1U_0603_10V6K 1U_0603_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
GND T_GND 2 2 2 2 2 2 2 2 2 2 2
A25 GND T_GND M16
C3 GND T_GND M17
C7 GND T_GND M18
C10 GND T_GND M19
D C13 GND T_GND N12 D
C18 N13 +VGA_CORE
GND T_GND
C21 GND T_GND N14
C24 GND T_GND N15
D4 GND T_GND N16 1 1 1 1 1 1 1
D28 N17 C119 C109 C89 C90 C118 C78 C77
GND T_GND
E5 GND T_GND N18
E8 N19 470P_0402_50V8J 470P_0402_50V8J 470P_0402_50V8J 470P_0402_50V8J 4700P_0402_25V7K 4700P_0402_25V7K 4700P_0402_25V7K
GND T_GND 2 2 2 2 2 2 2
E11 GND T_GND P12
E14 GND T_GND P13
E17 GND T_GND P14
E20 GND T_GND P15
E23 GND T_GND P16
F1 GND T_GND P17
F6 GND T_GND P18
F25 GND T_GND P19
F30 GND T_GND R12
G3 GND T_GND R13
G28 GND T_GND R14
H11 GND T_GND R15
H20 GND T_GND R16
H26 GND T_GND R17
J1 GND T_GND R18
J7 R19
GROUND

GND T_GND
J30 GND T_GND T12
K3 T13 +2.5VS
GND T_GND
K5 GND T_GND T14
K28 GND T_GND T15
L5 GND T_GND T16 1 1 1 1 1 1 1 1 1 1 1
C L8 T17 C58 C97 C79 C91 C105 C137 C66 C120 C121 C138 C153 C
GND T_GND
L23 GND T_GND T18
L26 T19 1U_0603_10V6K 1U_0603_10V6K 1U_0603_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
GND T_GND 2 2 2 2 2 2 2 2 2 2 2
M1 GND T_GND U12
M30 GND T_GND U13
N3 GND T_GND U14
N28 GND T_GND U15
P26 GND T_GND U16
T1 U17 +2.5VS
GND T_GND
U26 GND T_GND U18
V28 GND T_GND U19
W1 GND T_GND V12 1 1 1 1 1 1
W30 V13 C136 C152 C151 C150 C146 C149
GND T_GND
Y8 GND T_GND V14
Y23 V15 4700P_0402_25V7K 4700P_0402_25V7K 4700P_0402_25V7K 0.022U_0402_16V7K 0.022U_0402_16V7K 0.022U_0402_16V7K
GND T_GND 2 2 2 2 2 2
Y26 GND T_GND V16
AA5 GND T_GND V17
AA28 GND T_GND V18
AB1 GND T_GND V19
AB30 GND T_GND W12
AC11 W13 +3VS
GND T_GND
AC20 GND T_GND W14
AC26 GND T_GND W15
AD28 GND T_GND W16 1 1 1 1 1 1 1 1
AE1 W17 C54 C59 C85 C48 C52 C38 C51 C142
GND T_GND
AE6 GND T_GND W18
AE25 W19 1U_0603_10V6K 1U_0603_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.022U_0402_16V7K 0.022U_0402_16V7K
GND T_GND 2 2 2 2 2 2 2 2
AE30 GND
AF5 GND
B B
AF8 GND GND AH13
AF11 GND GND AH16
AF14 GND GND AH18
AF17 AH21 +3VS
GND GND
AF20 GND GND AH24
AF23 GND GND AH28
AF26 GND GND AK6 1 1 1 1
AG4 AK9 C140 C104 C101 C128
GND GND
AG27 GND GND AK12
AH3 AK15 0.022U_0402_16V7K 4700P_0402_25V7K 4700P_0402_25V7K 4700P_0402_25V7K
GND GND 2 2 2 2
AH7 GND GND AK19
AH10 GND GND AK22
A6 GND GND AK25

R24 NC
T24 NC NC G12
W24 NC NC G15
AB24 NC NC G16
A1 G19 +VGA_CORE
NC1 NC
AK30 NC2 NC G22
G6 NC3 NC J24
2

R7 NC4 NC M24
T7 R118
NC5 @470_0402_5%
1

NV34M_EPBGA701
Q8
1

D @2N7002
A A
2 SUSP SUSP 41,52
G
S
3

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
nVIDIA NV31M (DECOUPLING CAP)
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-2041
D ate: ¬P 期三, 七月 09, 2003 Sheet 19 of 56
5 4 3 2 1
 5 4 3 2 1

+2.5VS
As close as ppossible to related pin +2.5VS

R_NDQ MA[0..7] 22U_1206_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.01U_0402_16V7K 22U_1206_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.01U_0402_16V7K
17 R_NDQMA[0..7]
R_NDQS A[0..7] 1 1 1 1 1 1 1 1 1 1 1 1 1 1
17 R_NDQSA[0..7]

1
C122 C178 C133 C132 C144 C162 C161 C154 C139 C14 C473 C20 C29 C19 C57 C56 C46 C21
NM AA[0..11]
17 NMAA[0..11]

2
R_NM DA[0..63] 2 2 2 2 2 2 2 2 2 2 2 2 2 2
17 R_NMDA[0..63]
D D
22U_1206_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.01U_0402_16V7K 22U_1206_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.01U_0402_16V7K

0.01U_0402_16V7K
RP11 0.01U_0402_16V7K
NMDA5 1 16 R_NMDA5
NMDA1 2 15 R_NMDA1 RP7
NMDA0 3 14 R_NMDA0 NMDA45 16 1 R_NMDA45
NMDA2 4 13 R_NMDA2 NMDA47 15 2 R_NMDA47
NMDA4 5 12 R_NMDA4 NMDA42 14 3 R_NMDA42

G10

G10
D10
D11

H10

D10
D11

H10
B11

K10

B11

K10
F10

F10
J10

J10
G5

G5
D4
D5
D6
D9

H5

D4
D5
D6
D9

H5
NMDA3 R_NMDA3 NMDA40 R_NMDA40

B4

E6
E9

K5

B4

E6
E9

K5
F5

F5
6 11 13 4

J5

J5
NMDA7 7 10 R_NMDA7 U32 NMDA41 12 5 R_NMDA41 U29
NMDA6 8 9 R_NMDA6 NMDA44 11 6 R_NMDA44

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
NMDA43 10 7 R_NMDA43
22_16P8R_1206_5% NMDA46 9 8 R_NMDA46

NMAA0 N5 B7 NMDA7 22_16P8R_1206_5% NMAA0 N5 B7 NMDA47

NMAA1 A0 DQ0 NMDA6 NMAA1 A0 DQ0 NMDA46
N6 A1 DQ1 C6 N6 A1 DQ1 C6
RP13 NMAA2 NMDA5 RP9 NMAA2 NMDA45
M6 A2 DQ2 B6 M6 A2 DQ2 B6
NMDA31 8 9 R_NMDA31 NMAA3 N7 B5 NMDA4 NMDA48 16 1 R_NMDA48 NMAA3 N7 B5 NMDA44
NMDA30 R_NMDA30 NMAA4 A3 DQ3 NMDA0 NMDA49 R_NMDA49 NMAA4 A3 DQ3 NMDA40
7 10 N8 A4 DQ4 C2 15 2 N8 A4 DQ4 C2
NMDA29 6 11 R_NMDA29 NMAA5 M9 D3 NMDA3 NMDA50 14 3 R_NMDA50 NMAA5 M9 D3 NMDA43
NMDA28 R_NMDA28 NMAA6 A5 DQ5 NMDA2 NMDA51 R_NMDA51 NMAA6 A5 DQ5 NMDA41
5 12 N9 A6 DQ6 D2 13 4 N9 A6 DQ6 D2
NMDA27 4 13 R_NMDA27 NMAA7 N10 E2 NMDA1 NMDA52 12 5 R_NMDA52 NMAA7 N10 E2 NMDA42
NMDA26 R_NMDA26 NMAA8 A7 DQ7 NMDA24 NMDA54 R_NMDA54 NMAA8 A7 DQ7 NMDA49
3 14 N11 A8/AP DQ8 K13 11 6 N11 A8/AP DQ8 K13
NMDA25 2 15 R_NMDA25 NMAA9 M8 K12 NMDA25 NMDA53 10 7 R_NMDA53 NMAA9 M8 K12 NMDA48
NMDA24 R_NMDA24 NMAA10 A9 DQ9 NMDA26 NMDA55 R_NMDA55 NMAA10 A9 DQ9 NMDA50
1 16 L6 A10 DQ10 J13 9 8 L6 A10 DQ10 J13
NMAA11 M7 J12 NMDA27 NMAA11 M7 J12 NMDA51
22_16P8R_1206_5% NMA_BA0 A11 DQ11 NMDA28 22_16P8R_1206_5% NMA_BA0 A11 DQ11 NMDA54
17 NMA_BA0 N4 BA0 DQ12 G13 N4 BA0 DQ12 G13
C NMA_BA1 M5 G12 NMDA29 NMA_BA1 M5 G12 NMDA52 C
17 NMA_BA1 BA1 DQ13 BA1 DQ13
F13 NMDA30 F13 NMDA55
R_NDQMA0 R115 15_0402_5% NDQMA0 DQ14 NMDA31 R_NDQMA5 R75 15_0402_5% NDQMA5 DQ14 NMDA53
1 2 B3 DM0 DQ15 F12 1 2 B3 DM0 DQ15 F12
R_NDQMA3 R143 1 2 15_0402_5% NDQMA3 H12 F3 NMDA8 R_NDQMA6 R86 1 2 15_0402_5% NDQMA6 H12 F3 NMDA32
+2.5VS R_NDQMA1 R97 15_0402_5% NDQMA1 DM1 DQ16 NMDA10 R_NDQMA4 R53 15_0402_5% NDQMA4 DM1 DQ16 NMDA33
1 2 H3 DM2 DQ17 F2 1 2 H3 DM2 DQ17 F2
R_NDQMA2 R141 1 2 15_0402_5% NDQMA2 B12 G3 NMDA9 +2.5VS R_NDQMA7 R90 1 2 15_0402_5% NDQMA7 B12 G3 NMDA35
DM3 DQ18 NMDA11 DM3 DQ18 NMDA34
DQ19 G2 DQ19 G2
2

2
R _NDQSA0 R119 1 2 15_0402_5% N DQSA0 B2 J3 NMDA13 R _NDQSA5 R73 1 2 15_0402_5% N DQSA5 B2 J3 NMDA36
R382 R _NDQSA3 R142 15_0402_5% N DQSA3 DQS0 DQ20 NMDA12 R _NDQSA6 R93 15_0402_5% N DQSA6 DQS0 DQ20 NMDA37
1 2 H13 DQS1 DQ21 J2 1 2 H13 DQS1 DQ21 J2
R _NDQSA1 R102 1 2 15_0402_5% N DQSA1 H2 K2 NMDA15 R96 R _NDQSA4 R54 1 2 15_0402_5% N DQSA4 H2 K2 NMDA39
1K_0603_1% R _NDQSA2 R140 15_0402_5% N DQSA2 DQS2 DQ22 NMDA14 R _NDQSA7 R95 15_0402_5% N DQSA7 DQS2 DQ22 NMDA38
1 2 B13 DQS3 DQ23 K3 1 2 B13 DQS3 DQ23 K3
E13 NMDA21 1K_0603_1% E13 NMDA62
1

1
(25mil) VR_VREF_1 N13 DQ24 NMDA22 (25mil) VR_VREF_2 N13 DQ24 NMDA61
VREF DQ25 D13 VREF DQ25 D13
M13 D12 NMDA20 M13 D12 NMDA60
MCL DQ26 MCL DQ26
2

2
1 L9 C13 NMDA23 1 L9 C13 NMDA63
R386 RFU1 DQ27 NMDA19 R98 RFU1 DQ27 NMDA58
M10 RFU2 DQ28 B10 M10 RFU2 DQ28 B10
C510 B9 NMDA18 C68 B9 NMDA57
1K_0603_1% 0.1U_0402_10V6K NMRASA# DQ29 NMDA17 1K_0603_1% 0.1U_0402_10V6K NMRASA# DQ29 NMDA59
17 NMRASA# M2 RAS# DQ30 C9 M2 RAS# DQ30 C9
2 NMCASA# NMDA16 2 NMCASA# NMDA56
17 NMCASA# L2 B8 L2 B8
1

1
NMWEA# CAS# DQ31 NMWEA# CAS# DQ31
17 NMWEA# L3 WE# L3 WE#
NMCSA0# N2 NMCSA0# N2
17 NMCSA0# CS# CS#
VDDQ C3 VDDQ C3
NMCKEA N12 C5 NMCKEA N12 C5
17 NMCKEA CKE VDDQ CKE VDDQ
VDDQ C7 VDDQ C7
NMCLKA0 M11 C8 NMCLKA1 M11 C8
17 NMCLKA0 CK VDDQ 17 NMCLKA1 CK VDDQ
M12 CK# VDDQ C10 M12 CK# VDDQ C10
VDDQ C12 VDDQ C12
R131 C4 E3 R81 C4 E3
@120_0402_5% NC VDDQ @120_0402_5% NC VDDQ
C11 NC VDDQ E12 C11 NC VDDQ E12
B B
H4 NC VDDQ F4 H4 NC VDDQ F4
H11 NC VDDQ F11 H11 NC VDDQ F11
L12 NC VDDQ G4 L12 NC VDDQ G4
NMCLKA0# L13 G11 NMCLKA1# L13 G11
17 NMCLKA0# NC VDDQ +2.5VS 17 NMCLKA1# NC VDDQ +2.5VS
M3 NC VDDQ J4 M3 NC VDDQ J4
NMCSA1# 1 2CSA1# M4 J11 CSA1# M4 J11
17 NMCSA1# NC VDDQ NC VDDQ
R709 @0_0402_5% N3 K4 N3 K4
RP10 NC VDDQ RP4 NC VDDQ
Reserved for VDDQ K11 VDDQ K11
NMDA9 9 8 R_NMDA9 E7 NMDA39 16 1 R_NMDA39 E7
NMDA11 R_NMDA11 VSS NMDA38 R_NMDA38 VSS
10 7 Hynix 8Mx32 E8 VSS VDD D7 15 2 E8 VSS VDD D7
NMDA10 11 6 R_NMDA10 E10 D8 NMDA37 14 3 R_NMDA37 E10 D8
NMDA8 R_NMDA8 VSS VDD NMDA36 R_NMDA36 VSS VDD
12 5 K6 VSS VDD E4 13 4 K6 VSS VDD E4
NMDA13 13 4 R_NMDA13 K7 E11 NMDA35 12 5 R_NMDA35 K7 E11
NMDA12 R_NMDA12 VSS VDD NMDA34 R_NMDA34 VSS VDD
14 3 K8 VSS VDD L4 11 6 K8 VSS VDD L4
NMDA14 15 2 R_NMDA14 K9 L7 NMDA33 10 7 R_NMDA33 K9 L7
NMDA15 R_NMDA15 VSS VDD NMDA32 R_NMDA32 VSS VDD
16 1 L5 VSS VDD L8 9 8 L5 VSS VDD L8
L10 VSS VDD L11 L10 VSS VDD L11
E5 22_16P8R_1206_5% E5
VSS VSS
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH

VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
22_16P8R_1206_5%
RP8
RP12 NMDA56 R_NMDA56
16 1
NMDA22 1 16 R_NMDA22 NMDA59 15 2 R_NMDA59
NMDA23 2 15 R_NMDA23 NMDA60 14 3 R_NMDA60
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
NMDA21 3 14 R_NMDA21 K4D263238A-GC_FBGA144 NMDA58 13 4 R_NMDA58 K4D263238A-GC_FBGA144
NMDA20 4 13 R_NMDA20 NMDA57 12 5 R_NMDA57
NMDA17 5 12 R_NMDA17 NMDA61 11 6 R_NMDA61
NMDA19 6 11 R_NMDA19 NMDA62 10 7 R_NMDA62
NMDA16 7 10 R_NMDA16 NMDA63 9 8 R_NMDA63
A
NMDA18 8 9 R_NMDA18 A
22_16P8R_1206_5%

22_16P8R_1206_5%

Compal Electronics, Inc.

Title
VGA DDR FOR CHANNEL A
Size Document Number R ev
LA-2041 0.1

D ate: ¬P 期三, 七月 09, 2003 Sheet 20 of 56

5 4 3 2 1
 5 4 3 2 1

+2.5VS
As close as ppossible to related pin +2.5VS

R_NDQ MB[0..7] 22U_1206_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.01U_0402_16V7K 22U_1206_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.01U_0402_16V7K
17 R_NDQMB[0..7]
R_NDQS B[0..7] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
17 R_NDQSB[0..7]

1
C246 C559 C226 C240 C237 C236 C232 C227 C225 C221 C560 C229 C235 C228 C234 C241 C224 C239
NM AB[0..11]
17 NMAB[0..11]

2
R_NM DB[0..63] 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
D 17 R_NMDB[0..63] D

22U_1206_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.01U_0402_16V7K 22U_1206_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.01U_0402_16V7K

RP16 0.01U_0402_16V7K
NMDB0 16 1 R_NMDB0 0.01U_0402_16V7K
NMDB2 15 2 R_NMDB2
NMDB1 14 3 R_NMDB1
NMDB3 R_NMDB3 RP18
13 4
NMDB4 12 5 R_NMDB4 NMDB40 16 1 R_NMDB40
NMDB5 11 6 R_NMDB5 NMDB41 15 2 R_NMDB41

G10

G10
D10
D11

H10

D10
D11

H10
B11

K10

B11

K10
F10

F10
J10

J10
G5

G5
D4
D5
D6
D9

H5

D4
D5
D6
D9

H5
NMDB6 R_NMDB6 NMDB42 R_NMDB42

B4

E6
E9

K5

B4

E6
E9

K5
F5

F5
10 7 14 3

J5

J5
NMDB7 9 8 R_NMDB7 U40 NMDB43 13 4 R_NMDB43 U39
NMDB44 12 5 R_NMDB44

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
22_16P8R_1206_5% NMDB45 11 6 R_NMDB45
NMDB46 10 7 R_NMDB46
NMDB47 9 8 R_NMDB47
RP20 NMAB0 N5 B7 NMDB7 NMAB0 N5 B7 NMDB47
NMDB31 R_NMDB31 NMAB1 A0 DQ0 NMDB5 22_16P8R_1206_5% NMAB1 A0 DQ0 NMDB46
16 1 N6 A1 DQ1 C6 N6 A1 DQ1 C6
NMDB30 15 2 R_NMDB30 NMAB2 M6 B6 NMDB6 NMAB2 M6 B6 NMDB45
NMDB29 R_NMDB29 NMAB3 A2 DQ2 NMDB4 RP22 NMAB3 A2 DQ2 NMDB44
14 3 N7 A3 DQ3 B5 N7 A3 DQ3 B5
NMDB28 13 4 R_NMDB28 NMAB4 N8 C2 NMDB0 NMDB55 9 8 R_NMDB55 NMAB4 N8 C2 NMDB40
NMDB27 R_NMDB27 NMAB5 A4 DQ4 NMDB3 NMDB53 R_NMDB53 NMAB5 A4 DQ4 NMDB43
12 5 M9 A5 DQ5 D3 10 7 M9 A5 DQ5 D3
NMDB26 11 6 R_NMDB26 NMAB6 N9 D2 NMDB2 NMDB54 11 6 R_NMDB54 NMAB6 N9 D2 NMDB41
NMDB25 R_NMDB25 NMAB7 A6 DQ6 NMDB1 NMDB52 R_NMDB52 NMAB7 A6 DQ6 NMDB42
10 7 N10 A7 DQ7 E2 12 5 N10 A7 DQ7 E2
NMDB24 9 8 R_NMDB24 NMAB8 N11 K13 NMDB25 NMDB50 13 4 R_NMDB50 NMAB8 N11 K13 NMDB53
NMAB9 A8/AP DQ8 NMDB24 NMDB51 R_NMDB51 NMAB9 A8/AP DQ8 NMDB55
M8 A9 DQ9 K12 14 3 M8 A9 DQ9 K12
22_16P8R_1206_5% NMAB10 L6 J13 NMDB27 NMDB49 15 2 R_NMDB49 NMAB10 L6 J13 NMDB52
NMAB11 A10 DQ10 NMDB26 NMDB48 R_NMDB48 NMAB11 A10 DQ10 NMDB54
M7 A11 DQ11 J12 16 1 M7 A11 DQ11 J12
C NMB_BA0 N4 G13 NMDB29 NMB_BA0 N4 G13 NMDB51 C
17 NMB_BA0 BA0 DQ12 BA0 DQ12
NMB_BA1 M5 G12 NMDB28 22_16P8R_1206_5% NMB_BA1 M5 G12 NMDB50
17 NMB_BA1 BA1 DQ13 BA1 DQ13
F13 NMDB31 F13 NMDB48
R_NDQMB0 R157 15_0402_5% NDQMB0 DQ14 NMDB30 R_NDQMB5 R161 15_0402_5% NDQMB5 DQ14 NMDB49
2 1 B3 DM0 DQ15 F12 2 1 B3 DM0 DQ15 F12
R_NDQMB3 R165 2 1 15_0402_5% NDQMB3 H12 F3 NMDB9 R_NDQMB6 R167 2 1 15_0402_5% NDQMB6 H12 F3 NMDB38
+2.5VS R_NDQMB1 R166 15_0402_5% NDQMB1 DM1 DQ16 NMDB8 +2.5VS R_NDQMB4 R168 15_0402_5% NDQMB4 DM1 DQ16 NMDB39
2 1 H3 DM2 DQ17 F2 2 1 H3 DM2 DQ17 F2
R_NDQMB2 R156 2 1 15_0402_5% NDQMB2 B12 G3 NMDB11 R_NDQMB7 R160 2 1 15_0402_5% NDQMB7 B12 G3 NMDB36
DM3 DQ18 NMDB10 DM3 DQ18 NMDB37
DQ19 G2 DQ19 G2
2

2
R _NDQSB0 R158 2 1 15_0402_5% N DQSB0 B2 J3 NMDB13 R _NDQSB5 R162 2 1 15_0402_5% N DQSB5 B2 J3 NMDB34
R180 R _NDQSB3 R169 15_0402_5% N DQSB3 DQS0 DQ20 NMDB12 R _NDQSB6 R171 15_0402_5% N DQSB6 DQS0 DQ20 NMDB35
2 1 H13 DQS1 DQ21 J2 2 1 H13 DQS1 DQ21 J2
R _NDQSB1 R170 2 1 15_0402_5% N DQSB1 H2 K2 NMDB14 R181 R _NDQSB4 R172 2 1 15_0402_5% N DQSB4 H2 K2 NMDB33
R _NDQSB2 R155 15_0402_5% N DQSB2 DQS2 DQ22 NMDB15 R _NDQSB7 R159 15_0402_5% N DQSB7 DQS2 DQ22 NMDB32
2 1 B13 DQS3 DQ23 K3 2 1 B13 DQS3 DQ23 K3
1K_0603_1% E13 NMDB21 1K_0603_1% E13 NMDB62
1

1
(25mil) VR_VREF_3 N13 DQ24 NMDB22 (25mil) VR_VREF_4 N13 DQ24 NMDB61
VREF DQ25 D13 VREF DQ25 D13
M13 D12 NMDB20 M13 D12 NMDB60
MCL DQ26 MCL DQ26
2

2
1 L9 C13 NMDB23 1 L9 C13 NMDB63
R178 RFU1 DQ27 NMDB19 R179 RFU1 DQ27 NMDB58
M10 RFU2 DQ28 B10 M10 RFU2 DQ28 B10
C244 B9 NMDB17 C245 B9 NMDB57
1K_0603_1% 0.1U_0402_10V6K NMRASB# DQ29 NMDB18 1K_0603_1% 0.1U_0402_10V6K NMRASB# DQ29 NMDB59
17 NMRASB# M2 RAS# DQ30 C9 M2 RAS# DQ30 C9
2 NMCASB# NMDB16 2 NMCASB# NMDB56
17 NMCASB# L2 B8 L2 B8
1

1
NMWEB# CAS# DQ31 NMWEB# CAS# DQ31
17 NMWEB# L3 WE# L3 WE#
NMCSB0# N2 NMCSB0# N2
17 NMCSB0# CS# CS#
VDDQ C3 VDDQ C3
NMCKEB N12 C5 NMCKEB N12 C5
17 NMCKEB CKE VDDQ CKE VDDQ
VDDQ C7 VDDQ C7
NMCLKB0 M11 C8 NMCLKB1 M11 C8
17 NMCLKB0 CK VDDQ 17 NMCLKB1 CK VDDQ
M12 CK# VDDQ C10 M12 CK# VDDQ C10
VDDQ C12 VDDQ C12
R409 C4 E3 R183 C4 E3
B @120_0402_5% NC VDDQ @120_0402_5% NC VDDQ B
C11 NC VDDQ E12 C11 NC VDDQ E12
H4 NC VDDQ F4 H4 NC VDDQ F4
H11 NC VDDQ F11 H11 NC VDDQ F11
L12 NC VDDQ G4 L12 NC VDDQ G4
NMCLKB0# L13 G11 NMCLKB1# L13 G11
17 NMCLKB0# NC VDDQ +2.5VS 17 NMCLKB1# NC VDDQ +2.5VS
M3 NC VDDQ J4 M3 NC VDDQ J4
NMCSB1# 1 2CSB1# M4 J11 CSB1# M4 J11
17 NMCSB1# NC VDDQ NC VDDQ
R710 @0_0402_5% N3 K4 RP23 N3 K4
NC VDDQ NMDB32 R_NMDB32 NC VDDQ
Reserved for VDDQ K11 16 1 VDDQ K11
E7 NMDB33 15 2 R_NMDB33 E7
RP21 VSS NMDB34 R_NMDB34 VSS
Hynix 8Mx32 E8 VSS VDD D7 14 3 E8 VSS VDD D7
NMDB15 8 9 R_NMDB15 E10 D8 NMDB35 13 4 R_NMDB35 E10 D8
NMDB14 R_NMDB14 VSS VDD NMDB36 R_NMDB36 VSS VDD
7 10 K6 VSS VDD E4 12 5 K6 VSS VDD E4
NMDB13 6 11 R_NMDB13 K7 E11 NMDB37 11 6 R_NMDB37 K7 E11
NMDB12 R_NMDB12 VSS VDD NMDB38 R_NMDB38 VSS VDD
5 12 K8 VSS VDD L4 10 7 K8 VSS VDD L4
NMDB11 4 13 R_NMDB11 K9 L7 NMDB39 9 8 R_NMDB39 K9 L7
NMDB8 R_NMDB8 VSS VDD VSS VDD
3 14 L5 VSS VDD L8 L5 VSS VDD L8
NMDB9 2 15 R_NMDB9 L10 L11 22_16P8R_1206_5% L10 L11
NMDB10 R_NMDB10 VSS VDD VSS VDD
1 16 E5 VSS E5 VSS
RP17
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH

VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
22_16P8R_1206_5% NMDB56 16 1 R_NMDB56
NMDB57 15 2 R_NMDB57
RP15 NMDB59 R_NMDB59
14 3
NMDB16 16 1 R_NMDB16 NMDB58 13 4 R_NMDB58
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
NMDB17 15 2 R_NMDB17 K4D263238A-GC_FBGA144 NMDB60 12 5 R_NMDB60 K4D263238A-GC_FBGA144
NMDB18 14 3 R_NMDB18 NMDB63 11 6 R_NMDB63
NMDB19 13 4 R_NMDB19 NMDB61 10 7 R_NMDB61
NMDB20 12 5 R_NMDB20 NMDB62 9 8 R_NMDB62
A
NMDB21 11 6 R_NMDB21 A
NMDB22 10 7 R_NMDB22 22_16P8R_1206_5%
NMDB23 9 8 R_NMDB23

22_16P8R_1206_5%

Compal Electronics, Inc.

Title
VGA DDR FOR CHANNEL B
Size Document Number R ev
LA-2041 0.1

D ate: ¬P 期三, 七月 09, 2003 Sheet 21 of 56

5 4 3 2 1
 A B C D E

CRT, TV-OUT & LVDS CONNECTOR

1
TV-OUT Conn. D25 +3VALW LVDS Conn.
DAN217_SOT23

14
U13D
13 CHB2012U170_0805

P
39 INVT_PWM

3
A B_INVT_PWM
+3VS O 11
C501 1 2 22P_0402_50V8J D26 12 1 L7 2INVPW R_B+ 40
B B+

G
L24 1 L6 2 39
1 1 2 DAN217_SOT23 SN74LVC32APWLE_TSSOP14 CHB2012U170_0805 38 1
16 LUMA

7
FBM-11-160808-121T_0603 +3VALW POWER DAC_B RIG 37
39 DAC_BRIG
L26 JP20 B_INVT_PWM 36
1 2 DISPOFF# 35
16 CRMA
FBM-11-160808-121T_0603 1 1. Y ground 34
1 +LCDVDD
LUMA_1 2 2. C ground 33
2
16 COMPS 3 3
3. Y (luminance+sync) 32
1 2 CRMA_1 4 4. C (crominance) B+ 31
4
1

C512 TXOUT0+ 30
16 TXOUT0+

1
R74 R387 R356 C515 C497 22P_0402_50V8J SUYIN_030008FR004T101ZL TXOUT0- 29
16 TXOUT0-

1
C511 C502 TXOUT1+ 28
16 TXOUT1+

1
75_0603_1% 270P_0402_50V7K TXOUT1- 27
16 TXOUT1-
2

1
75_0603_1% 330P_0402_50V7K 330P_0402_50V7K R686 C12 C17 26
2

2
TXOUT2+ 25
16 TXOUT2+
@100K_0402_5% 0.1U_0603_50V4Z 10U_1210_35V4Z TXOUT2- 24
16 TXOUT2-

2
75_0603_1% 270P_0402_50V7K TXOUT3+ 23
16 TXOUT3+

2
TXOUT3- 22
16 TXOUT3-
21
TXCLK+ 20
16 TXCLK+
TXCLK- 19
16 TXCLK-
18
+3VS TZOUT0+ 17
+3VS 16 TZOUT0+
+12VALW TZOUT0- 16
16 TZOUT0-
TZOUT1+ 15
16 TZOUT1+
RP6 TZOUT1- 14
16 TZOUT1-
2

PID3 1 8 13

1
+LCDVDD R26 C6 PID2 2 7 TZOUT2+ 12
+5V 16 TZOUT2+
PID1 3 6 TZOUT2- 11
16 TZOUT2-
100K_0402_5% 4.7U_0805_10V4Z PID0 4 5 TZOUT3+ 10
16 TZOUT3+

2
1

1
2 D TZOUT3- 2
16 TZOUT3- 9
1

R16 2 Q3 10K_8P4R_1206_5% 8
2

G TZCLK+ 7
16 TZCLK+
1

100_0402_5% R6 S SI2302DS-T1_SOT23 TZCLK- 6

16 TZCLK-

3
1
10K_0402_5% R25 C5 5
1 2

+LCDVDD PID0 4
D 36 PID0
PID1 3
36 PID1
1

2
22K 200K_0402_5% 1000P_0402_50V7K PID2
2 1 2 2 36 PID2 2
2

G R5 22K PID3 1
36 PID3
S Q1 47K_0402_5%
3

1
2N7002 C107 C108 JP1
Q4
3

DTC124EK_SOT23 0.1U_0402_16V4Z 4.7U_0805_10V4Z IPEX_20323-040E-01

2
ENVDD 22K D41
16 ENVDD 2
22K
@DAN217_SOT23
+3VS
Q2 2
3

DTC124EK_SOT23 1
3

2
D24 D23 D22 R551
DAN217_SOT23 DAN217_SOT23 DAN217_SOT23 +5VS +R_CRT_VCC +CRT_VCC 10K_0402_5%
D20 F1 D32
1

2 1 1 2 RB751V_SOD323

1
1 2 DISPOFF#
CRT Conn. CH491D_SOT23 FUSE_1A
39 BKOFF#

1
3 +3VS C455 C680 3

1
D
0.1U_0402_16V4Z @2N7002 220P_0402_50V8K
JP15 16,39 ENBKL 2
2

2
CRT-15P G Q57
S

3
L3 6
11
16 R 1 2 C RT_R 1
FCM2012C-800_0805 7
L4 12
16 G 1 2 CRT_G 2 +CRT_VCC +CRT_VCC +5VS +5VS +5VS
FCM2012C-800_0805 8
L5 13

2
16 B 18P_0402_50V8K 1 2 CRT_B 3
FCM2012C-800_0805 CR T_VCC 9 R12 R13 R11 R1 R10
1

R7 R8 R9 14
1

C462 C463 C464 C461 C460 C458 4

10 4.7K_0402_5% 4.7K_0402_5% 100K_0402_5% 4.7K_0402_5% 4.7K_0402_5%

1
1

18P_0402_50V8K 15P_0402_50V8J 15P_0402_50V8J 15

2

75_0603_1% 5
2

2
C454 Q34

G
2

75_0603_1% 75_0603_1% 18P_0402_50V8K L1 15P_0402_50V8J 2N7002

+CRT_VCC DACA_HSYNC_1 1 2 DACA_HSYNC_2 DDC_DATA_1 1 3 DDC_DATA 16
0_0603_5%

S
1 2 100P_0402_50V8K

2
C1 L2 Q35

G
5
1

0.1U_0402_16V4Z 1 2 DACA_V SYNC_2 C453 2N7002

R4 0_0603_5% DD C_CLK_1 1 3
OE#
P

DDC_CLK 16
1

2 4 +CRT_VCC 1K_0402_5% C457 C456 C459 220P_0402_50V8K

S
16 D ACA_HSYNC
2

4 A Y 4
G

U27 1 2 @68P_0402_50V8K @68P_0402_50V8K

1

SN74AHCT1G125GW_SOT353-5 C2
3

5
1

220P_0402_50V8K
0.1U_0402_16V4Z
Compal Electronics, Inc.
OE#
P

16 DACA_VSYNC 2 A 4 DACA_V SYNC_1

Y U26
G

SN74AHCT1G125GW_SOT353-5 Title
CRT,TV-OUT & LVDS Connector
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2041
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: ¬P 期三, 七月 09, 2003 Sheet 22 of 56
A B C D E
 5 4 3 2 1

PCI_AD[0..31] +RTCVCC
26,27,29,30 PCI_AD[0..31]
+3VS INTRUD ER# 1 2
RP144 HUB_HL [0..10] U49A R264 10K_0402_5%
10 HUB_HL[0..10]
4 5 PCI_AD0 J4 Y12 INTRUD ER#
3 6 PCI_TRD Y# PCI_AD1 J5
AD0 ICH5/(ICH5-M) INTRUDER#
AD3 ICH _SMLINK0
ICH_G PIO4_PIRQG# PCI_AD2 AD1 SMLINK0 ICH _SMLINK1 +3VALW
2 7 G3 AD2 SMLINK1 AA2
1 8 PCI_ PIRQB# PCI_AD3 K4 V5 LINK_ALERT#
AD3
PCI_AD4 H5 AD4
SMB I/F LINKALERT#
SMBCLK AD2 ICH_SMB_CLK
ICH_SMB_CLK 12,13,15
ICH _SMLINK0 1 2
D 8.2K_8P4R_1206_5% PCI_AD5 H2 AD1 ICH_SMB_DATA R566 10K_0402_5% D
AD5 SMBDATA ICH_SMB_DATA 12,13,15
PCI_AD6 J3 AC3 GPI_11
+3VS PCI_AD7 AD6 SMBALERT#/GPI11 ICH _SMLINK1
RP140 J2 AD7 1 2
PCI_AD8 K5 T22 R547 10K_0402_5%
AD8 A20GATE GATEA20 39
4 5 P CI_REQ#2 PCI_AD9 F2 V23
AD9 A20M# H_A20M# 5
3 6 ICH_GPIO3_PIRQF# PC I_AD10 M4 A11 LINK_ALERT# 1 2
P CI_REQ#B PC I_AD11 AD10 NC R261 10K_0402_5%
2 7 H4 AD11 FERR# U24 H_FERR# 5
1 8 ICH_G PIO2_PIRQE# PC I_AD12 L5 R21
AD12 IGNNE# H_IGNNE# 5
PC I_AD13 G2 CPU I/F R23 GPI_11 1 2
AD13 INIT# H_INIT# 5
8.2K_8P4R_1206_5% PC I_AD14 K1 U23 R652 10K_0402_5%
AD14 INTR H_INTR 5
PC I_AD15 G5 R22
+3VS AD15 NMI H_NMI 5
PC I_AD16 G4 P24
RP146 AD16 CPUPWRGD/GPO49 H_PW RGOOD 5
PC I_AD17 L1 P23
AD17 RCIN# KBRST# 39
4 5 P C I_ I RDY# PC I_AD18 B2 P22 +3VS
AD18 CPUSLP# H_CPUSLP# 5
3 6 PCI_SERR# PC I_AD19 P5 V24 SMI# 2 1
AD19 SMI# 0_0402_5% H_SMI# 5
2 7 PCI_DEVSEL# PC I_AD20 H3 T24 R537 2 1 ICH_SMB_CLK 1 2
AD20 STPCLK# H_STPCLK# 5
1 8 PCI_PERR# PC I_AD21 N5 R24 R531 0_0402_5% R565 2.7K_0402_5%
AD21 NC/(DPSLP#) H_DPSLP# 5
PC I_AD22 C4
8.2K_8P4R_1206_5% PC I_AD23 AD22 H UB_HL0 ICH_SMB_DATA 1
N4 AD23 HI0 H20 2
PC I_AD24 E6 H21 H UB_HL1 R559 2.7K_0402_5%
+3VS PC I_AD25 AD24 HI1 H UB_HL2
RP143 P3 AD25 HI2 J20
PC I_AD26 D3 H23 H UB_HL3
PCI_STOP# PC I_AD27 AD26 HI3 H UB_HL4
4 5 N2 AD27 HI4 M23
3 6 P CI_FRAME# PC I_AD28 F5 M21 H UB_HL5
P CI_REQ#0 PC I_AD29 AD28 HI5 H UB_HL6 CLK_ICH_66M
2 7 P4 AD29 HI6 N21
1 8 PCI_PIRQD# PC I_AD30 F4 M20 H UB_HL7
AD30 HI7

2
PC I_AD31 P2 L22 H UB_HL8
8.2K_8P4R_1206_5% AD31 HI8 H UB_HL9 R249
PCI I/F HI9 J22
E3 HUB I/F K21 HUB_HL10
+3VS 26,27,29,30 PCI_C/BE#0 C/BE0# HI10
C J1 G22 HUB_HL11 2 1 @10_0402_5% C
RP142 26,27,29,30 PCI_C/BE#1 C/BE1# HI11
N3 R234 62_0402_5%
26,27,29,30 PCI_C/BE#2

1
ICH_GPIO5_PIRQH# C/BE2# CLK_ICH_66M
4 5 26,27,29,30 PCI_C/BE#3 M2 C/BE3# CLK66 N22 CLK_ICH_66M 15 2
3 6 PCI_ PIRQA# C383
2 7 PCI_PIRQC# P CI_REQ#0 D5 K23
30 PCI_REQ#0 REQ0# HI_STBF HUB_HLSTRF 10
1 8 P CI_REQ#1 C1 J24 @10P_0402_50V8K
29 PCI_REQ#1 REQ1# HI_STBS HUB_HLSTRS 10 1
P CI_REQ#2 C5
27 PCI_REQ#2 P CI_REQ#3 REQ2# HI_RCOM P_ICH
8.2K_8P4R_1206_5% 26 PCI_REQ#3 B6 REQ3# HIRCOMP N24 2 1 +1.5VS
P CI_REQ#4 C6 L24 HI_VREF_ICH R522 54.9_0603_1%
REQ4#/GPI40 HIREF HI_SW ING_ICH
HI_VSWING L20 change to 52.3_1%
+3VS DISABLE "TOP BLOCK SWAP" PCI_GNT#0 D4
(GNTA#) 30 PCI_GNT#0 PCI_GNT#1 GNT0#
29 PCI_GNT#1 A3 GNT1#
Interrupt I/F
1 2 PIDERST# PCI_GNT#2 B7 B3 PCI_ PIRQA#
27 PCI_GNT#2 GNT2# PIRQA# PCI_PIRQA# 16,27,30
R232 8.2K_0402_5% PCI_GNT#3 C7 E1 PCI_ PIRQB#
26 PCI_GNT#3 GNT3# PIRQB# PCI_PIRQB# 26,27 +3VS
A4 A2 PCI_PIRQC#
GNT4#/GPO48 PIRQC# PCI_PIRQC# 27,29
1 2 PCI_PLOCK# C2 PCI_PIRQD#
PIRQD# PCI_PIRQD# 27,29
R512 8.2K_0402_5% CLK_PCI_ICH N1 D7 ICH_G PIO2_PIRQE# IDE_IRQ15 1 2
15 CLK_PCI_ICH PCICLK PIRQE#/GPI2 ICH_GPIO3_PIRQF# R543 8.2K_0402_5%
PIRQF#/GPI3 A6
2 1 P CI_REQ#A P CI_FRAME# D2 E2 ICH_G PIO4_PIRQG#
26,27,29,30 PCI_FRAME# FRAME# PIRQG#/GPI4
R483 10K_0402_5% PCI_DEVSEL# L3 B1 ICH_GPIO5_PIRQH# IDE_IRQ14 1 2
26,27,29,30 PCI_DEVSEL# DEVSEL# PIRQH#/GPI5 8.2K_0402_5%
P C I_ I RDY# M3 Y17 IDE_IRQ14 R262
26,27,29,30 P C I_ IRDY# IRDY# IRQ14 IDE_IRQ14 35
1 2 P CI_REQ#4 PCI_PAR F1 Y24 IDE_IRQ15
26,27,29,30 PCI_PAR PAR IRQ15 IDE_IRQ15 34,35
R222 10K_0402_5% PCI_PERR# K2 F23 IRQ_SER IRQ IRQ_SER IRQ 1 2
26,27,29,30 PCI_PERR# PERR# SERIRQ SERIRQ 27,36,39
PCI_PLOCK# L2 R511 10K_0402_5%
P CI_REQ#1 PLOCK#
1 2 V2 PME#
EEPROM I/F EE_CS B10
R503 10K_0402_5% P CIRST# V4 B11
10,13,26,27,29,30,36,39 PCIRST# PCI_SERR# PCIRST# EE_DIN NC_EE_DOUT
26,27,29,30 PCI_SERR# L4 SERR# EE_DOUT B9 2 1
1 2 P CI_REQ#3 PCI_STOP# E5 A12 R220
26,27,29,30 PCI_STOP# STOP# EE_SHCLK
R479 10K_0402_5% PCI_TRD Y# E4 @1K_0402_5%
B 26,27,29,30 PCI_TRDY# TRDY# B
LAN_RXD0 C10
P CI_REQ#A A5 C9
P CI_REQ#B REQA#/GPI0 LAN_RXD1
E7 REQB#REQ5#/GPI1 LAN_RXD2 C11
D9
+1.5VS
35 PIDERST#
PIDERST# E8 GNTA#/GPO16
LAN I/F LAN_TXD0
LAN_TXD1 E9
B4 GNTB#/GNT5#/GPO17 LAN_TXD2 B12
LAN_CLK E10
LAN_RSTSYNC D10
1

AA1 LAN_RST# 2 1
R515 LAN_RST# R544
Note: IC H5 10K_0402_5%
226_0603_1% HI_SWING_MCH, HI_VREF_MCH
trace width of 10mils and
2

space 7mils +3V

HI_SW ING_ICH
2 1
C679 0.1U_0402_16V4Z
1

2 1 Close to ICH(L20) CLK_PCI_ICH

R513 C371
1

C377
147_0603_1% 0.1U_0402_16V4Z 0.01U_0402_16V7K R520
1 2
14
@10_0402_5%
2

Close to ICH ball <250mils 1OE# U51A

P
2

P CIRST# 2
HI_VREF_ICH
1 I O 3 B_PCIRST# 16,35
G

C667 +3V POWER

@10P_0402_50V8K
7

A A
1

Close to ICH(L24) 2 SN74LVC125APWLE_TSSOP14

2 1
R241 C379
C374
113_0603_1% 0.1U_0402_16V4Z 0.01U_0402_16V7K
1 2
2

Close to ICH ball <250mils

Compal Electronics, Inc.
Title
ICH5-PCI/HUB/LAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2041
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 七月 09, 2003 Sheet 23 of 56
5 4 3 2 1
 5 4 3 2 1

+3VALW

2 1 TP0_PU R251 R536

R550 10K_0402_5% 10K_0402_5% U49B 100K_0402_5%
2 1 SYS_RESET# 1 2 R5 U3 IC H _ACIN 1 2 IC H _ACIN 2 1 A C IN
R540 8.2K_0402_5%
+3VS
SYS_RESET# U1
GPI6/(AGPBUSY#) ICH5/(ICH5-M) GPI7
Y2 EC_SMI#
+3VS A C IN 39,44,46
SYS_RESET# GPI8 EC_SMI# 39
TP0_PU AB2 W4 EC_ SCI# RB751V_SOD323 D36
TP0/(BATLOW#) GPI12 EC_SCI# 39
+3VS R1 W5 EC_LID_OUT#
GPO21/(C3_SAT#) GPI13 EC_LID_OUT# 39
AC1 GPIO24/(CLKRUN#)
GPI GPIO25 W3 EC_FLASH# 40
2 1 ICH_VGATE PM_DPRSLPVR P20 V3 +3VALW
53 PM_DPRSLPVR NC/(DPRSLPVR) GPIO27
R253 10K_0402_5% Y4 W2
39 PBTN_OUT# PWRBTN# GPIO28 USB_EN# 37
2 1 EC_THRM# ICH _PW ROK AC12
R530 4.7K_0402_5% PWROK ID E_PDA0
39 EC_SW I# AB3 RI# PDA0 AA19 IDE_PDA0 35 2 1
D 2 1 PM_CLKRUN# EC_RSMRST# AB13 PM AD19 ID E_PDA1 C392 0.1U_0402_16V4Z D
39,45 EC_RSMRST# RSMRST# PDA1 IDE_PDA1 35
R653 10K_0402_5% PM_SLP_S1# T20 AC19 ID E_PDA2
15 PM_SLP_S1# GPO19/(SLP_S1#) PDA2 IDE_PDA2 35

5
PM_SLP_S3# W1 AB19 ID E_PDCS1# U17
39 PM_SLP_S3# SLP_S3# PDCS1# IDE_PDCS1# 35
PM_SLPS4# U2 Y18 ID E_PDCS3# PM_SLPS4# 1

P
+CPU_CORE SLP_S4# PDCS3# IDE_PDCS3# 35 IN1
PM_SLPS5# AA3 4
SLP_S5# O PM_SLP_S5# 39
STP_CPU# U22 AC17 IDE_P DDREQ PM_SLPS5# 2
15,53 STP_CPU# GPO20/(STP_CPU#) PDDREQ IDE_PDDREQ 35 IN2

G
2 1 H_C PUPERF# STP_PCI# U21 AC18 IDE_ PDDACK#
15 STP_PCI# GPO18/(STP_PCI#) PDDACK# IDE_PDDACK# 35
R257 10K_0402_5% SUSCLK Y1 AD18 IDE_PD IOR# SN74AHC1G08HDCK_TSSOP5
27 SUSCLK IDE_PDIOR# 35

3
SUSCLK PDIOR# IDE_ PDIOW #
AB1 SUS_STAT#/LPCPD# PDIOW# AA17 IDE_PDIOW # 35
EC_THRM# T2 AA18 ID E _ PDIORDY
39 EC_THRM# THRM# PIORDY ID E _ PDIORDY 35
2 1 SUSCLK
R542 @10K_0402_5% AB16 IDE_ PDD0
EC_RSMRST# PDD0 IDE_ PDD1
2 1 F22 GPO23/(SSMUXSEL) PDD1 Y13
R265 10K_0402_5% H_C PUPERF# U20 IST Y14 IDE_ PDD2
5 H_CPUPERF# GPO22/(CPUPERF#) PDD2
1 2 ICH_VGATE R20 AC14 IDE_ PDD3
50,52,53 VGATE VRMPWRGD/(VGATE) PDD3
R528 0_0402_5% AA14 IDE_ PDD4 ICH_SYNC# SYS_PWROK ICH_PWROK
ICH _AC_BITCLK PDD4 IDE_ PDD5
31,38 ICH_AC_BITCLK D8 AC_BIT_CLK PDD5 AC15
IC H_AC_RST_R#C12 AD14 IDE_ PDD6 0 0 0 +3VS
+3VS ICH_AC_SD IN0 AC_RST# PDD6 IDE_ PDD7
31 ICH_AC_SDIN0 E12 AC_SDIN0 PDD7 AB14
ICH_AC_SD IN1 D12 AC97 I/F AD15 IDE_ PDD8 0 1 0 ID E _ PDIORDY 2 1
38 ICH_AC_SDIN1 AC_SDIN1 PDD8
2 1 ICH _AC_SDOUT A13 AC_SDIN2 PDD9 Y15 IDE_ PDD9 R572 4.7K_0402_5%
R477 @8.2K_0402_5% ICH_ AC_SDOUT_R A9 AD16 IDE _PDD10 1 0 0
I CH_AC_SYNC_R B8 AC_SDOUT PDD10 IDE _PDD11 ID E _ SDIORDY
AC_SYNC PDD11 AA15 2 1
2 1 ICH _AC_BITCLK IDE I/F PDD12 AC16 IDE _PDD12 1 1 1 R546 4.7K_0402_5%
R225 @10K_0402_5% LPC_A D[0..3] LPC_AD0 T5 Y16 IDE _PDD13
13,36,39 LPC_AD[0..3] LAD0 PDD13
2 1 ICH_AC_SD IN0 LPC_AD1 R4 LAD1 PDD14 AA16 IDE _PDD14
R230 @10K_0402_5% LPC_AD2 R3 AB17 IDE _PDD15
LAD2 PDD15 +3VS
2 1 ICH_AC_SD IN1 LPC_AD3 U4 LAD3
LPC I/F
R229 @10K_0402_5% U5 W22 ID E_SDA0
LDRQ0# SDA0 IDE_SDA0 34,35
C LPC_DRQ1# R2 W23 ID E_SDA1 C
36 LPC_DRQ#1 LDRQ1#/GPI41 SDA1 IDE_SDA1 34,35

1
LPC_FRAME# T4 W21 ID E_SDA2
13,36,39 LPC_FRAME# LFRAME# SDA2 IDE_SDA2 34,35

1
V22 ID E_SDCS1# R580
SDCS1# IDE_SDCS1# 34,35
C23 V20 ID E_SDCS3# R571 @1K_0402_5% R582
37 USBP0+ USBP0P SDCS3# IDE_SDCS3# 34,35
+3VALW D23 @220_0402_5%
37 USBP0- USBP0N
RP141 A22 Y20 IDE_S DDREQ @220_0402_5%
IDE_SDDREQ 34,35

2
USB_OC3# USBP1P SDDREQ IDE_ SDDACK#
4 5 B22 W20 IDE_SDDACK# 34,35

2
USB_OC5# USBP1N SDDACK# IDE_SD IOR#
3 6 37 USBP2+ C21 USBP2P SDIOR# Y23 IDE_SDIOR# 34,35

1
2 7 USB_OC7# D21 Y22 IDE_ SDIOW #
37 USBP2- USBP2N SDIOW# IDE_SDIOW # 34,35
1 8 USB_OC1# A20 Y21 ID E _ SDIORDY 2 2
35 USBP3+ USBP3P SIORDY ID E _ SDIORDY 34,35
B20 Q60 Q59
35 USBP3- USBP3N
10K_8P4R_1206_5% C19 AA22 IDE_ SDD0 @MMBT3904_SOT23 @MMBT3904_SOT23
37 USBP4+

3
USBP4P SDD0 IDE_ SDD1
37 USBP4- D19 USBP4N SDD1 AB23 10 IC H _SYNC#
A18 AD23 IDE_ SDD2
38 USBP5+ USBP5P SDD2
B18 AD24 IDE_ SDD3 1 2 ICH _PW ROK
38 USBP5- USBP5N SDD3 7,42 SYS_PW ROK
C17 AB21 IDE_ SDD4 R570 0_0402_5%
+RTCVCC 37 USBP6+ USBP6P SDD4
D17 AC21 IDE_ SDD5
37 USBP6- USBP6N SDD5
A16 USB I/F AB20 IDE_ SDD6
35 USBP7+ USBP7P SDD6 IDE_PDD[0 ..15]
2 1 ICH_INTVRMEN B16 AC20 IDE_ SDD7
35 USBP7- USBP7N SDD7 IDE_PDD[0..15] 35
R577 330K_0402_5% Y19 IDE_ SDD8
USB_OC0# SDD8 IDE_ SDD9 IDE_SDD[0 ..15]
2 1 37 USB_OC0# C15 OC0# SDD9 AD22 IDE_SDD[0..15] 34,35
R576 @10K_0402_5% USB_OC1# D15 AC22 IDE _SDD10
USB_OC2# OC1# SDD10 IDE _SDD11
37 USB_OC2# D14 OC2# SDD11 AA20
USB_OC3# C14 AB22 IDE _SDD12 R573 +RTCVCC
USB_OC4# OC3# SDD12 IDE _SDD13
37 USB_OC4# B14 OC4#/GPI9 SDD13 AC24 2 1 2 1 2 1
USB_OC5# A14 AB24 IDE _SDD14 R476 J1
USB_OC6# OC5#/GPI10 SDD14 IDE _SDD15 4.7K_0402_5% JOPEN 200K_0402_5%
37 USB_OC6# D13 OC6#/GPI14 SDD15 AA23
USB_OC7# C13 C686
OC7#/GPI15
Note: SATA0TXP AA8 1U_0805_25V4Z
B US BRBIAS A24 IC H_RTCRST# B
USBRBIAS keep less than 500mils 1 2 USBRBIAS SATA0TXN AB8
R500 B24 AD7
22.6_0603_1% USBRBIAS# SATA0RXN
SATA0RXP AC7
+3VS T1 GPIO32
G23 GPIO33
SATA I/F SATA1TXP AA10
2 1 SPKR
35 SIDERST#
SIDERST# F21 GPIO34
GPIO SATA1TXN AB10 Note:
R504 @1K_0402_5% AD9 SATABIAS keep less than 500mils C691
ICH_INTVRMEN AD10 SATA1RXN @0.047U_0402_16V4Z
Disable timer timeout INTVRMEN SATA1RXP AC9
2 1ICH_V BIAS 2 1
Y11 SATABIAS 2 1 R569 R575 @1K_0402_5%
SPKR SATARBIAS R260 24.9_0603_1% @10M_0603_5%
33 SPKR E24 SPKR
MISC SATARBIAS# Y9 1 2
CLK_ICH_14M CLK_ICH_48M R578 @22M_0603_5%

2
CLK100P AC5
2

H_THERMTRIP# 1 2 T21 AD5 ICH_RTCX1 R568

5 H_THERMTRIP# THRMTRIP# CLK100N
R508 R258 0_0402_5%
R231 @10_0402_5% AA12 IC H_RTCRST# ICH_RTCX2 2 1 @2.4M_0603_1%
CLK_ICH_14M RTCRST# R567 10M_0402_5%
15 CLK_ICH_14M F20

1
@10_0402_5% CLK14 ICH_RTCX1
CLOCK AC11
2 1

RTCX1 X6
2
C353 CLK_ICH_48M F24 AB12 ICH_RTCX2
15 CLK_ICH_48M CLK48 RTCX2
@4.7P_0402_50V8C C650
@10P_0402_50V8K 32.768KHZ_12.5PF_CM155
IC H5
1

1 C697 C698

ICH _AC_BITCLK 12P_0402_50V8J 12P_0402_50V8J

2
R223
+CPU_CORE 2 1 IC H_AC_RST_R#
A 31,38 ICH_AC_RST# A
R486 33_0402_5% @10_0402_5%
1 2 H_THERMTRIP# 31,38 IC H _AC_SYNC 2 1 I CH_AC_SYNC_R

1
R254 62_0402_5% R485 33_0402_5% 2
Near ICH 31,38 ICH_AC_SDOUT 2 1 ICH_ AC_SDOUT_R C354
R484 33_0402_5%
@10P_0402_50V8K
1 Compal Electronics, Inc.
PM_CLKRUN# Title
26,27,29,30,36,39 PM_CLKRUN#
ICH5-IDE/LPC/PM/GPIO/USB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2041
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 七月 09, 2003 Sheet 24 of 56
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE
+3VS
U49C
A1 B5 +3VS
A7
VSS ICH5/(ICH5-M) VCC3_3 F6 1
VSS VCC3_3 C388
A10 VSS VCC3_3 G1
A15 VSS VCC3_3 H6
A17 K6 1 1 1 1 1 1 0.1U_0402_16V4Z
VSS VCC3_3 C373 C397 C385 C363 C381 C389 2
A19 VSS VCC3_3 L6 Place near
A21 VSS VCC3_3 M10 ball T22
D A23 N10 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z D
VSS VCC3_3 2 2 2 2 2 2
AA5 VSS VCC3_3 P6
AA7 VSS VCC3_3 R13
AA9 VSS VCC3_3 V19
AA11 VSS VCC3_3 W15 Place near ball(VSS)
AA13 VSS VCC3_3 W17 D1,A7,H1,P1,W24 and A21
AA21 W24 +1.5VS
VSS VCC3_3
AA24 VSS VCC3_3 AD13
AB5 VSS VCC3_3 AD20
AB7 G19 +1.5VS
VSS VCC3_3
AB9 VSS VCC3_3 G21 1 1
AB11 Power C382 C384
VSS
AB15 VSS VCCSUS3_3 E18 +3VALW
AB18 B15 1 1 1 1 1 1 2 0.1U_0402_16V4Z 0.01U_0402_16V7K
VSS VCCSUS3_3 C393 C401 C386 C368 C395 C360 C372 2 2
AC2 VSS VCCSUS3_3 E11
AC4 VSS VCCSUS3_3 F10
AC6 F11 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K Place near ball D24
VSS VCCSUS3_3 2 2 2 2 2 2 1
AC8 VSS VCCSUS3_3 E13
AC10 VSS VCCSUS3_3 E14
AC13 VSS VCCSUS3_3 U6
AC23 VSS VCCSUS3_3 V6 Place0.1u near ball(VSS)
AD4 VSS VCCSUS3_3 F16 G24,H24,K24,M24,AD4
AD6 VSS VCCSUS3_3 F17 and AD18; 0.01u near to
AD8 F18 +1.5VS
VSS VCCSUS3_3 ball AD8.
AD17 VSS VCCSUS3_3 K15
AD21 VSS
AD12 K10 +3VALW
VSS VCC1_5 +1.5VS
B13 VSS VCC1_5 K12 1 1
B17 K13 C378 C394
C VSS VCC1_5 C
B19 VSS VCC1_5 L19
B21 P19 1 1 1 1 1 0.1U_0402_16V4Z 0.01U_0402_16V7K
VSS VCC1_5 C356 C361 C357 C391 C387 2 2
B23 VSS VCC1_5 R10
C3 VSS VCC1_5 R6
C8 H24 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0603_10V6K Place near ball AD6
VSS VCC1_5 2 2 2 2 2
C16 VSS VCC1_5 J19
C18 VSS VCC1_5 K19
C20 VSS VCC1_5 M15
C22 VSS VCC1_5 N15 Place0.1u near ball(VSS)
D1 VSS VCC1_5 N23 A17,A23,V1.Addition cap near
D6 VSS VCC1_5 E15 A15,A19
D11 VSS VCC1_5 F15
D16 VSS VCC1_5 F14
+3VS +5VS
D18 VSS VCC1_5 W19
D20 VSS VCC1_5 R12
D22 VSS VCC1_5 W9 Decoupling Reference Document:

2
D24 W10
E17
VSS VCC1_5
W11
Springdale Chipset Platform Design guide Rev1.11 D30 R482
VSS VCC1_5
E19 VSS VCC1_5 W6 (12474)page278 RB751V_SOD323
E20 W7 1K_0402_5%
VSS VCC1_5
E21 W8

1
VSS VCC1_5
E23 VSS VCC1_5 E22
F3 ICH_V 5REF
VSS VCCSUS15_A
F9 VSS VCCSUS1_5_A F19
G6 Y5 VCCSUS15_B 1 1 1
VSS VCCSUS1_5_B C390 C349 C636
G20 VSS VCCSUS1_5_B AA4
G24 VSS VCCSUS1_5_B AB4
H1 F7 V CCSUS15_C 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0603_10V6K
VSS VCCSUS1_5_C 2 2 2
H19 VSS VCCSUS1_5_C F8 1 1 1
B C362 C398 C359 B
H22 VSS
J6 A8 ICH_V 5REF
VSS V5REF 0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K
J21 VSS V5REF W14
2 2 2 Place near ball A8
J23 VSS
K3 E16 ICH_ V5REF_SUS
VSS V5REF_SUS
K11 VSS
Place near Place near Place near
+3VALW +5VALW
K14 VSS V_CPU_IO R15 +CPU_CORE ball (VSS)A7 ball (VSS)AD4 ball (VSS)A19
K20 VSS V_CPU_IO R19
K22 VSS V_CPU_IO T19

2
K24 VSS
L10 AA6 +1.5VS D12 R233
VSS VCCSATAPLL
L11 VSS VCCSATAPLL AB6 RB751V_SOD323
L12 1K_0402_5%
VSS
L13 C24

1
VSS VCCUSBPLL +1.5VS +5VS ICH_ V5REF_SUS
L14 VSS
L15 VSS VCCRTC AD11 +RTCVCC
L21 VSS 1 1 1 1 1
L23 1 C358 C355 C364
VSS C402 C796 C797
M1 VSS VSS P14
M5 P15 1000P_0402_50V7K 1000P_0402_50V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0603_10V6K
VSS VSS 0.1U_0402_10V6K 2 2 2 2 2
M11 VSS VSS P21
2
M12 VSS VSS R11
M13 VSS VSS R14
M14 VSS VSS T23
M22 VSS VSS T3 Place near ball(VSS) A17
M24 VSS
GND VSS T6
N11 VSS VSS U19 Place near ball AD11
N12 VSS VSS V1
A N13 VSS VSS V21 A
N14 VSS VSS W16
N20 VSS VSS W18
P1 VSS VSS Y3
P10 VSS VSS Y6
P11 VSS VSS Y7
P12 Y8
P13
VSS VSS
Y10
Compal Electronics, Inc.
VSS VSS Title
IC H5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH5 Power & Decoupling
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-2041
D ate: ¬P 期三, 七月 09, 2003 Sheet 25 of 56
5 4 3 2 1
 5 4 3 2 1

TRACE=20mil
+2.5V_DLAN
0.1U_0402_16V4Z
Place closed to
RTL8101L pin58
LAN Realtek RT8101L
+2.5V_LAN
R388 0_0603_5%

1
C519 C534 22U_1206_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z

2
U37 C508 C509

1
PCI_AD0 47 48 C507 C506 C505
PCI_AD1 AD0 VDD25 0.1U_0402_16V4Z RTL8101L has internal
46 94

1
PCI_AD2 AD1 VDD25 +2.5V generator at pin58
45

2
PCI_AD[0..31] PCI_AD3 AD2 +2.5V_LAN TRACE=20mil
23,27,29,30 PCI_AD[0..31] 43 AD3 AVDD25 58 +2.5V_LAN

Power
D PCI_AD4 42 0.1U_0402_16V4Z D
PCI_AD5 AD4 +3V_LAN_VDD1 TRACE=20mil
41 AD5 AVDD 59 1 2 +3V
PCI_AD6 40 L25
PCI_AD7 AD6 +3V_LAN_VDD2 TRACE=20mil LQG21N4R7K10_0805
39 AD7 AVDD 70
PCI_AD8 36 TRACE=30mil
PCI_AD9 AD8 +3V_LAN_VDD3 TRACE=20mil
35 AD9 AVDD 75
PC I_AD10 34
PC I_AD11 AD10
33 AD11
PC I_AD12 32
PC I_AD13 AD12 U34
30 AD13
PC I_AD14 29 52 LAN_EEDO 4 5
PC I_AD15 AD14 EEDO LA N_EEDI DO GND +3V
28 AD15 EEDI 53 3 DI NC 6
PC I_AD16 15 54 LAN_EECLK 2 7
PC I_AD17 AD16 EESK LAN_EECS SK NC
14 AD17 EECS 55 1 CS VCC 8
PC I_AD18 13 AD18

1
PC I_AD19 12 78 ACTIVITY# AT93C46-10SI-2.7_SO8 C504
PC I_AD20 AD19 LED0 LINK10_100#
11 AD20 LED1 77 Layout Note
PC I_AD21 10 76 0.1U_0402_16V4Z H0013 pls close to

2
PC I_AD22 AD21 LED2
9 AD22 1 2 +3V conn.
PC I_AD23 8 72 LAN_TD+ R384 Closed to PULSE H0013

LAN I/F
PCI I/F
PC I_AD24 AD23 TXD+ LAN_TD- 5.6K_0402_5% U28
96 AD24 TXD- 71
PC I_AD25 93
PC I_AD26 AD25 LAN_RD+ LAN_RD+ RJ45_RX+
92 AD26 RXIN+ 68 1 RD+ RX+ 16
PC I_AD27 91 67 LA N_RD- LA N_RD- 2 15 RJ45_RX-
PC I_AD28 AD27 RXIN- RD- RX-
89 AD28 3 CT CT 14
PC I_AD29 87 61 LAN_X1 4 13
AD29 X1 NC NC

1
PC I_AD30 86 Closed to RT8101L 5 12
PC I_AD31 AD30 R324 R325 NC NC
85 AD31 6 CT CT 11
60 LAN_X2 49.9_0603_1% 49.9_0603_1% LAN_TD+ 7 10 RJ45_TX+
C PCI_C/BE#0 X2 LAN_TD- TD+ TX+ RJ45_TX- C
23,27,29,30 PCI_C/BE#0 38 C/BE#0 1 2 +3VS 8 TD- TX- 9
PCI_C/BE#1 27 64 R145 1K_0402_5%
23,27,29,30 PCI_C/BE#1

2
C/BE#1 LWAKE

1
PCI_C/BE#2 17
23,27,29,30 PCI_C/BE#2 C/BE#2

1
PCI_C/BE#3 84 74 1 2 +3V R326 R327 Pulse H0013
23,27,29,30 PCI_C/BE#3 C/BE#3 ISOLATE#

1
IDSEL:PCI_AD17 R146 15K_0402_5% C484 49.9_0603_1% (NS0013)
PC I_AD17 1 2 L AN_IDSEL 98 65 1 2 49.9_0603_1% R313 R312
IDSEL RTSET

1
R395 100_0402_5% R383 5.6K_0603_1% 0.1U_0402_16V4Z C476 75_0402_5% 75_0402_5%

2
24 63 Q9
23,27,29,30 PCI_PAR

2
PAR RTT3 E 0.1U_0402_16V4Z R J45_PR
23,27,29,30 PCI_FRAME# 18 47K @2SB1197K_SOT23

2
FRAME# B
23,27,29,30 P C I_ IRDY# 19 IRDY# VCTRL 56

1
20 2 C485
23,27,29,30 PCI_TRDY# TRDY#
21 1
AC-Link

23,27,29,30 PCI_DEVSEL# DEVSEL# AC_RST# 10K

23 3 C 0.1U_0402_16V4Z
23,27,29,30 PCI_STOP#

2
STOP# AC_SYNC
AC_DOUT 4
23,27,29,30 PCI_PERR# 25 5 reserve transistor for ver.C

1
PERR# AC_DIN
23,27,29,30 PCI_SERR# 26 SERR# AC_BCK 7 +2.5V_LAN

1
83 C177 Q38
23 PCI_REQ#3 REQ# DTA114YKA_SOT23 JP16
82 100

E
23 PCI_GNT#3 GNT# GPIO0 @22U_1206_10V4Z
99 3 1 1 2 12

2
GPIO1 +3V Amber LED+

47K
80 R331 300_0402_5%

C
23,27 PCI_PIRQB# INTA#
79 INTB# 11 Amber LED-

10K
57 51 16

B
27,29,30,39 LAN_PME# PME# ROMCS/OEB SHLD4
69 Y1 8
NC 25MHZ_20PF_6X25000017 PR4-
10,13,23,27,29,30,36,39 PCIRST# 81 15

2
C LK_PCI_LAN RST# LAN_X1 LAN_X2 SHLD3
15 CLK_PCI_LAN 97 PCICLK 7 PR4+
50 2 ACTIVITY#
24,27,29,30,36,39 PM_CLKRUN# CLKRUN# DGND1
1

1
16 RJ45_RX- 6
DGND2 C180 C179 PR2-
+3V 6 VDD DGND3 31
B 27P_0402_50V8J 27P_0402_50V8J B
22 44 5
2

2
VDD DGND4 PR3-

C LK_PCI_LAN
37
49
90
VDD
VDD
Power DGND5
AGND1
88
62
66
4 PR3+
VDD AGND2 RJ45_RX+
95 VDD AGND3 73 3 PR2+
1

R393 RTL8101L_LQFP100 RJ45_TX- 2

@10_0402_5% PR1-
SHLD2 14
RJ45_TX+ 1 PR1+
13
1 2

Q36 SHLD1
10 Green LED-
DTA114YKA_SOT23

E
C540 3 1 1 2 9
+3V Green LED+

47K
@10P_0402_50V8K R314 300_0402_5%

C
2

JP30 AMP 440470-4 RJ45 with LED

10K
1

B
NC

1
2

2
NC R15 R14
LINK10_100# 75_0402_5% 75_0402_5%
RJ11

2
3 R J45_PR 1 2 @0.1U_0402_16V4Z LAN GND
NC

1
4 C470 C449
NC 1000P_1206_2KV7K C450
4.7U_0805_10V4Z

2
SANTA_130403-1 Termination plane should be copled to chassis ground
A A
+3V

C527 C516 C550 C549 C536 C529

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

Title
Compal Electronics, Inc.
LAN REALTEK RTL8101L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LA-2041 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 七月 09, 2003 Sheet 26 of 56
5 4 3 2 1
 5 4 3 2 1

PCI_AD[31..0]
23,26,29,30 PCI_AD[31..0]
PCI_C/BE #[3..0] +3V
23,26,29,30 PCI_C/BE#[3..0]
U5A
PCI_AD0 K17 R2 SD C_D0
AD0 SDCD0

SD Interface
PCI_AD1 K18 T2 SD C_D1 C577 C586 C556 C584 C574 C589 C561
PCI_AD2 AD1 SDCD1 SD C_D2
K19 AD2 SDCD2 R3
PCI_AD3 L17 T3 SD C_D3 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
PCI_AD4 AD3 SDCD3
L18 AD4
PCI_AD5 L19 U1 SD CMD
PCI_AD6 AD5 SDCMD S DCLK
L20 AD6 SDCLK R4
D PCI_AD7 M17 D
PCI_AD8 AD7 SDC D#
M18 AD8 SDCD# T1
PCI_AD9 M19 P1 SDW P#
PC I_AD10 AD9 SDWP S DLED
M20 AD10 SDLED V13 SDLED 43
PC I_AD11 N17
PC I_AD12 AD11 S DPW R
N18 AD12 SDPWR R1
+5VS PC I_AD13 N19
PC I_AD14 AD13 SMD0
N20 AD14 SMD0 M1
PC I_AD15 P17 N4 SMD1
1
PC I_AD16 AD15 SMD1 SMD2
P18 AD16 SMD2 N5
R706 PC I_AD17 P19 P4 SMD3
AD17 SMD3

SmartMedia Interface
100K_0402_5% PC I_AD18 P20 N1 SMD4
PC I_AD19 AD18 SMD4 SMD5
P16 AD19 SMD5 N2 U41
PC I_AD20 R17 P2 SMD6
2

PC I_AD21 AD20 SMD6 SMD7

R18 AD21 SMD7 N3 +3V 4 VIN FLG# 3
PC I_AD22 R19 AD22
2
G

PC I_AD23 R20 M3 5 +SD3_VCC

PC I_AD24 AD23 SMCLE VOUT
T17 AD24 SMALE M2
P CI_REQ#2 3 1P CI_REQ#2_F PC I_AD25 T18 L1 S DPW R 1 2
23 PCI_REQ#2 AD25 SMCE# CE GND
PC I_AD26 C554
S

T19 AD26 SMWE# L3

PC I_AD27 T20 L2 RT9702_SOT23-5 R401
PC I_AD28 AD27 SMRE# 4.7U_0805_10V4Z 20K_0402_5%
Q72 U17 AD28 SMWP# K3
PC I_AD29 U18
2N7002 PC I_AD30 AD29
U19 AD30 SMRB# M4 +3V

PCI Interface
PC I_AD31 U20 L5
AD31 SMCD#
SMLVD L4
PCI_C/BE#0 V20 K4
PCI_C/BE#1 C/BE#0 SMWPD#
V19 C/BE#1 SMEJSW# K5
PCI_C/BE#2 V18
C PCI_C/BE#3 C/BE#2 C
V17 C/BE#3 SMLED# M5
SMLOCK# K2
PCI_PAR Y14 K1
23,26,29,30 PCI_PAR PAR SMEJCT#
PCI_PERR# V16
23,26,29,30 PCI_PERR# PERR#
PCI_SERR# U16 P3
23,26,29,30 PCI_SERR# SERR# SMVC3EN JP2
P CI_FRAME# W18 V12 +3V SDW P# 12 11
23,26,29,30 PCI_FRAME# FRAME# RSV0 Wr_Pt Com
P C I_ I RDY# W17 W12 R397 10K_0402_5% 13 1 2
23,26,29,30 P C I_ IRDY# IRDY# RSV1 SD I/O
PCI_TRD Y# Y18 Y12 SD C_D1 8 R674 @0_0402_5%
23,26,29,30 PCI_TRDY# TRDY# RSV2 SD4
PCI_STOP# Y17 W11 SD C_D0 7 +3V
23,26,29,30 PCI_STOP# STOP# RSV3 SD3
PCI_DEVSEL# W16 U6 6
23,26,29,30 PCI_DEVSEL# DEVSEL# RSV4 Vss2
P CI_REQ#2_F Y16 Y4 S DCLK 5
REQ# RSV5 SDCLK

1
PCI_GNT#2 Y15 U9 +SD3_VCC 4
23 PCI_GNT#2 GNT# RSV6 Vdd
PM_CLKRUN# W19 U10 3 R191
24,26,29,30,36,39 PM_CLKRUN# CLKRUN# RSV7 Vss1
P CIRST# K20 V9 SD CMD 2 10K_0402_5%
10,13,23,26,29,30,36,39 PCIRST# PCIRST# RSV8 SD2
U4 SD C_D3 1
IDSELSM RSV9 SD1
N16 U5

2
IDSELSM RSV10
Other Pins

PC I_AD22 R405 100_0402_5% IDS ELSD M16 W4 SD C_D2 9 10 SDC D#

PC I_AD20 R403 100_0402_5% IDSE LVI IDSELSD RSV11 SD5 CARD_DET#
L16 IDSELVI RSV12 W2
PC I_AD21 R404 100_0402_5% IDS ELFL K16 V2 ALPS_SCDA1A0301
R407 IDSELFL RSV13
RSV14 U3
@100_0402_5% IRQ_SER IRQ T14 U2
23,36,39 SERIRQ IRQDT# RSV15
PCI_ PIRQA# W15 V6
16,23,30 PCI_PIRQA# INTA# RSV16
R406 PCI_ PIRQB# V14 P5
23,26 PCI_PIRQB# INTB# RSV17
PCI_PIRQC# V15 V1
23,29 PCI_PIRQC# INTC# RSV18
10K_0402_5% PCI_PIRQD# U15 V5
23,29 PCI_PIRQD# INTD# RSV19
PCM_PME# U12 V4
26,29,30,39 PCM_PME# PME# RSV20
CLK_PCI_PCM T4 V11 +3V
B 15 CLK_PCI_PCM PCICLK RSV#0 B
Y5 RP111
RSV#1
Interface
System

SUSCLK W3 V8 R441 100K_0402_5%

24 SUSCLK CLK32 RSV#2
P CLR# Y11 V7 SMD3 1 8 +3V
PCLR# RSV#3 SMD2
39 PCM_SUSP# Y6 SUSPEND# RSV#4 U7 2 7
PCM_FCMODE U13 U8 R436 100K_0402_5% SMD1 3 6
R410 100_0402_5% FCMODE RSV#5 SMD7
RSV#6 U11 4 5
RSV#7 Y3
+3V H6 W7 100K_8P4R_1206_5%
VCC RSV#8 RP53
P6 VCC
P15 VCC GPO0 V10
GPIO Interface

R5 Y10 SMD6 1 8 +3V

VCC GPO1 SMD4
R6 VCC GPO2 T10 2 7
C ARD_RST 1 2 P CLR# R7 T9 SMD5 3 6
R687 @0_0402_5% VCC GPO3 +3V SMD0
R15 VCC GPO4 W9 4 5
R16 Y9 R419 100K_0402_5%
P CIRST# VCC GPO5 R423 100K_0402_5% 100K_8P4R_1206_5%
1 2 T6 VCC GPO6 W8
R688 0_0402_5% T15 Y8 R434 100K_0402_5% +3V +3V
VCC GPO7 R435 100K_0402_5% R689
GPO8 Y7
L9 W6 100K_0402_5% RP54
GND GPO9

14

14
L10 GND
L11 T5 U55F U55C SD CMD 1 8 +SD3_VCC
GND GND SD C_D1
L12 T16 2 7

P
GND GND C ARD_RST SD C_D0
M9 GND GND W1 13 I O 12 5 I O 6 3 6
CLK_PCI_PCM M10 Power Supply W20 2 SD C_D2 4 5
GND GND

G
M11 Y2 C776
GND GND R690 100K_8P4R_1206_5%
M12 Y19

7
R445 GND GND 1U_0805_25V4Z 100K_0402_5%
33_0402_5% 1
TC6385XB_PBGA328
A A
SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
+3V POWER +3V POWER
C588

10P_0402_50V8K
Compal Electronics, Inc.
Title
CARDBUS & SD CONN (1/2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE B LA-2041 0.1
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 七月 09, 2003 Sheet 27 of 56
5 4 3 2 1
 5 4 3 2 1

RP19 RP14
U5B U38 A VCC5_EN B VCC5_EN
1 8 1 8
S2_D0 F17 A8 S1_D0 +3VALW 27 2 A VCC3_EN 2 7 B VCC3_EN 2 7
SLTB30/D0/CAD27 SLTA30/D0/CAD27 AVCC3IN AVCCOUT +S1_VCC
S2_D1 F19 D9 S1_D1 26 AEN0 3 6 BEN0 3 6
S2_D2 SLTB31/D1/CAD29 SLTA31/D1/CAD29 S1_D2 Slot A AVCCOUT 28 AEN1 BEN1
G16 SLTB32/D2/RESERVED SLTA32/D2/RESERVED B9 +5VALW 1 AVCC5IN AVCCOUT 4 5 4 5
S2_D3 E10 J3 S1_D3 3
S2_D4 SLTB2/D3/CAD0 SLTA2/D3/CAD0 S1_D4 AVCC5IN Power 47K_8P4R_1206_5% 47K_8P4R_1206_5%
C10 SLTB3/D4/CAD1 SLTA3/D4/CAD1 H5 Supply AVPPOUT 24 +S1_VPP
S2_D5 E11 H2 S1_D5 +12VALW 23
S2_D6 SLTB4/D5/CAD3 SLTA4/D5/CAD3 S1_D6 AVPPIN C542
C11 G5
S2_D7
S2_D8
S2_D9
A11
F18
F20
SLTB5/D6/CAD5
SLTB6/D7/CAD7
SLTB64/D8/CAD28
SLTB65/D9/CAD30
SLTA5/D6/CAD5
SLTA6/D7/CAD7
SLTA64/D8/CAD28
SLTA65/D9/CAD30
G3
E9
C9
S1_D7
S1_D8
S1_D9
A VCC3_EN
A VCC5_EN
AEN0
6
5
7
AVCC3_EN
AVCC5_EN
AEN0 NC0 11
1U_0805_25V4Z CARDBUS
D S2_D10 G18 A9 S1_D10 AEN1 8 25 D
S2_D11
S2_D12
S2_D13
D10
B10
D11
SLTB66/D10/CAD31
SLTB37/D11/CAD2
SLTB38/D12/CAD4
SLTB39/D13/CAD6
SLTA66/D10/CAD31
SLTA37/D11/CAD2
SLTA38/D12/CAD4
SLTA39/D13/CAD6
J2
H3
H1
S1_D11
S1_D12
S1_D13
+3VALW 13
AEN1

BVCC3IN BVCCOUT
BVCCOUT
NC1
12
14
+S2_VCC
SOCKET
S2_D14 B11 G4 S1_D14 +5VALW 15 Slot B 16
S2_D15 SLTBA40/D14/RESERVED SLTA40/D14/RESERVED S1_D15 BVCC5IN BVCCOUT
E12 SLTB41/D15/CAD8 SLTA41/D15/CAD8 G2 17 BVCC5IN Power
Supply BVPPOUT 10 JP21
+S2_VPP
S2_A0 E19 C8 S1_A0 +12VALW 9
S2_A1 SLTB29/A0/CAD26 SLTA29/A0/CAD26 S1_A1 BVPPIN C531
D20 SLTB28/A1/CAD25 SLTA28/A1/CAD25 E8
S2_A2 D18 B7 S1_A2 B VCC3_EN 20 A1 B1
S2_A3 SLTB27/A2/CAD24 SLTA27/A2/CAD24 S1_A3 B VCC5_EN BVCC3_EN 1U_0805_25V4Z a68 b68
C20 SLTB26/A3/CAD23 SLTA26/A3/CAD23 D7 19 BVCC5_EN A2 a34 b34 B2
S2_A4 C18 A6 S1_A4 BEN0 21 4 S1_WP A3 B3 S2_WP
S2_A5 SLTB25/A4/CAD22 SLTA25/A4/CAD22 S1_A5 BEN1 BEN0 GND S1_CD2# a67 b67 S2_CD2#
A18 SLTB24/A5/CAD21 SLTA24/A5/CAD21 C6 22 BEN1 GND 18 A4 a33 b33 B4
S2_A6 B18 D6 S1_A6 S1_D2 A5 B5 S2_D2
S2_A7 SLTB23/A6/CAD20 SLTA23/A6/CAD20 S1_A7 C215 S1_D10 a66 b66 S2_D10 C216
B17 SLTB22/A7/CAD18 SLTA22/A7/CAD18 B5 MIC2563A-0BSM_SSOP28 A6 a32 b32 B6
S2_A8 E14 D4 S1_A8 S1_D1 A7 B7 S2_D1
S2_A9 SLTB12/A8/CCBE#1 SLTA12/A8/CCBE#1 S1_A9 1000P_0402_50V7K S1_D9 a65 b65 S2_D9 1000P_0402_50V7K
B13 SLTB11/A9/CAD14 SLTA11/A9/CAD14 E2 A8 a31 b31 B8
S2_A10 B12 F3 S1_A10 A9 B9
S2_A11 SLTB8/A10/CAD9 SLTA8/A10/CAD9 S1_A11 S1_D0 GND GND S2_D0
D13 SLTB10/A11/CAD12 SLTA10/A11/CAD12 E4 A10 a64 b64 B10
S2_A12 A16 A4 S1_A12 S1_D8 A11 B11 S2_D8
S2_A13 SLTB21/A12/CCBE#2 SLTA21/A12/CCBE#2 S1_A13 S1_A0 a30 b30 S2_A0
C14 SLTB13/A13/CPAR SLTA13/A13/CPAR D2 A12 a63 b63 B12
S2_A14 A14 C4 S1_A14 S1_BVD1 A13 B13 S2_BVD1
S2_A15 SLTB14/A14/CPERR# SLTA14/A14/CPERR# S1_A15 +3VALW +12VALW S1_A1 a29 b29 S2_A1
C16 SLTB20/A15/CIRDY# SLTA20/A15/CIRDY# A3 A14 a62 b62 B14
S2_A16 1 2 R_S2_A16 E17 D5 R_S1_A16 1 2 S1_A16 S1_BVD2 A15 B15 S2_BVD2
R402 S2_A17 SLTB19/A16/CCLK SLTA19/A16/CCLK S1_A17 R442 S1_A2 a28 b28 S2_A2
A13 SLTB46/A17/CAD16 SLTA46/A17/CAD16 E1 A16 a61 b61 B16
33_0402_5% S2_A18 D14 D3 S1_A18 33_0402_5% A17 B17
S2_A19 SLTB47/A18/RESERVED SLTA47/A18/RESERVED S1_A19 C526 C544 C538 C537 S1_REG# GND GND S2_REG#
B14 SLTB48/A19/CBLOCK# SLTA48/A19/CBLOCK# D1 A18 a27 b27 B18
S2_A20 D15 C3 S1_A20 S1_A3 A19 B19 S2_A3
S2_A21 SLTB49/A20/CSTOP# SLTA49/A20/CSTOP# S1_A21 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0805_25V7K 0.1U_0805_25V7K S1_INPACK# a60 b60 S2_INPACK#
B15 SLTB50/A21/CDEVSEL# SLTA50/A21/CDEVSEL# C1 A20 a26 b26 B20
C S2_A22 D16 B2 S1_A22 S1_A4 A21 B21 S2_A4 C
S2_A23 SLTB53/A22/CTRDY# SLTA53/A22/CTRDY# S1_A23 S1_WAIT# a59 b59 S2_WAIT#
B16 SLTB54/A23/CFRAME# SLTA54/A23/CFRAME# B4 A22 a25 b25 B22
S2_A24 C17 C5 S1_A24 S1_A5 A23 B23 S2_A5
S2_A25 SLTB55/A24/CAD17 SLTA55/A24/CAD17 S1_A25 +5VALW S1_RST a58 b58 S2_RST
A17 SLTB56/A25/CAD19 SLTA56/A25/CAD19 A5 A24 a24 b24 B24
A25 GND GND B25
S2_BVD1 E20 B8 S1_BVD1 S1_A6 A26 B26 S2_A6
S2_BVD2 SLTB63/BVD1/CSTSCHG SLTA63/BVD1/CSTSCHG S1_BVD2 S1_VS2 a57 b57 S2_VS2
E18 SLTB62/BVD2/CAUDIO SLTA62/BVD2/CAUDIO D8 A27 a23 b23 B27
S2_CD1# G19 J1 S1_CD1# C545 C525 C543 C530 S1_A7 A28 B28 S2_A7
S2_CD2# SLTB36/CD#1/CCD#1 SLTA36/CD#1/CCD#1 S1_CD2# S1_A25 a56 b56 S2_A25
H20 SLTB67/CD#2/CCD#2 SLTA67/CD#2/CCD#2 H4 A29 a22 b22 B29
S2_RD Y# A15 B3 S1_RD Y# 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K S1_A12 A30 B30 S2_A12
S2_WAIT# SLTB16/BSY#/CINT# SLTA16/BSY#/CINT# S1_WAIT# S1_A24 a55 b55 S2_A24
C19 SLTB59/WAIT#/CSERR# SLTA59/WAIT#/CSERR# E7 A31 a21 b21 B31
S2_WP G20 A10 S1_WP S1_A15 A32 B32 S2_A15
S2_INPACK# SLTB33/WP#/CCLKRUN# SLTA33/WP#/CCLKRUN# a54 b54
D17 SLTB60/INPACK#/CREQ# SLTA60/INPACK#/CREQ# C7 S1_INPACK# A33 GND GND B33
C247 S1_A23 A34 B34 S2_A23 C248
S2_CE1# S1_CE1# S1_A16 a20 b20 S2_A16
D12 SLTB7/CE#1/CCBE#0 SLTA7/CE#1/CCBE#0 G1 A35 a53 b53 B35
S2_CE2# C12 F4 S1_CE2# 0.1U_0805_25V7K S1_A22 A36 B36 S2_A22 0.1U_0805_25V7K
S2_WE# SLTB42/CE#2/CAD10 SLTA42/CE#2/CAD10 S1_WE# +S1_VCC +S2_VCC a19 b19
C15 SLTB15/WE#/CGNT# SLTA15/WE#/CGNT# C2 +S1_VPP A37 a52/a18 b52/b18 B37 +S2_VPP
S2 _IORD# E13 F1 S1 _IORD# A38 B38
S2_IOW R# SLTB44/IORD#/CAD13 SLTA44/IORD#/CAD13 S1_IOW R# C551 C521 none none
C13 SLTB45/IOWR#/CAD15 SLTA45/IOWR#/CAD15 E3 +S1_VCC A39 a51/a17 b51/b17 B39 +S2_VCC
S2_OE# A12 F2 S1_OE# S1_A21 A40 B40 S2_A21
S2_VS1 SLTB9/OE#/CAD11 SLTA9/OE#/CAD11 S1_VS1 1U_0805_25V4Z 1U_0805_25V4Z C253 S1_RD Y# a16 b16 S2_RD Y# C254
H18 SLTB43/VS1/CVS1 SLTA43/VS1/CVS1 J4 A41 a50 b50 B41
S2_VS2 H19 J5 S1_VS2 S1_A20 A42 B42 S2_A20
S2_REG# SLTB57/VS2/CVS2 SLTA57/VS2/CVS2 S1_REG# 0.1U_0402_10V6K a15 b15 0.1U_0402_10V6K
D19 SLTB61/REG#/CCBE#3 SLTA61/REG#/CCBE#3 A7 A43 GND GND B43
S2_RST B19 B6 S1_RST S1_WE# A44 B44 S2_WE#
SLTB58/RESET/CRST# SLTA58/RESET/CRST# S1_A19 a49 b49 S2_A19
This area close to MIC2563A-0BSM A45 a14 b14 B45
B VCC3_EN J18 H17 A VCC3_EN S1_A14 A46 B46 S2_A14
B VCC5_EN VC3ENB VC3ENA A VCC5_EN S1_A18 a48 b48 S2_A18
J19 VC5ENB VC5ENA G17 A47 a13 b13 B47
BEN0 J16 J20 AEN0 S1_A13 A48 B48 S2_A13
BEN1 VPEN0B VPEN0A AEN1 S1_A17 a47 b47 S2_A17
J17 VPEN1B VPEN1A H16 A49 a12 b12 B49
B S1_A8 S2_A8 B
A50 a46 b46 B50
T13 ZVBEN ZVAEN U14 A51 GND GND B51
S1_IOW R# A52 B52 S2_IOW R#
S1_A9 a11 b11 S2_A9
+S2_VCC E15 VCCB VCCA E6 +S1_VCC A53 a45 b45 B53
F14 F5 S1 _IORD# A54 B54 S2 _IORD#
VCCB VCCA +S1_VCC S1_A11 a10 b10 S2_A11
F15 VCCB VCCA F6 A55 a44 b44 B55
F16 F7 S1_VS1 A56 B56 S2_VS1
VCCB VCCA S1_OE# a9 b9 S2_OE#
G15 VCCB VCCA G6 A57 a43 b43 B57
S1_CE2# A58 B58 S2_CE2#
C576 C575 C585 a8 b8
A19 GND GND A2 A59 GND GND B59
B20 B1 S1_A10 A60 B60 S2_A10
GND GND 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K S1_D15 a42 b42 S2_D15
E16 GND GND E5 A61 a7 b7 B61
J11 J9 S1_CE1# A62 B62 S2_CE1#
GND GND S1_D14 a41 b41 S2_D14
J12 GND GND J10 A63 a6 b6 B63
K11 Slot B Slot A K9 S1_D7 A64 B64 S2_D7
GND GND S1_D13 a40 b40 S2_D13
K12 GND GND K10 A65 a5 b5 B65
S1_D6 A66 B66 S2_D6
System +S2_VCC a39 b39
T7 TSTI0 AUDIO W5 PCM_SPK# 33 A67 GND GND B67
T8 Interface V3 S1_D12 A68 B68 S2_D12
TSTI1 ALARM S1_D5 a4 b4 S2_D5
T11 TSTI2 EXSMI# W10 A69 a38 b38 B69
T12 S1_D11 A70 B70 S2_D11
TSTI3 C557 C558 C555 S1_D4 a3 b3 S2_D4
Test Pins NC0 A1 A71 a37 b37 B71
W14 A20 S1_CD1# A72 B72 S2_CD1#
TSTO1 NC1 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K S1_D3 a2 b2 S2_D3
W13 TSTO2
NC Pins NC2 Y1 A73 a36 b36 B73
Y13 Y20 C301 A74 B74 C302
TSTO3 NC3 a1 b1
A75 a35 b35 B75
TC6385XB_PBGA328 1000P_0402_50V7K 1000P_0402_50V7K

A This area close to TC6385XB PCMC150PIN

A

Compal Electronics, Inc.

Title
CARDBUS & PCMCIA (2/2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE B LA-2041 0.1
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 七月 09, 2003 Sheet 28 of 56
5 4 3 2 1
 PCI_AD[0..31]
PCI_AD[0..31] 23,26,27,30

+3V

1 2
C346 0.1U_0402_16V4Z

U10
5

TC7SH08FU_SSOP5
39 W L_OFF# 1 MINI_PCI SOCKET
4
33,38,39 KILL_SW# 2
P CIRST#
10,13,23,26,27,30,36,39 PCIRST#
JP27
3

TIP 1 2 RING
1 2
KEY KEY
3 3 4 4
LAN RESERVED 5 6
5 6
7 7 8 8
D9 9 10 LAN RESERVED
RB751V_SOD323 9 10
11 11 12 12
+3VS_MINIPCI 1 2 13 13 14 14
15 15 16 16
L17 PCI_PIRQD# 17 18 W=30mils
23,27 PCI_PIRQD#
W=40mils 17 18 +5VS_MINIPCI
1 2 19 20 PCI_PIRQC#
+3V 19 20 PCI_PIRQC# 23,27
21 21 22 22 +3VS_MINIPCI
0_0603_5% 23 24 W=40mils
23 24 +3V
CLK_PC I_MINI 25 26 P CIRST# L30
15 CLK_PCI_MINI 25 26 W=40mils
27 27 28 28 1 2 +3V
23 PCI_REQ#1 29 29 30 30 PCI_GNT#1 23
31 32 0_0603_5%
PC I_AD31 31 32
33 33 34 34 WLANPME# 26,27,30,39
PC I_AD29 35 36
35 36 PC I_AD30
37 37 38 38
PC I_AD27 39 40
PC I_AD25 39 40 PC I_AD28
41 41 42 42
43 44 PC I_AD26
43 44 PC I_AD24
23,26,27,30 PCI_C/BE#3 45 45 46 46
PC I_AD23 47 48 MINI_ IDSEL1 2 PC I_AD18 IDSEL : PCI_AD18
47 48 R440 100_0402_5%
49 49 50 50
PC I_AD21 51 52 PC I_AD22
PC I_AD19 51 52 PC I_AD20
53 53 54 54
55 55 56 56 PCI_PAR 23,26,27,30
PC I_AD17 57 58 PC I_AD18
57 58 PC I_AD16
23,26,27,30 PCI_C/BE#2 59 59 60 60
23,26,27,30 P C I_ IRDY# 61 61 62 62
63 63 64 64 PCI_FRAME# 23,26,27,30
24,26,27,30,36,39 PM_CLKRUN# 65 65 66 66 PCI_TRDY# 23,26,27,30
23,26,27,30 PCI_SERR# 67 67 68 68 PCI_STOP# 23,26,27,30 +5VS_MINIPCI
69 69 70 70
23,26,27,30 PCI_PERR# 71 71 72 72 PCI_DEVSEL# 23,26,27,30

1
73 74 C214 C233 C598 C600
23,26,27,30 PCI_C/BE#1 PC I_AD14 73 74 PC I_AD15
75 75 76 76
77 78 PC I_AD13 @1000P_0402_50V7K @0.1U_0402_16V4Z @0.1U_0402_16V4Z @10U_1206_16V4Z

2
PC I_AD12 77 78 PC I_AD11
79 79 80 80
PC I_AD10 81 82
81 82 PCI_AD9
83 83 84 84
PCI_AD8 85 86
CLK_PC I_MINI PCI_AD7 85 86 PCI_C/BE#0 23,26,27,30
87 87 88 88
89 90 PCI_AD6
89 90
1

PCI_AD5 91 92 PCI_AD4
91 92 +3VS_MINIPCI
R449 93 94 PCI_AD2
@33_0402_5% PCI_AD3 93 94 PCI_AD0
95 95 96 96

1
W=30mils 97 98 C304 C252 C255 C243 C288 C590
+5VS_MINIPCI 97 98
PCI_AD1 99 100
2

99 100 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_1206_16V4Z

101 102
1

2
101 102
103 103 104 104
1

105 105 106 106

C593 107 108
@10P_0402_50V8K 107 108
109 110
2

109 110
111 111 112 112
113 113 114 114
115 115 116 116
117 117 118 118
119 119 120 120
121 121 122 122
+5VS 1 2 W=30mils 123 123 124 124 W=20mils
+3V
L31 0_0603_5%
2

0603 Mini-PCI SLOT C289

+5VS_MINIPCI 0.1U_0402_16V4Z
1

Compal Electronics, Inc.

Title
MINI_PCI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-2041
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: ¬P 期三, 七月 09, 2003 Sheet 29 of 56
 A B C D E

+3VS
+3VS

1 2
R526 4.7K_0402_5%
1 2 C676 C675 C683 C685 C408 C409 C671 C410
R527 10K_0402_5%
+3VS 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R524 4.7K_0402_5%
1 2
R267 4.7K_0402_5%
1 2 1 1
R269 4.7K_0402_5% +3VS

PCI_AD[0..31] U52

20
35
48
62
78

87

86
96
10
11
23,26,27,29 PCI_AD[0..31]
C403 C400 C396 C670 C672

TEST17
TEST16
CYCLEIN
VDDP
VDDP
VDDP
VDDP
VDDP

CNA
CYCLEOUT/CARDBUS
DVDD 15 +3VS
PCI_AD0 84 27 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K
PCI_AD1 PCI_AD0 DVDD
82 PCI_AD1 DVDD 39
PCI_AD2 81 51
PCI_AD3 PCI_AD2 DVDD
80 PCI_AD3 DVDD 59
PCI_AD4 79 72
PCI_AD5 PCI_AD4 DVDD L18
77 PCI_AD5 DVDD 88
PCI_AD6 76 100 BLM21A601SPT_0805
PCI_AD7 PCI_AD6 DVDD 1394_PLLVDD 0.01U_0402_25V4Z
74 PCI_AD7 PLLVDD 7 1 2 +3VS
PCI_AD8 71 1
PCI_AD9
PC I_AD10
70
69
PCI_AD8
PCI_AD9
TSB43AB21 AVDD
AVDD 2
107
C407 C404

PC I_AD11
PC I_AD12
67
66
PCI_AD10
PCI_AD11
/(TSB43AB22) AVDD
AVDD 108
120
4.7U_0805_10V4Z

PC I_AD13 PCI_AD12 AVDD

65 PCI_AD13
PC I_AD14 63 PCI_AD14
PCI BUS INTERFACE
PC I_AD15 61 106 1 2
PC I_AD16 PCI_AD15 CPS R545 1K_0402_5%
46 PCI_AD16
PC I_AD17 45
PC I_AD18 PCI_AD17
43 PCI_AD18 NC/(TPBIAS1) 125
PC I_AD19 42 124
PC I_AD20 PCI_AD19 NC/(TPA1+)
41 PCI_AD20 NC/(TPA1-) 123
PC I_AD21 40 122
2 PC I_AD22 PCI_AD21 NC/(TPB1+) 2
38 PCI_AD22 NC/(TPB1-) 121
PC I_AD23 37
PC I_AD24 PCI_AD23
32 PCI_AD24 BIAS CURRENT R0 118
PC I_AD25 31
PC I_AD26 PCI_AD25 R564
IDSEL:PCI_AD16 29 PCI_AD26
PC I_AD27 28 6.34K_0603_1%
PC I_AD28 PCI_AD27
26 PCI_AD28
PC I_AD16 1 2 1394_IDSEL PC I_AD29 25 119
R563 100_0402_5% PC I_AD30 PCI_AD29 R1
24 PCI_AD30
PC I_AD31 22 6 C702
PCI_AD31 OSCILLATOR X0

2
PCI_C/BE#3 34 22P_0402_50V8J
23,26,27,29 PCI_C/BE#3 PCI_C/BE3
PCI_C/BE#2 47 X7
23,26,27,29 PCI_C/BE#2 PCI_C/BE2
PCI_C/BE#1 60 24.576MHz_16P_3XG-24576-43E1
23,26,27,29 PCI_C/BE#1 PCI_C/BE1
PCI_C/BE#0 73 5
23,26,27,29 PCI_C/BE#0

1
CLK_PCI_1394 PCI_C/BE0 X1
15 CLK_PCI_1394 16 PCI_CLK
PCI_GNT#0 18 C700
23 PCI_GNT#0 PCI_GNT
P CI_REQ#0 19 3 C694 22P_0402_50V8J
23 PCI_REQ#0
1394_IDSEL PCI_REQ FILTER FILTER0
36 PCI_IDSEL
P CI_FRAME# 49 4 0.1U_0402_16V4Z
23,26,27,29 PCI_FRAME# PCI_FRAME FILTER1
P C I_ I RDY# 50
23,26,27,29 P C I_ IRDY# PCI_IRDY
PCI_TRD Y# 52 92 1 2
23,26,27,29 PCI_TRDY#
PCI_DEVSEL# PCI_TRDY EEPROM 2 WIRE BUS SDA R525 220_0402_5%
23,26,27,29 PCI_DEVSEL# 53 PCI_DEVSEL
PCI_STOP# 54 91 1 2
23,26,27,29 PCI_STOP# PCI_STOP SCL 220_0402_5%
PCI_PERR# 56 R521 C684
23,26,27,29 PCI_PERR# PCI_PERR
PCI_ PIRQA# 13 POWER CLASS 99 R562 R561
16,23,27 PCI_PIRQA# PCI_INTA/CINT PC0
1394_PME# 21 98 56.2_0603_1% 56.2_0603_1% 0.33U_0603_16V4Z
26,27,29,39 1394_PME# PCI_PME/CSTSCHG PC1
PCI_SERR# 57 97
23,26,27,29 PCI_SERR# PCI_SERR PC2
PCI_PAR 58 JP35
23,26,27,29 PCI_PAR PCI_PAR
12 116 TPBIAS0
3 24,26,27,29,36,39 PM_CLKRUN#
P CIRST# PCI_CLKRUN PHY PORT 1 TPBIAS0 TPA0+ 3
10,13,23,26,27,29,36,39 PCIRST# 85 PCI_RST TPA0+ 115 4 4
114 TPA0- 3
TPA0- TPB0+ 3
TPB0 + 113 2 2
112 TPB0- 1
TPB0 - 1

SUYIN_020204FR004S507ZL
94 R557 R558
TEST9
TEST8 95 56.2_0603_1% 56.2_0603_1%
14 G_RST
TEST3 101
CLK_PCI_1394
PLLGND1

89 102
REG_EN

GPIO3 TEST2
90 104
REG18

REG18

GPIO2 TEST1
DGND
DGND

DGND
DGND
DGND
DGND
DGND
DGND
DGND

DGND
1

AGND
AGND
AGND
AGND
AGND
AGND
AGND

TEST0 105
R583 C681
@10_0402_5% R556
2

220P_0402_50V8K 5.11K_0603_1%
8
9
109
110
111
117
126
127
128
17
23
30
33
44
55
64
68
75
83
93
103

R516 R523 TSB43AB21_PQFP128

2

220_0402_5% 220_0402_5%

C696
1

@10P_0402_50V8K

C695 C668

0.1U_0402_16V4Z 0.1U_0402_16V4Z

4 4

Compal Electronics, Inc.

Title
1394 Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE B LA-2041 0.1
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 七月 09, 2003 Sheet 30 of 56
A B C D E
 5 4 3 2 1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
AC97 Codec PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Adjustable Output
2 1 +5VALW
R624 6.8K_0402_5% U22
2 1 4 5 +VDDA
R621 6.8K_0402_5% VIN VOUT +VDDA

2
2 1 LINEIN_L C432 C434 2 6
33 LINE_IN_L DELAY SENSE or ADJ
R623 6.8K_0402_5% C741 1U_0603_10V6K R279 C431
D 2 1 L INEIN_R 4.7U_0805_10V4Z 0.1U_0402_16V4Z 7 1 4.7U_0805_10V4Z D
33 LINE_IN_R ERROR CNOISE
R622 6.8K_0402_5% C738 1U_0603_10V6K 100K_0603_1%
34,39,40,41,49,50,51,52 SUSP# 8 3

1
SD GND C433
SI9182DH-AD_MSOP8
0.1U_0402_16V4Z

2
R278

33K_0603_1%
+AVDD_AC97

1
L36

+VDDA 1 2

CHB2012U170_0805 +5VCD POWER ON PATH

+VDDC
C737 C742
+V DDC C693 0.1U_0402_16V4Z
+3VS
0.1U_0402_16V4Z 10U_1206_16V4Z C709

14
1U_0603_10V6K
C747 C749 R_ INT_CD_L 1 2 CDROM_L
35 INT_CD_L
0.1U_0402_16V4Z 10U_1206_16V4Z

13
+AUD_VREF U53A
74HCT4066
U58

25

38
2

9
C R634 C731 1000P_0402_50V7K C

AVDD1

AVDD2

DVDD1

DVDD2
@0_0402_5% +5VCD
C732 1000P_0402_50V7K

14
1

14 35 LINEL C728 4.7U_0805_10V4Z EQ_LEFT

AUX_L LINE_OUT_L EQ_LEFT 32,33
R_INT _CD_R 11 10 CD ROM_R
35 INT_CD_R
C748 15 36 L INER C727 4.7U_0805_10V4Z EQ_RIGHT C690 1U_0603_10V6K
AUX_R LINE_OUT_R EQ_RIGHT 32,33
0.1U_0402_16V4Z

12
16 37 U53B
VIDEO_L MONO_OUT 74HCT4066
17 39 DM_ON#
VIDEO_R TRUE_LOUT_L
2 1
R631 6.8K_0402_5% LINEIN_L 23 41 1 2
LINE_IN_L TRUE_LOUT_R C752 15P_0402_50V8J +5VCD
2 1
R625 6.8K_0402_5% L INEIN_R 24 DIRECT PLAY PATH
LINE_IN_R

14
BIT_CLK 6 1 2 ICH_AC_BITCLK 24,38
CDROM_L 2 1 CD _L_R 18 R632 22_0402_5% 1 2
R630 20K_0402_5% C746 1U_0603_10V6K CD_L R638 @10K_0402_5% R_ INT_CD_L EQ_LEFT
SDATA_IN 8 1 2 ICH_AC_SDIN0 24 +2.5VOP_REF 2 1 4 3
CD ROM_R 2 1 CD_R_R 20 R636 22_0402_5% R601 10K_0402_5%
R626 20K_0402_5% C744 1U_0603_10V6K CD_R U53C
2

5
XTL_IN

2
CD_ GNA 19 74HCT4066
C751 0.01U_0402_25V4Z C745 1U_0603_10V6K CD_GND R280 X1
MIC C_M IC 21 1 2
33 MIC MIC1
2 1 C743 1U_0603_10V6K @1M_0402_5%
R635 10K_0402_5% 22 3 1 24.576MHz_16P_3XG-24576-43E1 1
+AUD_VREF

1
MIC2 XTL_OUT C435 C436 +5VCD
2 1 C_MD_SPK 13 29 C734 1000P_0402_50V7K
38 MD_SPK PHONE AFILT1
R637 10K_0402_5% C750 1U_0603_10V6K 22P_0402_25V8K 22P_0402_25V8K

14
C733 1000P_0402_50V7K 2 2
33 MONO_IN 12 PC_BEEP AFILT2 30
B B
+2.5VOP_REF 2 1 R_INT _CD_R 8 9 EQ_RIGHT
28 1 2 R581 10K_0402_5%
VREFOUT +AUD_VREF
2 1 11 R617 0_0402_5% U53D
24,38 ICH_AC_RST#

6
R633 100_0402_5% RESET# 74HCT4066
VREF 27
24,38 IC H _AC_SYNC 10 SYNC
32 C736 C729 DM_ON
VRDA
24,38 ICH_AC_SDOUT 5 SDATA_OUT 0.1U_0402_16V4Z 4.7U_0805_10V4Z
45 NC VRAD 31
46 33 1 2 C735 C723
XTLSEL DCVOL R616 @0_0402_5%
VAUX 34
47 43 0.01U_0402_25V4Z 1U_0603_10V6K
33 EAPD EAPD GPIO0 +5VCD
GPIO1 44
48 C724
SPDIFO
NC 40
2

4 26 AG ND 1U_0603_10V6K
DVSS1 AVSS1 R579
7 DVSS2 AVSS2 42
R627 100K_0402_5%
@0_0402_5%
1

ALC202_E_LQFP48
DGND AGND DM_ON#

1
D
+AUD_VREF DM_ON 2 Q61
34 DM_ON
1 2 G 2N7002_SOT23
R281 0_0603_5% S

3
A 2 1 CD_ GNA DM_ON H DIRECT CD A
1 2 35 CD_AGND R628
R272 0_0603_5% 20K_0402_5% DM_ON L SYSTEM ON
1

C717
R472 R629 C726
1 2 0.1U_0402_16V4Z 4.7U_0805_10V4Z
R277 0_0603_5% 0_0402_5% 6.8K_0402_5%
Compal Electronics, Inc.
2

Title
AC97 Codec
Size Document Number R ev
DGND AGND B 0.1
LA-2041
D ate: ¬P 期三, 七月 09, 2003 Sheet 31 of 56
5 4 3 2 1
 5 4 3 2 1

+5VCD +5VCD

+5VCD

C423 C422 C730

C425 100P_0402_50V8K
4.7U_0805_10V4Z 0.1U_0402_16V4Z
BTQ00 EQ Circuit UPDATA 03/26
0.1U_0402_16V4Z
1 2
R619
1.5K_0603_1%

4
C725 U57A

4
D 0.018U_0603_16V7K U56A 2 D

P
EQ_LEFT EQ_L_IN1# -
1 2 2 1AMP_LEFT_1 1 2AMP_LEFT

P
- O AMP_LEFT 33
R613 11.8K_0603_1% 1 EQ_L_OUT1 1 2 EQ_L_IN5 3 R684 0_0402_5%
O +

G
EQ_L_IN1 3 R612 4.99K_0603_1%
+

G
C718 LMV824MT_TSSOP14

11
1
0.018U_0603_16V7K LMV824MT_TSSOP14 OUTPUT TO AMPLIFIER

11
R614 C721 0.082U_0402 C704 4700P_0402_25V7K C701 1500P_0402_50V7K
107K_0603_1% 1 2 1 2 1 2
LEFT CHANNEL
R607 R598 R594
3.32K_0603_1% +5VCD 2.49K_0603_1% +5VCD 1.65K_0603_1%

2
+2.5VOP_REF +5VCD
C720 C705

4
1800P_0402_50V7K U56B C703 390P_0603_50V7K U56C U56D
6 9 390P_0603_50V7K 13

P
- EQ_L_OUT2 - EQ_L_OUT3 -
O 7 OUT 8 OUT 14 EQ_L_OUT4
EQ_L_IN2 5 EQ_L_IN3 10 EQ_L_IN4 12
AUDIO LEFT CHANNEL + + +

G
1
LMV824MT_TSSOP14 LMV824MT_TSSOP14 LMV824MT_TSSOP14

11

11

11
1

1
R589
R618 R590 100K_0603_1%
200K_0603_1%
200K_0603_1%

2
+2.5VOP_REF

2
+2.5VOP_REF +2.5VOP_REF

C C
BY-PASS EQ CIRCUIT +5VCD

+5VCD

4
EQ_LEFT 2 1 AMP_LEFT U57D
31,33 EQ_LEFT R609 @0_0402_5% 13

P
-

1
EQ_RIGHT 2 1 AMP_RIGHT +5VCD 14
31,33 EQ_RIGHT R608 @0_0402_5% R595 OUT
12 +

G
+2.5VOP_REF

4
100K_0603_1% U57C LMV824MT_TSSOP14

11
9

P
2
+5VCD -
OUT 8
10 +

G
+5VCD LMV824MT_TSSOP14 C722

11
1
C421 C418 100P_0402_50V8K
C708 R596
4.7U_0805_10V4Z 4.7U_0805_10V4Z
C420 0.1U_0402_16V4Z 100K_0603_1% 1 2
R620

2
0.1U_0402_16V4Z 1.5K_0603_1%

+5VCD

4
C719 U57B
4

0.018U_0603_16V7K U54A 6

P
EQ_RIGHT E Q_R_IN1# -
1 2 2 7AMP_RIGHT_1 1 2AMP_RIGHT
P

- O AMP_RIGHT 33
R603 11.8K_0603_1% 1 EQ_R_OUT1 1 2 EQ _R_IN5 5 R685 0_0402_5%
O +

G
B EQ _R_IN1 R600 4.99K_0603_1% B
3 +
G

C710 LMV824MT_TSSOP14

11
1

0.018U_0603_16V7K LMV824MT_TSSOP14 C713 0.082U_0402 C688 4700P_0402_25V8K OUTPUT TO AMPLIFIER

11

R606 C706 1500P_0402_50V7K

107K_0603_1% 1 2 1 2 1 2
RIGHT CHANNEL
R602 R586 R597
3.32K_0603_1% +5VCD 2.49K_0603_1% +5VCD 1.65K_0603_1%
2

+2.5VOP_REF +5VCD
C712 C707
4

4
1800P_0402_50V7K U54B C689 390P_0603_50V7K U54C 390P_0603_50V7K U54D
6 9 13
P

P
- - -
7EQ_R_OUT2 8 EQ_R_OUT3 14 EQ_R_OUT4
AUDIO RIGHT CHANNEL EQ _R_IN2 5 +
O EQ _R_IN3 10 +
OUT EQ _R_IN4 12 +
OUT
G

G
1
LMV824MT_TSSOP14 LMV824MT_TSSOP14 LMV824MT_TSSOP14
11

11

11
1

R584
R615 R585 100K_0603_1%
200K_0603_1% 200K_0603_1%

2
+2.5VOP_REF
2

+2.5VOP_REF +2.5VOP_REF

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
HAREWARE EQ
PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE B 0.1
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-2041
D ate: ¬P 期三, 七月 09, 2003 Sheet 32 of 56
5 4 3 2 1
 A B C D E

Audio AMP
+5VCD +5VCD

1
W=40Mil
R661
100K_0402_5%

1
C760
C761

2
0.1U_0402_16V4Z 4.7U_0805_10V4Z SHUTDOW N#

1
D
4 Q66 2 4
EAPD 31
HIGH PIN 4,10 ACTIVE G
NBA_PLUG 2N7002_SOT23 S

3
LOW PIN 5,9 ACTIVE
U59
3 15 R662
NBA_PLUG PVDD SHUTDOWN# NBA_PLUG
11 PVDD SE/BTL# 23 1 2 +5VCD
R604 7 17
@100K_0402_5% VDD BYPASS INTSPK_L2 100K_0402_5%
LOUT- 12
1 2 22 2 INTSPK_R2
VOL_AMP HP/LINE# ROUT-
21 VOLUME LIN 8
INTSPK_L1 14 6
0.47U_0603_16V4Z INTSPK_R1 0.47U_0603_16V4Z LOUT+ RIN
24 ROUT+
C762 1 2AMP_LEFT_1 1 2 C763 9 19 2
32 AMP_LEFT LLINEIN SEMAX

2
5 20 C767 C768
RLINEIN SEDIFF
32 AMP_RIGHT 1 2AMP_RIGHT_1 1 2 0.47U_0603_16V4Z 10 LHPIN
C766 0.47U_0603_16V4Z
C764 C765 4 1 1U_0603_10V4Z

1
0.47U_0603_16V4Z RHPIN PGND 1 0.47U_0603_16V4Z
PGND 13
16 FADE# AGND 18
C769 1 2 0.47U_0603_16V4Z
31,32 EQ_LEFT (0.47U~1U)
TPA6011A4_TSSOP24
C770 1 2 0.47U_0603_16V4Z
31,32 EQ_RIGHT
+5VCD +5VCD

1
C771 Enable Gain
R663 R664
soft start

1
0.1U_0402_16V4Z @10K_0402_5% 10K_0402_1%

2
R665 R666 SET SE MODE MAX

2
3 @820_0402_5% @820_0402_5% 3
2 2.7V--- (-4dB)

1
SET SE MODE MAX R667 R668
10K_0402_5% 11.8K_0603_1%
2.94V---0dB

2
JP9
INTSPK_R1
INTSPK_R2 1
2
fo=1/(2*3.14*R*C)=412Hz MOLEX_53398-0290
R=820 / C=0.47U

R697(1.5K)----------10dB
AUDIO Board Conn. R698(300)----------14dB

+3V +3V
39 BEEP# 1 2
C699 +VDDA R698 300_0402_5%
1

0.1U_0402_16V4Z +5VCD 1 2 16
R593 R697 @1.5K_0402_1% 16
+AVDD_AC97 15 15
1

2 2
+AUD_VREF 14 14
100K_0402_5% R640 NBA_PLUG 13
10K_0402_5% VOL_AMP 13
10

14

12
2

U55A R610 12
11 11
C715 560_0402_5% MIC 10
OE#

31 MIC 10
9 I O 8 1 2 1 I O 2 1 2 9 9
R599 LINE_IN _R 8
31 LINE_IN_R 8
G

8.2K_0402_5% 1U_0603_10V6K LINE _IN_L 7

31 LINE_IN_L 7
U51C R641 C754 6
7

+3V POWER +3V POWER 10K_0402_5% 10U_1206_16V4Z INTSPK_R1 6

5 5
SN74LVC125APWLE_TSSOP14 C714 INTSPK_L2 4
SN74LVC14APWLE_TSSOP14 C753 INTSPK_L1 4
3
2

1U_0603_10V6K KILL_SW# 3
29,38,39 KILL_SW# 2 2
0.22U_0603_16V4Z MO NO_IN 1
MONO_IN 31 1
R447
1

C587 560_0402_5% C Q63 1 2 JP10

+3V
1 2 2 R669 100K_0402_5% ACES_85201-1605
28 PCM_SPK# B 2SC2411K_SOT23 R639
1U_0603_10V6K E 2.4K_0402_5%
3

+3V
14

R611
C716 560_0402_5%
P

24 SPKR 3 I O 4 1 2
G

1
U55B 1U_0603_10V6K 1
1

SN74LVC14APWLE_TSSOP14 D35
7

+3V POWER R642

RB751V_SOD323
10K_0402_5%
2

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
AMP & Audio Jack
PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE B LA-2041 0.1
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 七月 09, 2003 Sheet 33 of 56
A B C D E
 L35
CDD[0..15] CHB1608G301_0603
35 CDD[0..15] +5VOZ 1 2

1 2 +5VCD
+5VOZ L34

1
C673 C662 C641 C642 CHB1608G301_0603

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2
U46

44

58
9
OZ168T-A1_TQFP100

VDD

VDD

VDD
+5VALW
24,35 IDE_SDD[0..15]
IDE_ SDD0 76 77 C DD0
IDE_ SDD1 HDD0 CDD0 C DD1
78 HDD1 CDD1 79
IDE_ SDD2 81 82 C DD2
HDD2 CDD2

2
IDE_ SDD3 83 84 C DD3 C606 C609
IDE_ SDD4 HDD3 CDD3 C DD4
86 HDD4 CDD4 87
IDE_ SDD5 90 91 C DD5 10U_1206_16V4Z 1U_0805_25V4Z

1
IDE_ SDD6 HDD5 CDD5 C DD6
95 HDD6 CDD6 96
IDE_ SDD7 97 98 C DD7 +5VCD
IDE_ SDD8 HDD7 CDD7 C DD8
2 HDD8 CDD8 1
IDE_ SDD9 4 3 C DD9
IDE _SDD10 HDD9 CDD9 CDD 10
8 HDD10 CDD10 7
IDE _SDD11 11 10 CDD 11 U43
HDD11 CDD11

1
IDE _SDD12 15 14 CDD 12 1 8 C608 C604
HDD12 CDD12 +5VALW S D
IDE _SDD13 18 17 CDD 13 2 7
IDE _SDD14 HDD13 CDD13 CDD 14 S D 10U_1206_16V4Z 0.1U_0402_16V4Z
20 19 3 6

2
IDE _SDD15 HDD14 CDD14 CDD 15 S D
22 HDD15 CDD15 21 +5VALW 1 2 4 G D 5
R470 240K_0402_5%
SI4425DY-T1_SO8
ID E_SDA0 68 69 CD_SBA0
24,35 IDE_SDA0 HDA0 CDA0 CD_SBA0 35
ID E_SDA1 70 71 CD_SBA1 2 1 2 1
24,35 IDE_SDA1 HDA1 CDA1 CD_SBA1 35
ID E_SDA2 66 67 CD_SBA2 C611 1U_0805_25V4Z R469
24,35 IDE_SDA2 HDA2 CDA2 CD_SBA2 35

1
10K_0402_5%
ID E_SDCS1# 63 64 C D_SCS1#
24,35 IDE_SDCS1# HCS0 CCS0 CD_SCS1# 35
ID E_SDCS3# 61 62 C D_SCS3#
24,35 IDE_SDCS3# HCS1 CCS1 CD_SCS3# 35
SUSP# 22K 22K CD_PLAY
31,39,40,41,49,50,51,52 SUSP# 2 2 CD_PLAY 39
IDE_SD IOR# 99 100 CD_S IOR# 22K 22K
24,35 IDE_SDIOR# HDIOR# CDIOR# CD_SIOR# 35
IDE_ SDIOW # 6 5 CD _SIOW #
24,35 IDE_SDIOW # HDIOW# CDIOW# CD_SIOW # 35
72 73 CIOCS16#
HIOCS16# CIOCS16# C D _ S IORDY Q46 Q44
24,35 ID E _ SDIORDY 93 94 C D _ S IORDY 35

3
HIORDY CIORDY @DTC124EK_SOT23 DTC124EK_SOT23

X4 IDE_IRQ15 74 75 C D_IRQ
23,35 IDE_IRQ15 HINTRQ CHINTRQ C D _IRQ 35
8MHZ_16PF_7D08000014 IDE_S DDREQ 12 13 CD_D REQ
24,35 IDE_SDDREQ HDMARQ CDMARQ CD_DREQ 35
OSC1 OSC2 IDE_ SDDACK# 88 89 CD_ DACK#
24,35 IDE_SDDACK# HDMACK# CHDMACK# CD_DACK# 35

SIDE_RST# 24 23 C D_RSTDRV#
35 SIDE_RST# HRESET# CRESET# CD_RSTDRV# 35
R510 59 60 CDA SPN
HDASPN CDASPN
48 HSYNC SSYNC 47
1M_0402_5% 53 52
HBIT_CLK SBIT_CLK +5VCD
55 HDATA_OUT SDATA_OUT 54
1

50 HDATA_IN SDATA_IN 49
C651 C659 46 45 R538
10P_0402_50V8K 10P_0402_50V8K HACRSTN SACRSTN +5VCD
2 1 RP83
2

DM_ON 28 @10K_0402_5% REVBTN# 8 1

PLAYBTN# PAV_EN R539 FR DBTN#
36 PLAY/PAUSE PWR_CTL 51 2 1 7 2
FR DBTN# 35 10K_0402_5% PLAYBTN# 6 3
REVBTN# FFORWARD STOPBTN#
34 REWIND 1 2 MEDIA_DETECT 39 5 4
STOPBTN# 37 80 1 2 ISCD ROM R518 0_0402_5%
STOP/EJECT ISCDROM R514 @0_0402_5% 10K_8P4R_1206_5%
39 GPIO_1
C3651 GPIO[1]/VOL_UP
210U_1206_16V4Z DM_ON 29 PCSYSTEM_OFF GPIO[0]/VOL_DN 40 GPIO_0 RP84
25 INTN 8 1
2 1 30 MODE1 7 2
+5VCD R498 10K_0402_5% RESET# R532 1
MODE0 56 2 @1K_0402_5% CDA SPN 6 3
1 2 Q50 57 MODE1 ISCD ROM 5 4
D31 MODE1
1 3 2N7002 26
D

5,39 EC_SMB_DA2 SDATA

1N4148_SOT23 10K_8P4R_1206_5%
PAVMODE 38 2 1
27 R235 10K_0402_5% GPIO_0 R244 2 1 10K_0402_5%
G
2

SCLK GPIO_1 R237 2

1 3 41 1 10K_0402_5%
D

5,39 EC_SMB_CK2 CSN

INCN 42
1

Q49 OSC1 31 43
2N7002 R496 OSC2 OSCI UDN +5VCD
32
G
2

OSCO
GND
GND
GND
GND
GND

R497
100K_0402_5% +5VCD
2

C D _ S IORDY 1 2
+5VCD
16
33
65
85
92

100K_0402_5% DM_ON H DIRECT CD R509 1K_0402_5%

1
C D_IRQ 1 2
R228 DM_ON L SYSTEM ON R534 4.7K_0402_5%
100K_0402_5%
CIOCS16# 1 2
R533 47K_0402_5%
2

DM_ON C DD7 2 1
DM_ON 31
R506 10K_0402_5%
1

D Q14 CD_D REQ 1 2

SUSP# 2 R495 5.6K_0402_5%
G 2N7002
S
3

Compal Electronics, Inc.

Title
OZ-168 CD_PLAY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-2041
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: ¬P 期三, 七月 09, 2003 Sheet 34 of 56
 IDE,CD-ROM Module CONN.
HDD CONNECTOR Placea caps. near HDD
CONN.
IDE_PDD[0 ..15] C645 +5VS
24 IDE_PDD[0..15]
0.1U_0402_16V4Z
+5VS

U47

5
JP34
PIDE_RST# C654 C656 C657 C655 C653 B_PCIRST# 1
1 2 16,23 B_PCIRST#
IDE_ PDD7 IDE_ PDD8 4 PIDE_RST#
IDE_ PDD6 3 4 IDE_ PDD9 1000P_0402_50V7K 10U_1206_16V4Z 10U_1206_16V4Z 1U_0805_25V4Z 0.1U_0402_16V4Z
5 6 23 PIDERST# 2
IDE_ PDD5 IDE _PDD10
IDE_ PDD4 7 8 IDE _PDD11

3
IDE_ PDD3 9 10 IDE _PDD12 TC7SH08FU_SSOP5
IDE_ PDD2 11 12 IDE _PDD13
IDE_ PDD1 13 14 IDE _PDD14
IDE_ PDD0 15 16 IDE _PDD15
17 18
IDE_P DDREQ 19 20
24 IDE_PDDREQ 21 22 +5VS
IDE_ PDIOW # C652
24 IDE_PDIOW # 23 24
IDE_PD IOR# 0.1U_0402_16V4Z
24 IDE_PDIOR# 25 26
24 ID E _ PDIORDY 27 28
PCSEL 1 2 EXTID1 EXTID0 Module
R236 470_0402_5%
24 IDE_PDDACK# 29 30
23 IDE_IRQ14
IDE_IRQ14
31 32
0 0 CDROM U48

5
ID E_PDA1
24 IDE_PDA1 33 34
24 IDE_PDA0
ID E_PDA0
35 36
ID E_PDA2
IDE_PDA2 24
0 1 FDD B_PCIRST# 1
ID E_PDCS1# ID E_PDCS3# 4 SIDE_RST#
24 IDE_PDCS1# 37 38 IDE_PDCS3# 24 SIDE_RST# 34
39 PHDD_LED# 39 40
1 0 HDD 24 SIDERST# 2
+5VS 41 42 +5VS
1 2 1 1 TV Tuner/No Module

3
+5VS R259 100K_0402_5% 43 44 TC7SH08FU_SSOP5

OCTEK AFH-22DC

EXTID3 EXTID2 Module

0 0 CDROM
0 1 FDD
1 0 HDD
1 1 TV Tuner/No Module

Main Module Conn. (Master) IDE_SDD[0 ..15]

2nd Module Conn. (Slave)
CDD[0..15] 24,34 IDE_SDD[0..15]
34 CDD[0..15]
JP29
JP28
IN T_CD_L INT_ CD_R 1 2
31 INT_CD_L 1 2 INT_CD_R 31 3 4
CD_A GND CD_A GND SIDE_RST# IDE_ SDD8
31 CD_AGND 3 4 5 6
C D_RSTDRV# C DD8 IDE_ SDD7 IDE_ SDD9
34 CD_RSTDRV# 5 6 7 8
C DD7 C DD9 IDE_ SDD6 IDE _SDD10
C DD6 7 8 CDD 10 IDE_ SDD5 9 10 IDE _SDD11
C DD5 9 10 CDD 11 IDE_ SDD4 11 12 IDE _SDD12
C DD4 11 12 CDD 12 IDE_ SDD3 13 14 IDE _SDD13
C DD3 13 14 CDD 13 IDE_ SDD2 15 16 IDE _SDD14
C DD2 15 16 CDD 14 IDE_ SDD1 17 18 IDE _SDD15
C DD1 17 18 CDD 15 IDE_ SDD0 19 20 IDE_S DDREQ
19 20 21 22 IDE_SDDREQ 24,34
C DD0 CD_D REQ PDIAG IDE_SD IOR#
21 22 CD_DREQ 34 23 24 IDE_SDIOR# 24,34
PDIAG CD_S IOR# IDE_ SDIOW # IDE_ SDDACK#
23 24 CD_SIOR# 34 24,34 IDE_SDIOW # 25 26 IDE_SDDACK# 24,34 +5VCD
CD _SIOW # CD_ DACK# ID E _ SIORDY ID E_SDA2
34 CD_SIOW # 25 26 CD_DACK# 34 24,34 ID E _ SDIORDY 27 28 IDE_SDA2 24,34
C D _ S IORDY CD_SBA2 IDE_IRQ15 ID E_SDCS3#
34 C D _ S IORDY 27 28 CD_SBA2 34 23,34 IDE_IRQ15 29 30 IDE_SDCS3# 24,34
C D_IRQ C D_SCS3# ID E_SDA1 EXTID2
34 C D _IRQ 29 30 CD_SCS3# 34 24,34 IDE_SDA1 31 32 EXTID2 39
CD_SBA1 EXTID0 ID E_SDA0 EXTID3
34 CD_SBA1 31 32 EXTID0 39 24,34 IDE_SDA0 33 34 EXTID3 39

2
CD_SBA0 EXTID1 ID E_SDCS1#
34 CD_SBA0 33 34 EXTID1 39 24,34 IDE_SDCS1# 35 36
C D_SCS1# SH DD_LED# R464
34 CD_SCS1# 35 36 37 38
SH DD_LED# HDSEL# EXTCSEL2 100K_0402_5%
37 38 HDSEL# 36 39 40
2 1 EXTCSEL1 39 40
WGATE#
WGATE# 36 41 42
R471 470_0402_5% USBP3+
USBP3+ 24

1
41 42 USBP7+ 43 44 USBP3- SH DD_LED#
43 44 USBP7+ 24 45 46 USBP3- 24 SHDD_LED# 39
RDATA# USBP7-
36 RDATA# 45 46 USBP7- 24 47 48
WP#
36 WP# 47 48 49 50
TRACK0# F D D IR#
36 TRACK0# 49 50 F D D IR# 36 51 52
WDATA# 3MODE#
36 WDATA# 51 52 3MODE# 36 53 54
STEP#
36 STEP# 53 54 55 56
MTR0#
36 MTR0# 55 56 57 58
DS KCHG# INDEX#
36 DSKCHG# 57 58 INDEX# 36 59 60 +5VS
D RV0#
36,39 DRV0# 59 60 +5VCD
SUYIN_100311MB060S106ZU
SUYIN_100311MB060S106ZU

+5VS
+5VCD +5VS
+3VALW
2

W=80mils W=80mils RP82

R467 EXTID0 8 1
C612 C610 C616 C613 100K_0402_5% C615 C617 C620 C614 EXTID1 7 2
EXTID2 6 3
1000P_0402_50V7K 10U_1206_16V4Z 1U_0805_25V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K 10U_1206_16V4Z 1U_0805_25V4Z 0.1U_0402_16V4Z EXTID3 5 4
1

1 2 EXTCSEL2
R468 470_0402_5% 10K_8P4R_1206_5%
1

Place component's closely MODULE CONNECTOR. D Place component's closely MODULE CONNECTOR.
2 EXTID0
G
+5VS RP139 S Q45
Compal Electronics, Inc.
3

RP138 STEP# 6 5 2N7002_SOT23

+5VS
1 8 MTR0# WDATA# 7 4 WP#
2 7 DS KCHG# F D D IR# 8 3 RDATA# Title
3 6 INDEX# TRACK0# 9 2 WGATE# IDE/ FDD MODULE CONN.
4 5 D RV0# 10 1 HDSEL#
+5VS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1K_8P4R_1206_5% B LA-2041 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1K_10P8R_1206_5%
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 七月 09, 2003 Sheet 35 of 56
 A B C D E

SUPER I/O SMsC FDC47N227 +3VS

1 1

1
R209
10K_0402_5%
LPC_A D[0..3] LPD[0 ..7]
13,24,39 LPC_AD[0..3] LPD[0..7] 38

2
U8
LPC_AD0 20 68 LPD0
LPC_AD1 LAD0 PD0/INDEX# LPD1
21 LAD1 PD1/TRK0 69
LPC_AD2 22 70 LPD2
LPC_AD3 LAD2 PD2/WRTPRT# LPD3
23 LAD3 PD3/RDATA# 71
72 LPD4
PD4/DSKCHG# LPD5
13,24,39 LPC_FRAME# 24 LFRAME# PD5 73
25 74 LPD6
24 LPC_DRQ#1 LDRQ# PD6/MTR0#
75 LPD7
PD7
10,13,23,26,27,29,30,39 PCIRST# 26 PCIRST#
27 79 L PTBUSY
LPCPD# BUSY/MTR1# LPTPE LPTBUSY 38
PE/WDATA# 78 LPTPE 38
R195 2 1 10K_0402_5% 50 77 LPTSLCT
+3VS R212 2 GPIO12/IO_SMI# SLCT/WGATE# LPTSLCT 38
1 10K_0402_5% 17 IO_PME# ERROR#/HDSEL# 81 LPTERR#
LPTERR# 38
30 80 LPTACK#
23,27,39 SERIRQ SIRQ ACK#/DS1# LPTACK# 38
CLK_14M_SIO 28 66
24,26,27,29,30,39 PM_CLKRUN# CLKRUN# INIT#/DIR# INIT# 38
CLK _PCI_SIO 29 82 +3VS +3VS
15 CLK_PCI_SIO PCICLK AUTOFD#/DRVDEN0# LPTAFD# 38
2

83 LPTSTB# 38 RP112 RP113

R214 CLK_14M_SIO STROBE#/DS0# D SR#1 CTS#2
15 CLK_14M_SIO 19 CLK14 SLCTIN#/STEP# 67 SLCTIN# 38 8 1 1 8
@10_0402_5% CTS#1 7 2 D SR#2 2 7
PID0 48 100 RI#1 6 3 DCD #2 3 6
PID1 GPIO10 DTR2# CTS#2 DCD #1 RI#2
54 99 5 4 4 5
1 1

2 P ID[0..3] PID2 GPIO15 CTS2# 2

22 P ID[0..3] 55 GPIO16 RTS2# 98
PID3 56 97 D SR#2 4.7K_8P4R_1206_5% 4.7K_8P4R_1206_5%
C341 GPIO17 DSR2#
38 BT_DET# 57 GPIO20 TXD2 96
@15P_0402_50V8J 58 95 1 2
2

GPIO21 RXD2 DCD #2 R206 1K_0402_5%

+3VS 1 2 59 GPIO22 DCD2# 94
R643 10K_0402_5% 6 92 RI#2
GPIO24 RI2# +5V
32 GPIO30
33 89 DTR#1
CLK _PCI_SIO GPIO31 DTR1# CTS#1
34 GPIO32 CTS1# 88 JP32
35 87 RTS#1
37 FIR_EN# GPIO33 RTS1#
2

36 86 D SR#1 1
R208 GPIO34 DSR1# TXD1 1
+3VS 1 2 37 GPIO35 TXD1 85 2 2
@33_0402_5% R644 10K_0402_5% 38 84 RXD1 1 2 RXD1 3
GPIO36 RXD1 DCD #1 R199 1K_0402_5% TXD1 3
39 GPIO37 DCD1# 91 4 4
40 90 RI#1 D SR#1 5
1

GPIO40 RI1# 5
1 C330 41 GPIO41
RTS#1 6 6
@22P_0402_25V8K 42 63 CTS#1 7
GPIO42 IRMODE/IRRX3 IRMODE 37 7
43 61 IRRX DTR#1 8
GPIO43 IRRX2 IRRX 37 8
44 62 IRRX 1 2 RI#1 9
2 GPIO44 IRTX2 IRTXOUT 37 9
45 R193 DCD #1 10
GPIO45 RDATA# 1K_0402_5% 10
46 GPIO46 RDATA# 16 RDATA# 35
47 10 WDATA#
GPIO47 WDATA# WDATA# 35
11 WGATE# @96212-1011S
WGATE# WGATE# 35
2 1 51 12 HDSEL#
10K_0402_5% GPIO13/IRQIN1 HDSEL# HDSEL# 35
R194 52 8 F D D IR#
GPIO14/IRQIN2 DIR# F D D IR# 35
2 1 64 9 STEP#
10K_0402_5% GPIO23/FDC_PP STEP# STEP# 35
R192 5 D RV0#
DS0# DRV0# 35,39
18 13 INDEX#
+3VS VTR INDEX# INDEX# 35
4 DS KCHG#
3 DSKCHG# DSKCHG# 35 3
53 15 WP#
VCC WRTPRT# WP# 35
65 14 TRACK0#
VCC TRK0# TRACK0# 35
93 3 MTR0#
VCC MTR0# MTR0# 35
DRVDEN0 1 3MODE# 35
1

C285 C315 C340 C286 7

0.1U_0402_16V4Z VSS
31 VSS DRVDEN1 2 2 1 +5VS
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 60 R213 10K_0402_5%
2

VSS
76 VSS GPIO11/SYSOPT 49 1 2
R198 1K_0402_5%

LPC47N227 TQFP100 SUPER I/O Base I/O Address

* 0 = 02Eh
1 = 04Eh

4 4

Compal Electronics, Inc.

Title
SUPER I/O
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE B LA-2041 0.1
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 七月 09, 2003 Sheet 36 of 56
A B C D E
 +USB_BS
+3VALW
+USB_AS +USB_BS
+USB_AS

1
1 1
R173 R174 1 1
+ C467 C11 C3 + C465
100K_0402_5% 100K_0402_5%
+5V 150U_D2_6.3VM 470P_0402_50V7K 470P_0402_50V7K 150U_D2_6.3VM

2
U4 2 2 2 2
1 8 1 2 USB_OC0#
GND OC1# USB_OC0# 24
2 7 R175
IN OUT1 47_0402_5%
1 3 EN1# OUT2 6
4 5 1 2 USB_OC2# R44 JP17 R46
EN2# OC2# USB_OC2# 24
1

+ C250 R176 0_0603_5% 1 5 0_0603_5%

C251 47_0402_5% USB0- VCC VCC USB2-
TPS2042ADR_SO8 24 USBP0- 1 2 2 6 1 2 USBP2- 24
150U_D2_6.3VM 0.1U_0402_16V4Z USB0+ D0- D1- USB2+
24 USBP0+ 1 2 3 7 1 2 USBP2+ 24
2

D0+ D1+

1
2 C230 C231 R45 R47
4 VSS VSS 8
0_0603_5% 0_0603_5%
0.1U_0402_16V4Z 0.1U_0402_16V4Z 10 9

2
G2 G1
12 G4 G3 11
24 USB_EN# 1 2 USBEN#
R182 @0_0402_5% SUYIN_020122MR008S516ZU
2

R177 (New)

0_0402_5%
1

+USB_CS +USB_DS
+USB_DS
+3VALW
+USB_CS
1 1
1 1
+ C660 C369 C370 + C658

1
R243 R242 150U_D2_6.3VM 470P_0402_50V7K 470P_0402_50V7K 150U_D2_6.3VM
2 2 2 2
+5V 100K_0402_5% 100K_0402_5%

2
U12
1 8 1 2 USB_OC4# R247 JP33 R252
GND OC1# USB_OC4# 24
2 7 R240 0_0603_5% 1 5 0_0603_5%
IN OUT1 47_0402_5% USB4- VCC VCC USB6-
1 3 EN1# OUT2 6 24 USBP4- 1 2 2 D0- D1- 6 1 2 USBP6- 24
4 5 1 2 USB_OC6# 1 2 USB4+ 3 7 USB6+ 1 2
EN2# OC2# USB_OC6# 24 24 USBP4+ D0+ D1+ USBP6+ 24
1

+ C348 R239 R250 4 8 R256

C350 47_0402_5% 0_0603_5% VSS VSS 0_0603_5%
TPS2042ADR_SO8
150U_D2_6.3VM 0.1U_0402_16V4Z 10 9
2

G2 G1

1
2 C376 C375 12 G4 G3 11

0.1U_0402_16V4Z 0.1U_0402_16V4Z SUYIN_020122MR008S516ZU

2
USBEN#
(New)

+3VS 1 2 +IR_ANODE
R99
FIR Module @3.3_1206_5%

1 1 2
C82 R87
3.3_1206_5%
+3VS 22U_1206_10V4Z
2
2

1
C81 R80 2 1
R85 U2
4.7U_0805_10V4Z 47_1206_5% 10K_0402_5% 1 +IR _ANODE
2 IRED_A IRTXOUT
2 3 IRTXOUT 36
1

IRRX IRED_C TXD IR MODE

36 IRRX 4 RXD SD/MODE 5 IRMODE 36
+IR_ VCC 6 7
VCC MODE
1 8 GND
1

C64
C63 IR_VISHAY_TFDU6101E-TR4_8P
100P_0402_50V8J 0.1U_0402_16V4Z
2

2 +IR_ GND

The component's most place

36 FIR_EN# 1
R645
2
0_0402_5%
cloely IRDA MODULE. Compal Electronics, Inc.
FIR_EN# Title
USB Conn.
LOW FIR Poped THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B 0.1
HIGH FIR Un-Poped DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-2041
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: ¬P 期三, 七月 09, 2003 Sheet 37 of 56
 BlueTooth Interface
MDC CONN. +5VS +3VS

2
JP19
R72 C76
1 2 100K_0402_5%
MONO_OUT/PC_BEEP AUDIO_PWDN 0.1U_0402_16V4Z
3 GND MONO_PHONE 4 MD_SPK 31

3
5 6

1
AUXA_RIGHT Bluetooth Enable
7 AUXA_LEFT GND 8 2
9 10 +5VS_MDC 1 2 Q7
CD_GND +5V +5VS
11 12 L23 SI2301DS-T1_SOT23
CD_RIGHT USB Data+

1
R100 13 14 CHB1608B121_0603 C27
0_0402_5% CD_LEFT USB Data-
15 16 1 2 +3VS

1
GND PRIMARY DN R350 0.1U_0402_16V4Z
+3V 1 2 17 3.3Vaux 5Vd 18 +BT_VCC
L22 19 20 10K_0402_5%
GND GND 22K
+3VS 1 2 +3VS_MDC 21 3.3Vmain AC97_SYNC 22 IC H _AC_SYNC 24,31 39 BT_PWR 2
CHB1608B121_0603 23 24 1 2 C25
24,31 ICH_AC_SDOUT AC97_SDATA_OUT AC97_SDATA_IN1 Q6
24,31 ICH_AC_RST# 25 26 R83 0_0402_5%
AC97_RESET# AC97_SDATA_IN0 22K 10U_1206_16V4Z
27 GND GND 28 1 2 ICH_AC_SDIN1 24 DTC124EK_SOT23
29 30 R79

3
AC97_MSTRCLK AC97_BITCLK 22_0402_5%
1 2 ICH_AC_BITCLK 24,31
ACES_88023-3010 R78
22_0402_5%

Module ID
Indication for polarity of reset JP18
Reset input High Active --> Low ,
+3V +3VS_MDC +5VS_MDC +3VS Reset input Low Active --> Open Module ID 1
C489 Module_Detect 2
36 BT_DET# 3
1 1 1 @0.1U_0402_16V4Z
4
C98 C80 C495 5
1U_0805_25V4Z 1U_0805_25V4Z 1U_0805_25V4Z U30 6
7

5
2 2 2 BT_RESET#
BT_WAKE_UP 8
29,33,39 KILL_SW# 1 39 BT_WAKE_UP 9
4 BT_RESET#
10
39 BT_RST# 2 11
12
39 BT_DETACH

3
+5V_PRN 13
14
LPTSLCT @TC7SH08FU_SSOP5 USBP5+ R338 0_0603_5% USB5+ 15
24 USBP5+ 16
LPTPE USBP5- R333 0_0603_5% USB5-
24 USBP5- 17
L PTBUSY 1 2
LPTACK# R344 0_0402_5% 18
19
+BT_VCC 20
(MAX=200mA) ACES_87153-2008
10
9
8
7
6

C477 (Top Contact)

RP87
2.7K_10P8R_1206_5% 1 2 LPTINIT# +5V_PRN 0.1U_0402_16V4Z Bluetooth Connector
36 INIT# R3 33_0402_5%

36 SLCTIN# 1 2 LPTSLCTIN#
33_0402_5%
D21 PARALLEL PORT
R2 2 1
+5VS
1
2
3
4
5

1
RP2 RB420D_SOT23
+5V_PRN LPD0 1 8 F D0 R304
LPD1 2 7 F D1 2.2K_0402_5%
LPTSLCTIN# LPD2 3 6 F D2 R303
LPTINIT# LPD3 4 5 F D3 33_0402_5% C452

2
LPTERR# LPTSTB# 1 2 1 2
AFD#/3M# 68_8P4R_1206_5% 36 LPTSTB#
LPD7 1 8 F D7 AFD#/3M# 220P_0402_50V8K CP11
LPD6 2 7 F D6 F D3 8 1
LPD5 3 6 F D5 1 LPTSLCTIN# 7 2
LPD4 4 5 F D4 1 2 14 F D2 6 3
+5V_PRN 36 LPTAFD# F D0 R302 33_0402_5% 2 LPTINIT# 5 4
RP1 LPTERR# 15
F D4 68_8P4R_1206_5% 36 LPTERR# F D1 220P_1206_8P4C_50V8_V1
3
F D5 LPTINIT# 16 CP9
F D6 F D2 4 LPTSLCT 8 1
F D7 LPTSLCTIN# 17 LPTPE 7 2
F D3 5 L PTBUSY 6 3
LPD[0 ..7] 18 LPTACK# 5 4
36 LPD[0..7] F D4
10

6
9
8
7
6

19 220P_1206_8P4C_50V8_V1
RP3 F D5 7 CP1
2.7K_10P8R_1206_5% 20 F D1 1 8
F D6 8 LPTERR# 2 7
21 JP14 F D0 3 6
F D7 9 AFD#/3M# 4 5
LPTCN-25
22
LPTACK# 10 (BTS88) 220P_1206_8P4C_50V8_V1
1
2
3
4
5

36 LPTACK# CP10
23
+5V_PRN L PTBUSY 11 F D7 8 1
36 LPTBUSY
24 F D6 7 2
F D3 LPTPE 12 F D5 6 3
F D2 36 LPTPE F D4
25 5 4
F D1 LPTSLCT 13
F D0 36 LPTSLCT 220P_1206_8P4C_50V8_V1

Compal Electronics, Inc.

Title
PARALLEL/MDC PORT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LA-2041 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 七月 09, 2003 Sheet 38 of 56
 5 4 3 2 1

+3VALW
+51VDD KBA[0..19]
0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VALW +51AVCC +RTCVCC 40 KBA[0..19] AD B[0..7]
40 ADB[0..7] For EC Tools
+3VS
1

2
C674 C678 C669 C661 C643 R552 0_0402_5%

1
C637 C677 JP31
1000P_0402_50V7K 1
2

1
1 +3VALW

123
136
157
166

161
0.1U_0402_16V4Z EC_TINIT#

16

34
45

95
2

2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K U50 2 EC_TCK
3 3
MEDIA_DETECT 2 1 4 EC_TDO

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6

VBAT
VDD

AVCC
R553 100K_0402_5% 4 EC_TDI
5 5
+RTCVCC +51AVCC +3VALW 6 EC_TMS
6
7
BATT_TEMP 7 EC_URXD
1 2 23,27,36 SERIRQ 7
SERIRQ AD0
81 BATT_TEMPA 47 8
8
L33 8 82 1 2 9 EC_UTXD
LDRQ# AD1 ADP_I 48,52 9
1

D C666 C639 FBM-L11-160808-800LMT_0603 BATT_OVP R499 100K_0402_5% EC_USCLK D

13,24,36 LPC_FRAME# 9 83 BATT_OVP 48 10
LPC_AD0 LFRAME# AD2 10
13,24,36 LPC_AD0 15 84 FAN_DET 42 1 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z LPC_AD1 LAD0 Host interface AD3 ALI/MH# C644 0.22U_0603_16V4Z
14 87
2

13,24,36 LPC_AD1 LPC_AD2 LAD1 IOPE0AD4 EMAIL# ALI/MH# 47

13 88 @96212-1011S
13,24,36 LPC_AD2 LPC_AD3 LAD2 IOPE1/AD5 MODE# EMAIL# 43
13,24,36 LPC_AD3 10 89 MODE# 44
ECAGND LAD3 AD Input IOPE2/AD6 INTERNET#
15 CLK_PCI_LPC 18 90 INTERNET# 43
LCLK IOPE3/AD7
+3VALW 2 1 EC_RST# 19 93 AD_BID0
RESET1# DP/AD8

1
R549 4.7K_0402_5% 22 94
R548 SMI# DN/AD9
23
@33_0402_5% PWUREQ# DAC_BRIG
99 DAC_BRIG 22
DA0 EN_DFAN2#
EC_SCI# 31 DA output DA1
100
101 IR EF EN_DFAN2 42 KEYBOARD CONN.

2
24 EC_SCI# IOPD3/ECSCI# DA2 EN_DFAN1# IREF 48 (ACES_85201-2405_24P)
DA3 102 EN_DFAN1 42
1 CP8 @100P_1206_8P4C_50V8
C682 EC_GA20 5 32 INVT_PWM 1 8
23 GATEA20 GA20/IOPB5 IOPA0/PWM0 INVT_PWM 22
@22P_0402_25V8K EC_KBRST# 6 33 BEEP# JP5 NUM_LED# 2 7
23 KBRST# KBRST/IOPB6 IOPA1/PWM1 BEEP# 33 NUM_LED# PADS_LED#
IOPA2/PWM2 36 SHDD_LED# 35 34 3 6
2 PWM 37 ACOFF PADS_LED# CAPS_LED# 4 5
KSI0 or PORTA IOPA3/PWM3 KILL_SW# ACOFF 48 33 CAPS_LED#
44 KSI0 71 KBSIN0 IOPA4/PWM4 38 KILL_SW# 29,33,38 32
KSI1 72 39 EC_ON 1 2 CP7 @100P_1206_8P4C_50V8
44 KSI1 KBSIN1 IOPA5/PWM5 EC_ON 43,45 31 300_0402_5% +3VS
KSI2 73 40 EC_LID_OUT# KSO15 R219 KSO15 1 8
44 KSI2 KSI3 KBSIN2 IOPA6/PWM6 BT_DETACH EC_LID_OUT# 24 30 KSO14 KSO14
44 KSI3 74 KBSIN3 IOPA7/PWM7 43 BT_DETACH 38 29
2 7
KSI4 77 KSO10 KSO10 3 6
43 KSI4 KSI5 KBSIN4 EC_URXD 28 KSO11 KSO11
78 KBSIN5 IOPB0/URXD 153 EC_URXD 45 27 4 5
KSI6 79 154 EC_UTXD KSO8
KSI7 KBSIN6 Key matrix scan IOPB1/UTXD EC_USCLK EC_UTXD 45 26 KSO9
+3VALW R494 80 162 CP6 @100P_1206_8P4C_50V8
KBSIN7 IOPB2/USCLK EC_SMB_CK1 EC_USCLK 45 25 KSO13 KSO8
100K_0402_5% 163 1 8
EMAIL# KSO0 PORTB IOPB3/SCL1 EC_SMB_DA1 EC_SMB_CK1 40,47 24 KSI7 KSO9
1 2 49 KBSOUT0 IOPB4/SDA1 164 EC_SMB_DA1 40,47 23 2 7
1 2 INTERNET# KSO1 50 165 KSO3 KSO13 3 6
KBSOUT1 IOPB7/RING/PFAIL/RESET2 PCIRST# 10,13,23,26,27,29,30,36 22
R478 KSO2 51 KSO7 KSI7 4 5
100K_0402_5% KSO3 KBSOUT2 PBTN_OUT# 21 KSO12
52 KBSOUT3 IOPC0 168 PBTN_OUT# 24 20
KSO4 53 169 EC_SMB_CK2 KSI4 CP5 @100P_1206_8P4C_50V8
C KSO5 KBSOUT4 IOPC1/SCL2 EC_SMB_DA2 EC_SMB_CK2 5,34 19 KSI6 KSO3 C
56 KBSOUT5 IOPC2/SDA2 170 EC_SMB_DA2 5,34 18 1 8
KSO6 57 171 FAN_SPEED1 KSI5 KSO7 2 7
KSO7 KBSOUT6 PORTC IOPC3/TA1 EC_PME# FAN_SPEED1 42 17 KSO6 KSO12
58 KBSOUT7 IOPC4/TB1/EXWINT22 172 16 3 6
+3VALW KSO8 59 175 EC_THRM# KSO5 KSI4 4 5
KSO9 KBSOUT8 IOPC5/TA2 FAN_SPEED2 EC_THRM# 24 15 KSI3
60 KBSOUT9 IOPC6/TB2/EXWINT23 176 FAN_SPEED2 42 14
KSO10 61 1 KSI0 CP4 @100P_1206_8P4C_50V8
KBSOUT10 IOPC7/CLKOUT BT_PWR 38 13
2

KSO11 64 KSO0 KSI6 1 8

R535 KSO12 KBSOUT11 AC IN 12 KSO1 KSI5
65 26 ACIN 24,44,46 2 7
10K_0402_5% KSO13 KBSOUT12 IOPD0/RI1/EXWINT20 CD _PLAY 11 KSI1 KSO6
66 29 CD_PLAY 34 3 6
KSO14 KBSOUT13 PORTD-1 IOPD1/RI2/EXWINT21 PM_SLP_S3# 10 KSI2 KSO5
67 30 PM_SLP_S3# 24 4 5
KSO15 KBSOUT14 IOPD2/EXWINT24/RESET2 9 KSO2
68
1

KBSOUT15 8 KSO4 CP3 @100P_1206_8P4C_50V8

26,27,29,30 WLANPME# 2 ON/OFF 43
EC_TINIT# IOPE4/SWIN PM_SLP_S5# 7 KSI3
105 44 PM_SLP_S5# 24 1 2 1 8
EC_TCK TINT# PORTE IOPE5/EXWINT40 BT_WAKE_UP 6 R218 300_0402_5% +3VS KSI0
26,27,29,30 PCM_PME# 106 24 BT_WAKE_UP 38 2 7
EC_TDO TCK IOPE6/LPCPD/EXWIN45 5 KSO0
107 25 PM_CLKRUN# 24,26,27,29,30,36 3 6
EC_TDI TDO JTAG debug port IOPE7/CLKRUN/EXWINT46 4 KSO1
26,27,29,30 1394_PME# 108 4 5
EC_TMS TDI KBA0 3
109 124
EC_PME# TMS IOPH0/A0/ENV0 KBA1 2 CP2 @100P_1206_8P4C_50V8
125 1 2
26,27,29,30 LAN_PME# IOPH1/A1/ENV1 KBA2 1 R217 300_0402_5% +3VS KSI1
35 EXTID0 110 126 1 8
PSCLK1/IOPF0 IOPH2/A2/BADDR0 KBA3 6278-34P-KBCON KSI2
35 EXTID1 111 127 2 7
PSDAT1/IOPF1 IOPH3/A3/BADDR1 KBA4 KSO2
35 EXTID2 114 128 3 6
PSCLK2/IOPF2 PORTH IOPH4/A4/TRIS KBA5 KSO4
35 EXTID3 115 131 4 5
ECAGND BATT_TEMP TP_CLK PSDAT2/IOPF3 PS2 interface IOPH5/A5/SHBM KBA6
2 1 44 TP_CLK 116 132
C649 0.01U_0402_25V4Z TP_DATA PSCLK3/IOPF4 IOPH6/A6 KBA7
44 TP_DATA 117 133
LID_SW# PSDAT3/IOPF5 IOPH7/A7
43 LID_SW# 118
PSCLK4/IOPF6 ADB0
34 MEDIA_DETECT 119 138
PSDAT4/IOPF7 IOPI0/D0 ADB1
139
+3VALW IOPI1/D1 ADB2
IOPI2/D2
140 (Need to check layout library with KB spec)
RP145 141 ADB3
MODE# C R Y1 PORTI IOPI3/D3 ADB4
1 8 158
32KX1/32KCLKIN IOPI4/D4
144 I/O Address
2 7 FR D# 145 ADB5
SELIO# C R Y2 IOPI5/D5 ADB6
3 6 160 146 BADDR1(KBA3) BADDR0(KBA2) Index Data
B FSEL# 32KX2 IOPI6/D6 ADB7 B
4 5 IOPI7/D7
147
0 0 2E 2F
10K_1206_8P4R_5% 150 FR D#
PORTJ-1 IOPJ0/RD FWR# FRD# 40
151 FWR# 40
0 1 4E 4F
+5VALW IOPJ1/WR0
RP85 152 SELIO# * 1 0 (HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1
EC_SMB_DA2 SELIO# SELIO# 40
8 1
7 2 EC_SMB_CK2 EC_SMI# 62 41 1 1 Reserved
EC_SMB_DA1 24 EC_SMI# IOPJ2/BST0 IOPD4 NUM_LED# PHDD_LED# 35
6 3 42 S4_SATA 63 42
EC_SMB_CK1 IOPJ3/BST1 PORTD-2 IOPD5 CAPS_LED#
5 4 29 WL_OFF# 69
IOPJ4/BST2 IOPD6
54
70 PORTJ-2 55 PADS_LED# ENV0 (KBA0) ENV1 (KBA1) TRIS (KBA4)
24 EC_SWI# IOPJ5/PFS IOPD7
10K_1206_8P4R_5% 75
38 BT_RST# EN_DFAN3 IOPJ6/PLI KBA8
42 EN_DFAN3 76 IOPJ7/BRKL_RSTO IOPK0/A8
143 IRE 0 0 0
142 KBA9 * OBD 0 1 0
SYSON IOPK1/A9 KBA10 DEV 1 0 0
41,42,50 SYSON 148 135
SUSP# IOPM0/D8 PORTK IOPK2/A10 KBA11 PROG
31,34,40,41,49,50,51,52 SUSP# 149 134 1 1 0
VR_ON IOPM1/D9 IOPK3/A11 KBA12
53 VR_ON 155 130
IOPM2/D10 PORTM IOPK4/A12 KBA13 SHBM(KBA5)=1: Enable shared memory with host BIOS
27 PCM_SUSP# 156 129
IOPM3/D11 IOPK5/A13_BE0 KBA14
24,45 EC_RSMRST# 3 121 TRIS(KBA4)=1: While in IRE and OBD, float all the
IOPM4/D12 IOPK6/A14_BE1 KBA15
35,36 DRV0# 4 120 signals for clip-on ISE use
IOPM5/D13 IOPK7/A15_CBRD
16,22 ENBKL 27
BKOFF# IOPM6/D14 KBA16 +3VALW
22 BKOFF# 28 113
IOPM7/D15 IOPL0/A16 KBA17
Analog Board ID definition, IOPL1/A17
112
+5VS
FSEL# 173 PORTL 104 KBA18 KBA1 1 2
Please see page 3. 40 FSEL# SEL0# IOPL2/A18 KBA19
174 103 R491 1K_0402_5%
SEL1# IOPL3/A19 FSTCHG TP_CLK KBA2
47 48 FSTCHG 48 1 2 1 2
+3VALW CLK IOPL4/WR1# R493 4.7K_0402_5% R490 @1K_0402_5%
TP_DATA 1 2 KBA3 1 2
AGND
GND1
GND2
GND3
GND4
GND5
GND6
GND7

4.7K_0402_5%
NC10

R519 R492 R489 1K_0402_5%

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

C R Y1 1 2 C R Y2 KBA5 1 2
2

R488 1K_0402_5%
2

R481 20M_0402_5% PC87591L-VPCN01 A2_LQFP176

17
35
46
122
159
167
137

96

11
12
20
21
85
86
91
92
97
98

A 100K_0402_5% R517 A
Ra
120K_0402_5%
D42
1

AD_BID0 X5 C798
1

2 1 2
2

C638 @0.1U_0402_16V4Z DAC_BRIG 1

2

32.768KHz_12.5P_CM155 ECAGND 1 2 3 +3VALW Compal Electronics, Inc.

1

Rb R487 0.1U_0402_16V4Z L32

2

0_0402_5% C664 C665 FBM-L11-160808-800LMT_0603 @DAN217_SOT23

10P_0402_50V8K 12P_0402_50V8J Title
1

PROPRIETARY NOTE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND EC PC87591
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE Custom 0.1
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-2041
Date: 星期四, 七月 10, 2003 Sheet 39 of 56
5 4 3 2 1
 +5VALW
+5VALW
1 2
1 2 C351 0.1U_0402_16V4Z
C367
0.1U_0402_16V4Z U11

20
20
U14 ADB0 3 2 KSO16

VCC
ADB0 +3VALW ADB1 D0 Q0 KSO17
3 2 4 5

VCC
D0 Q0 CDON_LED# 44 D1 Q1 KSO17 43,44
ADB1 4 5 C366 ADB2 7 6 HDD _LED#
D1 Q1 MP3_LED# 44 D2 Q2 HDD_LED# 43
ADB2 7 6 1 2 ADB3 8 9
D2 Q2 EMAIL_LED# 44 D3 Q3 WL_BT_LED# 43
+3VALW ADB3 8 9 ADB4 13 12
D3 Q3 PW R_LED# 44 D4 Q4 S4_LATCH 42
ADB4 13 12 0.1U_0402_16V4Z ADB5 14 15 EC_ RCVEN
D4 Q4 PW R_SUSP_LED# 44 D5 Q5 EC_RCVEN 45
ADB5 ADB6 EC_RCRST# to 3V

14
14 D5 Q5 15 BATT_LOW_LED# 44 17 D6 Q6 16 EC_RCRST# 45
ADB6 U13A ADB7

14
17 D6 Q6 16 BATT_CHGI_LED# 44 18 D7 Q7 19 CIR_GATING# 45
ADB7 18 19 CD_F DD_LED# KBA4 1

P
D7 Q7 CD_FDD_LED# 43 A
KBA2 4 3 CC 11

GND
P
A AA SELIO# O LARST# CP
6 11 2 1

GND
O CP B MR

G
SELIO# 5 LARST# 1
39 SELIO# B MR

G
SN74LVC32APWLE_TSSOP14 SN74HCT273PW_TSSOP20

10
U13B 7 SN74HCT273PW_TSSOP20

10
SN74LVC32APWLE_TSSOP14

C352
+5VALW 1 2 1 2
R224
20K_0402_5% 1U_0805_25V4Z

+3VALW +5VALW

AA 1 2 +5VALW

1
R246 100K_0402_5% C399
CC 1 2 1 2 0.1U_0402_16V4Z R266
R238 100K_0402_5%
+3VALW 100K_0402_5%
+3VALW U18

2
8 VCC A0 1
1

R245 7 2
100K_0402_5% WP A1
SUSP# 31,34,39,41,49,50,51,52 39,47 EC_SMB_CK1 6 SCL A2 3
39,47 EC_SMB_DA1 5 SDA GND 4
2
G
14

AT24C16N10SC-2.7_SO8
2

10 1 3
P

A EC_FLASH# 24
FWE# 8
D

S
O

1
B 9
G

U13C Q15 R263

SN74LVC32APWLE_TSSOP14 2N7002_SOT23
7

100K_0402_5%
FW R# 39

2
1MB Flash ROM 512KB Flash ROM
Flash ROM Socket Conn.
KB A[0..19]
39 KBA[0..19]
ADB[0 ..7] C663
39 ADB[0..7]
0.1U_0402_16V4Z
+3VALW 1 2
U15
U16
KBA0 21 31 JP7
KBA1 A0 VCC0 KBA18 KBA16 KBA17
20 A1 VCC1 30 1 1 NC VCC 32 +3VALW 1 2
KBA2 19 C380 KBA16 2 31 FWE# KBA15
KBA3 A2 KBA15 A16 WE* KBA17 KBA14 3 4
18 A3 3 A15 A17 30 5 6
KBA4 17 25 ADB0 0.1U_0402_16V4Z KBA12 4 29 KBA14 KBA13 KBA19
KBA5 A4 D0 ADB1 2 KBA7 A12 A14 KBA13 KBA12 7 8 KBA10
16 A5 D1 26 5 A7 A13 28 9 10
KBA6 15 27 ADB2 KBA6 6 27 KBA8 KBA11 ADB7
KBA7 A6 D2 ADB3 KBA5 A6 A8 KBA9 KBA9 11 12 ADB6
14 A7 D3 28 7 A5 A9 26 13 14
KBA8 8 32 ADB4 KBA4 8 25 KBA11 KBA8 ADB5
KBA9 A8 D4 ADB5 KBA3 A4 A11 F RD# FWE# 15 16 ADB4
7 A9 D5 33 9 A3 OE* 24 17 18
KBA10 36 34 ADB6 KBA2 10 23 KBA10 RESET#
A10 D6 A2 A10 19 20 +3VALW
KBA11 6 35 ADB7 KBA1 11 22 FSEL#
KBA12 A11 D7 KBA0 A1 CE* ADB7 21 22
5 A12 12 A0 DQ7 21 23 24
KBA13 4 ADB0 13 20 ADB6 KBA18 ADB3
KBA14 A13 RESET# ADB1 DQ0 DQ6 ADB5 KBA7 25 26 ADB2
3 A14 RP# 10 1 2 +3VALW 14 DQ1 DQ5 19 27 28
KBA15 2 11 R248 ADB2 15 18 ADB4 KBA6 ADB1
KBA16 A15 NC @100K_0402_5% DQ2 DQ4 ADB3 KBA5 29 30 ADB0
1 A16 READY/BUSY# 12 16 VSS DQ3 17 31 32
KBA17 40 29 KBA4 F RD#
KBA18 A17 NC0 KBA3 33 34
13 A18 NC1 38 35 36
KBA19 37 @29F040/SST39VF040_PLCC KBA2 FSEL#
A19 KBA1 37 38 KBA0
FSEL# 39 40
39 FSEL# 22 CE#
F RD# 24 23 @SUYIN-80065A-040G2T
39 F RD# OE# GND0
FWE# 9 39
WE# GND1

SST39VF080-70_TSOP40

Compal Electronics, Inc.

Title
BIOS & EXT. I/O PORT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-2041
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: ¬P 期三, 七月 09, 2003 Sheet 40 of 56
 A B C D E

+3V +5V +2.5VS

+3VALW TO +3V +5VALW TO +5V
+3V

2
+5VALW +5V R408 R505 R184
U23 @470_0805_5% @470_0805_5% @470_0805_5%
1 1 8 D S 1
C601 C599 7 2

1
D S
6 D S 3 1 1
10U_1206_16V4Z 1U_0805_25V4Z 5 4 C440 C438
D G

1
+3VALW 2 2 D D D
1 U44 1 SI4800DY_SO8 4.7U_0805_10V4Z 1U_0805_25V4Z 2 SYSON# 2 SYSON# 2 SUSP 1
2 2 G G G
8 D S 1
7 2 R426 C441 S Q39 S Q51 S Q11

3
D S 100K_0402_5% 4.7U_0805_10V4Z @2N7002_SOT23 @2N7002_SOT23 @2N7002_SOT23
6 D S 3
SYSON_ALW 2
5 D G 4 1 2 +12VALW

1
SI4800DY_SO8 2

1
C605 R427 D SYSON_ALW
1
C635 2 SYSON# 2
0.1U_0402_16V4Z @1M_0402_5% G C437
10U_1206_16V4Z 1 S Q41 +3VS +5VS
2

3
2 2N7002_SOT23 0.1U_0402_16V4Z
1

2
R475 R507
@470_0805_5% @470_0805_5%

1
+3VALW TO +3VS
+5VALW TO +5VS

1
D D
+3VS 2 SUSP 2 SUSP
G G
S Q48 S Q54

3
1 1 @2N7002_SOT23 @2N7002_SOT23
+3VALW C344 C343
+5VALW +5VS
U9 10U_1206_16V4Z 1U_0805_25V4Z U45
2 2
8 D S 1 8 D S 1
2 7 2 R474 7 2 2
D S 100K_0402_5% D S
6 D S 3 6 D S 3 1 1
5 4 5VS_GATE 1 2 +12VALW 5 4 C647 C648
D G D G +5VALW +5VALW
SI4800DY_SO8 1 SI4800DY_SO8 4.7U_0805_10V4Z 1U_0805_25V4Z
2 2
1

2
1 2 C646
1

C345 C342 R473 D 4.7U_0805_10V4Z R502 R501

SUSP 2 10K_0402_5% 10K_0402_5%
2
10U_1206_16V4Z 0.1U_0402_16V4Z @1M_0402_5% G
2 1 S Q47
2

1
2N7002_SOT23 5VS_GATE SYSON# SUSP
19,52 SUSP

1
D D
2
C640 S Y SON 2 Q53 2 Q52
39,42,50 S YSON 31,34,39,40,49,50,51,52 SUSP#
G 2N7002_SOT23 G 2N7002_SOT23
0.1U_0402_16V4Z S S

3
1

+3VALW +3VALW
+3V
+2.5V TO +2.5VS
+2.5V
+2.5VS
2
1

U3 C781
8 1 R699
3 D S 0.1U_0402_16V4Z 3
14

14
7 D S 2
0_0402_5% U61A 1 U61B
6 D S 3
5 4 1 1
P

P
2

D G C193 C194 1 I O 2 3 I O 4 V_ON 50

SI4800DY_SO8
G

G
1 4.7U_0805_10V4Z 1U_0805_25V4Z +3VALW POWER +3VALW POWER
2 2 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
7

7
C192
4.7U_0805_10V4Z
2
5VS_GATE

2
C170
+3VALW POWER
0.1U_0402_16V4Z +3VS
1
+3VALW +3VALW
1

R700
14

14

0_0402_5% U61C U61D

P

P
2

5 I O 6 9 I O 8 VS_ON 50,51,52
G

+3VALW POWER +3VALW POWER

SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
7

4 4

Compal Electronics, Inc.

Title
POWER CONTROL CKT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
PROPRIETARY TRADE
NOTE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE B LA-2041 0.1
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 七月 09, 2003 Sheet 41 of 56
A B C D E
 A B C D E

RTC Battery
FAN CONN. 1
- BATT1 + +RTCBATT

+5VALW 2 1 +RTCBATT
VS

1 2
C303 RTCBATT
Power ON Circuit

1
0.1U_0402_16V4Z
1 D27 1

1
U7A +3VS

1
D7 C287 BAS40-04_SOT23

1
EN_ DFAN1 3 C FMMT619_SOT23 10U_1206_16V4Z +3V +3V +RTCVCC
39 EN_DFAN1

2
+IN E N_FAN1
1 1 2 2

2
OUT

1
2 1 2 B Q71
-IN R705 E 1SS355_SOD323 R587 U55D
2

2
G
R211 100_0402_5% C782 SN74LVC14APWLE_TSSOP14

14

14
CHGRTC
10K_0402_5% LM358A_SO8 FA N1 180K_0402_5% U55E

1
0.1U_0402_16V4Z JP25 SN74LVC14APWLE_TSSOP14 C607

P
2
1
1
1 9 I O 8 11 I O 10 SYS_PW ROK 7,24
1 2 D8 0.1U_0402_16V4Z

2
2

G
R210 8.2K_0402_5% 2 +3V POWER +3V POWER
1N4148_SOT23 3 C692

7
4
R588

2
ACES_85205-0400 1U_0805_25V4Z
1 100K_0402_5%

+3VS 1 2
R529 10K_0402_5%

39 FAN_SPEED1
2 2
C791 C792

FAN CONN. 2 +5VALW

@1000P_0402_50V7K
1 1
1000P_0402_50V7K

2 2
U7B

1
1

1
EN_ DFAN2 5 C FMMT619_SOT23 D3 C249 RTCVREF RTCVREF RTCVREF RTCVREF
39 EN_DFAN2 +IN
7 E N_FAN2 1 2 2 10U_1206_16V4Z

2
OUT R200 B Q10
2 1 6 -IN 2
100_0402_5% C256 E

1
R202 1SS355_SOD323 D13 C406 0.1U_0402_10V6K

2
10K_0402_5% LM358A_SO8 0.1U_0402_16V4Z FA N2 R275 R271 R270 1 2
1
1 ON/OFFBTN# 43,45
JP23 100K_0402_5% 100K_0402_5% 680K_0402_5% 1N4148_SOT23
D5

2
1

5
2

1
1N4148_SOT23 D
1 2 3
R201 8.2K_0402_5% 1 2 2 4 1 2 2 Q17
2

ACES_85205-0300 C411 1U_0603_10V6K R268 G 2N7002_SOT23

U19 10K_0402_5% S

3
+3VS 1 2 D15 NC7SZ14M5X

3
1
R541 10K_0402_5% D
1 2 2 Q18
43 S4_LID_SW#
G 2N7002_SOT23
39 FAN_SPEED2
S

3
RB751V_SOD323

1
D
2 2
FAN CONN. 3 C793 C794
39,41,50 S YSON 2
G
+12VALW @1000P_0402_50V7K 1000P_0402_50V7K Q16 S

3
1 1 2N7002_SOT23
1

3 +5VALW R679 3
RTCVREF 1 2 1 2
10K_0402_5% R273 C412 1U_0805_16V7K
10K_0402_5%
1

RTCVREF
2 2

+3VALW R681 +5VALW U20 C405 0.1U_0402_10V6K

10K_0402_5% 1 CD1# VCC 14 1 2
2 D1 CD2# 13
D38 3 12
40 S4_LATCH
2

CP1 D2
1

1N4148_SOT23 C257 RTCVREF 1 2 4 11

SD1# CP2
1

C FMMT619_SOT23 D4 R274 1 5 10
1

Q1 SD2#
1

2 10U_1206_16V4Z 10K_0402_5% C413 6 09

2

R707 B Q12 Q1# Q2

7 GND Q2# 08
E @1U_0805_16V7K
3

10K_0402_5% 1SS355_SOD323 2
74LCX74
2
2

FAN2-1
2

Q69 1 2
B

+3VALW
1

2SA1036K_SOT23 2 D6 JP22 R276 D14

1
10K_0402_5% D
1 D_SET_S4 Q19
2 39 S4_SATA 2 1 2
1

D 1N4148_SOT23 G 2N7002_SOT23
3
C

EN_ DFAN3 Q73 1

39 EN_DFAN3 2 S
2

3
G 2N7002_SOT23 ACES_85205-0300 RB751V_SOD323
1

S
3

C795
1000P_0402_50V7K

C779 D40
4 4
+5V 1 2 2 1 2 1 FAN_DET 39
R695 10K_0402_5%
1

4.7U_0805_10V4Z
R205 RB751V_SOD323
2

E N_FAN2 1 2 1 2 R696 C780

R207 @0_0402_5% 100K_0402_5% 0.1U_0402_16V4Z
Compal Electronics, Inc.
2

@100_0402_5% C260
2

Title
0.1U_0402_16V4Z Power OK/Reset/RTC battery/Lid Switch/Int. KB
1

Size Document Number R ev

LA-2041 0.1

D ate: ¬P 期三, 七月 09, 2003 Sheet 42 of 56

A B C D E
 5 4 3 2 1

LID Switch
42 S4_LID_SW#
Button FPC Conn.
D10
D2 2INTERNET# INTERNET# 39 JP6
LID_SW # 2 INTERNET_BTN# 1
39 LID_SW # SW1
1 3 1 3 51ON# INTERNET_BTN#
EMIAL_BTN# 6
45 CIR_LID_SW # 3 5
DAN202U_SC70 +3VALW 4

1
D DAN202U_SC70 TV_OUT_EN# D
39 KSI4 3
+3VALW 2 1 KSO17
40,44 KSO17 2
R656 100K_0402_5% 4 2
D1 1
@DAN217_SOT23 H O R NG CHIH D11
2 EMAIL# EMAIL# 39 ACES_85201-0605

3
+3VALW EMIAL_BTN# 1
(DIFFERENT BETWEEN MPU-101-81A) 3 51ON#

DAN202U_SC70

+3VALW +5VS +5V

2 1
J2 JOPEN Power Button

3
C C
2

Q42 Q43
2 1 R560 E DTA114YKA_SOT23 E DTA114YKA_SOT23
47K 47K
J3 JOPEN B B
100K_0402_5% 2 CD_F DD_LED# CD_FDD_LED# 40 2 WL_BT_LED# WL_BT_LED# 40
10K 10K
1

D33 C C
2 O N/OFF 39
ON /OFFBTN# 1
42,45 ON/OFFBTN#

1
3 51ON#
51ON# 44,46
DAN202U_SC70 2 1 CD_FD DLED# 2 1 WL_BTLED#
R465 200_0402_5% R466 200_0402_5%
+3VALW
2

D34
C687
2

1
1

R554 1000P_0402_50V7K
4.7K_0402_5% C RLZ20A_LL34
Power FPC Conn.
2
1

E C_ON 1 2 2 22K
39,45 EC_ON B
R555
33K_0402_5% E +5VS
Q58 22K
DTC124EK_SOT23
3

3
1

D Q13
Q55 2 E DTA114YKA_SOT23
B 47K B
G B
2N7002_SOT23 S 2 HDD _LED# HDD_LED# 40
3

10K ACES_85201-1405
C
R215 WL_BTLED# 14 14
+5VS 2 1 13

1
SDLED# 13
12 12
200_0402_5% CD_FD DLED# 11
HDDL ED# HDDL ED# 11
2 1 10 10
R216 200_0402_5% ON /OFFBTN# 9
POW ER_ON_LED 9
44 POW ER_ON_LED 8 8
7 7
+5VALW 6 6
5 5
44 PW R_SUSPLED#_1 4 4
3 3
2 2
1 1

JP4

SDLED#

1
D Q56
27 SDLED S DLED 2
A
G 2N7002_SOT23 A
3 S

Compal Electronics, Inc.

Title
Switchs & Connectors
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-2041
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: ¬P 期三, 七月 09, 2003 Sheet 43 of 56
5 4 3 2 1
 5 4 3 2 1

BATT_CHGILED# BATT_LOWLED#
+5V

1
43 POW ER_ON_LED POW ER_ON_LED

3
R294 R297
Q31
200_0402_5% 200_0402_5% E DTA114YKA_SOT23
47K
B

1 2

1 2
PW RLED# 2EMAIL_LED# EMAIL_LED# 40
10K
C

1
200_0402_5% 200_0402_5%

2 1
100K 100K
D 40 BATT_CHGI_LED# BATT_CHGI_LED# 2 2 BATT_LOW_LED# BATT_LOW_LED# 40 D
R296 R646
PW R_SUSP_LED# 40 R295
2

2
DTC115EKA_SOT23 100K 100K DTC115EKA_SOT23
C772 1U_0805_25V4Z Q28 Q30 200_0402_5%

3
2 1

1
EMAILLED#

4 G
1
D
1 2 2 -IN BATTERY CHGI/LOW LED
PW R_LED# 2 Q29 R671 470K_0402_5% 1 2 1PW R_SUSPLED#
40 PW R_LED#
G 1 2 3
OUT R293 200_0402_5%
EMAIL LED
+5VALW +IN

1
S R672 100K_0603_1% D37
3

P
2N7002_SOT23 LM358A_SO8 2 1
U60A PW R_SUSPLED#_1 43
R678 200_0402_5%

8
1
C773 1U_0805_25V4Z R673
2 1

2
100K_0603_1% RB751V_SOD323 LED FPC Conn.

2
POWER/SUSP LED
+5VALW
JP12

1
C775 +5VALW 1
ACIN LED# 2
0.1U_0402_16V4Z PW RLED# 3 ACIN LED# 2 1

2
C PW R_SUSPLED# 4 R298 C
BATT_LOWLED# 5 200_0402_5%

1
BATT_CHGILED# D
6
EMAILLED# 7 2 A C IN A C IN 24,39,46
8 G
9 S Q32

3
10 2N7002_SOT23

ACES_85201-1005

+5VCD +5VCD
ACIN LED
3

Q20 Q21
DTA114YKA_SOT23 E DTA114YKA_SOT23 E U60B
47K 47K
B B

14
40 CDON_LED# CD ON_LED# 2 40 MP3_LED# MP3_LED# 2 5 U61E
+IN
7

P
10K 10K OUT
C C 6 11
-IN I O 10

G
+3VALW POWER
2 1

2 1

LM358A_SO8 SN74LVC14APWLE_TSSOP14

7
B +5VALW POWER B
R282 R283 Touch Pad Connector
200_0402_5% 200_0402_5%
1

JP8
R_C DON_LED# R_MP3_LED# TP_CLK

13

14
39 TP_CLK 1
TP_DATA U51D U61F
39 TP_DATA 2

OE#

P
3
4 12 I O 11 13 I O 12
5

G
+3VALW POWER
+5VS 6 SN74LVC14APWLE_TSSOP14

7
D16 SN74LVC125APWLE_TSSOP14
1

51ON# 2 1 C347 ACES 85201-0602_6P +3V POWER

43,46 51ON#
1N4148_SOT23
CDPLAY Board Conn. 1U_0603_10V6K
2

D17 ACES_85201-1405 D43

MODE# 2 1 D_MODE# @DAN217_SOT23
39 MODE#
+3VALW 14 14
1N4148_SOT23 13 2
13 TP_CLK
12 12 1
11 11 3 +5VS
D_MODE# 10
R_C DON_LED# 10
9 9
R_MP3_LED# 8 3
KSO17 8 TP_DATA
A 100P_0402 40,43 KSO17 7 7 1 A
39 KSI0 EC_PLAYBTN# 6 2
D_MODE# C783 @100P_0402_16V4Z EC_STOPBTN# 6
1 2 39 KSI1 5 5
R_C DON_LED# C784 1 2 @100P_0402_16V4Z 39 KSI2 EC_REVBTN# 4 D44
R_MP3_LED# C785 @100P_0402_16V4Z E C_FRDBTN# 4 @DAN217_SOT23
1 2 39 KSI3 3 3
KSO17 C786 1 2 @100P_0402_16V4Z 2
EC_PLAYBTN# C787 1 2 @100P_0402_16V4Z 1
2 Compal Electronics, Inc.
EC_STOPBTN# C788 @100P_0402_16V4Z 1
1 2
EC_REVBTN# C789 1 2 @100P_0402_16V4Z Title
JP11
E C_FRDBTN# C790 1 2 @100P_0402_16V4Z Switchs & Connectors
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-2041
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: ¬P 期三, 七月 09, 2003 Sheet 44 of 56
5 4 3 2 1
 5 4 3 2 1

H3 H4 H23 H24 H21 H22

H1 H2 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5x3.0 SCREW 8.5x3.0 SCREW 8.5x3.0 SCREW 8.5x3.0 Q33
SCREW 8.5x3.0 SCREW 8.5x3.0 SI2301DS 1P_SOT23

+5V_CIR 3 3 1 1 +5VALW EC_ON 39,43

1 1

2
C445
C442

2
1U_0603_10V6K 1U_0603_10V6K
1

1
2 2

100K
1 2

100K
C444 1U_0603_10V6K
D 1 2 1 2 1 3 D
R299 100K_0603_5% R289 10K_0402_5%
H5 H6 H7 H8 H9 H10 H11 H12
SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 U24
1 8 P2 Q22
OUT IN DTC115EKA_SOT23
2 SNS FB 7
P2 1 2 3 6 C443
R300 100K_0603_5% SHDN TAP
4 GND ERR# 5
1U_0805_25V4Z
43 CIR_LID_SW # MIC2951
1

1
D

P2 1 2 2
H13 H14 H15 H16 H17 H18 H19 H20 R284 G Q23

1
SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 100K_0402_5% D 2N7002_SOT23
S

3
24,39 EC_RSMRST# 2
G Q24
S 2N7002_SOT23

3
1

1
1 2 +5V_CIR
1 2 R290 @10K_0402_5% 2 1 +5V_CIR
C757 @10P_0402_50V8K U25 R657

1
H25 H26 H27 H28 H29 H30 3 20 CIR_RCVEN @10K_0402_5%
XIN P00

1
SCREW 8.5x3.0 SCREW 8.5x3.0 SCREW 8.5x3.0 SCREW 8.5x3.0 SCREW 8.5x3.0 SCREW 8.5x3.0 X2 R675 19 CIR_UTXD
P01
3 P02 18 1 2
4MHZ_30PF_6W04000042 @1M_0603_5% 17 R291 0_0402_5%
P03 ON/OFFBTN# 42,43

2
C 1 2 1 2 4 16 C
XOUT P10

1
C758 @10P_0402_50V8K R676 0_0402_5% D
P11 15
CIR_R CRST# 6 14 RC_ON /OFFBTN 2
1

1
RESET# P12/CNTR CIR_UTXD G Q25
P13/INT 13
7 S 2N7002_SOT23

3
P21/AIN1 CIR_U RXD
8 P20/AIN0 D0 12
11 CIR_US CLK +5V_CIR
1 D1
H31 H32 H33 H36 H37 H34 H35 C447 9
SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5X2.8 SCREW 8.5x3.0 SCREW 8.5x3.0 RCIR RX D3/K
10 D2/C CNVSS 5 1 2
0.1U_0402_16V4Z R301 0_0402_5%
2 C774
+5V_CIR 1 VDD VSS 2
1

1
C446 M34501M4-XXXFP 1U_0805_25V4Z

0.1U_0402_16V4Z
1

1
2 DTC115EKA_SOT23
100K
2
RP86 +5V_CIR Q67

1
CIR_RCVEN 1 8 100K
H38 H39 H40 H41 H42 CIR_R CRST# 2 7 R677

3
SCREW SCREW SCREW SCREW SCREW CIR_U RXD 3 6 47K_0402_5%
CIR_US CLK 4 5

2
10K_1206_8P4R_5%

+3VALW +5V_CIR
1

B CIR _GATING# B
40 CIR_GATING#

2
R286 R670

1
H43 H44 H45 H46 R650
SCREW SCREW SCREW SCREW CIR Reciever Board Conn. +3VALW 1 2 10K_0402_5% 10K_0402_5%

2 2
R285 @10K_0402_5%

1
JP13 10K_0402_5%

2 2
+5V_CIR 1 EC_UTXD 3 1 CIR_UTXD
2 39 EC_UTXD
RCIR RX Q26
3 MMBT3904_SOT23 CIR_RCVEN
40 EC_RCVEN 3 1
1

4
5 Q64 MMBT3904_SOT23
6
+3VALW 1 2
ACES_85201-0605 R287 10K_0402_5% CIR _GATING#

1
EC_URXD 2 1 CIR_U RXD R651
39 EC_URXD
D18

RB751V_SOD323 10K_0402_5%

2 2
+3VALW 1 2
C F5 CF11 C F8 CF20 C F7 CF14 C F6 C F9 CF13 CF10 CF15 CF18 CF16 CF19 R292 10K_0402_5%
SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80
3 1 CIR_R CRST#
40 EC_RCRST#
E C_USCLK 2 1 CIR_US CLK
39 EC_USCLK
D19 Q65 MMBT3904_SOT23
1

A A
CF21 CF27 CF23 CF24 CF22 CF26 CF25 CF28 C F2 C F4 CF12 CF17 C F1 C F3 RB751V_SOD323
SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80

Compal Electronics, Inc.

1

F D2 F D3 F D1 F D4 F D5 F D6 Title
F IDUCAL F IDUCAL F IDUCAL F IDUCAL F IDUCAL F IDUCAL CIR & Screws
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B LA-2041 0.1
1

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 七月 09, 2003 Sheet 45 of 56
5 4 3 2 1
 A B C D

VS

V IN V IN
PF1 1 2
12A_65VDC_451012 PL1 PR1 1M_0603_1%

1
1 2 1 2

1
PCN1 C8B BPH 853025_2P PR2
PR3 VS
1 1 5.6K_0603_5%

1
6 G 84.5K_0603_1% 1 2

2
A C IN 24,39,44

1
5 G PC1 PC2 PC3 PC4 PR4

8
4 G 2 PD1 PU1A 1K_0603_5%
2
3 EC10QS04 1000P_0603_50V7K 100P_0603_50V8J 1000P_0603_50V7K 100P_0603_50V8J 1 2 3

P
1 1
G

2
PR5 22K_0603_5% + P ACIN
1

2
O P ACIN 48,49
2 -

G
1
SINGA_2DC-S113L200

1
PC5 PR6 PC6 LM393M_SO8 PD2

4
PR7
20K_0603_1% 10K_0603_5%

2
RLZ4.3B_LL34

2
PR8
1000P_0603_50V7K 0.1U_0603_25V7K 2 1
Vin Detector
RTCVREF
10K_0603_5%
V IN 3.3V High 18.764 17.901 17.063
Low 17.745 16.903 16.038

2
PD3

1N4148_SOD80

1
PD4
BATT+ 2 1

1
RB751V_SOD323 PR9
VS
33_1206_5% 1 2
PR10

2
1K_1206_5%
2 CH GRTCP 1 2 N1 3 1 2

PR11 PQ1
200_0603_5% TP0610T_SOT23 PD5
1

2 1 N3 1 2
VIN B+
2
1

1
PR13 PC7 PR12
PC8 1N4148_SOD80 1K_1206_5%
100K_0603_5% 0.22U_1206_25V7M 0.1U_0603_25V7K
2

2
2

43,44 51ON# 1 2 1 2
PR14 22K_0603_5% PR15
1K_1206_5%
1

RTCVREF PR16
PU2
6.0V

1
S-81233SGUP-T1_SOT89 200_0603_5% 1 2 2 1
VS PR17 10K_0603_5% PR18 1M_0603_1% PR19
3.3V
2

PR200 PR20 499K_0603_1%

1 2 1 2 3 2 N2 PU1B
CHGRTC 3 2
1

PON LM393M_SO8

2
1

8
200_0603_5% 200_0603_5% PC9 PD6 PD7
1

2 5

P
PC10 1U_0805_25V4Z RLZ16B_LL34 47,49 MAINPWON 1 7
+
1

10U_1206_10V4Z O 10K_0603_5%
3 6
48 ACON
2

1
2

1
RB715F_SOT323 PR21

4
1

1
PD8 PC12 PC13 PR22 PC11
3 499K_0603_1% 3

2
1000P_0603_50V7K PR23 1000P_0603_50V7K

2
RLZ6.2C_LL34 215K_0603_1%

1
2

2
PJP1 RTCVREF
1 2 0.1U_0603_16V7K
3.3V
PAD-OPEN 4x4m

PJP2

1
+2.5V PJP3 PQ2 D
+2.5VP 1 2 (12A,480mils ,Via NO.=24) +5VALW
+5VALWP 1 2 2N7002_SOT23 2 2 1 P ACIN
PAD-OPEN 4x4m G PR24 47K_0603_5%
S
PAD-OPEN 4x4m Precharge detector

3
PJP4
+1.25VSP 1 2 +1.25VS (1.5A,120mils ,Via NO.= 6) (6A,240mils ,Via NO.= 12) 15.34 15.90 16.48

1
PAD-OPEN 4x4m PQ3
PJP5 13.13 13.71 14.20 DTC115EKA_SOT23
PJP6 1 2
+3VALWP +3VALW 100K
+CPUVIDP 2 1 +CPUVID (150mA,40mils ,Via NO.= 2) 2 +5VALWP
PAD-OPEN 4x4m
PAD-OPEN 2x2m
100K
(6A,240mils ,Via NO.= 12)
PJP7

3
+1.5VSP 1 2 +1.5VS (6A,240mils ,Via NO.= 12)
PJP8
PAD-OPEN 4x4m 1 2 +VGA_CORE
+VGA_COREP
4 4

PJP9 PAD-OPEN 4x4m

+12VALWP 2 1 +12VALW (300mA,20mils ,Via NO.= 1)
(5A,200mils ,Via NO.= 10)
PAD-OPEN 2x2m
PJP10
1 2
+VTT_GMCHP +VTT_GMCH
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
PAD-OPEN 3x3m OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
(1.2A,60mils ,Via NO.= 3) SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE DCIN & DETECTOR
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY LA-2041 0.1
THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS,
IN C . D ate: ¬P 期三, 七月 09, 2003 Sheet 46 of 56
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 84 degree C
Recovery at 45 degree C

1 1

VL VS VL
VMB
PCN2

2
1 PF2 PL2 10KB_0603_1%_TH11-3H103FT
BATT+ PH1 PR25
BATT+ 2 1 2 1 2 BATT+

1
3 ALI/N IMH# 2 1 C8B BPH 853025_2P
ID A B/I PR26 1K_0603_5% 15A_65VDC_451015 +3VALWP PC14 47K_0603_1%
B/I 4 MAINPW ON 46,49
5 TS_A 0.1U_0603_25V7K

1
TS

1
6 EC_SMDA 1 2 PC15 PC16
SMD

1
7 EC_SMCA PR27 47K_0603_5% 1 2

2
SMC 1000P_0603_50V7K 0.01U_0603_50V7K PR28
10 8

2
GND GND-
1

8
11 9 PR31 47K_0603_1% PQ4
GND GND- PR29 PR30 PU3A PD10
3 1 2 3

P
+ 100K
SUYIN_200275MR009G116ZL PR32 16.9K_0603_1%
100_0603_5% 100_0603_5% TM_REF1 O 1 2 1 2
DTC115EKA_SOT23
1 2 -

G
1K_0603_5% 1SS355_SOD323
2

2
2 LM393M_SO8 100K

3
PD9

@ BAS40-04_SOT23

1
PC17
PR33 PR34
ALI/MH# 39
2 1 VL

2
0.22U_0805_16V7K 3.32K_0603_1% 100K_0603_1%
1 2 +3VALWP

2
PR35 25.5K_0603_1%

1
2 2
1

1
PR36
PR37 PD11 PC18
1K_0603_5% @ BAS40-04_SOT23 100K_0603_1%

2
3
2

1000P_0603_50V7K
1

BATT_TEMPA 39
PH2 near main Battery CONN :
EC_SMB_DA1 39,40 BAT. thermal protection at 79 degree C
EC_SMB_CK1 39,40 Recovery at 45 degree C
1

PD12 PD13
@ BAS40-04_SOT23 @ BAS40-04_SOT23

VL VL
3

2
3 PH2 PR38 3

47K_0603_1%
10KB_0603_1%_TH11-3H103FT
PR39
+5VALWP

1
1 2
47K_0603_1%

8
PU3B
1 2 5 PD14

P
PR40 14.7K_0603_1% +
O 7 2 1
TM_REF2 6 -

G
1SS355_SOD323
LM393M_SO8

4
1
1
PC19 PR42
PR41
0.22U_0805_16V7K 3.48K_0603_1% 2 1 VL

1
100K_0603_1%

1
PC20 PR43
100K_0603_1%

2
1000P_0603_50V7K

4 4

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE BATTERY CONN / OTP
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY LA-2041 0.1
THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS,
IN C . D ate: ¬P 期三, 七月 09, 2003 Sheet 47 of 56
A B C D
 A B C D

Iadp=0~5.8A
P2 P3 B+ B++
PQ7
SI7447DP_SO8
PQ5 PQ6
PR44 PL3
V IN 8 D S 1 1 S D 8 2 1 1 2 1
7 2 2 7 C8B BPH 853025_2P 2
D S S D

1
6 3 3 6 0.01_2512_1% PC21 PC22 PC23 3 5
D S S D
5 D G 4 4 G D 5
1

1
1 4.7U_1210_25V6K 4.7U_1210_25V6K 4.7U_1210_25V6K 1

2
PR45 PR46

4
SI4825DY_SO8 SI4825DY_SO8
10K_0603_5% 200K_0603_1%
2

2
PR47 PR48
AC OFF# 1 2 1 2 V IN
10K_0603_5% 47K_0603_5%

1
PR49 PU4 PR50
PD15 1 24
39,52 ADP_I -INC2 +INC2

3
2
1
AC OFF#1 2 150K_0603_1% 0_0603_5%
2 PQ8

1
1SS355_SOD323 2 1 2 23 SI4835DY_SO8
PR51 100K_0603_5% OUTC2 GND PC24 N18 PQ9
4
0.022U_0603_25V7K DTC115EKA_SOT23
1

D CS
3 +INE2 CS 22 1 2 100K
P ACIN 1 2 2 PQ10 2
46,49 P ACIN ACOFF 39
PR52 G PC25

1
3K_0603_5% S 2N7002_SOT23 4 21 1 2
3

-INE2 VCC(o)

1
PR53 100K

5
6
7
8
1 PR54 PC27 PR55 0.1U_0603_25V7K

3
AC ON PC26 33.2K_0603_1% 1 2 1 2 5 20
46 ACON FB2 OUT
10K_0603_1% 10K_0603_5%
2

2
2 4700P_0603_50V7K
0.1U_0603_16V7K 6 19 1 2 LXCHRG
VREF VH PC28

1
PC29 PC30 PR56 0.1U_0603_25V7K
2
IREF=1.31*Icharge 1 2 1 2 7 18 1 2 2

0.1U_0603_16V7K 1K_0603_5% FB1 VCC PC31

IREF=0.73~3.3V 2 1000P_0603_50V7K 0.1U_0603_25V7K CC=0.5~2.7A
8 17 1 2
-INE1 RT PR57 CV=16.8V(12 CELLS LI-ION)
68K_0603_5%
1 2 9 16 PL4
39 IR E F 205K_0603_1% +INE1 -INE3
PR58 22UH_SPC-1204P-220A PR59 4.7U_1210_25V6K
PR61 PC32 1 2 1 2
+3VALWP 2 1 10 OUTC1 FB3 15 1 2 1 2
BATT+
1

PR60 10K_0603_5% 47K_0603_5% 0.02_2512_1%

1

CS PR62 PC33 1500P_0603_50V7K

1

11 14 AC ON
OUTD CTL
1

1
PR63 100K_0603_1% 0.1U_0603_16V7K PD16 PC34 PC35 PC36
2

47K_0603_5% PQ11
2

DTC115EKA_SOT23 12 13

2
-INC1 +INC1 RB051L-40_SOD106
2

100K
2

2
MB3887_SSOP24
1

PQ12 100K
DTC115EKA_SOT23
3

4.7U_1210_25V6K 4.7U_1210_25V6K
100K
39 FSTCHG 2

PR64 PR65
100K 2 1
4.2V 2 1
3

47.5K_0603_0.1% 143K_0603_0.1%
3 3

VMB
1

PR66
OVP voltage : LI 340K_0603_1%
4S3P : 17.4V--> BATT_OVP= 1.935V
2

(BAT_OVP=0.1111 *VMB)
1

PR67
+5VALWP 499K_0603_1%
2
8

PU5A
3
P

+
1
39 BATT_OVP 0
2
-
G

LM358A_SO8
4
1

4 4
1

PC37 PR68
1

PR69 PC38

@ 0.1U_0603_16V7K 2.2K_0603_5% 0.01U_0603_50V7K

2

105K_0603_0.5%
2

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CHARGER
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY LA-2041 0.1
THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS,
IN C . D ate: ¬P 期三, 七月 09, 2003 Sheet 48 of 56
A B C D
 5 4 3 2 1

PC39
4.7U_1210_25V6K
N4 1 2

1
PD17

2
PC40
PC41
470P_0805_100V7K EC11FS2_SOD106

1
D 1 2 BST31 BST51 D

2
PL5 B+++ S NB 2 1 FLYBACK
0.1U_0603_25V7K PR70 22_1206_5%

2
B+ 1 2

HCB4532K-800T90_1812

2
1

PC42 PC43 VS PD18 PC44

1 2

3
@ 4.7U_1210_25V6K PQ13 DAP202U_SOT323 PT1
2

1 8 P DH31 1 2 0.1U_0603_25V7K B+++ SDT-1205P-100

D1 G1

2
2 7 PR71 PD19

1
4.7U_1210_25V6K D1 S1/D2 0_0603_5% VL
3 G2 S1/D2 6
4 5 PLX3 1SS355_SOD323
S2 S1/D2 +12VALWP
SI4814DY_SO8 PC47

1
4.7U_1206_16V4Z PC46

1
PC45 4.7U_1210_25V6K

2
1
@ 4.7U_1210_25V6K

1
PDL3 PC48 PC49
1

0.1U_0603_25V7K PQ14

2
1

PC50 4.7U_1206_16V4Z

PDH3
1 8

2
PL6 D1 G1
2 7
2

47P_0603_50V8J PR72 D1 S1/D2

3 G2 S1/D2 6
SPC-1205P-100 PD H5 1 2 P DH51 4 5
S2 S1/D2
0_0603_5% SI4814DY_SO8
2

1
PC51

22

21
C C
25 4 PDL5 47P_0603_50V8J

VL
V+

2
BST3 12OUT
VDD 5
27 18 CS H5
DH3 BST5
1

PU6 DH5 16
PR74 PR73 26 17 PLX5
LX3 LX5

1
24 DL3 DL5 19

1
+3VALWP 0.012_2512_1% 1M_0603_1% 20 PR75
PGND PR76
14
2

CS H3 CSH5 2M_0603_5%
1 CSH3 CSL5 13
3.57K_0603_1% 2 12 0.012_2512_1%

2
CSL3 MAX1632 FB5
3 15

2
FB3 SEQ
1 1 46,48 PACIN 1 2 10 SKIP# REF 9 2.5VREF
1

PD20 PR77 23 6
SHDN# SYNC
1

PC52 + + PC53 PR78 PC54 @ 10K_0603_5% 11

RST#

1
7 PC55
150U_D2_6.3VM @ 150U_D2_6.3VM EP10QY03 TIME/ON5
31,34,39,40,41,50,51,52 SUSP# 1 2 +5VALWP
2

2 2 PR201 4.7U_1206_16V4Z
28

GND
2

2
10K_0603_5% RUN/ON3
1 1
1

1
100P_0603_50V8J

1
PC56 PR79 PC59 + +
2

PON 680P_0603_50V8J PC57 PD21

2

PR80 10.5K_0603_1% 100P_0603_50V8J 150U_D2_6.3VM PC58 EP10QY03

2
2 2

2
1

10K_0603_1% @ 150U_D2_6.3VM
PR81
1

1
47K_0603_5% PR82
B B
2

2 1 VL
PR83 10K_0603_1%

2
47K_0603_1%
1

PC60
+3.3V Ipeak = 6.66A ~ 10A
0.047U_0603_16V7K
+5V Ipeak = 6.66A ~ 10A
MAINPW ON 46,47
2

PC61

0.047U_0603_16V7K
2

A A

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE 5V/3.3V/12V
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY LA-2041 0.1
THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS,
IN C . D ate: ¬P 期三, 七月 09, 2003 Sheet 49 of 56
5 4 3 2 1
 A B C D

+2.5V/+VTT_GMCHP
PL7
1 2 B+

2
PR84 HCB4532K-800T90_1812

1
PC69 0_0603_5%
1 1

4.7U_1210_25V6K +5VALWP

1
PC66 PC62 PC63 PC64
4.7U_1210_25V6K

1
PC65 4.7U_1206_16V4Z 4.7U_1210_25V6K 4.7U_1210_25V6K

2
PD22
1U_0805_25V4Z

5
6
7
8
DAP202U_SOT323
PQ15

D
D
D
D
2

3
IRF7811A_SO8
PR85
PQ17 2 1
+2.5V

G
S
S
S
1 D1 G1 8

1
2 7 PC68 20_0603_5%
+1.45V/+1.225V

4
3
2
1
D1 S1/D2 1U_0603_10V6K PR87 PL8
3 G2 S1/D2 6
4 5 0_0603_5% 2.2H_SPC-1205P-2R2B_+40-20% +2.5VP

2
S2 S1/D2
1 2 2 1 1 2

1
PL9 SI4814DY_SO8 PR86 PC71

22
1 1

1
+VTT_GMCHP 5UH_SPC-06704-5R0_2.9A_30% PC70 0_0603_5% PU7 0.1U_0603_25V7K PC72 PD28

5
6
7
8
1 2 2 1 1 2 25 21 + +

VCC

UVP
V+
BST1 VDD PC73 EP10QY03
0.1U_0603_25V7K 26 19 PD23 220U_D2_4V 220U_D2_4V

2
DH1 BST2
1

2 2
1 18

2
DH2
1

2 PD27 PC76 27 17 EC31QS04 2

EP10QY03 + 150U_D2_6.3V LX1 LX2

24 DL1 DL2 20 4
CS2 16

2
PR89 28 PQ16
2

2 CS1 FDS6672A_SO8 PR92

1 15
2

4.53K_0603_1% OUT1 OUT2

14 15K_0603_1%

3
2
1
FB2
2 FB1 ON2 12

1
PR90 PGOOD 7
TON 5
1 2 11 ON1
41,51,52 VS_ON @ 0_0603_5% 13
ILIM2
3

SKIP
GND
OVP

REF
ILIM1
1

1
2 1 S YSON 39,41,42
PR88 1 2 PR94 @ 0_0603_5%
10K_0603_1% 31,34,39,40,41,49,51,52 SUSP# PR93

23

10
PR91 MAX1845EEI_QSOP28 PR99 2 1 V_ON 41 10K_0603_1%
@ 0_0603_5% 42.2K_0603_1% PR95 0_0603_5%
2

2
2 1

1 2
1

5,53 ENLL PR100

1

D PR96 PR206 220K_0603_1%

2 10K_0603_1% 0_0603_5% 1 2 1 2 2 1
53 GMCH_SEL G
PQ23 S 1 2 PR203 PR202
3

2N7002_SOT23 24,52,53 VGATE 0_0603_5% @ 0_0603_5%

1
PR207
@ 0_0603_5% PC79 PR97 PR98
3 0.22U_0805_16V7K 3

2
100K_0603_1% 100K_0603_1%

2.5V OCP 11.84A ~ 21A

2
GMCH_SEL=0 PRESCOTT VTT_GMCH=1.225V OCP 1.92A ~ 3.71A

GMCH_SEL=1 NORTHWOOD VTT_GMCH=1.45V OCP 1.98A ~ 3.78A

4 4

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE DDR_2.5V/VTT_GMCH
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY LA-2041 0.1
THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS,
IN C . D ate: ¬P 期三, 七月 09, 2003 Sheet 50 of 56
A B C D
 A B C D

PL10
1 2 B+

2
HCB4532K-800T90_1812

1
PC80 PC81 PR101 PC82 PC83

1
4.7U_1210_25V6K 4.7U_1210_25V6K 0_0603_5% +5VALWP

2
4.7U_1210_25V6K 4.7U_1210_25V6K

2
1 1

1
PC85

1
PC84 4.7U_1206_16V4Z

2
PD24

2
DAP202U_SOT323 1U_0805_25V4Z

3
+1.5V 1845VCC 2 1
PR102

PC87

1
1U_0603_10V6K 20_0603_5%
+1.5VSP PQ18
PL11 8 1

2
2.2H_SPC-1205P-2R2B_+40-20% G1 D1 PC89

22
7 S1/D2 D1 2

9
1 2 6 3 PC88 PR103 PU8 PR104
S1/D2 G2 0_0603_5% 0.1U_0603_25V7K
5 4 2 1 1 2 25 21

VCC

UVP
V+
S1/D2 S2 BST1 VDD
1

1 1 0.1U_0603_25V7K 1 2 2 1
PD29 PC90 PC91 SI4814DY_SO8 0_0603_5% 26 19
DH1 BST2
1

EP10QY03 + + PR194 18

470U_D2_2.5VM @ 470U_D2_2.5VM 5.1K_0603_1%

27
24
LX1
DH2
LX2 17
20
+1.28V/1.15V
2

2 2 DL1 DL2 PQ19

CS2 16
28 1 8 PL12
2

CS1 D1 G1 2.2H_SPC-1205P-2R2B_+40-20% +VGA_COREP

1 OUT1 OUT2 15 2 D1 S1/D2 7
2
FB2 14 3 G2 S1/D2 6 1 2 2

2 FB1 ON2 12 4 S2 S1/D2 5

1
1

1
7 SI4814DY_SO8 PR113 470U_D2_2.5VM PD30
PGOOD
1

PR195 PR106 5 PC156 1 1

SUSP# TON 2.8K_0603_1% PC94
1 2 11

2
10K_0603_1% 31,34,39,40,41,49,50,52 SUSP# @ 0_0603_5% ON1 @ 4700P_0603_50V7K + PC93 + EP10QY03
13

2
ILIM2
3

SKIP
GND
OVP

REF

2
VS_ON PR1072 ILIM1 @470U_D2_2.5VM
1
2

41,50,52 VS_ON 2 2
0_0603_5%

23

10
MAX1845EEI_QSOP28 2 1 SUSP#

1
PR108 PR112 @ 0_0603_5%
16.2K_0603_1% PC157 PR114
1 2 1 2 VS_ON @ 2200P_0603_50V7K

2
PR109 0_0603_5% 10K_0603_1%

2
PR205 PR204
1 2 1 2 1 PR117 2
43K_0603_1%
100K_0603_1% 16.2K_0603_1%

1
PR119 D

1
PC95 PR118 2 PR208
1.5V OCP 6.9A ~ 8.72A 0.22U_0805_16V7K 100K_0603_1%
100K_0603_1%
16 POW ER_SEL
PQ20
G
S 8.66K_0603_1%

3
2N7002_SOT23

2
3 3

NV34M Ultra

POWER_SEL=1 VOUT=1.28V OCP 7.1A ~ 8.9A PR113=2.8K_0603_1%

PR208=8.66K_0603_1%
POWER_SEL=0 VOUT=1.15V OCP 6.85A ~ 8.7A

NV31

POWER_SEL=1 VOUT=1.27V OCP 7.1A ~ 8.9A PR113=2.7K_0603_1%

4 4

POWER_SEL=0 VOUT=1V OCP 6.85A ~ 8.7A Unpop PR208

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE VGA_CORE/1.5V
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY LA-2041 0.1
THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS,
IN C . D ate: ¬P 期三, 七月 09, 2003 Sheet 51 of 56
A B C D
 5 4 3 2 1

+3VS
145W THROTTLING 1
PR120
2
1M_0603_1% VL
120W REVOVERY VS

1
1
t = -RC(1-Vb/Va) 100K_0603_5%
PR121
H_PROCHOT# 5,7

1
PC97 R422

8
365K_0603_1% Va PU9B
39,48 ADP_I

2
D 0.1U_0603_25V7K 1 2 5 D

P
+3VS

2
+

8
R658 200K_0603_1% 7 1 2
O CK409_PW RGD# 15

1
D R702 0_0402_5%
1 2 3 1 2 6

P
+ +CPU_CORE -

G
PR122 64.9K_0603_1% 1 2 PQ21 R659 10K_0603_1%
O G 2N7002_SOT23 LM393M_SO8
VL 1 2 2 Vb

4
-

1
PR123 249K_0603_1% PU9A S 1

3
LM393M_SO8 C759 R660

4
1

1
PR124 PC99 0.33U_0805_10V7F 100K_0603_1%
PC98 10P_0603_50V8J 2

2
100K_0603_1% 1000P_0603_50V7K

2
2

1
D
1 2 2 Q70
+CPU_CORE
R703 @0_0402_5% G @2N7002_SOT23
S

3
24,50,53 VGATE 1 2
R704 @0_0402_5%

+3VALWP

+3VALWP

2
PR125
0_1206_5%
C C
PR126

1
1 2

5.1_0603_5%

1
PC100 PC101
1U_0603_10V6K 4.7U_1206_16V4Z
PR110

2
1
2
100K_0603_5% PC92

2
0.1U_0603_16V7K

PU10 PL13 +1.25VSP

1 8 5UH_SPC-06704-5R0_2.9A_30%
VIN PVIN
2 GND LX 7 1 2
3 SD PGND 6
+2.5VP 2 1 4 VREF VFB 5
PR111 1
PR128
105K_0603_0.5% PQ46 CM3718 100K_0603_5%

F B_VDD+

1
2N7002_SOT23 1 2 + PC103
1

PC104 D 220U_D2_4VM
1

PR115 2 PC96

2
0.1U_0603_16V7K G 0.1U_0603_16V7K 2
105K_0603_0.5% S 1 PR129 2 1 2
2

PC102
2

B 1K_0603_5% B
470P_0603_50V8J
19,41 SUSP 1 2
PR196 @ 0_0603_5%
REMOTE SENSE

1 2
PR197 0_0603_5%
1

PR198 D
1 2 2 PR116
31,34,39,40,41,49,50,51 SUSP#
G @ 499K_0603_1%
@ 0_0603_5% S
3

PQ22
1

PR199 2N7002_SOT23
41,50,51 VS_ON 1 2

0_0603_5%

A A

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE DDR_1.25V/CLOCK THROTTLING
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY LA-2041 0.1
THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS,
IN C . D ate: ¬P 期三, 七月 09, 2003 Sheet 52 of 56
5 4 3 2 1
 A B C D

Different Pin Definition for ISL6561 in PU9

#7 GND #11 REF #33 EN #38 OVP

#9 TCOMP #14 IDROOP #35 GND #40 GND

1 1
B+
#10 DAC #18 RGND #37 GND +5VALWP
PR130
Battery Feed

2
80.6K_0603_1%
PR131 Forward

1
@ 0_0603_5%
PC106 PU11

1
PR133 1U_0603_10V6K 32 7 2 PR132
1

2
VCC RAMPS 10K_0603_5%
1 2
1 39 VGATE 24,50,52
5 H_VID4

1
0_0603_5% VID4 PGOOD
5 H_VID3 2 VID3
5 H_VID2 3 VID2

1
4 25 PWM1 54
5 H_VID1 VID1 PWM1
PR134 5
5 H_VID0 VID0 ISEN1+ 54
0_0603_5% 6 24
5 H_VID5 VID12.5 ISEN1+
ISEN1- 23
34 ISEN1- 54
5,50 ENLL
2
PR135 ENLL
1 2 33 26 PWM2 54
24 PM_DPRSLPVR DRSEN PWM2
@ 0_0603_5% 27 ISEN2+ 54
ISEN2+
15,24 STP_CPU# 2 1 35 DSEN# ISEN2- 28
PR136 ISEN2- 54
@ 0_0603_5%
20 PWM3 55
+5VALWP PWM3
2

1
10 OCSET
PR138 21 ISEN3+ 55
PR137 PR140 @ 1K_0603_1% ISEN3+
2
PC107 ISEN3- 22 2
1

1
@ 0_0603_5% PR142 2 PR139 1 ISEN3- 55
+5VALWP
PR141 2 1 11 @ 0_0603_5%
1

2
@ 0_0603_5% 69.8K_0603_1% SOFT PWM4 55
PWM4 31
475_0603_1%
1U_0603_10V6K ISEN4+ 55
30
2

2
ISEN4+
9 DSV ISEN4- 29
Frequency Select ISEN4- 55
PR144
1

PU5B 20K_0603_1%
1

PR143
+ 5 36 FS COMP 15 2 1 1
PC108 1000P_0603_50V7K
2
7 0
PC109 27.4K_0603_1% 6 2 1
2

100P_0603_50V8J - PC110 @ 1000P_0603_50V7K

37 13
2

PR145 DRSV FB
LM358A_SO8 @ 0_0603_5% PR146
1 2 38 14 2 1 PR148
VR-TT# NC
2

1
0_0603_5% @ 0_0603_5%
220P_0603_50V8J 40 16 2 1 2 1
+3VALWP NTC VDIFF

2
PR147 17 PC111
VSEN

1
PR149 100K_0603_5% PC112 PH3 12 18 @ 1000P_0603_50V7K
10K_0603_1% 330K_0402_5% GND VRTN
+5VALWP
1

19 8 1 2

2
GND OFS
2

PR151 Place close to IC PR150 2.26K_0603_1%

1
2

1
ISL6247_MLFP40 PR153

D
PR152 0.1U_0603_16V7K 3 1 2 1
PR155 PR154 1.2M_0603_5% PC113 PQ24
45.3K_0603_1% 32.4K_0603_1% NOW DISABLE THIS FUNCTION, POP 330K_0402_5% PQ25 2N7002_SOT23 16.2K_0603_1%
1

1
Panasonic ERTJ0EV334J (0402) TP0610T_SOT23 PC114

G
1

2
2
3 @ 10K_0603_5% 1U_0603_10V6K 3
Locate this NTC resistor on

2
1

2
PCB between phase 2 and 3 PR158
2 PR157 2 1 Remote
5 VID_PW RGD for thermal compensation. 5.1K_0603_1% PR159 0_0603_5%
+CPU_CORE
Sensing

1
+3VALWP PU12 PQ26 PR160

1
1

PR161 D 2N7002_SOT23 PR156 27K_0603_5% 2 1 VCCSENSE 5

1
2 1 1.2 VDD 1 5 +CPUVIDP 2 @ 0_0603_5%
IN OUT
1

G 340K_0603_1% PR162 Place near +VCC_CORE

1
0_0603_5% PC115 D
4 S 2 1
output capacitor
3

4.7U_1206_16V4Z PG PQ27 0_0603_5%

50 GMCH_SEL 2
2

3 2 G 2N7002_SOT23
EN GND PC116 S 2 PR163 1 VSSSENSE 5

3
1
4.7U_1206_16V4Z
2

MIC5258_SOT23-5 2 1 2 PQ28 @ 0_0603_5%

4 BOOTSELECT
2 1 PR164 MMBT3904_SOT23
39 VR_ON

1
22K_0603_5%

3
2

PR165
0_0603_5% PR167 PR166
100K_0603_5%
100K_0603_5%
2
1

1. When mode control signal is

high/ low, the VR will operate to
4
Northwood/ Prescott load line. 4

2. VID5(12.5) should be pulled

high, when the VR operates to
Nothwood load line.

BOOTSELECT=1 PRESCOTT THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS CPU_CORE_Controller
BOOTSELECT=0 NORTHWOOD AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY LA-2041 0.1
THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS,
IN C . D ate: ¬P 期三, 七月 09, 2003 Sheet 53 of 56
A B C D
 A B C D

CPU_B+
1 PL142 B+
+5VALWP PC117
1 1
2 1 4.7U_1210_25V6K

5
6
7
8

5
6
7
8

1
PQ29 PQ30 PC120 PC121 PC122 + PC118 + PC119 C8B BPH 853025_2P

2
22U_23V

D
D
D
D

D
D
D
D
PR168 0.22U_0805_16V7K 4.7U_1210_25V6K 22U_23V

2
4.7U_1210_25V6K 2 2
0_0603_5%

G
S
S
S

S
S
S
1 1

4
3
2
1

4
3
2
1
SI4892DY_SO8 SI4892DY_SO8
PU13
6 VCC BOOT 2
PR169
53 PWM1 3 PWM UGATE 1N5 2 1 N6
PR170 2.2_0603_5% PL15
2 1 7 8 PHASE1 1 2
2
0_0603_5% EN PHASE

2
PR171 PC123 4 5 0.6U_HK_AE26A0R6_26A_25%
GND LGATE

5
6
7
8

5
6
7
8

1
499K_0603_1% PC124 ISL6207CB-T_SO8 PQ31 PQ32

D
D
D
D

D
D
D
D
1
0.1U_0603_16V7K 1U_0805_25V4Z SI4362DY_SO8
1

1
SI4362DY_SO8 PR172
PR173 PC125
68_0805_5%

G
S
S
S

S
S
S
2 1 2 1

12
PC126

4
3
2
1

4
3
2
1
CPU_DRIVE_EN 220P_0603_50V8J
32.4K_0603_1% 0.01U_0603_16V7K

2
N7

PH4
53 ISEN1-
53 ISEN1+ 2 1

2
CPU_B+ 820B_0603_5%_ERAV33J821V 2
PC127
PC128
1 2 PC129 Local Transistor

5
6
7
8

5
6
7
8

1
PQ33 PQ34 4.7U_1210_25V6K Swtich Decoupling
2

1
D
D
D
D

D
D
D
D
PR174 0.22U_0805_16V7K PC130

2
0_0603_5% 4.7U_1210_25V6K 4.7U_1210_25V6K

2
G

G
S
S
S

S
S
S
1

4
3
2
1

4
3
2
1
SI4892DY_SO8
PU14 SI4892DY_SO8
6 VCC BOOT 2
PR175
53 PWM2 3 PWM UGATE 1N8 2 1 N9
2.2_0603_5% PL16
7 8 PHASE2 1 2 +CPU_CORE
EN PHASE
2

5
6
7
8

5
6
7
8
PR176 4 5 0.6U_HK_AE26A0R6_26A_25%
GND LGATE
2

1
499K_0603_1% PQ36

D
D
D
D

D
D
D
D
PC131 ISL6207CB-T_SO8 PQ35 SI4362DY_SO8
1U_0805_25V4Z PR177
1

SI4362DY_SO8 68_0805_5%
G

G
S
S
S

S
S
S
PR178 PC133

1 2
4
3
2
1

4
3
2
1
2 1 2 1
PC132
220P_0603_50V8J

2
32.4K_0603_1% 0.01U_0603_16V7K
3 3

N10

PH5
53 ISEN2-
53 ISEN2+ 2 1

820B_0603_5%_ERAV33J821V

Local Transistor
Swtich Decoupling

4 4

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CPU_CORE_Power stage 1
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY LA-2041 0.1
THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS,
IN C . D ate: ¬P 期三, 七月 09, 2003 Sheet 54 of 56
A B C D
 A B C D

CPU_B+
PC134
1 1 2 1

PC135 PC136 PC137

5
6
7
8

5
6
7
8

1
+5VALWP PQ37 @ 4.7U_1210_25V6K
PR179 0.22U_0805_16V7K PQ38

D
D
D
D

D
D
D
D
0_0603_5% 4.7U_1210_25V6K

2
4.7U_1210_25V6K

G
S
S
S

S
S
S
4
3
2
1

4
3
2
1
PU15 SI4892DY_SO8 SI4892DY_SO8
6 VCC BOOT 2
PR180
53 PWM3 3 PWM UGATE 1N11 2 1 N12
PL17
2.2_0603_5%
7 8 PHASE3 2 1
EN PHASE
2

PR181
4 GND LGATE 5 0.6U_HK_AE26A0R6_26A_25%

5
6
7
8

5
6
7
8

1
499K_0603_1%
PC138 ISL6207CB-T_SO8 PQ39 PQ40 PR182

D
D
D
D

D
D
D
D
1U_0805_25V4Z SI4362DY_SO8 SI4362DY_SO8 68_0805_5%
1

1
PR183 PC139

2
G

G
S
S
S

S
S
S
2 1 2 1

4
3
2
1

4
3
2
1

1
PC140
32.4K_0603_1% 0.01U_0603_16V7K
220P_0603_50V8J

2
2 N13 2

PH6
53 ISEN3-
53 ISEN3+ 2 1 +CPU_CORE
CPU_DRIVE_EN CPU_B+ 820B_0603_5%_ERAV33J821V
PC141
1 2
4.7U_1210_25V6K
2

5
6
7
8

5
6
7
8

1
0.22U_0805_16V7K
PQ41 PQ42 PC144 Local Transistor
PR184 PC142 Swtich Decoupling

D
D
D
D

D
D
D
D
0_0603_5% PC143 @ 4.7U_1210_25V6K

2
4.7U_1210_25V6K
1

G
S
S
S

S
S
S
4
3
2
1

4
3
2
1
PU16 SI4892DY_SO8 SI4892DY_SO8
6 VCC BOOT 2
PR185
53 PWM4 3 PWM UGATE 1N14 2 1 N15
2.2_0603_5% PL18
7 8 PHASE4 1 2
EN PHASE
2

PR186 4 5 0.6U_HK_AE26A0R6_26A_25%
GND LGATE
2

5
6
7
8

5
6
7
8

1
499K_0603_1%
PC145 ISL6207CB-T_SO8 PQ43 PQ44
D
D
D
D

D
D
D
D
1U_0805_25V4Z SI4362DY_SO8 SI4362DY_SO8 PR187
1

68_0805_5%
3 3
PR188 PC146

1 2
G

G
S
S
S

S
S
S
2 1 2 1
4
3
2
1

4
3
2
1
PC147
220P_0603_50V8J

2
32.4K_0603_1% 0.01U_0603_16V7K

N16

PH7
53 ISEN4-
53 ISEN4+ 1 2

820B_0603_5%_ERAV33J821V

4 4

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CPU_CORE_Power stage 2
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY LA-2041 0.1
THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS,
IN C . D ate: ¬P 期三, 七月 09, 2003 Sheet 55 of 56
A B C D
DBQ01 PIR LIST
************* Rev0.1 PIR List **************

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND DBQ01 PIR LIST
PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE B 0.1
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-2041
D ate: ¬P 期三, 七月 09, 2003 Sheet 56 of 56