A B C D E

1 1
ZZZ

PCB

2
Compal Confidential 2

HM51_TR/HM70_TR Discrete
NDWG2/NDWH1 LA5992 Schematic Document

Mobile AMD S1G3/RS880M/SB710

3 3

2009/12/02 Rev 1.0

4 4

Sec
Securityy Classification
i t on Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 1 of 55
A B C D E
 5 4 3 2 1

Compal confidential
DDRII 667/800 DDRII-SO-DIMM X2
Project Code: NDWG2/NDWH1 AMD S1G3 CPU page 10,11
File Name : LA-5992P 638P PGA
page 6,7,8,9 Dual Channel
D VRAM 512MB D

64M16 x 4 H_A#(3..31) H_D#(0..63)

page 21
HT 16x16 1000MHZ
DDR2 500MHz Clock Generator
LCD Conn. ATI M92-S2 XT PCI-Express 16x ATI-RS880M Thermal Sensor
page 30 ADM1032ARM SLG8SP626
page 17,18,19,20,21,22
465 BGA page 8
ICS9LPRS488BKLFT
page 16
page 12,13,14,15
CRT Conn.
page 29
PCIE X1 A-Link Express II
4 x PCIE

C C
USB 2 0

Mini card WLAN 10/100 LAN

AR8114 / AR8132 Int. Camera USB conn X2 CardReader
page 37 page 31
ATI-SB710 page 30 page 38 RTS5159
page 33

549 BGA SATA0 HDD Conn.

page 28
RJ45 CONN
page 32
page 23,24,25,26,27 ODD Conn.
SATA2
page 28

B
LPC BUS B

3.3V 33 MHz

Power On/Off CKT / LID switch / Power OK CKT Debug Port ENE KB926 D3 HDA Codec ALC272
page 34 page 34 page 41
page 39

DC/DC Interface CKT. LED RTC CKT.

page 43 page 40 page 23 Touch Pad Int.KBD SPI ROM AMPLIFIER MIC CONN HP CONN
page 35 page 35 page 36 TPA6017 page 42 page 42
page 42
Power Circuit DC/DC
page 43-53 SPK CONN
page 42
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 2 of 55
5 4 3 2 1
 5 4 3 2 1

Voltage Rails SIGNAL

STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
VIN Adapter power supply (19V) N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
B+ AC or battery power rail for power circuit. N/A N/A N/A
+CPU CORE Core voltage for CPU ON OFF OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
D D
+0.9V 0.9V switched power rail for DDR terminator ON ON OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+1.1VS 1.05V switched power rail ON OFF OFF
+1.2V HT 1.25V switched power rail ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.5VS 1.5V power rail for PCIE Card ON OFF OFF
+1.8V 1.8V power rail for CPU VDDIO and DDR ON ON OFF
+1.8VS 1.8V switched power rail ON OFF OFF Board ID / SKU ID Table for AD channel
+2.5VS 2.5V for CPU VDDA and MXM/B ON OFF OFF Vcc 3.3V +/- 5%
+3VALW 3.3V always on power rail ON ON ON* Ra/Rc/Re 100K +/- 5%
+3V LAN 3.3V power rail for LAN ON ON ON Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VS 3.3V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+5VALW 5V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+5VS 5V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+VSB VSB always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+RTCVCC RTC power ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
C C
Note ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
BTO Option Table
BOARD ID Table
BTO Item BOM Structure
Board ID PCB Revision 10/100 Lan 8114@
0 No Support VaryBright GIGA Lan 8132@
1 17" ID 17@
2 15" ID 15@
3 Support VaryBright
EC SM Bus1 address EC SM Bus2 address 4
5
B B
Device Address Device Address 6
Smart Battery 0001 011X b ADM1032 1001 100X b 7
GMT G781-1 (GPU) 1001 100X b

PROJECT ID Table
SKU ID SKU
0 NDWG2
SB710 SM Bus 1 address SB710 SM Bus 2 address 1
2
Device Address Device Address 3
Clock Generator 1101 001Xb New Card
4
5
DDR DIMM0 1001 000Xb 6
DDR DIMM2 1001 010Xb 7 NDWH1
A
Wireless Lan A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 3 of 55
5 4 3 2 1
 5 4 3 2 1

DIMMA
DDR A CLK[1..2]

D CPU CLK CPU D

DIMMB
DDR B CLK[1..2]
200MHZ S1G3
SOCKET

H CLKI[1 0] Host Bus H CLKO[1 0]

C C

CK SBLINK BCLK
100MHZ
14.31818MHz CLK NBHT ATI
EXTERNAL 66MHZ NB
CLK GEN. CLK NB 14.318M RS880M
SLG8SP626 / ICS9LPRS488
14.318MHZ
CLK NBGFX
100MHZ
CLK 48M SD
48MHZ

Cardreader
B RTS5159 CLK 14M SB B

14.318MHZ
CLK PCIE MINI

CLK PCIE LAN

ATI
100MHZ

100MHZ

CLK SBSRC BCLK

100MHZ
SB
SB710
CLK PCIE VGA

27M SSC

CLK PCI LPC EC

100MHZ

27MHZ

CLK 48M USB 33MHZ ENE

48MHZ KB926D3
RTC SATA

32.768K Hz
Graphics Mini PCI Socket LAN 25M Hz
32.768K Hz
M92 S2 XT Mini card Atheros
A A
AR8114/AR8132

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 4 of 55
5 4 3 2 1
 5 3 2 1

AMD CPU
S1G3 socket
+CPU_CORE
VDD 0.7V
VIN PU16
36 A
AC ADAPTOR 1.2V
19V 65W ISL6265IRZ-T +CPU_CORE_NB
VDDNB 0 8V 4A
1.1V
+3VS +2.5VS
BATT+ PU7 VDDA 2 5V 250 mA
BATTERY DDRII SODIMMX2
APL5508-25DC-TRL
D 11.1V VDDIO 1.8V 3.6 A D
PU10 +1.2VALW +1.2VALW +1.2V_HT
2.2Ah/6-cell VDD_MEM 1.8V 7A
U46 VLDT 1 2V 1.5 A
TPS51117RGYR
AO4430
VTT 0 9V 1.75 A
VTT_MEM 0.9V 430 mA
+1.8V PU6 +0 9V
PU17 RT9173DPSP
BATTERY CHARGER NB RS880MN
BQ24751ARHDR +NB_CORE
PU12 VDDC 0.95-1.1V 10 A
TPS51117RGYR
VDDHT 680 mA
B+ +1.2VALW +1.1VS PLLVDD 65 mA
PU15
VDDPCIE 1.1V 2.5 A
APL5912
+1 8V KAC-TRL VDDHTRX 680 mA
PU9
TPS51117RGYR IOPLLVDD
VDDHTTX 1.2V 400 mA
+1 8V U37 +1.8VS
AO4430 AVDDDI 20 mA

+3VS AVDDQ 4 mA
PU3
+3VALW U41
Q43 IOPLLVDD18
ISL6237IRZ-T AO4468
+1.5VS SI2301BDS PLLVDD18 1.8V 20 mA
C C
PU8
APL5915KAI +VGA_BBP +1 2V_HT VDD18 10 mA

+USB_VCCA +5VALW VDDA18PCIE 700 mA

U4 20 mA
VDDA18HTPLL
TPS2061DRG4
VDDA18PCIEPLL 120 mA
VDDLT18 300 mA
+5VS
U7 VDDLTP18 15 mA
+3VALW
AO4468 VDD33 60 mA
3.3V
AVDD 110 mA

B+ PU17 +VGA_CORE VGA M92-S2 XT

ISL6268CAZ-T SB SB710
DP[B:A]_VDD10 200 mA
S5_1.2V 510mA
DP[F:E]_VDD10 170 mA
USB_PHY_1.2V 113 mA
DPLL_VDDC 1.1V 150 mA
Q41 VDD 197 mA
PCIE_VDDC 1400 mA
SI2301BDS AVDDCK_1.2V 62 mA
VDDC+VDDCI 11500 mA CKVDD_1.2V 1.2V
+3V_DELAY SPV10 1.2V 120 mA
B
AVDD_SATA 43 mA B
BBP 22 mA
PLLVDD_SATA 600 mA
+5VS VDDR1+VDDRHx 1200 mA
PCIE_VDDR 567 mA
VDD_CT 110 mA
PCIE_PVDD 93 mA
+3VS DPE_PVDD 20 mA
S5_3.3V 32 mA
DP[B:A]_PVDD 20 mA
AVDD TX/RX 17 mA
DP[F:E]_VDD18 200 mA
1.8V AVDDC 658 mA
DPLL_PVDD 120 mA VDDQ 3.3V 131 mA
PCIE_PVDD 40 mA
VDD33_18 71 mA
FAN Control Realtek EC LAN PCIE_VDDR 362 mA
USB X2 AVDDCK_3.3V 47 mA
APL5607 RTS5159 ENE KB926 Atheros AR8114 +1 2V_HT TSVDD 20 mA
XTLVDD_SATA 6 mA
+5V AVDD 70 mA
Dual +5VS 500mA +3.3VS 43mA +3.3VALW 20mA +3.3VALW 300mA V5_VREF 5V 1 mA
+3.3VS 3mA VDD1DI 45 mA
1.5A
VDD2DI 40 mA VBAT 2.5~3.6V

A2VDDQ 7 mA
RTC
VDDR4 170 mA
CLK GEN Bettary
Mini Card VDDR5 170 mA
VRAM HYB18T256161BF x4
A
SLG8SP626VTR A
VDDR3 50 mA VDD 1208mA
+1.5VS 500mA +3.3VS 400mA 3.3V
A2VDD 65 mA VDDL 1.8V
+3.3VS 1A
+3.3VALW 330mA +1.2V_HT 250mA VDDQ
LCD panel Audio AMP Audio Codec
TPA6017A2 ALC272 SATA
15.6"
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
B+ 850mA +5VS 600mA +5VS 45mA +5VS 3A
SCHEMATIC MB A5992
+3.3VS 455mA +3.3VS 25mA +3 3VS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401836 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date Thursday, March 18, 2010 Sheet 5 of 55
5 3 2 1
 5 4 3 2 1

12 H_CADIP[0..15]
H CADIP[0..15] H CADOP[0..15]
H_CADOP[0..15] 12 FAN Control Circuit
H CADIN[0..15] H CADON[0..15]
12 H_CADIN[0..15] H_CADON[0..15] 12
Reserve when PVT
5VS
5VS
for cos down
Change as 10U C92 10U_0805_10V4Z

1
D
1.2V_HT 1.2V_HT for Tigris 1 2 D
JCPU1A D13

2
@ 1SS355_SOD323-2
VLDT=1500mA for HT3 D1 HT L NK AE2 1 2 R247
VLDT_A0 VLDT_B0 C84 10U_0805_10V4Z
D2 AE3 0_0603_5%

2
VLDT_A1 VLDT_B1 U1 @ D4 BAS16_SOT23-3
D3 VLDT_A2 VLDT_B2 AE4 @
D4 AE5 close CPU 1 8 1 2

1
VLDT_A3 VLDT_B3 EN GND
2 VIN GND 7
H CADIP0 E3 AD1 H CADOP0 VCC FAN1 3 6
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0 VOUT GND C97
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1 34 EN_DFAN1 1 2 4 VSET GND 5
H_CADIP1 E1 AC2 H_CADOP1 R733 0_0402_5% 1 10U_0805_10V4Z
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1 C760 APL5607KI-TRG_SO8
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3 1 2
H_CADIP2 G3 AB1 H_CADOP2 @
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2 0.01U_0402_25V4Z 3VS C96
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 H_CADOP3 2 1000P_0402_50V7K
G1 L0_CADIN_H3 L0_CADOUT_H3 AA2
H_CADIN3 H1 AA3 H_CADON3 1 2
L0_CADIN_L3 L0_CADOUT_L3

1
H_CADIP4 J1 W2 H_CADOP4
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4 R37
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
H_CADIP5 L3 V1 H_CADOP5 10K_0402_5%
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
H_CADIP6
L2 L0_CADIN_L5 L0_CADOUT_L5 U1
H_CADOP6
40mil JP12
L1 U2

2
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6 VCC_FAN1
M1 L0_CADIN_L6 L0_CADOUT_L6 U3 1
H_CADIP7 N3 T1 H_CADOP7
L0_CADIN_H7 L0_CADOUT_H7 34 FAN_SPEED1 2
H CADIN7 N2 R1 H CADON7
H CADIP8 L0_CADIN_L7 L0_CADOUT_L7 H CADOP8 3
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4 1
H CADIN8 F5 AD3 H CADON8 C91 CONN@
H CADIP9 L0_CADIN_L8 L0_CADOUT_L8 H CADOP9 1000P_0402_50V7K ACES_85205-03001
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5
H CADIN9 F4 AC5 H CADON9
H CADIP10 L0_CADIN_L9 L0_CADOUT_L9 H CADOP10 2
C H CADIN10
G5
H5
L0_CADIN_H10 L0_CADOUT_H10 AB4
AB3 H CADON10 3VS LDO FAN C
H CADIP11 L0_CADIN_L10 L0_CADOUT_L10 H CADOP11
H3 L0_CADIN_H11 L0_CADOUT_H11 AB5

1
H CADIN11 H4 AA5 H CADON11
H CADIP12 L0_CADIN_L11 L0_CADOUT_L11 H CADOP12 R40
K3 L0_CADIN_H12 L0_CADOUT_H12 Y5
H CADIN12 K4 W5 H CADON12 10K_0402_5% JP38
H_CADIP13 L0_CADIN_L12 L0_CADOUT_L12 H_CADOP13 @ VCC_FAN1
L5 L0_CADIN_H13 L0_CADOUT_H13 V4 1 1
H_CADIN13 M5 V3 H_CADON13 2

2
H_CADIP14 L0_CADIN_L13 L0_CADOUT_L13 H_CADOP14 FANPWN 2
M3 L0_CADIN_H14 L0_CADOUT_H14 V5 34 FANPWM 3 3
H_CADIN14 M4 U5 H_CADON14 4
H_CADIP15 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP15 4
N5 L0_CADIN_H15 L0_CADOUT_H15 T4
H_CADIN15 P5 T3 H_CADON15 CONN@
L0_CADIN_L15 L0_CADOUT_L15 ACES_85205-0400
12 H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 12
12 H_CLKIN0 J2
J5
L0_CLKIN_L0 L0_CLKOUT_L0 W1
Y4
H_CLKON0 12 PWM FAN
12 H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKOP1 12
12 H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 12

12 H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 12

12 H_CTLIN0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 H_CTLON0 12
12 H_CTLIP1 P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 H_CTLOP1 12
12 H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 12

6090022100G_B
Athlon 64 S1
Processor Socket

B B

1.2V_HT

250 mil
VLDT CAP.
2 2 1 1 1 1
C86 C82 C90 C89 C83 C85
0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
10U_0805_10V4Z 10U_0805_10V4Z
1 1 2 2 2 2

Change as 10U Near CPU Socket

for Tigris

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 6 of 55

5 4 3 2 1
 A B C D E

0.9V 0.9V JCPU1C

11 DDRB_SDQ[63..0]
JCPU1B MEM:DATA
DDRA_SDQ[63..0] 10
DDRB_SDQ0 C11 G12 DDRA_SDQ0
DDRB_SDQ1 MB_DATA0 MA_DATA0 DDRA_SDQ1
D10 VTT1 W10 A11 F12
Place them close to CPU within 1" C10 MEM:CMD/CTRL/CLK VTT5 AC10 DDRB_SDQ2 A14
MB_DATA1 MA_DATA1
H14 DDRA_SDQ2
VTT2 VTT6 DDRB_SDQ3 MB_DATA2 MA_DATA2 DDRA_SDQ3
B10 VTT3 VTT7 AB10 B14 MB_DATA3 MA_DATA3 G14
AD10 AA10 DDRB_SDQ4 G11 H11 DDRA_SDQ4
R6 39.2_0402_1% VTT4 VTT8 DDRB_SDQ5 MB_DATA4 MA_DATA4 DDRA_SDQ5
VTT9 A10 E11 MB_DATA5 MA_DATA5 H12
1 2 AF10 @ DDRB SDQ6 D12 C13 DDRA SDQ6
MEMZP DDRB SDQ7 MB_DATA6 MA_DATA6 DDRA SDQ7
1.8V 1 2 AE10 MEMZN VTT_SENSE Y10 PAD T2 A13 MB_DATA7 MA_DATA7 E13
4 R7 39.2_0402_1% DDRB SDQ8 A15 H15 DDRA SDQ8 4
MCH REF DDRB SDQ9 MB_DATA8 MA_DATA8 DDRA SDQ9
H16 RSVD_M1 MEMVREF W17 A16 MB_DATA9 MA_DATA9 E15
@ DDRB SDQ10 A19 E17 DDRA SDQ10
DDRA ODT0 DDRB SDQ11 MB_DATA10 MA_DATA10 DDRA SDQ11
10 DDRA_ODT0 T19 MA0_ODT0 RSVD_M2 B18 PAD T17 A20 MB_DATA11 MA_DATA11 H17
DDRA ODT1 V22 DDRB SDQ12 C14 E14 DDRA SDQ12
10 DDRA_ODT1 MA0_ODT1 MB_DATA12 MA_DATA12
U21 W26 DDRB ODT0 DDRB SDQ13 D14 F14 DDRA SDQ13
MA1_ODT0 MB0_ODT0 DDRB_ODT0 11 MB_DATA13 MA_DATA13
V19 W23 DDRB ODT1 DDRB SDQ14 C18 C17 DDRA SDQ14
MA1_ODT1 MB0_ODT1 DDRB_ODT1 11 MB_DATA14 MA_DATA14
Y26 DDRB SDQ15 D18 G17 DDRA SDQ15
DDRA SCS0# MB1_ODT0 DDRB SDQ16 MB_DATA15 MA_DATA15 DDRA SDQ16
10 DDRA_SCS0# T20 MA0_CS_L0 D20 MB_DATA16 MA_DATA16 G18
DDRA_SCS1# U19 V26 DDRB_SCS0# DDRB_SDQ17 A21 C19 DDRA_SDQ17
10 DDRA_SCS1# MA0_CS_L1 MB0_CS_L0 DDRB_SCS0# 11 MB_DATA17 MA_DATA17
U20 W25 DDRB_SCS1# DDRB_SDQ18 D24 D22 DDRA_SDQ18
MA1_CS_L0 MB0_CS_L1 DDRB_SCS1# 11 MB_DATA18 MA_DATA18
V20 U22 DDRB_SDQ19 C25 E20 DDRA_SDQ19
MA1_CS_L1 MB1_CS_L0 DDRB_SDQ20 MB_DATA19 MA_DATA19 DDRA_SDQ20
B20 MB_DATA20 MA_DATA20 E18
DDRA_CKE0 J22 J25 DDRB_CKE0 DDRB_SDQ21 C20 F18 DDRA_SDQ21
10 DDRA_CKE0 MA_CKE0 MB_CKE0 DDRB_CKE0 11 MB_DATA21 MA_DATA21
DDRA_CKE1 J20 H26 DDRB_CKE1 DDRB_SDQ22 B24 B22 DDRA_SDQ22
10 DDRA_CKE1 MA_CKE1 MB_CKE1 DDRB_CKE1 11 MB_DATA22 MA_DATA22
DDRB_SDQ23 C24 C23 DDRA_SDQ23
DDRB_SDQ24 MB_DATA23 MA_DATA23 DDRA_SDQ24
N19 MA_CLK_H0 MB_CLK_H0 P22 E23 MB_DATA24 MA_DATA24 F20
N20 R22 DDRB_SDQ25 E24 F22 DDRA_SDQ25
DDRA_CLK0 MA_CLK_L0 MB_CLK_L0 DDRB_CLK0 DDRB_SDQ26 MB_DATA25 MA_DATA25 DDRA_SDQ26
10 DDRA_CLK0 E16 MA_CLK_H1 MB_CLK_H1 A17 DDRB_CLK0 11 G25 MB_DATA26 MA_DATA26 H24
DDRA_CLK0# F16 A18 DDRB_CLK0# DDRB_SDQ27 G26 J19 DDRA_SDQ27
10 DDRA_CLK0# MA_CLK_L1 MB_CLK_L1 DDRB_CLK0# 11 MB_DATA27 MA_DATA27
DDRA_CLK1 Y16 AF18 DDRB_CLK1 DDRB_SDQ28 C26 E21 DDRA_SDQ28
10 DDRA_CLK1 MA_CLK_H2 MB_CLK_H2 DDRB_CLK1 11 MB_DATA28 MA_DATA28
DDRA_CLK1# AA16 AF17 DDRB_CLK1# DDRB_SDQ29 D26 E22 DDRA_SDQ29
10 DDRA_CLK1# MA_CLK_L2 MB_CLK_L2 DDRB_CLK1# 11 MB_DATA29 MA_DATA29
P19 R26 DDRB_SDQ30 G23 H20 DDRA_SDQ30
MA_CLK_H3 MB_CLK_H3 DDRB SDQ31 MB_DATA30 MA_DATA30 DDRA SDQ31
P20 MA_CLK_L3 MB_CLK_L3 R25 G24 MB_DATA31 MA_DATA31 H22
DDRB SDQ32 AA24 Y24 DDRA SDQ32
10 DDRA_SMA[15..0] DDRB_SMA[15..0] 11 MB_DATA32 MA_DATA32
DDRA SMA0 N21 P24 DDRB SMA0 DDRB SDQ33 AA23 AB24 DDRA SDQ33
DDRA SMA1 MA_ADD0 MB_ADD0 DDRB SMA1 DDRB SDQ34 MB_DATA33 MA_DATA33 DDRA SDQ34
M20 MA_ADD1 MB_ADD1 N24 AD24 MB_DATA34 MA_DATA34 AB22
DDRA SMA2 N22 P26 DDRB SMA2 DDRB SDQ35 AE24 AA21 DDRA SDQ35
DDRA SMA3 MA_ADD2 MB_ADD2 DDRB SMA3 DDRB SDQ36 MB_DATA35 MA_DATA35 DDRA SDQ36
M19 MA_ADD3 MB_ADD3 N23 AA26 MB_DATA36 MA_DATA36 W22
3 DDRA SMA4 M22 N26 DDRB SMA4 DDRB SDQ37 AA25 W21 DDRA SDQ37 3
DDRA SMA5 MA_ADD4 MB_ADD4 DDRB SMA5 DDRB SDQ38 MB_DATA37 MA_DATA37 DDRA SDQ38
L20 MA_ADD5 MB_ADD5 L23 AD26 MB_DATA38 MA_DATA38 Y22
DDRA SMA6 M24 N25 DDRB SMA6 DDRB SDQ39 AE25 AA22 DDRA SDQ39
DDRA SMA7 MA_ADD6 MB_ADD6 DDRB SMA7 DDRB SDQ40 MB_DATA39 MA_DATA39 DDRA SDQ40
L21 MA_ADD7 MB_ADD7 L24 AC22 MB_DATA40 MA_DATA40 Y20
DDRA SMA8 L19 M26 DDRB SMA8 DDRB SDQ41 AD22 AA20 DDRA SDQ41
DDRA_SMA9 MA_ADD8 MB_ADD8 DDRB_SMA9 DDRB_SDQ42 MB_DATA41 MA_DATA41 DDRA_SDQ42
K22 MA_ADD9 MB_ADD9 K26 AE20 MB_DATA42 MA_DATA42 AA18
DDRA_SMA10 R21 T26 DDRB_SMA10 DDRB_SDQ43 AF20 AB18 DDRA_SDQ43
DDRA_SMA11 MA_ADD10 MB_ADD10 DDRB_SMA11 DDRB_SDQ44 MB_DATA43 MA_DATA43 DDRA_SDQ44
L22 MA_ADD11 MB_ADD11 L26 AF24 MB_DATA44 MA_DATA44 AB21
DDRA_SMA12 K20 L25 DDRB_SMA12 DDRB_SDQ45 AF23 AD21 DDRA_SDQ45
DDRA_SMA13 MA_ADD12 MB_ADD12 DDRB_SMA13 DDRB_SDQ46 MB_DATA45 MA_DATA45 DDRA_SDQ46
V24 MA_ADD13 MB_ADD13 W24 AC20 MB_DATA46 MA_DATA46 AD19
DDRA_SMA14 K24 J23 DDRB_SMA14 DDRB_SDQ47 AD20 Y18 DDRA_SDQ47
DDRA_SMA15 MA_ADD14 MB_ADD14 DDRB_SMA15 DDRB_SDQ48 MB_DATA47 MA_DATA47 DDRA_SDQ48
K19 MA_ADD15 MB_ADD15 J24 AD18 MB_DATA48 MA_DATA48 AD17
DDRB_SDQ49 AE18 W16 DDRA_SDQ49
DDRA_SBS0# DDRB_SBS0# DDRB_SDQ50 MB_DATA49 MA_DATA49 DDRA_SDQ50
10 DDRA_SBS0# R20 MA_BANK0 MB_BANK0 R24 DDRB_SBS0# 11 AC14 MB_DATA50 MA_DATA50 W14
DDRA_SBS1# R23 U26 DDRB_SBS1# DDRB_SDQ51 AD14 Y14 DDRA_SDQ51
10 DDRA_SBS1# MA_BANK1 MB_BANK1 DDRB_SBS1# 11 MB_DATA51 MA_DATA51
DDRA_SBS2# J21 J26 DDRB_SBS2# DDRB_SDQ52 AF19 Y17 DDRA_SDQ52
10 DDRA_SBS2# MA_BANK2 MB_BANK2 DDRB_SBS2# 11 MB_DATA52 MA_DATA52
DDRB_SDQ53 AC18 AB17 DDRA_SDQ53
DDRA_SRAS# DDRB_SRAS# DDRB_SDQ54 MB_DATA53 MA_DATA53 DDRA_SDQ54
10 DDRA_SRAS# R19 MA_RAS_L MB_RAS_L U25 DDRB_SRAS# 11 AF16 MB_DATA54 MA_DATA54 AB15
DDRA_SCAS# T22 U24 DDRB_SCAS# DDRB_SDQ55 AF15 AD15 DDRA_SDQ55
10 DDRA_SCAS# MA_CAS_L MB_CAS_L DDRB_SCAS# 11 MB_DATA55 MA_DATA55
DDRA SWE# T24 U23 DDRB SWE# DDRB SDQ56 AF13 AB13 DDRA SDQ56
10 DDRA_SWE# MA_WE_L MB_WE_L DDRB_SWE# 11 MB_DATA56 MA_DATA56
DDRB SDQ57 AC12 AD13 DDRA SDQ57
DDRB SDQ58 MB_DATA57 MA_DATA57 DDRA SDQ58
AB11 MB_DATA58 MA_DATA58 Y12
Athlon 64 S1 DDRB SDQ59 Y11 W11 DDRA SDQ59
Processor DDRB SDQ60 MB_DATA59 MA_DATA59 DDRA SDQ60
AE14 MB_DATA60 MA_DATA60 AB14
Socket DDRB SDQ61 AF14 AA14 DDRA SDQ61
DDRB SDQ62 MB_DATA61 MA_DATA61 DDRA SDQ62
AF11 MB_DATA62 MA_DATA62 AB12
DDRB SDQ63 AD11 AA12 DDRA SDQ63
MB_DATA63 MA_DATA63
PLACE CLOSE TO PROCESSOR 11 DDRB_SDM[7..0] DDRA_SDM[7..0] 10
DDRB SDM0 A12 E12 DDRA SDM0
2 WITHIN 1.5 INCH DDRB SDM1 MB_DM0 MA_DM0 DDRA SDM1 2
B16 MB_DM1 MA_DM1 C15
1.8V DDRB_SDM2 A22 E19 DDRA_SDM2
DDRA_CLK0 DDRB_SDM3 MB_DM2 MA_DM2 DDRA_SDM3
E25 MB_DM3 MA_DM3 F24
1 DDRB_SDM4 AB26 AC24 DDRA_SDM4
MB_DM4 MA_DM4
2

DDRB_SDM5 AE22 Y19 DDRA_SDM5

R4 C104 DDRB_SDM6 MB_DM5 MA_DM5 DDRA_SDM6
AC16 MB_DM6 MA_DM6 AB16
1K_0402_1% 1.5P_0402_50V8C DDRB_SDM7 AD12 Y13 DDRA_SDM7
DDRA_CLK0# 2 MB_DM7 MA_DM7
DDRB_SDQS0 C12 G13 DDRA_SDQS0
11 DDRB_SDQS0 DDRA_SDQS0 10
1

MCH_REF DDRA_CLK1 DDRB_SDQS0# MB_DQS_H0 MA_DQS_H0 DDRA_SDQS0#

11 DDRB_SDQS0# B12 MB_DQS_L0 MA_DQS_L0 H13 DDRA_SDQS0# 10
1000P_0402_25V8J

DDRB_SDQS1 DDRA_SDQS1
0.1U_0402_16V4Z

1 11 DDRB_SDQS1 D16 MB_DQS_H1 MA_DQS_H1 G16 DDRA_SDQS1 10

2

1 1 DDRB_SDQS1# C16 G15 DDRA_SDQS1#

11 DDRB_SDQS1# MB_DQS_L1 MA_DQS_L1 DDRA_SDQS1# 10
C16

C100

R5 C102 DDRB_SDQS2 A24 C22 DDRA_SDQS2

1.5P_0402_50V8C 11 DDRB_SDQS2 MB_DQS_H2 MA_DQS_H2 DDRA_SDQS2 10
1K_0402_1% DDRB_SDQS2# A23 C21 DDRA_SDQS2#
2 11 DDRB_SDQS2# MB_DQS_L2 MA_DQS_L2 DDRA_SDQS2# 10
DDRA_CLK1# DDRB_SDQS3 F26 G22 DDRA_SDQS3
2 2 11 DDRB_SDQS3 MB_DQS_H3 MA_DQS_H3 DDRA_SDQS3 10
DDRB SDQS3# E26 G21 DDRA SDQS3#
11 DDRB_SDQS3# DDRA_SDQS3# 10
1

DDRB SDQS4 MB_DQS_L3 MA_DQS_L3 DDRA SDQS4

11 DDRB_SDQS4 AC25 MB_DQS_H4 MA_DQS_H4 AD23 DDRA_SDQS4 10
DDRB CLK0 DDRB SDQS4# AC26 AC23 DDRA SDQS4#
11 DDRB_SDQS4# MB_DQS_L4 MA_DQS_L4 DDRA_SDQS4# 10
1 DDRB SDQS5 AF21 AB19 DDRA SDQS5
11 DDRB_SDQS5 MB_DQS_H5 MA_DQS_H5 DDRA_SDQS5 10
DDRB SDQS5# AF22 AB20 DDRA SDQS5#
11 DDRB_SDQS5# MB_DQS_L5 MA_DQS_L5 DDRA_SDQS5# 10
C105 DDRB SDQS6 AE16 Y15 DDRA SDQS6
1.5P_0402_50V8C 11 DDRB_SDQS6 MB_DQS_H6 MA_DQS_H6 DDRA_SDQS6 10
DDRB SDQS6# AD16 W15 DDRA SDQS6#
2 11 DDRB_SDQS6# MB_DQS_L6 MA_DQS_L6 DDRA_SDQS6# 10
DDRB CLK0# DDRB SDQS7 AF12 W12 DDRA SDQS7
11 DDRB_SDQS7 MB_DQS_H7 MA_DQS_H7 DDRA_SDQS7 10
DDRB SDQS7# AE12 W13 DDRA SDQS7#
11 DDRB_SDQS7# MB_DQS_L7 MA_DQS_L7 DDRA_SDQS7# 10
DDRB CLK1
1
6090022100G_B Athlon 64 S1
C17 Processor Socket
1.5P_0402_50V8C
1
DDRB_CLK1# 2
Processor DDR2 Memory Interface 1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 7 of 55
A B C D E
 5 4 3 2 1

1.8V 1 2
R18 10K_0402_5%
2.5VDDA 1 2
L4 R8 300_0402_5%
2.5VS 1 2 3300P_0402_50V7K

2
B
FCM2012CF-800T06_2P 1 R2 2 MAINPWON 45,47,52
1 1 1 1 Q3 @ 0_0402_5%

E
C113 CPU_THERMTRIP#_R 3 1 1 R17 2 H_THERMTRIP# 24

C
+ C116 C118 C22 0_0402_5%
4.7U_0805_10V4Z 0.22U_0603_16V4Z MMBT3904_NL_SOT23-3
150U_D2_6.3VM 2 2 2
2
change to polymer
D JCPU1D D
1.8V 1 2
F8 M11 R20 300_0402_5%
VDDA1 KEY1
F9 VDDA2 KEY2 W18

16 CLK_CPU_BCLK 1 2 3900P 0402 50V7K CPU CLKIN SC P A9 CLKIN_H SVC A6 CPU SVC
CPU_SVC 53
C109 CPU CLKIN SC N A8 A4 CPU SVD H PROCHOT# 1 R52 2
CLKIN_L SVD CPU_SVD 53 H_PROCHOT_R# 23

1
LDT RST# B7 0_0402_5%
R22 H_PWRGD RESET_L
A7 PWROK
169_0402_1% LDT_STOP# F10 AF6 CPU_THERMTRIP#_R
CPU_LDT_REQ# LDTSTOP_L THERMTRIP_L H_PROCHOT#
13 CPU_LDT_REQ# C6 AC7

2
LDTREQ_L PROCHOT_L @
16 CLK_CPU_BCLK# 1 2 MEMHOT_L AA8 2 1 1.8V
C23 3900P_0402_50V7K CPU_SIC AF4 R218 300_0402_5% CPU_CORE_NB
CPU_SID SIC
AF5 SID
1.8VS AE6 W7 THERMDC_CPU @ R201 10_0402_5%
ALERT_L THERMDC THERMDA_CPU CPU_VDDNB_FB_H 1
THERMDA W8 2
R16 1 2 44.2_0402_1% CPU_HTREF0 R6 HT_REF0
2

R216 2.2K_0402_5% 1.2V_HT R61 1 2 44.2_0402_1% CPU_HTREF1 P6 CPU_VDDNB_FB_L 1 2

R334 CPU_SID HT_REF1 @ R202 10_0402_5%
1.8V 2 1
300_0402_5% 53 CPU_VDD0_FB_H CPU_VDD0_FB_H F6 W9
VDD0_FB_H VDDIO_FB_H PAD T5
R217 2.2K_0402_5% 53 CPU_VDD0_FB_L CPU_VDD0_FB_L E6 Y9
VDD0_FB_L VDDIO_FB_L PAD T6
2 1 CPU_SIC
1

LDT RST# CPU VDD1 FB H Y6 H6 CPU VDDNB FB H 1.2V_HT

23 LDT_RST# 53 CPU_VDD1_FB_H VDD1_FB_H VDDNB_FB_H CPU_VDDNB_FB_H 53
53 CPU_VDD1_FB_L CPU VDD1 FB L AB6 G6 CPU VDDNB FB L
CPU_CORE_0 VDD1_FB_L VDDNB_FB_L CPU_VDDNB_FB_L 53
1 R151 0_0402_5%
C721 @ R204 10_0402_5% CPU DBRDY G10 CPU TEST10 1 @ 2
0.01U_0402_25V4Z DBRDY
1 2CPU VDD0 FB H CPU TMS AA9 TMS DBREQ_L E10 CPU DBREQ#
@ 1 2CPU VDD0 FB L CPU TCK AC9
C 2 @ R205 10_0402_5% CPU TRST# TCK CPU TDO 1.8V C
AD9 TRST_L TDO AE9
CPU TDI AF9 TDI R152 1K_0402_5%
T3 PAD CPU TEST23 AD7 J7 CPU TEST28 H PLLCHRZ P CPU SVC 1 2
CPU_CORE_1 TEST23 TEST28_H PAD T9
R206 H8 CPU TEST28 L PLLCHRZ N R153 1K_0402_5%
1.8VS TEST28_L PAD T10
10K_0402_5% T8 PAD CPU_TEST18 H10 CPU_SVD 1 2
@ TEST18
1 2CPU_VDD1_FB_H T12 PAD CPU_TEST19 G9 TEST19 TEST17 D7 CPU_TEST17
PAD T20
1 @ 2CPU_VDD1_FB_L E7 CPU_TEST16
TEST16 PAD T19
2

TEST25_H E9 F7 CPU_TEST15
TEST25_H TEST15 PAD T11
R346 10K_0402_5% TEST25_L E8 C7 CPU_TEST14
TEST25_L TEST14 PAD T21
300_0402_5% R209 CPU_TEST21 2 1
T4 PAD CPU_TEST21 AB8 C3 CPU_TEST7 R154 300_0402_5%
TEST21 TEST7 PAD T13
T24 PAD CPU_TEST20 AF7 K8 CPU_TEST10 CPU_TEST24 2 1
PAD T14
1

H_PWRGD T26 PAD CPU_TEST24 TEST20 TEST10 R155 300_0402_5%

23 H_PWRGD R212, R211 pop for Tigris AE7 TEST24
T25 PAD CPU_TEST22 AE8 C4 CPU_TEST8 CPU_TEST20 2 1
TEST22 TEST8 PAD T28
1 T7 PAD CPU_TEST12 AC8 R160 300_0402_5%
C720 1.8V 1.8V T27 PAD CPU_TEST27 TEST12 CPU_TEST23
AF8 TEST27 2 1
0.01U_0402_25V4Z C9 CPU_TEST29_H_FBCLKOUT_P R162 300_0402_5%
TEST29_H PAD T18
1 R214 2 0_0402_5% C2 TEST9 TEST29_L C8 CPU_TEST29_L_FBCLKOUT_N
PAD T16
CPU_TEST18 1 2
1

2 CPU TEST6 R220 @ 300_0402_5%

AA6 TEST6
R210 R212 T22 PAD CPU TEST19 1 2
@ 510_0402_5% 510_0402_5% A3 H18 R221 @ 300_0402_5%
RSVD1 RSVD10 CPU TEST22
A5 RSVD2 RSVD9 H19 1 2
B3 AA7 R222 @ 300_0402_5%
2

1.8VS TEST25 H TEST25 L RSVD3 RSVD8

B5 RSVD4 RSVD7 D5
C1 RSVD5 RSVD6 C5
2

R342 R211 R213 6090022100G_B

B 510_0402_5% @ 510_0402_5% B
300_0402_5%
1

LDT_STOP# 1.8V
13,23 LDT_STOP#

1
C719

220_0402_5% R33

220_0402_5% R38

220_0402_5% R34

220_0402_5% R35

300_0402_5% R36
0.01U_0402_25V4Z
@

1
2

JP3
1 2
2

2
3 4
3VS CPU DBREQ# @ @ @ @ 5 6
CPU DBRDY 7 8
CPU TCK 9 10
FDV301N, the Vgs is 11 12
CPU TMS
min = 0.65V 13 14
0.1U_0402_16V4Z

1 CPU TDI
Typ = 0.85V CPU TRST# 15 16
C119 17 18
Max = 1.5V CPU TDO
19 20 R25 @ 0_0402_5%
2 21 22 HDT RST# LDT RST#
23 24 1 2
U3
EC SMB CK2 26
1 VDD SCLK 8 EC_SMB_CK2 22,34 NOTE HDT TERMINATION IS REQUIRED
THERMDA_CPU 2 EC_SMB_DA2
FOR REV. Ax SILICON ONLY. @ SAMTEC_ASP-68200-07
D+ SDATA 7 EC_SMB_DA2 22,34
C120
A A
1 2 THERMDC_CPU 3 6
3300P_0402_50V7K D- ALERT#
4 THERM# GND 5

C120 3300p for tigris

2200p change to ADM1032ARMZ_MSOP8
1000p for ADT7421 Address:100_1101 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 8 of 55
5 4 3 2 1
 5 3 2 1

JCPU1F
VDD0 = 18A VDD1 =18A
VDD(+CPU_CORE) decoupling. +CPU_CORE_0 JCPU1E +CPU_CORE_1
AA4
AA11
VSS1
VSS2
VSS66
VSS67
J6
J8
AA13 VSS3 VSS68 J10
G4 VDD0_1 VDD1_1 P8 AA15 VSS4 VSS69 J12
H2 VDD0_2 VDD1_2 P10 AA17 VSS5 VSS70 J14
+CPU_CORE_0 +CPU_CORE_1 J9 R4 AA19 J16
VDD0_3 VDD1_3 VSS6 VSS71
J11 VDD0_4 VDD1_4 R7 AB2 VSS7 VSS72 J18
J13 VDD0_5 VDD1_5 R9 AB7 VSS8 VSS73 K2
J15 VDD0_6 VDD1_6 R11 AB9 VSS9 VSS74 K7
1 1 K6 VDD0_7 VDD1_7 T2 AB23 VSS10 VSS75 K9
K10 VDD0_8 VDD1_8 T6 AB25 VSS11 VSS76 K11
+ C26 + C32 + C45 + C27 + C28 K12 T8 AC11 K13
D 330U_X_2VM_R6M 330U_X_2VM_R6M @ 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M VDD0_9 VDD1_9 VSS12 VSS77 D
K14 VDD0_10 VDD1_10 T10 AC13 VSS13 VSS78 K15
L4 VDD0_11 VDD1_11 T12 AC15 VSS14 VSS79 K17
2 2 2 2 2
L7 VDD0_12 VDD1_12 T14 AC17 VSS15 VSS80 L6
L9 VDD0_13 VDD1_13 U7 AC19 VSS16 VSS81 L8
L11 VDD0_14 VDD1_14 U9 AC21 VSS17 VSS82 L10
L13 U11 AD6 L12
Near CPU Socket L15
VDD0_15
VDD0_16
VDD1_15
VDD1_16 U13 AD8
VSS18
VSS19
VSS83
VSS84 L14
M2 VDD0_17 VDD1_17 U15 AD25 VSS20 VSS85 L16
VDDNB=4A M6 VDD0_18 VDD1_18 V6 AE11 VSS21 VSS86 L18
M8 VDD0_19 VDD1_19 V8 AE13 VSS22 VSS87 M7
+CPU_CORE_0 (For Tigris) M10 V10 AE15 M9
+CPU_CORE_1 VDD0_20 VDD1_20 VSS23 VSS88
VDDNB=3A N7 VDD0_21 VDD1_21 V12 AE17 VSS24 VSS89 AC6
N9 VDD0_22 VDD1_22 V14 AE19 VSS25 VSS90 M17
+CPU_CORE_NB N11 W4 AE21 N4
VDD0_23 VDD1_23 VSS26 VSS91
1 1 1 VDD1_24 Y2 AE23 VSS27 VSS92 N8
C33 C36 C34 C35 1 K16 AC4 B4 N10
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M C178 C41 C190 C39 VDDNB_1 VDD1_25 +1.8V VSS28 VSS93
M16 VDDNB_2 VDD1_26 AD2 B6 VSS29 VSS94 N16
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M VDDIO=3A P16 B8 N18
2 2 2 2 VDDNB_3 VSS30 VSS95
T16 VDDNB_4 VDDIO27 Y25 B9 VSS31 VSS96 P2
2 2 2 2 +1.8V V16 VDDNB_5 VDDIO26 V25 B11 VSS32 VSS97 P7
VDDIO25 V23 B13 VSS33 VSS98 P9
+CPU_CORE_0 H25 V21 B15 P11
+CPU_CORE_1 VDDIO1 VDDIO24 VSS34 VSS99
J17 VDDIO2 VDDIO23 V18 B17 VSS35 VSS100 P17
K18 VDDIO3 VDDIO22 U17 B19 VSS36 VSS101 R8
K21 VDDIO4 VDDIO21 T25 B21 VSS37 VSS102 R10
1 1 1 K23 VDDIO5 VDDIO20 T23 B23 VSS38 VSS103 R16
C128 C129 C151 C122 C47 C5 K25 T21 B25 R18
0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J VDDIO6 VDDIO19 VSS39 VSS104
L17 VDDIO7 VDDIO18 T18 D6 VSS40 VSS105 T7
M18 VDDIO8 VDDIO17 R17 D8 VSS41 VSS106 T9
2 2 2 2 2 2
M21 VDDIO9 VDDIO16 P25 D9 VSS42 VSS107 T11
M23 P23 D11 T13
Under CPU Socket M25
VDDIO10
VDDIO11
VDDIO15
VDDIO14 P21 D13
VSS43
VSS44
VSS108
VSS109 T15
C C
N17 VDDIO12 VDDIO13 P18 D15 VSS45 VSS110 T17
D17 VSS46 VSS111 U4
D19 VSS47 VSS112 U6
6090022100G_B D21 U8
Athlon 64 S1 VSS48 VSS113
D23 VSS49 VSS114 U10
Processor Socket D25 U12
VSS50 VSS115
E4 VSS51 VSS116 U14
F2 U16
VDDIO decoupling. F11
F13
VSS52
VSS53
VSS117
VSS118 U18
V2
+1.8V
+CPU_CORE_NB decoupling. F15
F17
VSS54
VSS55
VSS56
VSS119
VSS120
VSS121
V7
V9
F19 VSS57 VSS122 V11
F21 VSS58 VSS123 V13
1 1 1 +CPU_CORE_NB F23 V15
C170 C181 C124 C147 C6 C7 VSS59 VSS124
F25 VSS60 VSS125 V17
22U_0805_6.3V6M 22U_0805_6.3V6M H7 W6
0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J VSS61 VSS126
1 H9 VSS62 VSS127 Y21
2 2 2 2 2 2 C8 C9 C11 H21 VSS63 VSS128 Y23
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M H23 N6
VSS64 VSS129
J4 VSS65
2 2 2
6090022100G_B
Under CPU Socket Athlon 64 S1
Processor Socket

Between CPU Socket and DIMM +0.9V

+1.8V Near Power Supply
B B

C157
1
C182
1
C68 C188
VTT decoupling. +
C66
C14
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 22U_0805_6.3V6M
220U_D2_4VM_R15
2 2 2 2 2 2
change to polymer

180PF Qt'y follow the distance between

+1.8V +1.8V CPU socket and DIMM0. <2.5inch> +0.9V

1 1 1
C175 C159 C189 C136 C156 C158 1 1 1 1
0.01U_0402_25V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J C155 C146 C184 C173 C72 C145 C180 C121
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2
2 2 2 2 2 2 2 2

+1.8V
Near CPU Socket Right side.
+0.9V
1
1 1
+ C162 + C12
C76 C167 C187 C132 220U_Y_4VM 220U_Y_4VM 1 1 1 1
4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z C73 C70 C127 C185 C164 C163 C152 C179
2 2 2 2 2 2 @
NBO CAP 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2 2 2
A A

Near CPU Socket Left side.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401836 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date Thursday, March 18, 2010 Sheet 9 of 55
5 3 2 1
 A B C D E

+1.8V +1.8V

JDIMM1
+V_DDR_MCH_REF 1 VREF VSS 2
3 4 DDRA SDQ4 DDRA_SDQ[0..63]
DDRA_SDQ0 VSS DQ4 DDRA_SDQ5 DDRA_SDQ[0..63] 7
5 6
DDRA SDQ1 7
DQ0
DQ1
DQ5
VSS 8 RESERVE DDRA SDM[0..7]
DDRA_SDM[0..7] 7
9 10 DDRA SDM0
7 DDRA_SDQS0#
DDRA SDQS0#
DDRA SDQS0
11
VSS
DQS0#
DM0
VSS 12
DDRA SDQ6
+V_DDR_MCH_REF BUFFER CIRCUIT DDRA SMA[0..15]
DDRA_SMA[0..15] 7
7 DDRA_SDQS0 13 DQS0 DQ6 14
15 16 DDRA_SDQ7
DDRA SDQ2 VSS DQ7
17 DQ2 VSS 18
DDRA_SDQ3 19 20 DDRA_SDQ12
1 DQ3 DQ12 DDRA SDQ13 1
21 VSS DQ13 22
DDRA_SDQ8 23 24
DDRA SDQ9 DQ8 VSS DDRA SDM1 +0.9V +1.8V
25 DQ9 DM1 26
27 28 +1.8V RP1
DDRA SDQS1# VSS VSS DDRA SMA4
7 DDRA_SDQS1# 29 DQS1# CK0 30 DDRA_CLK0 7 1 8 1 2
DDRA_SDQS1 31 32 DDRA_SMA14 2 7 C81 0.1U_0402_16V4Z
7 DDRA_SDQS1 DQS1 CK0# DDRA_CLK0# 7

2
33 34 DDRA SMA15 3 6 1 2
DDRA_SDQ10 VSS VSS DDRA_SDQ14 R398 DDRA_CKE1 C139 0.1U_0402_16V4Z
35 DQ10 DQ14 36 4 5
DDRA SDQ11 37 38 DDRA SDQ15 1K_0402_1%
DQ11 DQ15 47_0804_8P4R_5%
39 VSS VSS 40

1
+V DDR MCH REF +V_DDR_MCH_REF DDRA CKE0 47 0402 5% 1 R407 2 1 2

0.1U_0402_16V4Z
41 42 DDRA_SBS2# 47_0402_5% 1 R408 2 C192 0.1U_0402_16V4Z
VSS VSS

1000P_0402_25V8J
DDRA SDQ16 43 44 DDRA SDQ20 1 DDRA SMA6 47 0402 5% 1 R411 2 1 2
DQ16 DQ20

2
C503
DDRA_SDQ17 45 46 DDRA_SDQ21 DDRA_SMA2 47_0402_5% 1 R412 2 C88 0.1U_0402_16V4Z
DQ17 DQ21

C507
47 48 R397
DDRA_SDQS2# VSS VSS 1K_0402_1%
7 DDRA_SDQS2# 49 DQS2# NC 50
DDRA SDQS2 DDRA SDM2 2 2 RP3
7 DDRA_SDQS2 51 DQS2 DM2 52
53 54 DDRA_SMA0 1 8 1 2

1
DDRA SDQ18 VSS VSS DDRA SDQ22 DDRA SBS1# C117 0.1U_0402_16V4Z
55 DQ18 DQ22 56 2 7
DDRA_SDQ19 57 58 DDRA_SDQ23 DDRA_SMA11 3 6 1 2
DQ19 DQ23 DDRA SMA7 C144 0.1U_0402_16V4Z
59 VSS VSS 60 4 5
DDRA SDQ24 61 62 DDRA SDQ28
DDRA_SDQ25 DQ24 DQ28 DDRA_SDQ29 47_0804_8P4R_5%
63 DQ25 DQ29 64
65 66 RP4
DDRA_SDM3 VSS VSS DDRA_SDQS3# DDRA_SMA5
67 DM3 DQS3# 68 DDRA_SDQS3# 7 8 1 1 2
69 70 DDRA SDQS3 DDRA SMA8 7 2 C114 0.1U_0402_16V4Z
NC DQS3 DDRA_SDQS3 7 DDRA_SMA9
71 VSS VSS 72 6 3 1 2
DDRA SDQ26 73 74 DDRA SDQ30 DDRA SMA12 5 4 C95 0.1U_0402_16V4Z
DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ31
75 DQ27 DQ31 76
77 78 47_0804_8P4R_5%
DDRA_CKE0 VSS VSS DDRA_CKE1 RP5
7 DDRA_CKE0 79 CKE0 NC/CKE1 80 DDRA_CKE1 7
2 DDRA SBS0# 2
81 VDD VDD 82 8 1 1 2
83 84 DDRA_SMA15 DDRA_SMA10 7 2 C193 0.1U_0402_16V4Z
DDRA SBS2# NC NC/A15 DDRA SMA14 DDRA SMA1
7 DDRA_SBS2# 85 BA2 NC/A14 86 6 3 1 2
87 88 DDRA SMA3 5 4 C125 0.1U_0402_16V4Z
DDRA SMA12 VDD VDD DDRA SMA11
89 A12 A11 90
DDRA SMA9 91 92 DDRA SMA7 47_0804_8P4R_5%
DDRA_SMA8 A9 A7 DDRA_SMA6 RP6
93 A8 A6 94
95 96 DDRA SCS1# 8 1 1 2
DDRA_SMA5 VDD VDD DDRA_SMA4 DDRA_ODT1 C103 0.1U_0402_16V4Z
97 A5 A4 98 7 2
DDRA SMA3 99 100 DDRA SMA2 DDRA SWE# 6 3 1 2
DDRA_SMA1 A3 A2 DDRA_SMA0 DDRA_SCAS# C99 0.1U_0402_16V4Z
101 A1 A0 102 5 4
103 VDD VDD 104
DDRA_SMA10 105 106 DDRA_SBS1# 47_0804_8P4R_5%
A10/AP BA1 DDRA_SBS1# 7
DDRA SBS0# 107 108 DDRA SRAS# RP7
7 DDRA_SBS0# BA0 RAS# DDRA_SRAS# 7
DDRA_SWE# 109 110 DDRA_SCS0# DDRA_ODT0 1 8 1 2
7 DDRA_SWE# WE# S0# DDRA_SCS0# 7
111 112 DDRA SMA13 2 7 C107 0.1U_0402_16V4Z
DDRA SCAS# VDD VDD DDRA ODT0 DDRA SCS0#
7 DDRA_SCAS# 113 CAS# ODT0 114 DDRA_ODT0 7 3 6 1 2
DDRA SCS1# 115 116 DDRA SMA13 DDRA SRAS# 4 5 C98 0.1U_0402_16V4Z
7 DDRA_SCS1# NC/S1# NC/A13
117 VDD VDD 118
DDRA_ODT1 119 120 47_0804_8P4R_5%
7 DDRA_ODT1 NC/ODT1 NC
121 VSS VSS 122
DDRA_SDQ32 123 124 DDRA_SDQ36
DDRA SDQ33 DQ32 DQ36 DDRA SDQ37
125 DQ33 DQ37 126
127 VSS VSS 128
DDRA SDQS4# 129 130 DDRA SDM4
7 DDRA_SDQS4# DDRA_SDQS4 DQS4# DM4
7 DDRA_SDQS4 131 DQS4 VSS 132
133 134 DDRA SDQ38
DDRA_SDQ34 VSS DQ38 DDRA_SDQ39
135 DQ34 DQ39 136
DDRA SDQ35 137 138
DQ35 VSS DDRA_SDQ44 +0.9V
139 VSS DQ44 140
DDRA SDQ40 141 142 DDRA SDQ45 +1.8V
DDRA SDQ41 DQ40 DQ45
143 DQ41 VSS 144
3 DDRA_SDQS5# @ 0.1U_0402_16V4Z @ 0.1U_0402_16V4Z 3
145 VSS DQS5# 146 DDRA_SDQS5# 7
DDRA SDM5 147 148 DDRA SDQS5 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DM5 DQS5 DDRA_SDQS5 7
149 VSS VSS 150 1 1 1
DDRA SDQ42 151 152 DDRA SDQ46
DDRA_SDQ43 DQ42 DQ46 DDRA_SDQ47 C60 C63 C64 C65 C67 C69 C71 C75
153 DQ43 DQ47 154
155 VSS VSS 156
DDRA_SDQ48 DDRA_SDQ52 2 2 2 2 2 2 2 2
157 DQ48 DQ52 158
DDRA SDQ49 159 160 DDRA SDQ53 0.1U_0402_16V4Z 0.1U_0402_16V4Z @ 0.1U_0402_16V4Z @ 0.1U_0402_16V4Z
DQ49 DQ53
161 VSS VSS 162
163 NC,TEST CK1 164 DDRA_CLK1 7
165 VSS CK1# 166 DDRA_CLK1# 7
DDRA SDQS6# 167 168
7 DDRA_SDQS6# DDRA SDQS6 DQS6# VSS DDRA SDM6
7 DDRA_SDQS6 169 DQS6 DM6 170
171 VSS VSS 172
DDRA SDQ50 173 174 DDRA SDQ54
DDRA_SDQ51 DQ50 DQ54 DDRA_SDQ55
175 DQ51 DQ55 176
177 VSS VSS 178
DDRA_SDQ56 179 180 DDRA_SDQ60
DDRA SDQ57 DQ56 DQ60 DDRA SDQ61
181 DQ57 DQ61 182
183 VSS VSS 184
DDRA SDM7 185 186 DDRA SDQS7#
DM7 DQS7# DDRA_SDQS7 DDRA_SDQS7# 7
187 VSS DQS7 188 DDRA_SDQS7 7
DDRA SDQ58 189 190
DDRA_SDQ59 DQ58 VSS DDRA_SDQ62
191 DQ59 DQ62 192
193 194 DDRA SDQ63
SB CK SDAT VSS DQ63
11,16,24,37 SB_CK_SDAT 195 SDA VSS 196
SB CK SCLK 197 198 R12 1 2 10K 0402 5%
11,16,24,37 SB_CK_SCLK SCL SAO
+3VS 199 200 R10 1 2 10K 0402 5%
VDDSPD SA1
203 GND GND 204

FOX_AS0A426-M2RN-7F
+3VS CONN@

1
C448 C310 DIMM1 REV H:5.2mm (BOT)
4.7U_0603_6.3V6K 0.1U_0402_16V4Z
2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401836 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date Thursday, March 18, 2010 Sheet 10 of 55
A B C D E
 A B C D E

+1.8V

+1.8V
DDRB_SDQ[0..63]
JDIMM2 DDRB_SDQ[0..63] 7
1 2 DDRB_SDM[0..7]
+V_DDR_MCH_REF VREF VSS DDRB_SDM[0..7] 7
3 4 DDRB SDQ4
DDRB SDQ0 VSS DQ4 DDRB SDQ5 DDRB_SMA[0..15]
5 DQ0 DQ5 6 DDRB_SMA[0..15] 7
DDRB SDQ1 7 8
DQ1 VSS DDRB SDM0
9 VSS DM0 10
DDRB_SDQS0# 11 12
7 DDRB_SDQS0# DDRB SDQS0 DQS0# VSS DDRB SDQ6
7 DDRB_SDQS0 13 DQS0 DQ6 14
15 16 DDRB_SDQ7
1 DDRB SDQ2 VSS DQ7 1
17 DQ2 VSS 18
DDRB_SDQ3 19 20 DDRB_SDQ12
DQ3 DQ12 DDRB SDQ13 +0.9V +1.8V
21 VSS DQ13 22
DDRB_SDQ8 23 24 RP9
DDRB SDQ9 DQ8 VSS DDRB SDM1 +1.8V DDRB SMA4
25 DQ9 DM1 26 1 8 2 1
27 28 DDRB_SMA0 2 7 C196 0.1U_0402_16V4Z
DDRB SDQS1# VSS VSS DDRB SMA2
7 DDRB_SDQS1# 29 DQS1# CK0 30 DDRB_CLK0 7 3 6 1 2
DDRB_SDQS1 31 32 DDRB_SRAS# 4 5 C209 0.1U_0402_16V4Z
7 DDRB_SDQS1 DQS1 CK0# DDRB_CLK0# 7 330U_X_2VM_R6M +
33 VSS VSS 34
DDRB SDQ10 35 36 DDRB SDQ14 C212 47_0804_8P4R_5%
DDRB_SDQ11 DQ10 DQ14 DDRB_SDQ15 @
37 DQ11 DQ15 38
2 RP10
39 VSS VSS 40
DDRB_SMA14 1 8 2 1
DDRB SMA7 2 7 C197 0.1U_0402_16V4Z
41 42 DDRB_SMA11 3 6 1 2
DDRB SDQ16 VSS VSS DDRB SDQ20 DDRB SMA6 C211 0.1U_0402_16V4Z
43 DQ16 DQ20 44 4 5
DDRB_SDQ17 45 46 DDRB_SDQ21
DQ17 DQ21 47_0804_8P4R_5%
47 VSS VSS 48
DDRB_SDQS2# 49 50
7 DDRB_SDQS2# DDRB SDQS2 DQS2# NC DDRB SDM2 RP11
7 DDRB_SDQS2 51 DQS2 DM2 52 Place near to D MM2 DDRB_SBS2#
53 VSS VSS 54 8 1 2 1
DDRB SDQ18 55 56 DDRB SDQ22 DDRB CKE0 7 2 C205 0.1U_0402_16V4Z
DDRB SDQ19 DQ18 DQ22 DDRB SDQ23 DDRB SMA15
57 DQ19 DQ23 58 6 3 1 2
59 60 DDRB_CKE1 5 4 C213 0.1U_0402_16V4Z
DDRB SDQ24 VSS VSS DDRB SDQ28 +V DDR MCH REF
61 DQ24 DQ28 62 +V_DDR_MCH_REF

22U_0805_6.3V6M
0.1U_0402_16V4Z
DDRB_SDQ25 63 64 DDRB_SDQ29 47_0804_8P4R_5%
DQ25 DQ29

1000P_0402_25V8J
65 VSS VSS 66 1 1

C202

C198

C25
DDRB_SDM3 67 68 DDRB_SDQS3# RP12
DM3 DQS3# DDRB SDQS3 DDRB_SDQS3# 7 DDRB SMA3
69 NC DQS3 70 DDRB_SDQS3 7 8 1 2 1
71 72 DDRB_SMA8 7 2 C199 0.1U_0402_16V4Z
DDRB SDQ26 VSS VSS DDRB SDQ30 2 2 2 @ DDRB SMA9
73 DQ26 DQ30 74 6 3 1 2
DDRB_SDQ27 75 76 DDRB_SDQ31 DDRB_SMA12 5 4 C200 0.1U_0402_16V4Z
2 DQ27 DQ31 2
77 VSS VSS 78
DDRB_CKE0 79 80 DDRB_CKE1 47_0804_8P4R_5%
7 DDRB_CKE0 CKE0 NC/CKE1 DDRB_CKE1 7
81 VDD VDD 82
83 84 DDRB SMA15 RP13
DDRB SBS2# NC NC/A15 DDRB SMA14 DDRB SBS0#
7 DDRB_SBS2# 85 BA2 NC/A14 86 8 1 2 1
87 88 DDRB SMA10 7 2 C206 0.1U_0402_16V4Z
DDRB_SMA12 VDD VDD DDRB_SMA11 DDRB_SMA1
89 A12 A11 90 AMD recommend 6 3 1 2
DDRB SMA9 91 92 DDRB SMA7 DDRB SMA5 5 4 C201 0.1U_0402_16V4Z
DDRB_SMA8 A9 A7 DDRB_SMA6
93 A8 A6 94
95 96 47_0804_8P4R_5%
DDRB_SMA5 VDD VDD DDRB_SMA4
97 A5 A4 98
DDRB SMA3 99 100 DDRB SMA2 RP14
DDRB_SMA1 A3 A2 DDRB_SMA0 DDRB_SCAS#
101 A1 A0 102 8 1 2 1
103 104 DDRB ODT1 7 2 C210 0.1U_0402_16V4Z
DDRB_SMA10 VDD VDD DDRB_SBS1# DDRB_SCS1#
105 A10/AP BA1 106 DDRB_SBS1# 7 6 3 1 2
DDRB SBS0# 107 108 DDRB SRAS# DDRB SWE# 5 4 C208 0.1U_0402_16V4Z
7 DDRB_SBS0# BA0 RAS# DDRB_SRAS# 7
DDRB SWE# 109 110 DDRB SCS0#
7 DDRB_SWE# WE# S0# DDRB_SCS0# 7
111 112 47_0804_8P4R_5%
DDRB SCAS# VDD VDD DDRB ODT0
7 DDRB_SCAS# 113 CAS# ODT0 114 DDRB_ODT0 7
DDRB_SCS1# 115 116 DDRB_SMA13 RP15
7 DDRB_SCS1# NC/S1# NC/A13
117 118 DDRB SBS1# 1 8 2 1
DDRB_ODT1 VDD VDD DDRB_SCS0# C194 0.1U_0402_16V4Z
7 DDRB_ODT1 119 NC/ODT1 NC 120 2 7
121 122 DDRB ODT0 3 6 1 2
DDRB_SDQ32 VSS VSS DDRB_SDQ36 DDRB_SMA13 C207 0.1U_0402_16V4Z
123 DQ32 DQ36 124 4 5
DDRB SDQ33 125 126 DDRB SDQ37
DQ33 DQ37 47_0804_8P4R_5%
127 VSS VSS 128
DDRB SDQS4# 129 130 DDRB SDM4
7 DDRB_SDQS4# DDRB_SDQS4 DQS4# DM4
7 DDRB_SDQS4 131 DQS4 VSS 132
133 134 DDRB SDQ38
DDRB_SDQ34 VSS DQ38 DDRB_SDQ39
135 DQ34 DQ39 136
DDRB SDQ35 137 138
DQ35 VSS DDRB SDQ44
139 VSS DQ44 140
3 DDRB_SDQ40 DDRB_SDQ45 3
141 DQ40 DQ45 142
DDRB SDQ41 143 144
DQ41 VSS DDRB_SDQS5#
145 VSS DQS5# 146 DDRB_SDQS5# 7
DDRB SDM5 147 148 DDRB SDQS5
DM5 DQS5 DDRB_SDQS5 7
149 VSS VSS 150
DDRB SDQ42 151 152 DDRB SDQ46
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47
153 DQ43 DQ47 154
155 VSS VSS 156
DDRB_SDQ48 157 158 DDRB_SDQ52
DDRB SDQ49 DQ48 DQ52 DDRB SDQ53
159 DQ49 DQ53 160
161 VSS VSS 162
163 NC,TEST CK1 164 DDRB_CLK1 7
165 VSS CK1# 166 DDRB_CLK1# 7
DDRB SDQS6# 167 168
7 DDRB_SDQS6# DDRB SDQS6 DQS6# VSS DDRB SDM6
7 DDRB_SDQS6 169 DQS6 DM6 170
171 VSS VSS 172
DDRB SDQ50 173 174 DDRB SDQ54
DDRB_SDQ51 DQ50 DQ54 DDRB_SDQ55
175 DQ51 DQ55 176
177 VSS VSS 178
DDRB_SDQ56 179 180 DDRB_SDQ60
DDRB SDQ57 DQ56 DQ60 DDRB SDQ61
181 DQ57 DQ61 182
183 VSS VSS 184
DDRB SDM7 185 186 DDRB SDQS7#
DM7 DQS7# DDRB_SDQS7 DDRB_SDQS7# 7
187 VSS DQS7 188 DDRB_SDQS7 7
DDRB SDQ58 189 190
DDRB SDQ59 DQ58 VSS DDRB SDQ62
191 DQ59 DQ62 192
193 194 DDRB SDQ63
SB CK SDAT VSS DQ63
10,16,24,37 SB_CK_SDAT 195 SDA VSS 196
SB CK SCLK 197 198 R11 1 2 10K 0402 5% +3VS
10,16,24,37 SB_CK_SCLK SCL SAO
+3VS 199 200 R9 1 2 10K 0402 5%
C313 VDDSPD SA1
201 GND GND 202

0.1U_0402_16V4Z FOX_AS0A426-MARG-7F
2
CONN@

DIMM1 REV H:9.2mm (BOT)

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401836 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date Thursday, March 18, 2010 Sheet 11 of 55
A B C D E
 5 4 3 2 1

U22B
PCIE_GTX_C_MRX_P0 D4 A5 PCIE_MTX_GRX_P0 C647 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
PCIE_GTX_C_MRX_N0 GFX_RX0P GFX_TX0P PCIE_MTX_GRX_N0 C646 1
C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0
PCIE_GTX_C_MRX_N1 A3 A4 PCIE_MTX_GRX_P1 C649 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
H CADOP[0..15] PCIE_GTX_C_MRX_P1 GFX_RX1P GFX_TX1P PCIE_MTX_GRX_N1 C648 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1
H_CADOP[0..15] 6 B3 GFX_RX1N GFX_TX1N B4 2
PCIE_GTX_C_MRX_P2 C2 C3 PCIE_MTX_GRX_P2 C651 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
H CADON[0..15] PCIE_GTX_C_MRX_N2 GFX_RX2P GFX_TX2P PCIE_MTX_GRX_N2 C650 1
H_CADON[0..15] 6 C1 GFX_RX2N GFX_TX2N B2 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
PCIE_GTX_C_MRX_P3 E5 D1 PCIE_MTX_GRX_P3 C653 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
H CADIP[0..15] PCIE_GTX_C_MRX_N3 GFX_RX3P GFX_TX3P PCIE_MTX_GRX_N3 C652 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
H_CADIP[0..15] 6 F5 GFX_RX3N GFX_TX3N D2 2
PCIE_GTX_C_MRX_P4 G5 E2 PCIE_MTX_GRX_P4 C654 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
H_CADIN[0..15] PCIE GTX C MRX N4 GFX_RX4P GFX_TX4P PCIE MTX GRX N4 C655 1
H_CADIN[0..15] 6 G6 GFX_RX4N GFX_TX4N E1 2 0.1U 0402 16V7K PCIE MTX C GRX N4
PCIE GTX C MRX P5 H5 F4 PCIE MTX GRX P5 C656 1 2 0.1U 0402 16V7K PCIE MTX C GRX P5
PCIE GTX C MRX N5 GFX_RX5P GFX_TX5P PCIE MTX GRX N5 C657 1 0.1U 0402 16V7K PCIE MTX C GRX N5
D H6 GFX_RX5N GFX_TX5N F3 2 D
PCIE_GTX_C_MRX_P[0..15] PCIE GTX C MRX N6 J6 F1 PCIE MTX GRX P6 C659 1 2 0.1U 0402 16V7K PCIE MTX C GRX P6
PCIE_GTX_C_MRX_P[0..15] 17 GFX_RX6P GFX_TX6P
PCIE GTX C MRX P6 J5 F2 PCIE MTX GRX N6 C660 1 2 0.1U 0402 16V7K PCIE MTX C GRX N6
PCIE_GTX_C_MRX_N[0..15] PCIE GTX C MRX P7 GFX_RX6N GFX_TX6N PCIE MTX GRX P7 C642 0.1U 0402 16V7K PCIE MTX C GRX P7
PCIE_GTX_C_MRX_N[0..15] 17 J7 GFX_RX7P GFX_TX7P H4 1 2
PCIE GTX C MRX N7 J8 H3 PCIE MTX GRX N7 C641 1 2 0.1U 0402 16V7K PCIE MTX C GRX N7
PCIE_MTX_C_GRX_P[0..15] PCIE GTX C MRX P8 GFX_RX7N GFX_TX7N PCIE MTX GRX P8 C638 0.1U 0402 16V7K PCIE MTX C GRX P8
PCIE_MTX_C_GRX_P[0..15] 17 L5 GFX_RX8P GFX_TX8P H1 1 2
PCIE GTX C MRX N8 L6 H2 PCIE MTX GRX N8 C636 1 2 0.1U 0402 16V7K PCIE MTX C GRX N8
PCIE_MTX_C_GRX_N[0..15] PCIE GTX C MRX P9 GFX_RX8N GFX_TX8N PCIE MTX GRX P9 C637 0.1U 0402 16V7K PCIE MTX C GRX P9
PCIE_MTX_C_GRX_N[0..15] 17 M8 GFX_RX9P GFX_TX9P J2 1 2
PCIE GTX C MRX N9 L8 J1 PCIE MTX GRX N9 C635 1 2 0.1U 0402 16V7K PCIE MTX C GRX N9
PCIE_GTX_C_MRX_P10 GFX_RX9N GFX_TX9N PCIE_MTX_GRX_P10 C634 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10

PCIE I/F GFX

P7 GFX_RX10P GFX_TX10P K4 1 2
PCIE_GTX_C_MRX_N10 M7 K3 PCIE_MTX_GRX_N10 C633 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
PCIE_GTX_C_MRX_P11 GFX_RX10N GFX_TX10N PCIE_MTX_GRX_P11 C631 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
P5 GFX_RX11P GFX_TX11P K1 1 2
PCIE_GTX_C_MRX_N11 M5 K2 PCIE_MTX_GRX_N11 C630 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11
PCIE_GTX_C_MRX_P12 GFX_RX11N GFX_TX11N PCIE_MTX_GRX_P12 C629 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
R8 GFX_RX12P GFX_TX12P M4 1 2
PCIE_GTX_C_MRX_N12 P8 M3 PCIE_MTX_GRX_N12 C627 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
PCIE_GTX_C_MRX_P13 GFX_RX12N GFX_TX12N PCIE_MTX_GRX_P13 C625 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
R6 GFX_RX13P GFX_TX13P M1 1 2
PCIE_GTX_C_MRX_N13 R5 M2 PCIE_MTX_GRX_N13 C623 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13
PCIE_GTX_C_MRX_P14 GFX_RX13N GFX_TX13N PCIE_MTX_GRX_P14 C620 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
P4 GFX_RX14P GFX_TX14P N2 1 2
PCIE_GTX_C_MRX_N14 P3 N1 PCIE_MTX_GRX_N14 C624 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
PCIE_GTX_C_MRX_P15 GFX_RX14N GFX_TX14N PCIE_MTX_GRX_P15 C621 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
T4 GFX_RX15P GFX_TX15P P1 1 2
PCIE_GTX_C_MRX_N15 T3 P2 PCIE_MTX_GRX_N15 C619 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15
GFX_RX15N GFX_TX15N
AE3 AC1 PCIE_ITX_PRX_P0 C600 1 2 0.1U_0402_16V7K
37 PCIE_PTX_C_IRX_P0 GPP_RX0P GPP_TX0P PCIE_ITX_C_PRX_P0 37
WLAN 37 PCIE_PTX_C_IRX_N0 AD4 AC2 PCIE ITX PRX N0 C601 1 2 0.1U 0402 16V7K WLAN
GPP_RX0N GPP_TX0N PCIE_ITX_C_PRX_N0 37
AE2 AB4 PCIE ITX PRX P1 C602 1 2 0.1U 0402 16V7K
31 PCIE_PTX_C_IRX_P1 GPP_RX1P GPP_TX1P PCIE_ITX_C_PRX_P1 31
LAN 31 PCIE_PTX_C_IRX_N1 AD3 AB3 PCIE ITX PRX N1 C605 1 2 0.1U 0402 16V7K LAN
GPP_RX1N GPP_TX1N PCIE_ITX_C_PRX_N1 31
AD1 GPP_RX2P GPP_TX2P AA2
AD2 GPP_RX2N PCIE I/F GPP GPP_TX2N AA1
V5 GPP_RX3P GPP_TX3P Y1
C W6 Y2 C
GPP_RX3N GPP_TX3N
U5 GPP_RX4P GPP_TX4P Y4
U6 GPP_RX4N GPP_TX4N Y3
U8 GPP_RX5P GPP_TX5P V1
U7 GPP_RX5N GPP_TX5N V2

23 SB_RX0P AA8 AD7 SB_TX0P_C C259 1 2 0.1U_0402_16V7K

SB_RX0P SB_TX0P SB_TX0P 23
23 SB_RX0N Y8 AE7 SB_TX0N_C C272 1 2 0.1U_0402_16V7K
SB_RX0N SB_TX0N SB_TX0N 23
23 SB_RX1P AA7 AE6 SB_TX1P_C C254 1 2 0.1U_0402_16V7K
SB_RX1P SB_TX1P SB_TX1P 23
23 SB_RX1N Y7 AD6 SB_TX1N_C C252 1 2 0.1U_0402_16V7K
SB_RX1N SB_TX1N SB_TX1N 23
23 SB_RX2P AA5 PCIE I/F SB AB6 SB_TX2P_C C168 1 2 0.1U_0402_16V7K
SB_RX2P SB_TX2P SB_TX2P 23
23 SB_RX2N AA6 AC6 SB_TX2N_C C261 1 2 0.1U_0402_16V7K
SB_RX2N SB_TX2N SB_TX2N 23
23 SB_RX3P W5 AD5 SB_TX3P_C C248 1 2 0.1U_0402_16V7K
SB_RX3P SB_TX3P SB_TX3P 23
23 SB_RX3N Y5 AE5 SB_TX3N_C C275 1 2 0.1U_0402_16V7K
SB_RX3N SB_TX3N SB_TX3N 23
AC8 R29 1 2 1.27K_0402_1%
U22A PCE_CALRP(PCE_BCALRP) R32 2K_0402_1%
PCE_CALRN(PCE_BCALRN) AB8 1 2 1.1VS
H_CADOP0 Y25 D24 H_CADIP0
H_CADON0 HT_RXCAD0P HT_TXCAD0P H_CADIN0
H CADOP1
Y24 HT_RXCAD0N PART 1 OF 6 HT_TXCAD0N D25
H CADIP1
RS880M_FCBGA528
V22 HT_RXCAD1P HT_TXCAD1P E24
H CADON1 V23 E25 H CADIN1
H CADOP2 HT_RXCAD1N HT_TXCAD1N H CADIP2
V25 HT_RXCAD2P HT_TXCAD2P F24
H CADON2 V24 F25 H CADIN2
H CADOP3 HT_RXCAD2N HT_TXCAD2N H CADIP3
U24 HT_RXCAD3P HT_TXCAD3P F23
H CADON3 U25 F22 H CADIN3
H CADOP4 HT_RXCAD3N HT_TXCAD3N H CADIP4
T25 HT_RXCAD4P HT_TXCAD4P H23
H CADON4 T24 H22 H CADIN4
H CADOP5 HT_RXCAD4N HT_TXCAD4N H CADIP5
HYPER TRANSPORT CPU I/F

P22 HT_RXCAD5P HT_TXCAD5P J25

H CADON5 P23 J24 H CADIN5
B H CADOP6 HT_RXCAD5N HT_TXCAD5N H CADIP6 B
P25 HT_RXCAD6P HT_TXCAD6P K24
H_CADON6 P24 K25 H_CADIN6
H_CADOP7 HT_RXCAD6N HT_TXCAD6N H_CADIP7
N24 HT_RXCAD7P HT_TXCAD7P K23
H_CADON7 N25 K22 H_CADIN7
HT_RXCAD7N HT_TXCAD7N
H_CADOP8 AC24 F21 H_CADIP8
H_CADON8 HT_RXCAD8P HT_TXCAD8P H_CADIN8
AC25 HT_RXCAD8N HT_TXCAD8N G21
H_CADOP9 AB25 G20 H_CADIP9
H_CADON9 HT_RXCAD9P HT_TXCAD9P H_CADIN9
AB24 HT_RXCAD9N HT_TXCAD9N H21
H_CADOP10 AA24 J20 H_CADIP10
H_CADON10 HT_RXCAD10P HT_TXCAD10P H_CADIN10
AA25 HT_RXCAD10N HT_TXCAD10N J21
H_CADOP11 Y22 J18 H_CADIP11
H_CADON11 HT_RXCAD11P HT_TXCAD11P H_CADIN11
Y23 HT_RXCAD11N HT_TXCAD11N K17
H_CADOP12 W21 L19 H_CADIP12
H_CADON12 HT_RXCAD12P HT_TXCAD12P H_CADIN12
W20 HT_RXCAD12N HT_TXCAD12N J19
H CADOP13 V21 M19 H CADIP13
H CADON13 HT_RXCAD13P HT_TXCAD13P H CADIN13
V20 HT_RXCAD13N HT_TXCAD13N L18
H CADOP14 U20 M21 H CADIP14
H CADON14 HT_RXCAD14P HT_TXCAD14P H CADIN14
U21 HT_RXCAD14N HT_TXCAD14N P21
H CADOP15 U19 P18 H CADIP15
H CADON15 HT_RXCAD15P HT_TXCAD15P H CADIN15
Check AMD U18 HT_RXCAD15N HT_TXCAD15N M18

6 H_CLKOP0 T22 HT_RXCLK0P HT_TXCLK0P H24 H_CLKIP0 6

6 H_CLKON0 T23 HT_RXCLK0N HT_TXCLK0N H25 H_CLKIN0 6
6 H_CLKOP1 AB23 HT_RXCLK1P HT_TXCLK1P L21 H_CLKIP1 6
6 H_CLKON1 AA22 HT_RXCLK1N HT_TXCLK1N L20 H_CLKIN1 6
H_CTLOP0 M22 M24 H_CTLIP0
6 H_CTLOP0 HT_RXCTL0P HT_TXCTL0P H_CTLIP0 6
H_CTLON0 M23 M25 H_CTLIN0
A 6 H_CTLON0 HT_RXCTL0N HT_TXCTL0N H_CTLIN0 6 A
H_CTLOP1 R21 P19 H_CTLIP1
6 H_CTLOP1 HT_RXCTL1P HT_TXCTL1P H_CTLIP1 6
H_CTLON1 R20 R18 H_CTLIN1
6 H_CTLON1 HT_RXCTL1N HT_TXCTL1N H_CTLIN1 6
1 R67 2 C23 B24 1 R79 2
HT_RXCALP HT_TXCALP
A24 HT_RXCALN HT_TXCALN B25
301_0402_1%~D 301_0402_1%~D
Place within 1" RS880M_FCBGA528 Place within 1" Security Classification Compal Secret Data Compal Electronics, Inc.
layout 4/8 layout 4/8 Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
HT Link SCHEMATIC MB A5992
When tune trace length, must THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
keep 1:4 on self-trace Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 12 of 55
5 4 3 2 1
 5 4 3 2 1

1.8VS NB_HTPVDD 3VS

L10 L8
1 2 <20mA> 1 2 AVDD1 <110mA>
MBC1608121YZF_0603 1 HCB1608KF-221T20_0603 C40 1
22U_0805_6.3V6M
C78 1.8VS
2.2U_0603_6.3V4Z L23
2 AVDD2 2
1 2
HCB1608KF-221T20_0603 1 1 L68
2.2U_0603_6.3V4Z 0.1U_0402_16V4Z U22C VDDLTP18 1 2 1.8VS
D C265 C74 F12 A22 1 MBC1608121YZF_0603 D
1.8VS AVDD1(NC) TXOUT_L0P(NC)
2 2
E12 AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC) B22
1.8VS VDDA18HTPLL <20mA> F14 A21 C449
L24 L25 AVDDDI(NC) TXOUT_L1P(NC) 2.2U_0603_6.3V4Z
G15 AVSSDI(NC) TXOUT_L1N(NC) B21
AVDDQ 2
1 2 <20mA> 1 2 <4mA> H15 AVDDQ(NC) TXOUT_L2P(NC) B20
MBC1608121YZF_0603 1 HCB1608KF-221T20_0603 1 H14 A20
AVSSQ(NC) TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC) A19
C266 C267 E17 B19 L67
2.2U_0603_6.3V4Z 2.2U_0603_6.3V4Z C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2) VDDLT18

CRT/TVOUT
F17 Y(DFT_GPIO2) 1 2 1.8VS
2 2 MBC1608121YZF_0603
F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18 1 1
TXOUT_U0N(NC) A18
G18 A17 C115 C455
RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3) 0.1U_0402_16V4Z 4.7U_0805_10V4Z
G17 REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) B17
2 2
E18 GREEN(DFT_GPIO1) TXOUT_U2P(NC) D20
1.8VS VDDA18PCIEPLL F18 D21
L5 GREENb(NC) TXOUT_U2N(NC)
E19 BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5) D18
1 2 <120mA> F19 BLUEb(NC) TXOUT_U3N(NC) D19
MBC1608121YZF_0603 1
GMCH_CRT_HSYNC A11 B16
15 GMCH_CRT_HSYNC DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1)
C31 GMCH_CRT_VSYNC B11 A16
15 GMCH_CRT_VSYNC DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3)
2.2U_0603_6.3V4Z F8 D16
2 DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4)
E8 DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1) D17
R59 1 2 715 0402 1% G14 DAC_RSET(PWM_GPIO1) VDDLTP18
VDDLTP18(NC) A13 <15mA>
10mil within 1 inch NB_PLLVDD NB PLLVDD A12 B13
NB HTPVDD PLLVDD(NC) VSSLTP18(NC)
NB_HTPVDD D14 PLLVDD18(NC)
1.1VS B12 A15 <300mA> VDDLT18

LVTM
L50 NB_PLLVDD PLLVSS(NC) VDDLT18_1(NC)
B15

PLL PWR
VDDLT18_2(NC)
C 1 2 <65mA> VDDA18HTPLL H17 VDDA18HTPLL VDDLT33_1(NC) A14 C
MBC1608121YZF_0603 1 B14
VDDLT33_2(NC)
VDDA18PCIEPLL D7 VDDA18PCIEPLL1
C400 E7 C14
2.2U_0603_6.3V4Z R319 0_0402_5% VDDA18PCIEPLL2 VSSLT1(VSS)
VSSLT2(VSS) D15
2 NB_RESET#
15,17,23,31,34,37 PLT_RST# 1 2 D8 SYSRESETb VSSLT3(VSS) C16
24 NB_PWRGD A10 POWERGOOD VSSLT4(VSS) C18
1.8VS 1 2 NB_LDTSTOP# C10 C20
R326 300_0402_5% NB_ALLOW_LDTSTOP LDTSTOPb VSSLT5(VSS)
NB PGRGD (SB) C12 E20

PM
ALLOW_LDTSTOP VSSLT6(VSS)
Output, OD VSSLT7(VSS) C22
16 CLK_NBHT C25 HT_REFCLKP
CLK_NB_14.318M C24
16 CLK_NB_14.318M 16 CLK_NBHT# HT_REFCLKN
@ @ CLK_NB_14.318M E11 REFCLK_P/OSCIN(OSCIN)

CLOCKs
1 2 1 2 F11 REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) E9
LVDS_BLON(PCE_RCALRP) F7
For EMI request C691 R637 1.1VS 1 2 1 2 T2 G12
16 CLK_NBGFX GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) PAD T23
22P_0402_50V8J 10_0402_5% R58 R43 T1
16 CLK_NBGFX# GFX_REFCLKN
4.7K_0402_5% 4.7K_0402_5%
U1 GPP_REFCLKP
U2 GPP_REFCLKN

16 CLK_SBLINK_BCLK V4 GPPSB_REFCLKP(SB_REFCLKP)
R85 0_0402_5% V3
16 CLK_SBLINK_BCLK# GPPSB_REFCLKN(SB_REFCLKN)
1 2 NB LDTSTOP#
8,23 LDT_STOP#
B9 I2C_CLK
LDT_STP# (SB) LDTSTOP# (NB) A9 I2C_DATA MIS. TMDS_HPD(NC) D9
B8 D10 2 @ 1
Output, OD In Lagcy mode: Input, 1.8V signal can be used DDC_DATA0/AUX0N(NC) HPD(NC) R328 10K_0402_5%
A8 DDC_CLK0/AUX0P(NC)
B In CLMC mode: Output, OD 2 @ 1 1 2 B7 D12 1 2
B
3VS DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5) SUS_STAT# 24
R327 10K_0402_5% R552 2K_0402_1% A7 R48 0_0402_5%
DDC_DATA1/AUX1N(NC)
THERMALDIODE_P AE8 SUS_STAT_R# 15 Strap Pin
POWER_SEL 1 2 B10 AD8
48 POWER_SEL STRP_DATA THERMALDIODE_N
R320 @ 0_0402_5%
G11 RSVD TESTMODE D13 1 2
R343
POWER_SEL C8 1.8K_0402_5%
15 AUX_CAL AUX_CAL(NC)
LOW 1.1V Strap pin RS880M_FCBGA528
HIGH 0.95V
1.8VS

2
R28
Change as 1K_5% ohm
for Tigris
Unpop for Tigris 1K_0402_5%

1
R3 @ 0_0402_5%
8 CPU_LDT_REQ# 1 2

R553 0_0402_5%
1 2 NB_ALLOW_LDTSTOP
23 ALLOW_LDTSTOP

A SB I/ OD ALLOW_LDTSTOP (NB) A
In Lagcy mode: Output,OD
In CLMC mode: Input, 1.8Vsignal can be used

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 13 of 55
5 4 3 2 1
 5 4 3 2 1

U22F
A25 VSSAHT1 VSSAPCIE1 A2
D23 PART 6/6 B1 L14 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VSSAHT2 VSSAPCIE2 VDDHT
E22 VSSAHT3 VSSAPCIE3 D3 1.1VS 2 1
G22 D5 BMA-L11-201209-221LMA30T_0805
VSSAHT4 VSSAPCIE4
G24 VSSAHT5 VSSAPCIE5 E4 1 1 1 1 1
G25 G1 L16
VSSAHT6 VSSAPCIE6 C108 C131 C249 C253 C126
H19 VSSAHT7 VSSAPCIE7 G2 2 1 1.1VS
J22 G4 FBMA-L11-201209-221LMA30T_0805
VSSAHT8 VSSAPCIE8 2 2 2 2 2 U22E
L17 VSSAHT9 VSSAPCIE9 H7 <2.5A>
D L22 J4 22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z J17 A6 VDDA11PCIE 1 2 D
VSSAHT10 VSSAPCIE10 VDDHT_1 VDDPCIE_1 C19
L24 VSSAHT11 VSSAPCIE11 R7 K16 VDDHT_2 PART 5/6 VDDPCIE_2 B6 1 2 22U 0805 6.3V6M
L25 L1 L16 C6 C15 22U_0805_6.3V6M
VSSAHT12 VSSAPCIE12 L22 VDDHT_3 VDDPCIE_3
M20 VSSAHT13 VSSAPCIE13 L2 M16 VDDHT_4 VDDPCIE_4 D6
N22 L4 2 1 0.1U 0402 16V4Z 0.1U 0402 16V4Z VDDHTRX P16 E6 C42 1 2 1U 0402 6.3V4Z
VSSAHT14 VSSAPCIE14 VDDHT_5 VDDPCIE_5 C59 1U 0402 6.3V4Z
P20
R19
VSSAHT15 VSSAPCIE15 L7
M6 FBMA-L11-201209-221LMA30T_0805
0.68A R16
T16
VDDHT_6 VDDPCIE_6 F6
G7 C44
1
1
2
2 1U 0402 6.3V4Z
VSSAHT16 VSSAPCIE16 1 1 1 1 1 VDDHT_7 VDDPCIE_7
R22 N4 <680mA> H8 C38 1 2 1U 0402 6.3V4Z
VSSAHT17 VSSAPCIE17 C154 C257 C219 C264 C273 VDDPCIE_8
R24 VSSAHT18 VSSAPCIE18 P6 H18 VDDHTRX_1 VDDPCIE_9 J9
R25 VSSAHT19 VSSAPCIE19 R1 G19 VDDHTRX_2 VDDPCIE_10 K9 1 2
2 2 2 2 2 C51
H20 VSSAHT20 VSSAPCIE20 R2 F20 VDDHTRX_3 VDDPCIE_11 M9 1 2 0.1U_0402_16V4Z
U22 R4 22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z E21 L9 C43 0.1U_0402_16V4Z
VSSAHT21 VSSAPCIE21 VDDHTRX_4 VDDPCIE_12
V19 VSSAHT22 VSSAPCIE22 V7 D22 VDDHTRX_5 VDDPCIE_13 P9
GROUND

W22 VSSAHT23 VSSAPCIE23 U4 B23 VDDHTRX_6 VDDPCIE_14 R9

W24 VSSAHT24 VSSAPCIE24 V8 A23 VDDHTRX_7 VDDPCIE_15 T9
W25 V6 L21 V9
VSSAHT25 VSSAPCIE25 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDHTTX VDDPCIE_16
Y21 VSSAHT26 VSSAPCIE26 W1 1.2V_HT 2 1 <680mA> AE25 VDDHTTX_1 VDDPCIE_17 U9
AD25 W2 AD24 @ L7
VSSAHT27 VSSAPCIE27 FBMA-L11-201209-221LMA30T_0805 VDDHTTX_2
VSSAPCIE28 W4 1 1 1 1 1 AC23 VDDHTTX_3 VDDC_1 K12 1.1VS 2 1 NB_CORE
L12 W7 AB22 J14 FBMA-L11-201209-221LMA30T_0805
VSS11 VSSAPCIE29 C262 C130 C258 C171 C255 VDDHTTX_4 VDDC_2
M14 VSS12 VSSAPCIE30 W8 AA21 VDDHTTX_5 VDDC_3 U16 2 1
N13 Y6 Y20 J11 FBMA-L11-201209-221LMA30T_0805
VSS13 VSSAPCIE31 2 2 2 2 2 VDDHTTX_6 VDDC_4 @ L6
P12 VSS14 VSSAPCIE32 AA4 W19 VDDHTTX_7 VDDC_5 K15

POWER
P15 AB5 22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z V18 M12
VSS15 VSSAPCIE33 VDDHTTX_8 VDDC_6
R11 VSS16 VSSAPCIE34 AB1 U17 VDDHTTX_9 VDDC_7 L14 <10A>
R14 VSS17 VSSAPCIE35 AB7 T17 VDDHTTX_10 VDDC_8 L11
T12 VSS18 VSSAPCIE36 AC3 R17 VDDHTTX_11 VDDC_9 M13
U14 VSS19 VSSAPCIE37 AC4 P17 VDDHTTX_12 VDDC_10 M15
U11 VSS20 VSSAPCIE38 AE1 M17 VDDHTTX_13 VDDC_11 N12

330U_D2E_2.5VM_R9M
C110

C112

C57

C123

C215

C256

C80

C218

C251

C18

C20
C U15 AE4 L9 N14 1 C
VSS21 VSSAPCIE39 0.1U 0402 16V4Z 0.1U 0402 16V4Z VDDA18PCIE VDDC_12
V12 VSS22 VSSAPCIE40 AB2 1.8VS 2 1 <700mA> J10 VDDA18PCIE_1 VDDC_13 P11 1 1 1 1 1 1 1 1 1 2 2

C10
W11 FBMA-L11-201209-221LMA30T_0805 P10 P13 +
VSS23 VDDA18PCIE_2 VDDC_14
W15 VSS24 1 1 1 1 1 1 1 K10 VDDA18PCIE_3 VDDC_15 P14

22U 0805 6.3V6M

22U 0805 6.3V6M

C52

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
AC12 VSS25 VSS1 AE14 M10 VDDA18PCIE_4 VDDC_16 R12
22U_0805_6.3V6M C53 C37 C55 C58 C56 C62 2 2 2 2 2 2 2 2 2 1 1 2
AA14 VSS26 VSS2 D11 L10 VDDA18PCIE_5 VDDC_17 R15
Y18 VSS27 VSS3 G8 W9 VDDA18PCIE_6 VDDC_18 T11
2 22U_0805_6.3V6M 2 2 2 2 2 2
AB11 VSS28 VSS4 E14 H9 VDDA18PCIE_7 VDDC_19 T15
AB15 E15 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z T10 U12
VSS29 VSS5 VDDA18PCIE_8 VDDC_20
AB17 VSS30 VSS6 J15 R10 VDDA18PCIE_9 VDDC_21 T14
AB19 VSS31 VSS7 J12 Y9 VDDA18PCIE_10 VDDC_22 J16
AE20 VSS32 VSS8 K14 AA9 VDDA18PCIE_11
AB21 VSS33 VSS9 M11 AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10
K11 VSS34 VSS10 L15 AD9 VDDA18PCIE_13 VDD_MEM2(NC) AA11
AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11
RS880M_FCBGA528 U10 AD10
VDDA18PCIE_15 VDD_MEM4(NC)
VDD_MEM5(NC) AB10
1.8VS <10mA> F9 VDD18_1 VDD_MEM6(NC) AC10
G9 VDD18_2
1 1 R82 2 AE11 H11 <60mA> 3VS
C398 0 0402 5% VDD18_MEM1(NC) VDD33_1(NC)
AD11 VDD18_MEM2(NC) VDD33_2(NC) H12
1U_0402_6.3V4Z within 15mil 1 1
RS880M_FCBGA528
U22D 2 C93 C61
PAR 4 OF 6 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
AB12 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) AA18
AE16 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) AA20
V11 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) AA19
AE15 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) Y19
B B
AA12 MEM_A4(NC) MEM_DQ4(NC) V17
AB16 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA17
AB14 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) AA15
AD14 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) Y15
AD13 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) AC20
AD15 MEM_A9(NC) MEM_DQ9/DVO_D5(NC) AD19
SBD_MEM/DVO_I/F

AC16 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) AE22

AE13 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) AC18
AC14 MEM_A12(NC) MEM_DQ12(NC) AB20
Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22
MEM_DQ14/DVO_D10(NC) AC22
AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
AE17 MEM_BA1(NC)
AD17 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) Y17
MEM_DQS0N/DVO_IDCKN(NC) W18
W12 MEM_RASb(NC) MEM_DQS1P(NC) AD20
Y12 MEM_CASb(NC) MEM_DQS1N(NC) AE21
AD18 MEM_WEb(NC)
AB13 MEM_CSb(NC) MEM_DM0(NC) W17
AB18 MEM_CKE(NC) MEM_DM1/DVO_D8(NC) AE19
V14 MEM_ODT(NC)
IOPLLVDD18(NC) AE23 1.8VS
V15 MEM_CKP(NC) IOPLLVDD(NC) AE24 1.1VS
W14 MEM_CKN(NC)
IOPLLVSS(NC) AD23
AE12 MEM_COMPP(NC)
AD12 MEM_COMPN(NC) MEM_VREF(NC) AE18 1 2
R351 0_0402_5%
RS880M_FCBGA528
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A5992
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 14 of 55
5 4 3 2 1
 5 4 3 2 1

DFT GPIO5 STRAP DEBUG BUS GPIO ENABLEb

13 GMCH_CRT_VSYNC 2 1 3VS Enables the Test Debug Bus using GPIO. (VSYNC)
D R341 3K_0402_5% 1 : Disable (RS880) D
2 1
R337 @ 3K_0402_5% 0 : Enable (Rs880)

DFT GPIO1 LOAD EEPROM STRAPS

13 AUX_CAL 1 2 Selects Loading of STRAPS from EPROM

@ R315 150_0402_1% 1 : Bypass the loading of EEPROM straps and use Hardware Default Values
@ 0 : I2C Master can load strap values from EEPROM if connected, or use
RS880M DFT_GPIO1 13 SUS_STAT_R# 2 1 PLT_RST# 13,17,23,31,34,37
default values if not connected
RS740/RX780/RS880M: DFT_GPIO1 RS880M:SUS_STAT
D22 CH751H-40PT_SOD323-2

C C

RS880 use HSYNC to enable SIDE PORT

RS880 use HSYNC to enable SIDE PORT RS740/RS780/RS880M: Enables Side port memory ( RS880M use HSYNC#)
0. Enable (RS880M)
2 1
1 : Disable(RS880M)
13 GMCH_CRT_HSYNC 3VS
R332 3K_0402_5%
2 @ 1
R331 3K_0402_5%

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 15 of 55
5 4 3 2 1
 5 4 3 2 1

1.2V_HT VDDCLK_IO
3VS 3VS_CLK
L31
L30 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 FBMA-L11-201209-221LMA30T_0805 C367 C138 C278 C404 C295 C274 C160 C140 C268 C294 C297
FBMA-L11-201209-221LMA30T_0805 C260 C142 C298 C293 C280 C135 C263
22U_0805_6.3V6M 1U_0402_6.3V4Z
2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z

D 1U CLOSE PIN 69 D
L36
3VS_CLK 1 2 3VS CLKVDDA

FBMA-L11-201209-221LMA30T_0805
1 1 U15
C161
C141
22U_0805_6.3V6M
2 2
0.1U_0402_16V4Z ICS 9LPRS488 3VS_CLK
49 VDDA SMBCLK 1
SEL_27M 1 configure as 27M and 27M_SS output SB_CK_SCLK 10,11,24,37
48 GNDA SMBDAT 2

1
SB_CK_SDAT 10,11,24,37
0 configure as SRC_7 output R161
3VS_CLK 62 41 SRC_SLOW 8.2K_0402_5%
VDDREF SB_SRC_SLOW# CLK_CPU_BCLK 8

2
66 GNDREF
1 * configure as 27M and 27M_SS output C277 2 1 R169

2
27M_SEL 0.1U_0402_16V4Z @ 261_0402_1% CPU
0 configure as SRC_7 output VDDCLK_IO 12 56 CLK_CPU 1 2 SRC_SLOW
* default VDDSRC_IO CPUKG0T_LPRS CLK_CPU# R170 1
18 55 2 0_0402_5% CLK_CPU_BCLK# 8

1
VDDSRC_IO CPUKG0C_LPRS R168 0_0402_5%
28 VDDATIG_IO

1
37 VDDSB_SRC_IO
53 60 CLK_HTT 1 2 R111
VDDCPU_IO HTT0T_LPRS / 66 M CLK_NBHT 13
1 configure as single-ended 66MHz output 59 CLK_HTT# R175 1 2 0_0402_5% NB HTT 8.2K_0402_5% @
3VS_CLK HTT0C_LPRS / 66 M CLK_NBHT# 13
SEL_HTT66 R172 0_0402_5%
0* configure as differential 100MHz output 3VS_CLK 3

2
VDDDOT
17 VDDSRC SB_SRC0T_LPRS 40
1* SS 100M SATA SRC6 output 29 39
VDDATIG SB_SRC0C_LPRS
R490 8.2K_0402_5%

SEL_SATA 38 VDDSB_SRC
R495 8.2K_0402_5%

0 SS 100M SATA SRC6 output 44 VDDSATA

2

C * default 3VS 54 35 C
VDDCPU SB_SRC1T_LPRS
2

L35 61 34
VDDHTT SB_SRC1C_LPRS
1 2 69 VDD48
FBM-L11-160808-800LMT_0603 3VS_CLK
1 2 33 CLK ATIG0 1 2 CLK_NBGFX 13
1

C282 @ 2.2U_0603_6.3V4Z ATIG0T_LPRS CLK_ATIG0# R174 1

32 2 0_0402_5% CLK_NBGFX# 13 NB GFX
1

ATIG0C_LPRS R176 0_0402_5%

1 2
C281 0.1U_0402_16V4Z 24 CLKREQ0 # CLK_VGA R177 1
ATIG1T_LPRS 31 2 CLK_PCIE_VGA 17
51 30 CLK_VGA# 1 2 0_0402_5% VGA
LAN request CLKREQ1# ATIG1C_LPRS CLK_PCIE_VGA# 17

2
31 LAN_CLKREQ# R203 0_0402_5%
50 R112 R187
MiniCard1 request 37 MINI1_CLKREQ# CLKREQ2#
26 8.2K_0402_5% @ @
ATIG2T_LPRS 8.2K_0402_5%
43 CLKREQ3# ATIG2C_LPRS 25

1
42 CLKREQ4#
23 CLK_SRC0 1 2 SEL_SATA
SRC0T_LPRS CLK_PCIE_LAN 31
22 CLK_SRC0# R189 1 2 0_0402_5% LAN SEL_HT66
SRC0C_LPRS CLK_PCIE_LAN# 31
R190 0_0402_5%

2
3VS_CLK 1 R223 2 8.2K 0402 5% 27M SEL 63 REF2/SEL_27 SRC1T_LPRS 21 R182 R188
External 14MHz CLK 20 8.2K_0402_5% @
SRC1C_LPRS
for SB710 23 CLK_14M_SB 1 R109 2 33 0402 5% SEL SATA 64 REF1/SEL_SATA
8.2K_0402_5%

1
1 2 SEL HT66 65 16 CLK SRC2 1 2
13 CLK_NB_14.318M REF0/SEL_HTT66 SRC2T_LPRS CLK_PCIE_MINI1 37
R179 158_0402_1% 15 CLK SRC2# R197 1 2 0 0402 5% MiniCard
SRC2C_LPRS CLK_PCIE_MINI1# 37
1 2 R196 0_0402_5%
R178 90.9_0402_1%
2 1 CLK 48M 0 71 14
B 33 CLK_48M_SD R194 33_0402_5% 48MHz_0 SRC3T_LPRS B
SRC3C_LPRS 13
2 1 CLK_48M_1 70
24 CLK_48M_USB R193 33_0402_5% 48MHz_1
10 CLK_SRC4 1 2
SRC4T_LPRS CLK_SBLINK_BCLK 13
9 CLK_SRC4# R200 1 2 0_0402_5% NB A LINK
SRC4C_LPRS CLK_SBLINK_BCLK# 13
CLK_XTAL_IN 67 R199 0_0402_5%
X1
NB CLOCK INPUT TABLE CLK_XTAL_OUT 68 8 SRC 0 LAN
X2 SRC5T_LPRS
SRC5C_LPRS 7
NB CLOCKS RS740 RX780 RS780 SRC 1
HT_REFCLKP 6 46 CLK_SRC6 1 2 SRC 2 MINI1 (WLAN)
66M SE(SINGLE END) GNDDOT SRC6T/SATAT_LPRS CLK_SBSRC_BCLK 23
100M DIFF 100M DIFF 11 45 CLK_SRC6# R163 1 2 0_0402_5% SB RCLK
GNDSRC SRC6C/SATAC_LPRS CLK_SBSRC_BCLK# 23
HT_REFCLKN NC 100M DIFF 100M DIFF 19 R164 0_0402_5% SRC 3
GNDSRC
27 GNDATIG
REFCLK_P 36 5 27M SSC R 1 @ 2 SRC 4 NB-Alink
GNDSB_SRC SRC7T_LPRS/27MHz_SS 27M_SSC 18
14M SE (3.3V) 14M SE (1.8V) 14M SE (1.1V) 47 4 27M NSSC R R166 1 2 0 0402 5%
GNDSATA SRC7C_LPRS/27MHz_NS 27M_NSSC 18
REFCLK_N NC NC vref 52 R165 0_0402_5% SRC 5
GNDCPU
58 GNDHTT
GFX_REFCLK 100M DIFF 100M DIFF 100M DIFF(IN/OUT)* 72 SRC 6 SB-Alink
GND48
73 GNDPAD PD# 57 2 1 3VS_CLK
GPP_REFCLK NC 100M DIFF NC CLK XTAL OUT R173 8.2K_0402_5%
1
GPPSB_REFCLK 100M DIFF 100M DIFF 100M DIFF CLK XTAL IN C299
ICS9LPRS488AKLFT_MLF72_10x10
1U_0402_6.3V4Z
2
Main--SLG8SP626VTR-SA00001Z310
A Y4 Second--ICS9LPRS488CKLFT-SA000023H10 A

2 1 FUJICOM
14.31818MHZ_20P_6X1430004201
1 1
C290 C288
Security Classification Compal Secret Data Compal Electronics, Inc.
33P_0402_50V8J 33P_0402_50V8J 2009/09/25 2010/09/25 Title
2 2 Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
SCHEMATIC MB A5992
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 16 of 55
5 4 3 2 1
 5 4 3 2 1

PCIE LANE REVERSAL U88A PCIE LANE REVERSAL

PCIE_MTX_C_GRX_N15 AF30 AH30 PEG_NRX_C_GTX_N15 C595 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N15
PCIE MTX C GRX P15 AE31 PCIE_RX0P PCIE_TX0P PEG NRX C GTX P15 C596 0.1U 0402 16V7K PCIE GTX C MRX P15
PCIE_RX0N PCIE_TX0N AG31 1 2
PCIE_GTX_C_MRX_P[0..15]
12 PCIE_GTX_C_MRX_P[0..15]
D D
PCIE_GTX_C_MRX_N[0..15] PCIE MTX C GRX N14 AE29 AG29 PEG NRX C GTX N14 C597 1 2 0.1U 0402 16V7K PCIE GTX C MRX N14
12 PCIE_GTX_C_MRX_N[0..15] PCIE_RX1P PCIE_TX1P
PCIE MTX C GRX P14 AD28 AF28 PEG NRX C GTX P14 C598 1 2 0.1U 0402 16V7K PCIE GTX C MRX P14
PCIE_MTX_C_GRX_P[0..15] PCIE_RX1N PCIE_TX1N
12 PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15] PCIE MTX C GRX N13 AD30 AF27 PEG NRX C GTX N13 C599 1 2 0.1U 0402 16V7K PCIE GTX C MRX N13
12 PCIE_MTX_C_GRX_N[0..15] PCIE_RX2P PCIE_TX2P
PCIE MTX C GRX P13 AC31 AF26 PEG NRX C GTX P13 C608 1 2 0.1U 0402 16V7K PCIE GTX C MRX P13
PCIE_RX2N PCIE_TX2N

PCIE_MTX_C_GRX_N12 AC29 AD27 PEG_NRX_C_GTX_N12 C609 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N12

PCIE_MTX_C_GRX_P12 AB28 PCIE_RX3P PCIE_TX3P PEG_NRX_C_GTX_P12 C607 0.1U_0402_16V7K PCIE_GTX_C_MRX_P12
PCIE_RX3N PCIE_TX3N AD26 1 2

PCIE_MTX_C_GRX_N11 AB30 AC25 PEG_NRX_C_GTX_N11 C613 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N11

PCIE_RX4P PCIE_TX4P

PCI EXPRESS INTERFACE

PCIE_MTX_C_GRX_P11 AA31 AB25 PEG_NRX_C_GTX_P11 C606 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P11
PCIE_RX4N PCIE_TX4N

PCIE_MTX_C_GRX_N10 AA29 Y23 PEG_NRX_C_GTX_N10 C700 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N10

PCIE_MTX_C_GRX_P10 PCIE_RX5P PCIE_TX5P PEG_NRX_C_GTX_P10 C702 0.1U_0402_16V7K PCIE_GTX_C_MRX_P10
Y28 PCIE_RX5N PCIE_TX5N Y24 1 2

PCIE_MTX_C_GRX_N9 Y30 AB27 PEG_NRX_C_GTX_N9 C696 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N9

PCIE_MTX_C_GRX_P9 PCIE_RX6P PCIE_TX6P PEG_NRX_C_GTX_P9 C612 0.1U_0402_16V7K PCIE_GTX_C_MRX_P9
W31 PCIE_RX6N PCIE_TX6N AB26 1 2

PCIE MTX C GRX N8 W29 Y27 PEG NRX C GTX N8 C697 1 2 0.1U 0402 16V7K PCIE GTX C MRX N8
PCIE MTX C GRX P8 PCIE_RX7P PCIE_TX7P PEG NRX C GTX P8 C610 0.1U 0402 16V7K PCIE GTX C MRX P8
V28 PCIE_RX7N PCIE_TX7N Y26 1 2

C PCIE MTX C GRX N7 V30 W24 PEG NRX C GTX N7 C611 1 2 0.1U 0402 16V7K PCIE GTX C MRX N7 C
PCIE MTX C GRX P7 PCIE_RX8P PCIE_TX8P PEG NRX C GTX P7 C643 0.1U 0402 16V7K PCIE GTX C MRX P7
U31 PCIE_RX8N PCIE_TX8N W23 1 2

PCIE MTX C GRX N6 U29 V27 PEG NRX C GTX N6 C615 1 2 0.1U 0402 16V7K PCIE GTX C MRX N6
PCIE_MTX_C_GRX_P6 PCIE_RX9P PCIE_TX9P PEG_NRX_C_GTX_P6 C614 0.1U_0402_16V7K PCIE_GTX_C_MRX_P6
T28 PCIE_RX9N PCIE_TX9N U26 1 2

PCIE_MTX_C_GRX_N5 T30 U24 PEG_NRX_C_GTX_N5 C699 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N5

PCIE_MTX_C_GRX_P5 PCIE_RX10P PCIE_TX10P PEG_NRX_C_GTX_P5 C616 0.1U_0402_16V7K PCIE_GTX_C_MRX_P5
R31 PCIE_RX10N PCIE_TX10N U23 1 2

PCIE_MTX_C_GRX_N4 R29 T26 PEG_NRX_C_GTX_N4 C617 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N4

PCIE_MTX_C_GRX_P4 PCIE_RX11P PCIE_TX11P PEG_NRX_C_GTX_P4 C618 0.1U_0402_16V7K PCIE_GTX_C_MRX_P4
P28 PCIE_RX11N PCIE_TX11N T27 1 2

PCIE_MTX_C_GRX_N3 P30 T24 PEG_NRX_C_GTX_N3 C622 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N3

PCIE_MTX_C_GRX_P3 PCIE_RX12P PCIE_TX12P PEG_NRX_C_GTX_P3 C626 0.1U_0402_16V7K PCIE_GTX_C_MRX_P3
N31 PCIE_RX12N PCIE_TX12N T23 1 2

PCIE MTX C GRX N2 N29 P27 PEG NRX C GTX N2 C701 1 2 0.1U 0402 16V7K PCIE GTX C MRX N2
PCIE MTX C GRX P2 PCIE_RX13P PCIE_TX13P PEG NRX C GTX P2 C639 0.1U 0402 16V7K PCIE GTX C MRX P2
M28 PCIE_RX13N PCIE_TX13N P26 1 2

PCIE MTX C GRX N1 M30 P24 PEG NRX C GTX N1 C640 1 2 0.1U 0402 16V7K PCIE GTX C MRX N1
PCIE MTX C GRX P1 PCIE_RX14P PCIE_TX14P PEG NRX C GTX P1 C628 0.1U 0402 16V7K PCIE GTX C MRX P1
L31 PCIE_RX14N PCIE_TX14N P23 1 2

PCIE MTX C GRX N0 L29 M27 PEG NRX C GTX N0 C698 1 2 0.1U 0402 16V7K PCIE GTX C MRX N0
B PCIE MTX C GRX P0 PCIE_RX15P PCIE_TX15P PEG NRX C GTX P0 C644 0.1U 0402 16V7K PCIE GTX C MRX P0 B
K30 PCIE_RX15N PCIE_TX15N N26 1 2

CLOCK
CLK_PCIE_VGA AK30
16 CLK_PCIE_VGA PCIE_REFCLKP
CLK_PCIE_VGA# AK32
16 CLK_PCIE_VGA# PCIE_REFCLKN
For Future ASIC Pin CALIBRATION
N10 need pull down
L9 Y22 R467 1 2 1.27K_0402_1%
@ 10K_0402_5% NC#1 PCIE_CALRP
N9 NC#2
2 1 N10 AA22 R469 1 2 2K_0402_1% 1.1VS
R468 NC_PWRGOOD PCIE_CALRN

2 R578 1 AL27
13,15,23,31,34,37 PLT_RST# PERSTB
0_0402_5%

2 1 216-0728018 A12 M92-S2 XT FCBGA 0FA

@ C645 10P_0402_50V8J

For ESD Request

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 17 of 55
5 4 3 2 1
 5 3 2 1

U88B

+3.3V_DELAY MUTI GFX For M92-S2: DO NOT Install any Component U88F VARY@
1 2 AA1 AF2 R560 10K_0402_5%
1 2 VGA LCD CLK R470 @ 150_0402_1% Y4 DVPCNTL_MVP_0 TXCAP_DPA3P
AF4
in this Box. 1 2
R474 4.7K_0402_5% DVPCNTL_MVP_1 TXCAM_DPA3N
AC7 DVPCNTL_0
1 2 VGA LCD DATA Y2 AG3 +1.8VS LVDS CONTROL AB11
DVPCNTL_1 TX0P_DPA2P VARY_BL VGA_VARIBL 30
R476 4.7K_0402_5% U5 AG5 (1.8V@120mA +DPLL PVDD) AB12
DVPCNTL_2 DPA TX0M_DPA2N L44 DIGON VGA_ENVDD 30
U1 DVPCLK
R584 2 1 VGA PWRSEL1 VRAM ID0 Y7 AH3 1 2 @ 1U 0402 6.3V4Z +DPC VDD18
22 VRAM_ID0 DVPDATA_0 TX1P_DPA1P
@ 10K_0402_5% VRAM ID1 V2 AH1
22 VRAM_ID1 DVPDATA_1 TX1M_DPA1N
R477 2 1 VGA PWRSEL0 VRAM ID2 Y8 @ MCK1608471YZF 0603 1
22 VRAM_ID2 DVPDATA_2
@ 10K_0402_5% VRAM_ID3 V4 AK3 C733 C731 C709 AH20 VGA_TZCLK+ 30
22 VRAM_ID3 DVPDATA_3 TX2P_DPA0P TXCLK_UP_DPF3P
AB7 AK1 @ 10U_0603_6.3V6M AJ19 VGA_TZCLK- 30
DVPDATA_4 TX2M_DPA0N TXCLK_UN_DPF3N
W1 DVPDATA_5
D +3.3V_DELAY 2 2 2 D
AB8 DVPDATA_6 TXCBP_DPB3P AK5 TXOUT_U0P_DPF2P AL21 VGA_TZOUT0+ 30
W3 AM3 VGA_CRT_R 1 2 AK20 VGA_TZOUT0- 30
DVPDATA_7 TXCBM_DPB3N R472 150_0402_1% TXOUT_U0N_DPF2N
AB9 DVPDATA_8
W5 AK6 VGA_CRT_G 1 2 @ 0.1U_0402_10V6K AH22 VGA_TZOUT1+ 30
DVPDATA_9 TX3P_DPB2P TXOUT_U1P_DPF1P
1

AC6 AM5 R473 150_0402_1% AJ21 VGA_TZOUT1- 30

@ R484 +DPC_VDD18 W6 DVPDATA_10 DPB TX3M_DPB2N VGA_CRT_B TXOUT_U1N_DPF1N
DVPDATA_11 1 2
10K_0402_5% AD7 AJ7 R475 150_0402_1% AL23 VGA_TZOUT2+ 30
DVPDATA_12 TX4P_DPB1P +1.1VS TXOUT_U2P_DPF0P
AA3 DVPDATA_13 TX4M_DPB1N AH6 (1.8V@120mA +DPLL PVDD) TXOUT_U2N_DPF0N AK22 VGA_TZOUT2- 30
AC8 L45
2

+DPC VDD10 DVPDATA_14 @ 1U 0402 6.3V4Z +DPC VDD10

AA5 DVPDATA_15 TX5P_DPB0P AK8 1 2 TXOUT_U3P AK24
BB_EN AE8 AL7 AJ23
DVPDATA_16 TX5M_DPB0N @ MCK1608471YZF 0603 TXOUT_U3N
1 2 AA6 DVPDATA_17 1
Back bias (BB) control R471 @ AE9 C728 C724 C735
+3.3V_DELAY 0_0402_5% DVPDATA_18 @ 10U_0603_6.3V6M LVTMDP
Back Bias Disabled : AB4 DVPDATA_19
GPIO_21_BB_EN = 0V AD9 DVPDATA_20 2 2 2
AB2 DVPDATA_21 R AM26 VGA_CRT_R 29 TXCLK_LP_DPE3P AL15 VGA_TXCLK+ 30
BBP connect directly to VDDC AC10 DAC1 AK14
DVPDATA_22 TXCLK_LN_DPE3N VGA_TXCLK- 30
1

AC5 DVPDATA_23 RB AK26

R485 @ 0.1U_0402_10V6K AH16 VGA_TXOUT0+ 30
TXOUT_L0P_DPE2P
10K_0402_5% G AL25 VGA_CRT_G 29 TXOUT_L0N_DPE2N AJ15 VGA_TXOUT0- 30
AJ25
LCD GB
AL17 VGA_TXOUT1+ 30
2

GPIO23 CLKREQB I2C TXOUT_L1P_DPE1P

30 VGA_LCD_CLK R1 SCL B AH24 VGA_CRT_B 29 TXOUT_L1N_DPE1N AK16 VGA_TXOUT1- 30
30 VGA_LCD_DATA R3 SDA BB AG25
27MCLK AH18 VGA_TXOUT2+ 30
TXOUT_L2P_DPE0P
HSYNC AH26 VGA_CRT_HSYNC 22,29 TXOUT_L2N_DPE0N AJ17 VGA_TXOUT2- 30

1
GPIO_5_AC_BATT VSYNC AJ27 VGA_CRT_VSYNC 22,29
AC(Performance mode) = 3.3V TXOUT_L3P AL19
GENERAL PURPOSE I/O @ R512 AK18
Battery saving mode = 0.0V TXOUT_L3N
RSET AD22 1 R478 2 1M_0402_5%
499_0402_1%

2
GPU_GPIO0 U6 AG24 +AVDD XTALOUT
C 22 GPU_GPIO0 GPIO_0 AVDD C
GPU GPIO1 U10 AE22
22 GPU_GPIO1 GPIO_1 AVSSQ
GPU_GPIO2 T10 @ Y5 216-0728018 A12 M92-S2 XT FCBGA 0FA
22 GPU_GPIO2 GPIO_2
+3.3V_DELAY R585 1 2 100K 0402_5% U8 AE23 +VDD1DI 4 3
D32 RB751V_SOD323 GPIO_3_SMBDATA VDD1DI GND OUT
U7 GPIO_4_SMBCLK VSS1DI AD23
1 2 GPIO 5 AC BATT#
T9 1 2 1
25,34,44 ACIN GPIO_5_AC_BATT IN GND
1 2 10K 0402_5% T8 GPIO_6
@ C722
R480 T7 27MHz_16PF_6P27000126 22P_0402_50V8J
34 ENBKL GPIO_7_BLON
SOUT GPIO8 P10 +1.8VS (1.8V@70mA AVDD) +AVDD
22 SOUT_GPIO8 GPIO_8_ROMSO 2
GPU_GPIO9 P4 @ C725
@C725 L46
22 GPU_GPIO9 GPIO_9_ROMSI 2 22P_0402_50V8J
P2 AM12 2 1 1U 0402 6.3V4Z
GPU_GPIO11 GPIO_10_ROMSCK R2 BLM18PG121SN1D_0603
22 GPU_GPIO11 N6 GPIO_11 R2B AK12 Close to M92 1 1
GPU GPIO12 N5 C714 C717 C705
22 GPU_GPIO12 GPIO_12
GPU_GPIO13 N3 AL11
22 GPU_GPIO13 GPIO_13 G2
Y9 AJ11 10U_0603_6.3V
VGA_PWRSEL0 GPIO_14_HPD2 G2B 2 2 2
51 VGA_PWRSEL0 N1 GPIO_15_PWRCNTL_0
16 27M_SSC
@ 1 R481 2 0 0402 5% R 27M SSC M4 GPIO_16_SSIN B2 AK10 0.1U_0402_10V6K
22 THM_ALERT# R6 GPIO_17_THERMAL_INT B2B AL9
W10 DAC2 (1.8V@45mA VDD1DI) +VDD1DI
GPIO_18_HPD3
@ 1 R482 2 10K 0402 5% GPU CTF M2 GPIO_19_CTF
+1.8VS L47
VGA_PWRSEL1 P8 AH12 PADT29
PAD T29 (1.8V@120mA +DPLL PVDD) 2 1 1U_0402_6.3V4Z
51 VGA_PWRSEL1 GPIO_20_PWRCNTL_1 C L52
BB EN 1 R483 2 0 0402 5% GPU GPIO21 P7 AM10 PAD T37
PADT37 BLM18PG121SN1D_0603 1 1
20 BB_EN GPIO_21_BB_EN Y
N8 AJ9 PAD T30
PADT30 1 2 1U_0402_6.3V4Z +DPLL_PVDD C706 C723 C704
GPIO23 CLKREQB GPIO_22_ROMCSB COMP
N7 GPIO_23_CLKREQB
T11 MCK1608471YZF 0603 1 10U_0603_6.3V
GPIO_29_DRM_0 C718 C716 C713 2 2 2
R11 GPIO_30_DRM_1 H2SYNC AL13 HSYNC_DAC2 22
AJ13 10U_0603_6.3V6M 0.1U_0402_10V6K
10/24 Reference AMD REF136-1 GPIO24 TRSTB L6
V2SYNC VSYNC_DAC2 22
0.1U_0402_10V6K
T31 PAD JTAG_TRSTB 2 2 2
L5 JTAG_TDI (1.8V@1mA A2VDDQ)
T32 PAD L3 AD19 +VDD1DI +A2VDDQ
T33 PAD JTAG_TCK VDD2DI L49
L1 JTAG_TMS VSS2DI AC19
+3.3V_DELAY T34 PAD K4 2 1 1U 0402 6.3V4Z
TESTEN JTAG_TDO +1.1VS BLM18PG121SN1D_0603
20 TESTEN AF24 TESTEN 1
B +A2VDD C732 C727 C711 B
A2VDD AE20 L53 (1.1V@300mA +DPLL VDDC)
1

AB13 GENERICA
R492 +1.8VS W8 AE17 +A2VDDQ 1 2 1U_0402_6.3V4Z +DPLL_VDDC 10U_0603_6.3V
@ GENERICB A2VDDQ 2 2 2
W9 GENERICC
10K_0402_5% W7 AE19 MCK1608471YZF 0603 1 0.1U_0402_10V6K
GENERICD A2VSSQ C726 C703 C707
AD10
2

GENERICE_HPD4
1

TESTEN 10U_0603_6.3V6M
R486 AC14 AG13 1 R515 2 0.1U_0402_10V6K
499_0402_1% HPD1 R2SET 2 2 2
1

715_0402_1% (3.3V@65mA A2VDD)

R493 +3.3V_DELAY L74 +A2VDD
2

1K_0402_5%
VREF AC16 DDC/AUX 2 1 1U 0402 6.3V4Z
VREFG BLM18PG121SN1D_0603
AE6 VGA_PWRSEL_0 VGA_PWRSEL_1 +VGA_CORE
VGA_CRT_CLK 29 CRT 1
2

DDC1CLK C708 C734 C710

DDC1DATA AE5 VGA_CRT_DATA 29
1

0.1U_0402_10V6K 0 0 1.2V
R488 C730 AD2 10U_0603_6.3V
PLL/CLOCK AUX1P +3.3V_DELAY 2 2 2
AUX1N AD4 0 1 1.1V
249_0402_1% +DPLL PVDD AF14 0.1U_0402_10V6K
2 DPLL_PVDD
AE14 AC11 1 0 0.95V
2

DPLL_PVSS DDC2CLK
1

AC13 @
DDC2DATA R516 1 1
+DPLL VDDC AD14 AD13 10K_0402_5% 0 9V
DPLL_VDDC AUX2P
AUX2N AD11
75_0402_1% 1.8V
2

1 2 27MCLK AM28 GPIO24 TRSTB

16 27M_NSSC XTALIN
R489 XTALOUT AK28 AB22 PADT35
PAD T35
XTALOUT NC1
2

AC22 PAD T36

PADT36
NC2
1

R491 @
R513
100_0402_5% AE16 1K_0402_5%
DDCAUX5P
22 GPU_THERMAL_D+ T4 AD16
1

A DPLUS THERMAL DDCAUX5N A

22 GPU_THERMAL_D- T2
2

DMINUS
DDC6CLK AC1
DDC6DATA AC3
L51 1U_0402_6.3V4Z T41 PAD R5
+TSVDD TS_FDO
+1.8VS 2 1 AD17 TSVDD NC_DDCAUX7P AD20
1 1 AC17 TSVSS NC_DDCAUX7N AC20
BLM18PG121SN1D_0603 C715 C729 C712

10U_0603_6.3V
2 2 2
0.1U_0402_ 0V6K Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
(1.8V@20mA TSVDD) 216-0728018 A12 M92-S2 XT FCBGA 0FA SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date Thursday, March 18, 2010 Sheet 18 of 55
5 3 2 1
 5 4 3 2 1

MAA[12..0]
MAA[12..0] 21 MDA[63..0]
U88G
BA[2..0] 21 MDA[63..0]
(1.8V@200mA +DPE VDD18) BA[2..0] 21
1.8VS DPE_VDD18 DP E/F POWER DP A/B POWER
L57
2 1 1U_0402_6.3V4Z AG15 AE11 DPA_VDD18 U88C
BLM18PG121SN1D_0603 DPE_VDD18#1 NC_DPA_VDD18#1
AG16 DPE_VDD18#2 NC_DPA_VDD18#2 AF11
1 1 1 1.1VS
C661 C662 C663 DPF_VDD10 (1.1V@200mA +DPA VDD10) MDA0 K27 K17 MAA0
L71 MDA1 DQA_0 MAA_0 MAA1
J29 DQA_1 MAA_1 J20
10U_0603_6.3V 0.1U_0402_10V6K AG20 AF6 DPA VDD10 1U 0402 6.3V4Z 2 1 MDA2 H30 H23 MAA2
2 2 2 DPE_VDD10#1 DPA_VDD10#1 BLM18PG121SN1D_0603 MDA3 DQA_2 MAA_2 MAA3
AG21 DPE_VDD10#2 DPA_VDD10#2 AF7 H32 DQA_3 MAA_3 G23
MDA4 MAA4

MEMORY INTERFACE
D 1 1 1 G29 DQA_4 MAA_4 G24 D
C664 C665 C666 MDA5 F28 H24 MAA5
DPE_VDD18 MDA6 DQA_5 MAA_5 MAA6
AG14 DPE_VSSR#1 DPA_VSSR#1 AE1 F32 DQA_6 MAA_6 J19
1.8VS R496 AH14 AE3 0U_0603_6 3V 0.1U_0402_10V6K MDA7 F30 K19 MAA7
DPE_VSSR#2 DPA_VSSR#2 2 2 2 DQA_7 MAA_7
1 2 0 0402 5% 1U 0402 6.3V4Z AM14 DPE_VSSR#3 DPA_VSSR#3 AG1 MDA8 C30 DQA_8 MAA_8 J14 MAA8
1 1 1 AM16 AG6 MDA9 F27 K14 MAA9
C667 C668 C669 DPE_VSSR#4 DPA_VSSR#4 MDA10 DQA_9 MAA_9 MAA10
2 1 AM18 DPE_VSSR#5 DPA_VSSR#5 AH5 A28 DQA_10 MAA_10 J11
@ L72 MDA11 C28 J13 MAA11
BLM18PG121SN1D_0603 10U_0603_6.3V DPF_VDD18 MDA12 DQA_11 MAA_11 MAA12
E27 DQA_12 MAA_12 H11
2 2 2 MDA13 BA2
G26 DQA_13 MAA_13/BA2 G11
AF16 AE13 MDA14 D26 J16 BA0
0.1U_0402_10V6K DPF_VDD18#1 NC_DPB_VDD18#1 MDA15 DQA_14 MAA_14/BA0 BA1
AG17 DPF_VDD18#2 NC_DPB_VDD18#2 AF13 F25 DQA_15 MAA_15/BA1 L15
1.1VS MDA16 A25 DQA_16 DQMA#[7..0] 21
DPF_VDD10 MDA17 C25 E32 DQMA#0
L66 1U_0402_6.3V4Z MDA18 DQA_17 DQMA_0 DQMA#1
E25 DQA_18 DQMA_1 E30
2 1 AF22 AF8 MDA19 D24 A21 DQMA#2
BLM18PG121SN1D_0603 DPF_VDD10#1 DPB_VDD10#1 MDA20 DQA_19 DQMA_2 DQMA#3
AG22 DPF_VDD10#2 DPB_VDD10#2 AF9 E23 DQA_20 DQMA_3 C21
1 1 1 MDA21 F23 E13 DQMA#4
C670 C671 C685 MDA22 DQA_21 DQMA_4 DQMA#5
(1.1V@170mA +DPF VDD10) D22 DQA_22 DQMA_5 D12
AF23 AF10 MDA23 F21 E3 DQMA#6
10U_0603_6.3V 0.1U_0402_10V6K DPF_VSSR#1 DPB_VSSR#1 MDA24 DQA_23 DQMA_6 DQMA#7
AG23 DPF_VSSR#2 DPB_VSSR#2 AG9 E21 DQA_24 DQMA_7 F4
2 2 2 MDA25
AM20 DPF_VSSR#3 DPB_VSSR#3 AH8 D20 DQA_25 QSA[7..0] 21
AM22 AM6 MDA26 F19 H28 QSA0
DPF_VSSR#4 DPB_VSSR#4 MDA27 DQA_26 RDQSA_0 QSA1
AM24 DPF_VSSR#5 DPB_VSSR#5 AM8 A19 DQA_27 RDQSA_1 C27
MDA28 D18 A23 QSA2
MDA29 DQA_28 RDQSA_2 QSA3
F17 DQA_29 RDQSA_3 E19
R497 R498 MDA30 A17 E15 QSA4
150_0402_1% 150_0402_1% MDA31 DQA_30 RDQSA_4 QSA5
C17 DQA_31 RDQSA_5 D10
1 2 AF17 AE10 1 2 (1.8V@20mA +DPA PVDD) MDA32 E17 D6 QSA6
1.8VS DPEF_CALR DPAB_CALR 1.8VS MDA33 DQA_32 RDQSA_6 QSA7
C (1.8V@20mA +DPE PVDD) D16 DQA_33 RDQSA_7 G5 QSA#[7..0] 21
C
DPE_PVDD MDA34 F15
L73 L70 MDA35 DQA_34 QSA#0
A15 DQA_35 WDQSA_0 H27
2 1 1U 0402 6.3V4Z AG18 DP PLL POWER AG8 DPA PVDD 1U 0402 6.3V4Z 2 1 MDA36 D14 A27 QSA#1
BLM18PG121SN1D_0603 DPE_PVDD DPA_PVDD BLM18PG121SN1D_0603 MDA37 DQA_36 WDQSA_1 QSA#2
AF19 DPE_PVSS DPA_PVSS AG7 F13 DQA_37 WDQSA_2 C23
1 1 1 1 1 1 MDA38 A13 C19 QSA#3
C684 C694 C686 DPE_PVDD 10U_0603_6.3V C678 C693 C680 MDA39 DQA_38 WDQSA_3 QSA#4
C13 DQA_39 WDQSA_4 C15
MDA40 E11 E9 QSA#5
10U_0603_6.3V 0.1U_0402_10V6K DPB_PVDD 0.1U_0402_10V6K MDA41 DQA_40 WDQSA_5 QSA#6
AG19 NC_DPF_PVDD DPB_PVDD AG10 A11 DQA_41 WDQSA_6 C5
2 2 2 2 2 2 MDA42 QSA#7
AF20 NC_DPF_PVSS DPB_PVSS AG11 C11 DQA_42 WDQSA_7 H4
MDA43 F11
MDA44 DQA_43 ODTA0
A9 DQA_44 ODTA0 L18 ODTA0 21
MDA45 C9 K16 ODTA1
DQA_45 ODTA1 ODTA1 21
216-0728018 A12 M92-S2 XT FCBGA 0FA MDA46 F9
MDA47 DQA_46 CLKA0
D8 DQA_47 CLKA0 H26 CLKA0 21
(1.8V@20mA +DPB PVDD) 1.8VS MDA48 E7 H25 CLKA0#
DQA_48 CLKA0B CLKA0# 21
1.8VS MDA49 A7
L60 MDA50 DQA_49 CLKA1
L61 (1.8V@120mA +DPLL PVDD) C7 DQA_50 CLKA1 G9 CLKA1 21
1U_0402_6.3V4Z 2 1 MDA51 F7 H9 CLKA1#
DQA_51 CLKA1B CLKA1# 21
1 2 @ 1U 0402 6.3V4Z DPA VDD18 BLM18PG121SN1D_0603 MDA52 A5
MDA53 DQA_52 RASA#0
1 1 1 E5 DQA_53 RASA0B G22 RASA#0 21
@ MCK1608471YZF 0603 1 1 1 C679 C687 C681 MDA54 C3 G17 RASA#1
DQA_54 RASA1B RASA#1 21
C682 C683 C688 MDA55 E1
@ 10U_0603_6.3V6M 0.1U_0402_10V6K MDA56 DQA_55 CASA#0
G7 DQA_56 CASA0B G19 CASA#0 21
@ 0.1U_0402_10V6K 10U_0603_6.3V 2 2 2 MDA57 G6 G16 CASA#1
2 2 2 DQA_57 CASA1B CASA#1 21
MDA58 G1
MDA59 DQA_58 CSA0#
G3 DQA_59 CSA0B_0 H22 CSA0# 21
MDA60 J6 J22
MDA61 DQA_60 CSA0B_1
J1 DQA_61
B MDA62 CSA1# B
J3 DQA_62 CSA1B_0 G13 CSA1# 21
1.8VS MDA63 J5 K13
DQA_63 CSA1B_1
VDD_MEM18_REFD K26 K20 CKEA0
MVREFDA CKEA0 CKEA0 21
VDD_MEM18_REFS J26 J17 CKEA1
1.8VS 1.8VS MVREFSA CKEA1 CKEA1 21
@ 243_0402_1% 1 R499 2 J25 G25 WEA#0
NC_MEM_CALRN0 WEA0B WEA#0 21
@ 243_0402_1% 1 R501 2 K7 H10 WEA#1
Close to K26 Close to J26 NC_MEM_CALRN1 WEA1B WEA#1 21
1

R507 R511 243_0402_1% 1 R502 2 J8 AB16

100_0402_1% 100_0402_1% @ 243_0402_1% 1 R506 MEM_CALRP1 RSVD#1 PAD T38
2 K25 NC_MEM_CALRP0 RSVD#2 G14
G20 PAD T39
RSVD#3 PAD T40
L10
2

DRAM_RST
VDD_MEM18_REFD VDD_MEM18_REFS K8 CLKTESTA
L7 CLKTESTB
1 1
1

C695 C692
R509 0.1U_0402_16V4Z R510 0.1U_0402_16V4Z 216-0728018 A12 M92-S2 XT FCBGA 0FA

1
100_0402_1% 100_0402_1%
2 2
R504 R505
2

4.7K_0402_5% 4.7K_0402_5%

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 19 of 55
5 4 3 2 1
 5 3 2 1

+1.8VS
(1.8V@2200mA) U88E

1U_0402_6.3V4Z 1U_0402_6.3V4Z
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
(1.8V@500mA +PCIE GDDR) AA27 PCIE_VSS#1 GND#1 A3
+1.8VS AB24 A30
1 1 1 1 1 1 PCIE_VSS#2 GND#2

C751

C792

C791

C764

C765

C789

C771

C811

C847

C845
1U_0402_6.3V4Z L92 AB32 AA13
U88D +PCIE GDDR 0.1U 0402 10V6K 1U 0402 6.3V4Z PCIE_VSS#3 GND#3
1 2 AC24 PCIE_VSS#4 GND#4 AA16
1 1 1 1 1 1 MCK2012221YZF 0805 AC26 AB10
1U_0402_6.3V4Z2 2 2 2 2 2 2 2 2 2 PCIE_VSS#5 GND#5

C888

C742

C863

C883

C891

C866

C779

C774
MEM I/O AC27 AB15
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z PCIE PCIE_VSS#6 GND#6
AD25 PCIE_VSS#7 GND#7 AB6
1U_0402_6.3V4Z H13 AB23 10U_0603_6.3V AD32 AC9
1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_10V6K 0.1U 0402_10V6K VDDR1#1 PCIE_VDDR#1 2 2 2 2 2 2 2 2 PCIE_VSS#8 GND#8
H16 VDDR1#2 PCIE_VDDR#2 AC23 AE27 PCIE_VSS#9 GND#9 AD6
D 0.1U 0402_10V6K 1U_0402_6.3V4Z 1U_0402_6.3V4Z D
H19 VDDR1#3 PCIE_VDDR#3 AD24 AF32 PCIE_VSS#10 GND#10 AD8
1 1 1 1 1 1 J10 AE24 1U_0402_6.3V4Z AG27 AE7
VDDR1#4 PCIE_VDDR#4 PCIE_VSS#11 GND#11
C842

C841

C846

C843

C844

C849

C850

C861

C882

C864
J23 VDDR1#5 PCIE_VDDR#5 AE25 AH32 PCIE_VSS#12 GND#12 AG12
J24 VDDR1#6 PCIE_VDDR#6 AE26 K28 PCIE_VSS#13 GND#13 AH10
1U_0402_6.3V4Z J9 AF25 K32 AH28
2 2 2 2 2 2 2 2 2 2 VDDR1#7 PCIE_VDDR#7 +1.1VS PCIE_VSS#14 GND#14
K10 VDDR1#8 PCIE_VDDR#8 AG26 L27 PCIE_VSS#15 GND#15 B10
1U_0402_6.3V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K K23 (1.1V@2000mA +PCIE VDDC) M32 B12
1U_0402_6.3V4Z 0.1U_0402_10V6K VDDR1#9 PCIE_VSS#16 GND#16
K24 VDDR1#10 N25 PCIE_VSS#17 GND#17 B14
K9 L23 1U 0402 6.3V4Z 1U 0402 6.3V4Z 1U 0402 6.3V4Z 10U 0603_6.3V N27 B16
VDDR1#11 PCIE_VDDC#1 PCIE_VSS#18 GND#18
1 1 L11 VDDR1#12 PCIE_VDDC#2 L24 1 1 1 1 P25 PCIE_VSS#19 GND#19 B18
C848

C736

C744

C797

C748

C806

C783

C738

C754

C780

C878

C879

C804
10U_0603_6.3V L12 L25 P32 B20
VDDR1#13 PCIE_VDDC#3 PCIE_VSS#20 GND#20
L13 VDDR1#14 PCIE_VDDC#4 L26 R27 PCIE_VSS#21 GND#21 B22
L20 VDDR1#15 PCIE_VDDC#5 M22 T25 PCIE_VSS#22 GND#22 B24
2 2 2 2 2 2 2 2 2 2 2 2 2
L21 VDDR1#16 PCIE_VDDC#6 N22 T32 PCIE_VSS#23 GND#23 B26
10U_0603_6.3V 10U_0603_6.3V 0U_0603_6.3V L22 N23 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z U25 B6
10U_0603_6.3V VDDR1#17 PCIE_VDDC#7 PCIE_VSS#24 GND#24
PCIE_VDDC#8 N24 U27 PCIE_VSS#25 GND#25 B8
+1.8VS +VDDC_CT R22 +VGA_CORE V32 C1
PCIE_VDDC#9 PCIE_VSS#26 GND#26
PCIE_VDDC#10 T22 W25 PCIE_VSS#27 GND#27 C32
LEVEL U22 (+VGA CORE@9000mA +VDDC) W26 E28
L78 10U_0603_6.3V TRANSLATION PCIE_VDDC#11 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z PCIE_VSS#28 GND#28
(1.8V@136mA +VDDC CT) PCIE_VDDC#12 V22 W27 PCIE_VSS#29 GND#29 F10
2 1 AA20 1U 0402 6.3V4Z 1U 0402 6.3V4Z 1U 0402 6.3V4Z 1U 0402 6.3V4Z Y25 F12
BLM18PG121SN1D_0603 1 VDD_CT#1 PCIE_VSS#30 GND#30
1 AA21 VDD_CT#2 Y32 PCIE_VSS#31 GND#31 F14
C753

C800

C877

C865

C737

AB20 VDD_CT#3 VDDC#1 AA15 1 1 1 1 1 1 1 GND#32 F16

C805

C798

C763

C788

C787

C801

C739

C784

C772

C786

C862

C885

C884
AB21 CORE N15 + C766 F18
VDD_CT#4 VDDC#2 330U_D2E_2.5VM_R9 GND#33
VDDC#3 N17 GND#34 F2
2 2 2 2 2
VDDC#4 R13 GND#35 F20
+3.3V_DELAY 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_10V6K I/O 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VDDC#5 R16 M6 GND#56 GND#36 F22
1U_0402_6.3V4Z AA17 R18 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z N11 F24
VDDR3#1 VDDC#6 1U_0402_6.3V4Z 1U_0402_6.3V4Z GND#57 GND#37
AA18 VDDR3#2 VDDC#7 R21 N12 GND#58 GND#38 F26
10U_0603_6.3V 1U_0402_6.3V4Z AB17 T12 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z N13 F6
VDDR3#3 VDDC#8 1U 0402 6.3V4Z 1U 0402 6.3V4Z 1U 0402 6.3V4Z GND#59 GND#39
AB18 T15 N16 F8
1 1 VDDR3#4 VDDC#9 GND#60
GND GND#40
C777

C793

C752

C740

1 @ 2 T17 N18 G10

C 18 TESTEN VDDC#10 GND#61 GND#41 C
R5180_0402_5% T20 1 1 1 1 1 1 1 1U_0402_6.3V4Z N21 G27
VDDC#11 GND#62 GND#42

C869

C872

C867

C868

C887

C871

C870

C889

C749

C741

C747

C775

C808
1 2 U11 VDDR5#1 VDDC#12 U13 P6 GND#63 GND#43 G31
2 2 2 2 R517 0_0402_5% U12 VDDR5#2 VDDC#13 U16 P9 GND#64 GND#44 G8
1U_0402_6.3V4Z 1U_0402_6.3V4Z V11 U18 R12 H14
+VDDR5 VDDR5#3 VDDC#14 2 2 2 2 2 2 2 2 2 2 2 2 2 GND#65 GND#45
V12 VDDR5#4 VDDC#15 U21 R15 GND#66 GND#46 H17

POWER
(3.3V@60mA VDDR3) V15 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z R17 H2
VDDC#16 1U_0402_6.3V4Z 1U_0402_6.3V4Z GND#67 GND#47
VDDC#17 V17 R20 GND#68 GND#48 H20
+VDDR4 AA11 V20 10U 0603 6.3V T13 H6
VDDR4#1 VDDC#18 GND#69 GND#49
AA12 VDDR4#2 VDDC#19 V21 T16 GND#70 GND#50 J27
Y11 Y13 10U_0603_6.3V 1 1 1 1 10U_0603_6.3V T18 J31
VDDR4#3 VDDC#20 GND#71 GND#51

C886

C874

C873

C875

C782

C785

C799
Y12 VDDR4#4 VDDC#21 Y16 T21 GND#72 GND#52 K11
+1.8VS Y18 T6 K2
L75 VDDC#22 GND#73 GND#53
VDDC#23 Y21 U15 GND#74 GND#54 K22
+VDDRHA 1U 0402 6.3V4Z 1U 0402 6.3V4Z MEM CLK 2 2 2 2 2 2 2
2 1 U17 GND#75 GND#55 K6
BLM18PG121SN1D_0603 1 1 L17 10U_0603_6.3V 10U_0603_6.3V U20
VDDRHA GND#76
C790

C781

10U_0603_6.3V 10U_0603_6.3V U3
ISOLATED GND#77
L16 VSSRHA U9 GND#78
CORE I/O V13
+1.8VS 2 2 GND#79
VDDCI#1 M13 V16 GND#80
L93 PLL M15 V18
1U 0402 6.3V4Z +PCIE PVDD VDDCI#2 GND#81
2 1 AM30 PCIE_PVDD VDDCI#3 M16 V6 GND#82
BLM18PG121SN1D_0603 1 M17 Y10 A32
VDDCI#4 GND#83 VSS_MECH#1
C743

C755

C802

(1.8V@180mA PCIE PVDD) VDDCI#5 M18 Y15 GND#84 VSS_MECH#2 AM1

L8 NC_MPV18 VDDCI#6 M20 Y17 GND#85 VSS_MECH#3 AM32
VDDCI#7 M21 Y20 GND#86
+VGA_CORE 2 2 2
VDDCI#8 N20 Y6 GND#87
10U_0603_6.3V 0.1U_0402_10V6K H7
L90 NC_SPV18
(+VGA CORE@2000mA +VDDCI)
1 2 1U 0402 6.3V4Z +SPV10 H8 +VDDCI 1U 0402 6.3V4Z 10U 0603 6.3V 1 2
MCK1608471YZF 0603 SPV10 L76 216-0728018 A12 M92-S2 XT FCBGA 0FA
(0.95-1.1V@35mA SPV10) J7 1 1 1 1 MCK2012221YZF 0805
SPVSS
C750

C803

C807

C767

C745

C746

C778

C890

C876
B B

2 2 2 BACK BIAS 2 2 2 2 2 2 +VGA_CORE +VGA_BBP +1.8VS

10U_0603 6.3V 0.1U_0402_10V6K M11 1U_0402_6.3V4Z 1U_0402_6.3V4Z 10U_0603_6.3V 10U_0603_6.3V
BBP#1
M12 BBP#2
+VGA_BBP 1U 0402 6.3V4Z @
1 1 2 1
C773

C770

L91 BLM18PG121SN1D_0603
216-0728018 A12 M92-S2 XT FCBGA 0FA 2
1U_0402_6.3V4Z
2 2 C810

1
0.1U_0402_10V6K D

(1.8V@170mA +VDDR4) 2 2
+3.3V_DELAY Q41 +1.8VS G

2N7002DW-T/R7_SOT363-6
Q42A

SI2301BDS_SOT23
Q43
1U 0402 6.3V4Z +VDDR4 S

3
S

1 3 1 1
D

+3VS
C795

C796

C776

L94
SI2301BDS_SOT23 2 1
2

R520 BLM18PG121SN1D_0603
G
2

100K_0402_5% 2 2 2
10U_0603_6.3V 0.1U_0402_10V6K +5VS
(1.8V@170mA +VDDR5)
+1.8VS 2 1
1

3
1U 0402 6.3V4Z +VDDR5 R522 100K_0402_5%
1 1
C761

C769

C809

L79
2 1 BB EN 5
18 BB_EN
1

D BLM18PG121SN1D_0603 2N7002DW-T/R7_SOT363-6

1
Q44 2 2 2 Q42B
+3VS 1 2 2

4
R521 150K_0402_5% G 10U_0603_6.3V 0.1U_0402_10V6K R523
A S 2N7002_SOT23-3 10K_0402_5% A
3

2
C794
0.1U_0402_10V6K
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date Thursday, March 18, 2010 Sheet 20 of 55
5 3 2 1
 5 3 2 1

U31 U32
BA0 L2 B9 MDA20 BA0 L2 B9 MDA5 U33 U34
BA1 BA0 DQ15 MDA21 BA1 BA0 DQ15 MDA4 BA0 MDA45 BA0 MDA48
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1 L2 BA0 DQ15 B9 L2 BA0 DQ15 B9
D9 MDA17 D9 MDA6 BA1 L3 B1 MDA42 BA1 L3 B1 MDA53
MAA12 DQ13 MDA23 MAA12 DQ13 MDA3 BA1 DQ14 MDA47 BA1 DQ14 MDA49
R2 A12 DQ12 D1 R2 A12 DQ12 D1 DQ13 D9 DQ13 D9
MAA11 P7 D3 MDA22 Group2 MAA11 P7 D3 MDA0 Group0 MAA12 R2 D1 MDA41 MAA12 R2 D1 MDA55
MAA10 A11 DQ11 MDA19 MAA10 A11 DQ11 MDA7 MAA11 A12 DQ12 MDA40 MAA11 A12 DQ12 MDA52
M2 A10/AP DQ10 D7 M2 A10/AP DQ10 D7 P7 A11 DQ11 D3 Group5 P7 A11 DQ11 D3 Group6
MAA9 P3 C2 MDA16 MAA9 P3 C2 MDA2 MAA10 M2 D7 MDA46 MAA10 M2 D7 MDA50
MAA8 A9 DQ9 MDA18 MAA8 A9 DQ9 MDA1 MAA9 A10/AP DQ10 MDA44 MAA9 A10/AP DQ10 MDA54
P8 A8 DQ8 C8 P8 A8 DQ8 C8 P3 A9 DQ9 C2 P3 A9 DQ9 C2
MAA7 P2 F9 MDA8 MAA7 P2 F9 MDA30 MAA8 P8 C8 MDA43 MAA8 P8 C8 MDA51
MAA6 A7 DQ7 MDA10 MAA6 A7 DQ7 MDA26 MAA7 A8 DQ8 MDA34 MAA7 A8 DQ8 MDA60
N7 A6 DQ6 F1 N7 A6 DQ6 F1 P2 A7 DQ7 F9 P2 A7 DQ7 F9
MAA5 N3 H9 MDA9 MAA5 N3 H9 MDA29 MAA6 N7 F1 MDA35 MAA6 N7 F1 MDA61
MAA4 A5 DQ5 MDA15 MAA4 A5 DQ5 MDA25 MAA5 A6 DQ6 MDA37 MAA5 A6 DQ6 MDA56
N8 A4 DQ4 H1 N8 A4 DQ4 H1 N3 A5 DQ5 H9 N3 A5 DQ5 H9
MAA3 N2 H3 MDA11 Group1 MAA3 N2 H3 MDA24 Group3 MAA4 N8 H1 MDA36 MAA4 N8 H1 MDA62
MAA2 A3 DQ3 MDA12 MAA2 A3 DQ3 MDA28 MAA3 A4 DQ4 MDA33 MAA3 A4 DQ4 MDA58
D
M7 A2 DQ2 H7 M7 A2 DQ2 H7 N2 A3 DQ3 H3 Group4 N2 A3 DQ3 H3 Group7 D
MAA1 M3 G2 MDA13 MAA1 M3 G2 MDA27 MAA2 M7 H7 MDA39 MAA2 M7 H7 MDA57
MAA0 A1 DQ1 MDA14 MAA0 A1 DQ1 MDA31 MAA1 A2 DQ2 MDA32 MAA1 A2 DQ2 MDA59
M8 A0 DQ0 G8 M8 A0 DQ0 G8 M3 A1 DQ1 G2 M3 A1 DQ1 G2
MAA0 M8 G8 MDA38 MAA0 M8 G8 MDA63
A0 DQ0 A0 DQ0
CLKA0# K8 A9 +1.8VS CLKA0# K8 A9 +1.8VS
CLKA0 J8 CK VDDQ1 CLKA0 J8 CK VDDQ1 CLKA1# K8 CLKA1#
CK VDDQ2 C1 CK VDDQ2 C1 CK VDDQ1 A9 +1.8VS K8 CK VDDQ1 A9 +1.8VS
C3 C3 CLKA1 J8 C1 CLKA1 J8 C1
CKEA0 VDDQ3 CKEA0 VDDQ3 CK VDDQ2 CK VDDQ2
K2 CKE VDDQ4 C7 K2 CKE VDDQ4 C7 VDDQ3 C3 VDDQ3 C3
C9 C9 CKEA1 K2 C7 CKEA1 K2 C7
VDDQ5 VDDQ5 CKE VDDQ4 CKE VDDQ4
VDDQ6 E9 VDDQ6 E9 VDDQ5 C9 VDDQ5 C9
VDDQ7 G1 VDDQ7 G1 VDDQ6 E9 VDDQ6 E9
CSA0# L8 G3 CSA0# L8 G3 G1 G1
CS VDDQ8 CS VDDQ8 CSA1# VDDQ7 CSA1# VDDQ7
VDDQ9 G7 VDDQ9 G7 L8 CS VDDQ8 G3 L8 CS VDDQ8 G3
WEA#0 K3 G9 WEA#0 K3 G9 G7 G7
WE VDDQ10 WE VDDQ10 WEA#1 VDDQ9 WEA#1 VDDQ9
K3 WE VDDQ10 G9 K3 WE VDDQ10 G9
RASA#0 K7 A1 RASA#0 K7 A1
RAS VDD1 RAS VDD1 RASA#1 RASA#1
VDD2 E1 VDD2 E1 K7 RAS VDD1 A1 K7 RAS VDD1 A1
CASA#0 L7 J9 CASA#0 L7 J9 E1 E1
CAS VDD3 CAS VDD3 CASA#1 VDD2 CASA#1 VDD2
VDD4 M9 VDD4 M9 L7 CAS VDD3 J9 L7 CAS VDD3 J9
DQMA#1 F3 R1 DQMA#3 F3 R1 M9 M9
DQMA#2 B3 LDM VDD5 DQMA#0 LDM VDD5 DQMA#4 F3 VDD4 DQMA#7 VDD4
UDM B3 UDM LDM VDD5 R1 F3 LDM VDD5 R1
J1 0.1U 0402 16V4Z +1.8VS J1 0.1U 0402 16V4Z +1.8VS DQMA#5 B3 DQMA#6 B3
VDDL VDDL UDM 0.1U 0402 16V4Z UDM 0.1U 0402 16V4Z
VSSDL J7 1 1 VSSDL J7 1 1 VDDL J1 +1.8VS VDDL J1 +1.8VS
ODTA0 K9 ODTA0 K9 J7 1 1 J7 1 1
ODT C812 C831 ODT C826 C897 ODTA1 VSSDL ODTA1 VSSDL
K9 ODT K9 ODT
C822 C892 C839
QSA1 2 2 1U_0402_6.3V4Z QSA3 2 2 1U_0402_6.3V4Z C981 1U_0402_6.3V4Z
F7 LDQS F7 LDQS
QSA#1 QSA#3 QSA4 2 2 1U_0402_6.3V4Z QSA7 2 2
E8 LDQS VSSQ1 A7 E8 LDQS VSSQ1 A7 F7 LDQS F7 LDQS
B2 B2 QSA#4 E8 A7 QSA#7 E8 A7
VSSQ2 VSSQ2 LDQS VSSQ1 LDQS VSSQ1
VSSQ3 B8 VSSQ3 B8 VSSQ2 B2 VSSQ2 B2
VSSQ4 D2 VSSQ4 D2 VSSQ3 B8 VSSQ3 B8
QSA2 B7 D8 QSA0 B7 D8 D2 D2
C QSA#2 UDQS VSSQ5 QSA#0 UDQS VSSQ5 QSA5 VSSQ4 QSA6 VSSQ4 C
A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7 B7 UDQS VSSQ5 D8 B7 UDQS VSSQ5 D8
F2 F2 QSA#5 A8 E7 QSA#6 A8 E7
VSSQ7 VSSQ7 UDQS VSSQ6 UDQS VSSQ6
VSSQ8 F8 VSSQ8 F8 VSSQ7 F2 VSSQ7 F2
+VRAM REF1 J2 H2 +VRAM REF2 J2 H2 F8 F8
VREF VSSQ9 VREF VSSQ9 +VRAM REF3 J2 VSSQ8 +VRAM REF4 VSSQ8
VSSQ10 H8 VSSQ10 H8 VREF VSSQ9 H2 J2 VREF VSSQ9 H2
A2 NC#A2 A2 NC#A2 VSSQ10 H8 VSSQ10 H8
E2 NC#E2 VSS1 A3 E2 NC#E2 VSS1 A3 A2 NC#A2 A2 NC#A2
BA2 L1 E3 BA2 L1 E3 E2 A3 E2 A3
NC#L1 VSS2 NC#L1 VSS2 BA2 NC#E2 VSS1 BA2 NC#E2 VSS1
R3 NC#R3 VSS3 J3 R3 NC#R3 VSS3 J3 L1 NC#L1 VSS2 E3 L1 NC#L1 VSS2 E3
R7 NC#R7 VSS4 N1 R7 NC#R7 VSS4 N1 R3 NC#R3 VSS3 J3 R3 NC#R3 VSS3 J3
R8 NC#R8 VSS5 P9 R8 NC#R8 VSS5 P9 R7 NC#R7 VSS4 N1 R7 NC#R7 VSS4 N1
R8 NC#R8 VSS5 P9 R8 NC#R8 VSS5 P9

HYB18T256161BF-25 HYB18T256161BF-25
VRAM@ VRAM@ HYB18T256161BF-25 HYB18T256161BF-25
VRAM@ VRAM@

+1.8VS +1.8VS +1.8VS

+1.8VS
1

CLKA1 BA[2..0]
19 CLKA1 BA[2..0] 19
1

1
R529
R524 R526 4.99K_0402_1% R527 CLKA1# QSA[7..0]
19 CLKA1# QSA[7..0] 19
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%

1
QSA#[7..0]
QSA#[7..0] 19
2

R532 R536
2

2
+VRAM_REF1 +VRAM_REF2 +VRAM_REF3 +VRAM_REF4 56_0402_5% 56_0402_5% DQMA#[7..0]
DQMA#[7..0] 19
1

1
1 1 1 MAA[12..0]
MAA[12..0] 19

2
R531 R533 R530 R538
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% MDA[63..0]
B C814 C980 C840 C828 MDA[63..0] 19 B
2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
2

2
ODTA0
ODTA0 19
C819
470P_0402_50V7K CKEA0
2 CKEA0 19
RASA#0
RASA#0 19
CASA#0
CASA#0 19
WEA#0
+1.8VS +1.8VS WEA#0 19
CSA0#
CSA0# 19
10U 0603 6.3V6M 0.1U 0402 16V4Z 0.1U 0402 16V4Z 0.01U_0402_16V7K 10U 0603 6.3V6M 0.1U 0402 16V4Z 0.1U 0402 16V4Z 0.01U_0402_16V7K
ODTA1
ODTA1 19
1 1 1 1 1 1 1 1 1
CLKA0 CKEA1
19 CLKA0 CKEA1 19
C823 C835 C912 C830 C837 C894 C820 C895 C817 C825 C832 C926 C911 C829 C838 C985
CLKA0# RASA#1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 19 CLKA0# RASA#1 19

1
10U_0603_6.3V6M 10U_0603_6.3V6M CASA#1
CASA#1 19
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R535 R537
56_0402_5% 56_0402_5% WEA#1
+1.8VS WEA#1 19
CSA1#
CSA1# 19

2
10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K

1 1 1 1
+1.8VS
1
C833 C813 C827 C987 C896 C821 C818 C824 C913
10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 470P_0402_50V7K
2 2 2 2 2 2 2 2
A 10U_0603_6.3V6M 2 A
1 1 1 1 1
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C986 C836 C972 C816 C898 C893 C815 C834
2 2 2 2 2 2 2 2
10U_0603_6.3V6M
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDEN IAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date Thursday, March 18, 2010 Sheet 21 of 55
5 3 2 1
 5 4 3 2 1

STRAPS 3.3V_DELAY CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
18 GPU_GPIO0 GPU_GPIO0 R539 2 1 10K_0402_5%
18 GPU_GPIO1 GPU_GPIO1 R542 2 1 10K_0402_5%
18 GPU_GPIO2 GPU_GPIO2 R541 2 1 10K_0402_5% STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS RECOMMENDED SETTINGS
18 SOUT_GPIO8 SOUT_GPIO8 @ R579 2 1 10K_0402_5%

TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING 1

D 18 GPU_GPIO9 GPU GPIO9 @ R540 2 1 10K 0402 5% D
18 GPU_GPIO11 GPU GPIO11 R577 2 1 10K 0402 5%
18 GPU_GPIO12 GPU GPIO12 @ R581 2 1 10K 0402 5% TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 1
GPU GPIO13 @ R543 10K 0402 5%
18 GPU_GPIO13 2 1 VSYNC_DAC1 and HSYNC_DAC1
pull up to HDMI & DISPLAYPORT BIF_GEN2_EN_A GPIO2 PCIE GNE2 ENABLED 1
9/1 For PVT AUDIO funciton
18,29 VGA_CRT_VSYNC @ R570 2 1 10K 0402 5%
18,29 VGA_CRT_HSYNC @ R574 2 1 10K 0402 5% BIF_CLK_PM_EN GPIO8 BIF_CLK_PM_EN 0
18 VSYNC_DAC2 @ R569 2 1 10K 0402_5%
18 HSYNC_DAC2 @ R573 2 1 10K_0402_5%
BIF_VGA DIS GPIO9 VGA ENABLED 0

GPIO5_AC_BATT TEST 0
3.3V_DELAY BIF_RX_PLL_CALIB_BP GPIO21

BIOS_ROM_EN GPIO_22_ROMCSB 1
1

R576
10K_0402_5% ROMIDCFG(2:0) GPIO[13:11] BIF_RX_PLL_CALIB_BP 0 0 1
2

3.3V_DELAY VIP_DEVICE_STRAP_ENA V2SYNC ENABLE EXTERNAL BIOS ROM 0

R572
10K_0402_5%
SMS_EN_HARD H2SYNC SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT 0
2

IGNORE VIP DEVICE STRAPS

C CCBYPASS GENERICC 0 C
EC SMB CK2 PX 6 1 EC_SMB_CK2 8,34
AUD[1] AUD[0]
5

Q45A AUD[1] HSYNC 0 0 No audio function

2N7002DW-T/R7_SOT363-6 0 1 Audio for DisplayPort and HDMI if dongle is detected XX
EC_SMB_DA2_PX 3 4 AUD[0] VSYNC 1 0 Audio for DisplayPort only
EC_SMB_DA2 8,34
1 1 Audio for both DisplayPort and HDMI
Q45B
2N7002DW-T/R7_SOT363-6

3.3V_DELAY
AMD RESERVED CONFIGURATION STRAPS
VGA Thermal Sensor ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
2 THEY MUST NOT CONFLICT DURING RESET
C988

0.1U_0402_16V4Z
Closed to GPU H2SYNC GENERICC
1
U38
1 8 EC SMB CK2 PX PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
VCC SMBCLK
18 GPU_THERMAL_D 2 7 EC SMB DA2 PX THEY MUST NOT CONFLICT DURING RESET
C989 2200P_0402_50V7K DXP SMBDATA
1 2 3 DXN ALERT 6 THM_ALERT# 18
GPIO_28_TDO GPIO21_BB_EN
4 5 3.3V_DELAY
18 GPU_THERMAL_D- THERM GND
B B
1 2
G781-1_SOP8 R580 4.7K_0402_5%

Change to SA007810210
STRAPS PIN GPU Project VRAM size Vendor Part Number# Compal Part Number# VRAM ID 3,2,1,0
Address 1001 101X b 512MB(x4) Hynix 64Mx16 1.8V SA00002UH20 0001
512MB(x4) ATI 64Mx16 1 8V SA00003LT10 0010
2 1 1.8VS 2 1 1 8VS
R575 @ 10K_0402_5% R571 @ 10K_0402_5% M92 S2-XT 512MB(x4) Samsung 64Mx16 1 8V (E-die) SA000031O10 0100
VRAM_ID0 18 VRAM_ID1 18
2 1 2 1
R593 @ 10K_0402_5% R590 @ 10K_0402_5% DVPDATA
VRAM_ID0=VRAM_ID0_0 VRAM_ D[3:0] (3,2,1,0)
VRAM_ID1=VRAM_ID1_1
VRAM_ID2=VRAM_ID2_2
VRAM_ID3=VRAM_ID3_3

2 1 1.8VS 2 1 1.8VS
R567 @ 10K_0402_5% R568 @ 10K_0402_5%
VRAM_ID2 18 VRAM_ID3 18
A A
2 1 2 1
R591 @ 10K_0402_5% R592 @ 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 22 of 55
5 4 3 2 1
 5 4 3 2 1

U10A

A_RST# N2
SB700 P4
A_RST# PCICLK0
Part 1 of 5 PCICLK1 P3

PCI CLKS
C172 1 2 0.1U_0402_16V7K SB_RX0P_C V23 P1 1 2 A_RST#
12 SB_RX0P PCIE_TX0P PCICLK2 PCI_CLK2 27
C246 1 2 0.1U_0402_16V7K SB_RX0N_C V22 P2 R135 @ 8.2K_0402_5%
12 SB_RX0N PCIE_TX0N PCICLK3 PCI_CLK3 27
C402 1 2 0.1U_0402_16V7K SB_RX1P_C V24 T4 Strap pin
12 SB_RX1P PCIE_TX1P PCICLK4 PCI_CLK4 27
C176 1 2 0.1U_0402_16V7K SB_RX1N_C V25 T3
12 SB_RX1N PCIE_TX1N PCICLK5/GPIO41 PCI_CLK5 27
C183 1 2 0.1U_0402_16V7K SB_RX2P_C U25
12 SB_RX2P PCIE_TX2P
C186 1 2 0.1U_0402_16V7K SB_RX2N_C U24
12 SB_RX2N PCIE_TX2N
C204 1 2 0.1U_0402_16V7K SB_RX3P_C T23
12 SB_RX3P PCIE_TX3P 3VALW
C214 1 2 0.1U 0402 16V7K SB RX3N C T22 N1
12 SB_RX3N PCIE_TX3N PCIRST# C177

PCI EXPRESS INTERFACE

D 12 SB_TX0P U22 PCIE_RX0P 2 1 D
12 SB_TX0N U21 PCIE_RX0N AD0 U2

5
12 SB_TX1P U19 P7 0.1U_0402_16V4Z U11
PCIE_RX1P AD1
12 SB_TX1N V19 V4 2

P
PCIE_RX1N AD2 B PLT RST#
12 SB_TX2P R20 PCIE_RX2P AD3 T1 Y 4 PLT_RST# 13,15,17,31,34,37
12 SB_TX2N R21 V3 A RST# 1
PCIE_RX2N AD4 A

G
12 SB_TX3P R18 PCIE_RX3P AD5 U1

1
12 SB_TX3N R17 V1 NC7SZ08P5X_NL_SC70-5

3
PCIE_RX3N AD6 R293
AD7 V2
R127 2 1 562_0402_1% T25 T2
R131 2.05K_0402_1% T24 PCIE_CALRP AD8 100K_0402_5%
PCIE_VDDR 2 1 PCIE_CALRN AD9 W1
T9 2 1

2
SB_PCIEVDD AD10 R134 @ 33_0402_5%
1.2V_HT 1 2 <43mA> P24 PCIE_PVDD AD11 R6
L59 2 1 R7
MBC1608121YZF_0603 C468 C472 AD12
P25 PCIE_PVSS AD13 R5
AD14 U8
1U_0402_6.3V4Z U5
2.2U_040 1_6.3V6M 2 AD15
AD16 Y7
AD17 W8
AD18 V9
Y8 @ R101 20M_0402_5%
AD19
AD20 AA8 1 2
AD21 Y4
AD22 Y3 C203
Y2 PCI AD23
AD23 PCI_AD23 27
AA2 PCI AD24 1 2 SB 32KHI
AD24 PCI_AD24 27
AB4 PCI AD25
AD25 PCI_AD25 27 Y2
N25 AA1 PCI AD26 18P_0402_50V8J
16 CLK_SBSRC_BCLK PCIE_RCLKP/NB_LNK_CLKP AD26 PCI_AD26 27

1
N24 AB3 PCI AD27 4 3
16 CLK_SBSRC_BCLK# PCIE_RCLKN/NB_LNK_CLKN AD27 PCI_AD27 27 OUT NC
C AB2 PCI AD28 R91 C
AD28 PCI_AD28 27
K23 AC1 20M_0603_5% 1 2
NB_DISP_CLKP AD29 IN NC
K22 NB_DISP_CLKN AD30 AC2
AD1 C403

2
AD31 32.768KHZ_12.5P_MC-306
M24 W2

PCI NTERFACE
NB_HT_CLKP CBE0# SB_32KHO
M25 NB_HT_CLKN CBE1# U7 1 2
CBE2# AA7
P17 Y1 18P_0402_50V8J
CPU_HT_CLKP CBE3#
M18 CPU_HT_CLKN FRAME# AA6
DEVSEL# W5 Close to SB
M23 SLT_GFX_CLKP IRDY# AA5
M22 SLT_GFX_CLKN TRDY# Y5
PAR U6
J19 GPP_CLK0P STOP# W6
J18 W4 3VS
GPP_CLK0N PERR# 1.8VS
SERR# V7

2
L20 GPP_CLK1P REQ0# AC3
L19 AD4 R41
GPP_CLK1N REQ1#
REQ2# AB7 4.7K_0402_5%
M19 GPP_CLK2P REQ3#/GPIO70 AE6

2
G
M20 AB6

1
GPP_CLK2N REQ4#/GPIO71
GNT0# AD2
CLOCK GENERATOR

N22 AE4 H PWRGD 3 1

GPP_CLK3P GNT1# H_PWRGD_L 53

D
External 14MHz for SB710 P22 GPP_CLK3N GNT2# AD5
Q2 FDV301N_NL_SOT23-3
GNT3#/GPIO72 AC6
16 CLK_14M_SB L18 25M_48M_66M_OSC GNT4#/GPIO73 AE5
AD6 PM CLKRUN# R 1 2 PM_CLKRUN# 34 R13 0_0402_5%
CLKRUN#
1

V5 R149 0_0402_5% 1 2
R635 LOCK# @
J21 25M_X1
B @ 10_0402_5% B
INTE#/GPIO33 AD3
INTF#/GPIO34 AC4 level shift to ISL6265
AE2
2

INTG#/GPIO35
1 J20 25M_X2 INTH#/GPIO36 AE3
C690
@ 22P_0402_50V8J G22 CLK_LPC_EC R108 1 2 22_0402_5% CLK_PCI_EC
2 LPCCLK0 CLK_PCI_EC 27,34
SB_32KHI A3
LPCCLK1 E22
H24
LPCCLK1 27 STRAP PIN
X1 LAD0 LPC_AD0 34
LAD1 H23 LPC_AD1 34
For EMI request LAD2 J25 LPC_AD2 34
J24
RTC XTAL

LAD3 LPC_AD3 34
LPC

SB_32KHO B3 H25
X2 LFRAME# LPC_FRAME# 34
LDRQ0# H22
LDRQ1#/GNT5#/GPIO68 AB8
BMREQ#/REQ5#/GPIO65 AD7
SERIRQ V15 SERIRQ 34
F23
STRAP PIN
13 ALLOW_LDTSTOP ALLOW_LDTSTP
F24 C3 RTC_CLK 27 RTCVCC RTCBATT
8 H_PROCHOT_R# PROCHOT# RTCCLK
F22 C2 1 @ 2 RTCVCC
8 H_PWRGD LDT_PG INTRUDER_ALERT# R107 1M_0402_5%
CPU

8,13 LDT_STOP# G25 LDT_STP# VBAT B2 D5

G24 R556 1K_0402_5%
8 LDT_RST# LDT_RST#
1 2 2 1 3
R C

R385 510_0402_5%
C405 1 1 C134

0.1U_0402_16V4Z
W=20mils 1
0.1U_0402_16V4Z

1U_0402_6.3V4Z

218S7EALA11FG_BGA528_SB710 1
LDT_PG: OD pin @ R379 C339 2
A 0_0603_5% A
2 2
SB710 Ver:A14 <SA000030740> for Clear CMOS 2 BAS40-04_SOT23-3

CHGRTC

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 23 of 55
5 4 3 2 1
 5 4 3 2 1

For EMI request.

U10D @
1 @ 2 1 2
Part 4 of 5 R124 33_0402_5% C269 22P_0402_50V8J
E1
SB700
34 EC_SWI# PCI_PME#/GEVENT4#
E2 RI#/EXTEVNT0# USBCLK/14M_25M_48M_OSC C8 CLK_48M_USB 16
CRT_DET_R H7
3VS SLP_S2/GPM9# USB RCOMP 1
34 PM_SLP_S3# F5 SLP_S3# USB_RCOMP G8 2
G1 R390 11.8K_0402_1%
34 PM_SLP_S5# SLP_S5#

ACPI / WAKE UP EVENTS

USB MISC
D 34 PBTN_OUT# H2 PWR_BTN# D
R395 1 2 4.7K 0402 5% SUS STAT# L H1
39 SB_PWRGD PWR_GOOD
SUS STAT# 1 2 SUS STAT# L K3
13 SUS_STAT# SUS_STAT#
R409 1 2 2.2K 0402 5% SB CK SCLK R555 0_0402_5% TP10 H5 E6
TP11 TEST2 USB_FSD13P
H4 TEST1 USB_FSD13N E7
R399 1 2 2.2K 0402 5% SB CK SDAT TP12 H3 OHCI4 Disable
TEST0

USB 1.1
34 EC_GA20 Y15 GA20IN/GEVENT0# USB_FSD12P F7
34 EC_KBRST# W15 KBRST#/GEVENT1# USB_FSD12N E8
34 EC_SCI# K4 LPC_PME#/GEVENT3#
34 EC_SMI# K24 LPC_SMI#/EXTEVNT1# USB_HSD11P H11
3VALW F1 J10
T15 S3_STATE/GEVENT5# USB_HSD11N
J2 SYS_RESET#/GPM7#
37 SB_PCIE_WAKE# H6 WAKE#/GEVENT8# USB_HSD10P E11
F2 BLINK/GPM6# USB_HSD10N F11
R525 1 @ 2 100K_0402_5% EC_LID_OUT# H_THERMTRIP# J6
8 H_THERMTRIP# SMBALERT#/THRMTRIP#/GEVENT2#
NB_PWRGD W14 A11
13 NB_PWRGD NB_PWRGD USB_HSD9P
R415 1 2 10K_0402_5% SB_PCIE_WAKE# B11
RSMRST# USB_HSD9N
34 RSMRST# D3 RSMRST# EHCI1 Disable
USB_HSD8P C10
USB_HSD8N D10

AE18 SATA_IS0#/GPIO10 USB_HSD7P G11

3VS 1 2 AD18 CLK_REQ3#/SATA_IS1#/GPIO6 USB_HSD7N H12
R393 2 @ 1 10K 0402 5% HDA SDIN0 SKU ID: DIS R404 2.2K_0402_5% AA19
@ SKUID SMARTVOLT1/SATA_IS2#/GPIO4
Combine NAL00 SW code 1 2 W17 CLK_REQ0#/SATA_IS3#/GPIO0 USB_HSD6P E12
R116 2 @ 1 10K 0402 5% HDA BITCLK R410 2.2K_0402_5% V17 E14
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 USB_HSD6N
W20 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
41 SB_SPKR W21 C12 USB20 P5

USB 2.0
SPKR/GPIO2 USB_HSD5P USB20_P5 37
10,11,16,37 SB_CK_SCLK SB CK SCLK AA18 D12 USB20 N5 MiniCard1(WLAN)
SCL0/GPOC0# USB_HSD5N USB20_N5 37
C CLK Gen, WLAN, DDR 10,11,16,37 SB_CK_SDAT SB CK SDAT W18 C
SDA0/GPOC1# USB20 P4
K1 SCL1/GPOC2# USB_HSD4P B12 USB20_P4 33
K2 A12 USB20 N4 Card Reader S3 Power off
SDA1/GPOC3# USB_HSD4N USB20_N4 33
AA20 DDC1_SCL/GPIO9

GPIO
Y18 G12 USB20 P3
DDC1_SDA/GPIO8 USB_HSD3P USB20_P3 30
C1 G14 USB20_N3 Camera
LLB#/GPIO66 USB_HSD3N USB20_N3 30
Y19 SMARTVOLT2/SHUTDOWN#/GPIO5
G5 DDR3_RST#/GEVENT7# USB_HSD2P H14
USB_HSD2N H15

A13 USB20_P1
USB_HSD1P USB20_P1 38
B13 USB20_N1 M/B conn S3 Wake Up
USB_HSD1N USB20_N1 38
B14 USB20_P0
USB_HSD0P USB20_P0 38
B9 A14 USB20_N0 M/B conn
USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N USB20_N0 38
B8 USB_OC5#/IR_TX0/GPM5#
A8 A18

USB OC
34 EC_LID_OUT# USB_OC4#/IR_RX0/GPM4# IMC_GPIO8
A9 USB_OC3#/IR_RX1/GPM3# IMC_GPIO9 B18
E5 USB_OC2#/GPM2# IMC_PWM0/IMC_GPIO10 F21
USB OC#1 F8 D21
38 USB_OC#1 USB_OC1#/GPM1# SCL2/IMC_GPIO11
USB OC#0 E4 F19
38 USB_OC#0 USB_OC0#/GPM0# SDA2/IMC_GPIO12
SCL3_LV/IMC_GPIO13 E20
R119 33 0402 5% 1 2 HDA BITCLK M1 E21
41 HDA_BITCLK_AUDIO AZ_BITCLK SDA3_LV/IMC_GPIO14
R120 33 0402 5% 1 2 HDA SDOUT M2 E19
41 HDA_SDOUT_AUDIO AZ_SDOUT IMC_PWM1/IMC_GPIO15
HDA SDIN0
41 HDA_SDIN0 J7 AZ_SDIN0/GPIO42 IMC_PWM2/IMC_GPO16 D19 GPIO16 27 STRAP PIN
J8
L8
AZ_SDIN1/GPIO43 IMC_PWM3/IMC_GPO17 E18 GPIO17 27 STRAP PIN

HD AUDIO
AZ_SDIN2/GPIO44
M3 AZ_SDIN3/GPIO46 IMC_GPIO18 G20
R125 33 0402 5% 1 2 HDA SYNC L6 G21
B 41 HDA_SYNC_AUDIO AZ_SYNC IMC_GPIO19 B
M4 AZ_RST# IMC_GPIO20 D25
L5 AZ_DOCK_RST#/GPM8# IMC_GPIO21 D24

INTEGRATED uC
IMC_GPIO22 C25
R117 33_0402_5% 1 2 HDARST# C24
41 HDA_RST_AUDIO# IMC_GPIO23
IMC_GPIO24 B25
STRAP PIN 27 HDARST# IMC_GPIO25 C23

IMC_GPIO26 B24
IMC_GPIO27 B23
IMC_GPIO28 A23
3VALW
IMC_GPIO29 C22
SB Power Domain :S5 IMC_GPIO30 A22
IMC_GPIO31 B22
2

R413
High: CRT Plugged 3VS IMC_GPIO32 B21
IMC_GPIO33 A21
H19 IMC_GPIO0 IMC_GPIO34 D20
100K_0402_5% H20 C20
IMC_GPIO1 IMC_GPIO35
NTEGRATED uC
H21 A20
1

@ SPI_CS2#/IMC_GPIO2 IMC_GPIO36
1 2 F25 IDE_RST#/F_RST#/IMC_GPO3 IMC_GPIO37 B20
CRT DET 1 @ 2 CRT DET R R126 2.2K_0402_5% B19
R558 0_0402_5% IMC_GPIO38
D22 IMC_GPIO4 IMC_GPIO39 A19
1

D
E24 IMC_GPIO5 IMC_GPIO40 D18
29 CRT_DET# 2 E25 IMC_GPIO6 IMC_GPIO41 C18
Q40G D23
2N7002_SOT23 IMC_GPIO7
S
3

218S7EALA11FG_BGA528_SB710
A A
SB710 Ver:A14 <SA000030740>

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 24 of 55
5 4 3 2 1
 5 4 3 2 1

U10B

Port Number Pri/SEC,Mas/Slave assignment SATA drive controlled by SB700

28 SATA_STX_DRX_P0 AD9 SATA_TX0P IDE_IORDY AA24
AE9 Part 2 of 5 AA25
Port 0 Primary master SATA controler Main 28 SATA_STX_DRX_N0 SATA_TX0N IDE_IRQ
IDE_A0 Y22
AB10 AB23
HDD 28 SATA_DTX_C_SRX_N0
28 SATA_DTX_C_SRX_P0 AC10
SATA_RX0N
SATA_RX0P
IDE_A1
IDE_A2 Y23
Port 2 Primary slave SATA controler IDE_DACK# AB24
AE10 SATA_TX1P IDE_DRQ AD25
AD10 SATA_TX1N IDE_IOR# AC25
D Port 3 Secondary slave SATA controler IDE_IOW# AC24 D
AD11 SATA_RX1N IDE_CS1# Y25
AE11 SATA_RX1P IDE_CS3# Y24

28 SATA_STX_DRX_P2 AB12 SATA_TX2P IDE_D0/GPIO15 AD24

AC12 AD23
Main 28 SATA_STX_DRX_N2 SATA_TX2N IDE_D1/GPIO16

ATA 66/100/133
IDE_D2/GPIO17 AE22
AE12 AC22
ODD 28 SATA_DTX_C_SRX_N2
28 SATA_DTX_C_SRX_P2 AD12
SATA_RX2N
SATA_RX2P
IDE_D3/GPIO18
IDE_D4/GPIO19 AD21
IDE_D5/GPIO20 AE20
28 SATA_STX_DRX_P3 AD13 SATA_TX3P IDE_D6/GPIO21 AB20
AE13 AD19
2nd 28 SATA_STX_DRX_N3 SATA_TX3N IDE_D7/GPIO22
AE19

SERIAL ATA
IDE_D8/GPIO23
AB14 AC20
ODD 28 SATA_DTX_C_SRX_N3
28 SATA_DTX_C_SRX_P3 AC14
SATA_RX3N
SATA_RX3P
IDE_D9/GPIO24
IDE_D10/GPIO25 AD20
IDE_D11/GPIO26 AE21
AE14 SATA_TX4P IDE_D12/GPIO27 AB22
AD14 SATA_TX4N IDE_D13/GPIO28 AD22
IDE_D14/GPIO29 AE23
AD15 SATA_RX4N IDE_D15/GPIO30 AC23
AE15 SATA_RX4P
27P_0402_50V8J 1 2 C276 SATA_X1 AB16 SATA_TX5P
AC16 SATA_TX5N

1
SPI_DI/GPIO12 G6
R150 AE16 D2
25MHZ_20P Y3 SATA_RX5N SPI_DO/GPIO11
AD16 SATA_RX5P SPI_CLK/GPIO47 D1
10M_0402_5% F4

SPI ROM
2
SATA CAL SPI_HOLD#/GPIO31
2 1 V12 F3

2
27P 0402 50V8J 1 SATA_CAL SPI_CS1#/GPIO32
C 2 C279 SATA X2 R400 1K_0402_1% C
SATA X1 Y12 U15
SATA_X1 LAN_RST#/GPIO13
ROM_RST#/GPIO14 J1
SATA X2 AA12 SATA_X2
3VS R401 1 2 10K 0402 5% FANOUT0/GPIO3 M8
40 SATA_LED# W11 SATA_ACT#/GPIO67 FANOUT1/GPIO48 M5
1.2V_HT M7
L64 FANOUT2/GPIO49
2 1 PLLVDD_SATA <93mA> AA11 P5
BLM18PG121SN1D_0603 PLLVDD_SATA FANIN0/GPIO50
FANIN1/GPIO51 P8

SATA PWR
1 1 <6mA> W12 XTLVDD_SATA FANIN2/GPIO52 R8
C530 C497
TEMP_COMM C6
2.2U_0603_6.3V4Z 0.1U_0402_ 6V4Z B6
2 2 TEMPIN0/GPIO61
TEMPIN1/GPIO62 A6
TEMPIN2/GPIO63 A5
B5

HW MONITOR
TEMPIN3/TALERT#/GPIO64 EC_THERM# 34

VIN0/GPIO53 A4 2 1 ACIN 18,34,44

3VS L62 B4 D25 CH751H-40PT_SOD323-2
XTLVDD SATA VIN1/GPIO54
2 1 VIN2/GPIO55 C4
BLM18PG121SN1D_0603 2 1 D4 R377 1 2 100K 0402 5% 3VS
VIN3/GPIO56
VIN4/GPIO57 D5
C493 C496 D6 R378 1 @ 2 100K 0402 5% 3VALW
1U_0402_6.3V4Z 0.1U_0402_16V4Z VIN5/GPIO58
VIN6/GPIO59 A7
1 2
VIN7/GPIO60 B7 for ACIN level issue
3VALW
L55
B SB AVDD B
AVDD F6 <5mA> 2 1
1 1 BLM18PG121SN1D_0603
AVSS G7
C457
2.2U_0603_6.3V4Z
2 2
218S7EALA11FG_BGA528_SB710
C456
0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 25 of 55
5 4 3 2 1
 5 4 3 2 1

U10C U10E
<131mA> SB700 <510mA>
SB_VDD
3VS L9
M9
VDDQ_1
Part 3 of 5
VDD_1 L15
M12
1
R418
2
0_0805_5%
1.2V_HT SB700 A2
C524 22U_0805_6.3V6M VDDQ_2 VDD_2 VSS_1
1 2 T15 VDDQ_3 VDD_3 M14 1 2 VSS_2 A25
U9 N13 C528 22U_0805_6.3V6M B1

CORE S0
C604 1U_0402_6.3V4Z VDDQ_4 VDD_4 C484 1U_0402_6.3V4Z VSS_3
1 2 U16 VDDQ_5 VDD_5 P12 2 1 VSS_4 D7
C603 1 2 1U_0402_6.3V4Z U17 P14 C487 2 1 1U_0402_6.3V4Z T10 F20
VDDQ_6 VDD_6 AVSS_SATA_1 VSS_5

PCI/GPIO /O
C508 1 2 1U_0402_6.3V4Z V8 R11 C475 2 1 1U_0402_6.3V4Z U10 G19
C489 1U_0402_6.3V4Z VDDQ_7 VDD_7 C471 1U_0402_6.3V4Z AVSS_SATA_2 VSS_6
1 2 W7 VDDQ_8 VDD_8 R15 2 1 U11 AVSS_SATA_3 VSS_7 H8
C512 1 2 1U 0402 6.3V4Z Y6 T16 C492 2 1 0.1U 0402 16V4Z U12 K9
C529 0.1U 0402 16V4Z VDDQ_9 VDD_9 C485 0.1U 0402 16V4Z AVSS_SATA_4 VSS_8
1 2 AA4 VDDQ_10 2 1 V11 AVSS_SATA_5 VSS_9 K11
D C490 1 2 0.1U 0402 16V4Z AB5 V14 K16 D
C465 0.1U 0402 16V4Z VDDQ_11 AVSS_SATA_6 VSS_10
1 2 AB21 VDDQ_12 W9 AVSS_SATA_7 VSS_11 L4
Y9 AVSS_SATA_8 VSS_12 L7
Y11 AVSS_SATA_9 VSS_13 L10
Y14 AVSS_SATA_10 VSS_14 L11
<71mA> L28 Y17 L12
1.2V CKVDD AVSS_SATA_11 VSS_15
3VS Y20 VDD33_18_1 CKVDD_1.2V_1 L21 2 1 1.2V_HT AA9 AVSS_SATA_12 VSS_16 L14
AA21 L22 FBMA-L11-160808-221LMT 0603 AB9 L16
VDD33_18_2 CKVDD_1.2V_2 AVSS_SATA_13 VSS_17
1 @ 2 AA22 L24 C515 1 2 1U 0402 6.3V4Z AB11 M6

DE/FLSH I/O

CLKGEN I/O
C516 22U_0805_6.3V6M VDD33_18_3 CKVDD_1.2V_3 AVSS_SATA_14 VSS_18
AE25 VDD33_18_4 CKVDD_1.2V_4 L25 AB13 AVSS_SATA_15 VSS_19 M10
C495 1 @ 2 0.1U_0402_16V4Z C285 1 2 1U_0402_6.3V4Z AB15 M11
C518 AVSS_SATA_16 VSS_20
1 @ 2 0.1U_0402_16V4Z AB17 AVSS_SATA_17 VSS_21 M13
C522 1 2 0.1U_0402_16V4Z C521 2 1 0.1U_0402_16V4Z AC8 M15
@ AVSS_SATA_18 VSS_22
AD8 AVSS_SATA_19 VSS_23 N4
C523 2 1 0.1U_0402_16V4Z AE8 N12
AVSS_SATA_20 VSS_24
VSS_25 N14
PCIE_VDDR C284 1 2 10U_0805_10V4Z P6
L65 POWER VSS_26
VSS_27 P9
1.2V_HT 2 1 <600mA> VSS_28 P10
FBMA-L11-201209-221LMA30T_0805 A15 P11
AVSS_USB_1 VSS_29
P18 PCIE_VDDR_1 B15 AVSS_USB_2 VSS_30 P13
1 2 P19 3VALW C14 P15
C250 22U_0805_6.3V6M PCIE_VDDR_2 AVSS_USB_3 VSS_31
P20 PCIE_VDDR_3 <32mA> D8 AVSS_USB_4 VSS_32 R1
1 2 P21 A17 S5 3V 1 2 D9 R2

A-LINK /O
C520 4.7U_0805_10V4Z PCIE_VDDR_4 S5_3.3V_1 R416 0_0805_5% AVSS_USB_5 VSS_33
R22 PCIE_VDDR_5 S5_3.3V_2 A24 D11 AVSS_USB_6 VSS_34 R4
C467 1 2 1U 0402 6.3V4Z R24 B17 1 2 D13 R9
PCIE_VDDR_6 S5_3.3V_3 AVSS_USB_7 VSS_35

GROUND
R25 J4 C481 22U_0805_6.3V6M D14 R10
PCIE_VDDR_7 S5_3.3V_4 AVSS_USB_8 VSS_36

3.3V_S5 I/O
C247 1 2 0.1U 0402 16V4Z J5 1 2 D15 R12
C514 1 S5_3.3V_5 AVSS_USB_9 VSS_37
2 0.1U 0402 16V4Z S5_3.3V_6 L1 C483 2.2U_0603_6.3V4Z E15 AVSS_USB_10 VSS_38 R14
C L2 1 2 F12 T11 C
1.2V_SATA S5_3.3V_7 C525 2 AVSS_USB_11 VSS_39
1 2.2U 0603 6.3V4Z F14 AVSS_USB_12 VSS_40 T12
L63 <567mA> C510 2 1 0.1U 0402 16V4Z G9 T14
C470 2 AVSS_USB_13 VSS_41
1.2V_HT 2 1 AA14 AVDD_SATA_1 1 0.1U 0402 16V4Z H9 AVSS_USB_14 VSS_42 U4
FBMA-L11-201209-221LMA30T_0805 AB18 C504 0.1U_0402_16V4Z 1.2VALW H17 U14
AVDD_SATA_4 AVSS_USB_15 VSS_43
AA15 AVDD_SATA_2 <113mA> J9 AVSS_USB_16 VSS_44 V6
1 2 AA17 G2 S5_1.2V R528 0_0603_5% J11 Y21

CORE S5
AVDD_SATA_3 S5_1.2V_1 AVSS_USB_17 VSS_45
SATA I/O
C526 22U_0805_6.3V6M AC18 G4 J12 AB1
C517 1 AVDD_SATA_5 S5_1.2V_2 1.2VALW AVSS_USB_18 VSS_46
2 1U_0402_6.3V4Z AD17 AVDD_SATA_6 2 1 J14 AVSS_USB_19 VSS_47 AB19
C527 1 2 1U_0402_6.3V4Z AE17 <197mA> L29 C460 2 1 1U_0402_6.3V4Z J15 AB25
C509 1 AVDD_SATA_7 AVSS_USB_20 VSS_48
2 0.1U_0402_16V4Z 1.2_USB 2 1 C461 1U_0402_6.3V4Z K10 AVSS_USB_21 VSS_49 AE1
C511 1 2 0.1U_0402_16V4Z A10 FBMA-L11-160808-221LMT 0603 K12 AE24
USB_PHY_1.2V_1 AVSS_USB_22 VSS_50
USB_PHY_1.2V_2 B10 1 2 K14 AVSS_USB_23
C271 22U_0805_6.3V6M K15
C286 2 AVSS_USB_24
1 0.1U_0402_16V4Z PCIE_CK_VSS_9 P23
C270 2 1 0.1U_0402_16V4Z R16
R419 2 PCIE_CK_VSS_10
1 1K_0402_5% Reserve for SB700 leakage voltage issue PCIE_CK_VSS_11 R19
AVDD_USB T17
L26 PCIE_CK_VSS_12
<658mA> PCIE_CK_VSS_13 U18
3VALW 2 1 A16 AE7 <1mA> V5 VREF R417 2 1 1K 0402 5% 5VS H18 U20
FBMA-L11-201209-221LMA30T_0805 AVDDTX_0 V5_VREF PCIE_CK_VSS_1 PCIE_CK_VSS_14
B16 AVDDTX_1 2 2 J17 PCIE_CK_VSS_2 PCIE_CK_VSS_15 V18
C16 AVDDTX_2 AVDDCK_3.3V J16 <47mA> AVDDCK 3.3V 1 2 3VS J22 PCIE_CK_VSS_3 PCIE_CK_VSS_16 V20
C217 1 2 10U 0805 10V4Z D16 C513 C519 K25 V21
C216 10U 0805 10V4Z AVDDTX_3 PCIE_CK_VSS_4 PCIE_CK_VSS_17
1 2 D17 K17 <62mA> AVDDCK 1.2V 1U_0603_10V4Z D27 CH751H-40PT_SOD323-2 M16 W19
PLL

C458 1U 0402 6.3V4Z AVDDTX_4 AVDDCK_1.2V 0.1U_0402_16V4Z 1 1 PCIE_CK_VSS_5 PCIE_CK_VSS_18

1 2 E17 AVDDTX_5 M17 PCIE_CK_VSS_6 PCIE_CK_VSS_19 W22
USB I/O

C459 1 2 1U 0402 6.3V4Z F15 E9 <17mA> AVDDC M21 W24

C466 0.1U 0402 16V4Z AVDDRX_0 AVDDC PCIE_CK_VSS_7 PCIE_CK_VSS_20
1 2 F17 AVDDRX_1 P16 PCIE_CK_VSS_8 PCIE_CK_VSS_21 W25
C494 1 2 0.1U 0402 16V4Z F18 L54
C469 0.1U 0402 16V4Z AVDDRX_2
1 2 G15 AVDDRX_3 2 1 3VALW F9 AVSSC AVSSCK L17
B BLM18PG121SN1D_0603 B
G17 AVDDRX_4 Part 5 of 5
G18 AVDDRX_5 2.2U_0603_6.3V4Z 2 1 C463 218S7EALA11FG_BGA528_SB710

0.1U_0402_16V4Z 2 1 C462 SB710 Ver:A14 <SA000030740>

218S7EALA11FG_BGA528_SB710

SB710 Ver:A14 <SA000030740>

L56 L58
AVDDCK 1.2V 2 1 1.2V_HT AVDDCK 3.3V 2 1 3VS
BLM18PG121SN1D_0603 BLM18PG121SN1D_0603

2.2U 0603 6.3V4Z 2 1 C464 2.2U 0603 6.3V4Z 2 1 C498

0.1U 0402 16V4Z 2 1 C491 0.1U 0402 16V4Z 2 1 C499

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 26 of 55
5 4 3 2 1
 5 4 3 2 1

REQUIRED STRAPS NOTE: SB700 HAS NTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

LPC_CLK0
PCI_CLK2 PCI CLK3 PCI CLK4 PCI CLK5 CLK_PCI_EC LPC CLK1 RTC CLK AZ RST CD# GP17 GP16

PULL BOOTFA L USE RESERVED RESERVED ENABLE PCI CLKGEN INTERNAL EC Internal pull up
HIGH TIMER DEBUG MEM BOOT ENABLED RTC ENABLED
ENABLED STRAPS H,H = Reserved
D DEFAULT D
H,L = SPI ROM
EXT. RTC
PULL BOOTFAIL IGNORE DISABLE PCI CLKGEN (PD on X1, EC
LOW TIMER DEBUG MEM BOOT DISABLED apply DISABLED L,H = LPC ROM (Default L,NC)
DISABLED STRAPS 32KHz to DEFAULT L,L = FWH ROM
DEFAULT DEFAULT DEFAULT DEFAULT RTC_CLK)

3VS 3VS 3VS 3VS 3VALW 3VALW 3VALW 3VALW 3VALW 3VALW

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R145

R138

R144

R146

R136

R89

R394

R142

R87

R494
2

2
@ @ @ @ @ @ @ @ @
23 PCI_CLK2
23 PCI_CLK3
23 PCI_CLK4
23 PCI_CLK5
23,34 CLK_PCI_EC
23 LPCCLK1
C C
23 RTC_CLK
24 HDARST#
24 GPIO17
24 GPIO16
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
1

1
R386

R137

R94
R143

R133

R141

R132

R129

R96

R130
2

2
@ @ @ @

DEBUG STRAPS
SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

PCI AD28 PCI AD27 PCI AD26 PCI AD25 PCI AD24 PCI AD23

B
USE USE PCI USE ACPI USE IDE USE DEFAULT RESERVED B
PULL LONG PLL BCLK PLL PCIE STRAPS
HIGH RESET
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT

PULL USE BYPASS BYPASS BYPASS IDE USE EEPROM

LOW SHORT PCI PLL ACPI PLL PC E STRAPS
RESET BCLK

23 PCI_AD28
23 PCI_AD27
23 PCI_AD26
23 PCI_AD25
23 PCI_AD24
23 PCI_AD23
1

1
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R156

R148

R158

R157

R147

R159
2

2
@ @ @ @ @ @
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 27 of 55
5 4 3 2 1
 5 4 3 2 1

5VS 3VS 5VS

Place Caps. near the ODD CONN.
0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1 1 1 1 1 1 1
C351 C349 C347 C346
C360 C148
C363 C366 C368 15@ C153 15@ C150 15@ 15@ C149
10U_0805_10V4Z 10U_0805_10V4Z
2 2 2 2 2 2 2 2 2 2 2 2
D D
1U 0402 6.3V4Z
0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K

SATA HDD CONN SATA ODD CONN

JSATA2 JSATA1

1 15@ 1
C289 1 GND GND
25 SATA_STX_DRX_P0 2 0.01U_0402_25V7K SATA_STX_C_DRX_P0 2 HTX+ 25 SATA_STX_DRX_P2
C308 1 2 0.01U_0402_25V7K SATA_STX_C_DRX_P2 2 A+
C291 1 2 0.01U_0402_25V7K SATA_STX_C_DRX_N0 3 C307 1 2 0.01U_0402_25V7K SATA_STX_C_DRX_N2 3
25 SATA_STX_DRX_N0 HTX- +5VS 25 SATA_STX_DRX_N2 A-
4 15@ 15@ 4
C302 1 GND GND
25 SATA_DTX_C_SRX_N0 2 0.01U_0402_25V7K SATA_DTX_SRX_N0 5 HRX- 25 SATA_DTX_C_SRX_N2
C311 1 2 0.01U_0402_25V7K SATA_DTX_SRX_N2 5 B-
C305 1 2 0.01U_0402_25V7K SATA_DTX_SRX_P0 6 1 C312 1 2 0.01U_0402_25V7K SATA_DTX_SRX_P2 6
25 SATA_DTX_C_SRX_P0 HRX+ C370 25 SATA_DTX_C_SRX_P2 15@ B+
7 GND 7 GND
+
@
R544 1 2 8
150U_D2_6.3VM 2 R617 @ 1K_0402_1% DP
+3VS 1 2 8 VCC3.3 9 +5V
9 VCC3.3 5VS 10 +5V
C 0_0805_5% 10 11 C
VCC3.3 MD
11 GND 12 GND GND 15
12 GND 13 GND GND 14
R545 13 GND
+5VS 1 2 14 VCC5
Close to SATA HDD
15 P-TWO_121138-13241_13P
0_0805_5% VCC5 CONN@
16 VCC5
17 GND
18 RESERVED
19 GND
20 VCC12
21 VCC12 GND 24
22 VCC12 GND 23

OCTEK_SAT-22SU1G_NR
CONN@

JP2
1 1 2 2 5VS
3 3 4 4
5 5 6 6
7 7 8 8
9 9 10 10
11 11 12 12
17@ 13 14
C323 1 13 14
25 SATA_STX_DRX_P3 2 0.01U 0402 25V7K SATA STX C DRX P3 15 15 16 16 3VS
C317 1 2 0.01U 0402 25V7K SATA STX C DRX N3 17 18
B 25 SATA_STX_DRX_N3 17 18 B
17@ 17@ 19 20
Second ODD 25 SATA_DTX_C_SRX_N3
C320 1 2 0.01U_0402_25V7K SATA_DTX_SRX_N3 21
19
21
20
22 22
C319 1 2 0.01U_0402_25V7K SATA_DTX_SRX_P3 23 24
25 SATA_DTX_C_SRX_P3 23 24
17@ 25 26
25 26
27 27 28 28
29 30

GND
GND
GND
GND
GND
GND
29 30

ACES_88018-304G

31
32
33
34
35
36
CONN@

5VS 3VS

0.1U 0402 16V4Z 0.1U 0402_16V4Z 0.1U 0402 16V4Z

1 1 1 1 1 1 1
C574 C577 C579 C580 C572 C573 C571
17@ 17@ 17@ 17@ 17@ 17@ 17@
2 2 2 2 2 2 2

1000P_0402_50V7K 10U_0805_10V4Z 1000P_0402_50V7K 10U_0805_10V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 28 of 55
5 4 3 2 1
 A B C D E

CRT Connector
D18 D19 D20
@ @ @ 5VS R_CRT_VCC CRT_VCC
DAN217_SC59 DAN217_SC59 DAN217_SC59 W=40mils
D17 F1 W=40mils

1
2 1 1 2

1 RB491D_SC59-3 1.1A_6VDC_FUSE 1
1
C407

3
0.1U_0402_16V4Z
2
5VS

L42 L32 JCRT1

1 2 CRT_R_1 1 2 CRT_R_2 6
18 VGA_CRT_R
FCM2012C-800_0805 FCM2012CF-800T06_2P 11
L39 L34 1
1 2 CRT_G_1 1 2 CRT_G_2 7
18 VGA_CRT_G
FCM2012C-800_0805 FCM2012CF-800T06_2P 12
L40 L33 2
1 2 CRT_B_1 1 2 CRT_B_2 8
18 VGA_CRT_B
FCM2012C-800_0805 FCM2012CF-800T06_2P 13
8P_0402_50V8D 3
1

1 1 1 1 1 1 1 1 1 9
R339 R338 R340 C547 C534 C532 C408 C412 C414 14
C413 C410 C409 4
150_0402_1% 150_0402_1% 3.3P_0402_50V8J 3.3P_0402_50V8J 10
2 2 2 2 8P_0402_50V8D 2 8P_0402_50V8D 2 8P_0402_50V8D 2 2 2 SUYIN_070549FR015S208CR
15
2

3.3P 0402 50V8J 8P_0402 50V8D 8P 0402 50V8D C406 5

150_0402_1% 100P_0402_50V8J CONN@

16

17
CRT_VCC HSYNC L
1 2
2 L38 MBC1608121YZF_0603 2
Change 3.3p For M92 1 2 2 1 D DDC DATA
C434 0.1U_0402_16V4Z R360 10K_0402_5% 1 2 VSYNC L
L37 MBC1608121YZF_0603 1

1
U36 C411

10P_0402_50V8J

10P_0402_50V8J
1 1

OE#
CRT_DET# 24
1 2 CRT_HSYNC 2 4 D_CRT_HSYNC 68P_0402_50V8J
18,22 VGA_CRT_HSYNC A Y 2
R354 0_0402_5% C424 C423

G
D_DDC_CLK

2
74AHCT1G125GW_SOT353-5 2 2

3
1 R636
CRT_VCC C422 100K_0402_5%

1 2 68P_0402_50V8J

1
C433 0.1U_0402_16V4Z 2

1
U35

OE#
1 2 CRT_VSYNC 2 4 D_CRT_VSYNC CRT_VCC
18,22 VGA_CRT_VSYNC A Y
R356 0_0402_5%

G
74AHCT1G125GW_SOT353-5

3
3 3

Close to Conn side

3.3V_DELAY
CRT_VCC

3VS

1
1

R72 R77 4.7K_0402_5% 4.7K_0402_5%

6.8K_0402_5% 6.8K_0402_5% R479 R503
2

2
2

Q50A
2

D DDC DATA 6 1
VGA_CRT_DATA 18
2N7002DW-T/R7_SOT363-6
5

D DDC CLK 3 4 VGA_CRT_CLK 18

Q50B
2N7002DW-T/R7_SOT363-6

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 29 of 55
A B C D E
 5 4 3 2 1

3VS INVT_PWM
2

1
1
D21 C416
100K_0402_5% R347 LCD POWER CIRCUIT BAS16_SOT23-3
@
1U_0402_6.3V4Z
@
2
D D
1

2
3VS

LCDVDD 3VALW
1
C77
1

2
@ 4.7U_0805_10V4Z
R274
150_0603_5% R348
2
LCD/PANEL CONN.
2N7002DW-T/R7_SOT363-6

510_0402_5% W=60mils
6 2

3
S
G Q23 JLVDS1
2 1 2 42 GND GND 41
Q22A

R278 100K_0402_5% AO3413_SOT23-3 INVPWR_B 40 39 DAC_BRIG

40 39 DAC_BRIG 34
2 1
D 38 37 INVT_PWM

1
LCDVDD 38 37 DISPOFF#
W=60mils 3VS
EDID_LCD_CLK
36 36 35 35
18 VGA_LCD_CLK 34 33 LCDVDD
1

34 33
3

2N7002DW-T/R7_SOT363-6

C431 LCDVDD 18 VGA_LCD_DATA EDID_LCD_DAT 32 31

2 0.047U_0402_16V7K 32 31
Q22B

30 30 29 29
1 1 18 VGA_TZOUT0- 28 28 27 27
VGA ENVDD 5 C415 C420 26 25
18 VGA_ENVDD 18 VGA_TZOUT0 26 25 VGA_TXOUT0- 18
24 24 23 23 VGA_TXOUT0 18
4.7U_0805_10V4Z 0.1U_0402_16V4Z 22 21
18 VGA_TZOUT1
4

22 21
1

2 2
18 VGA_TZOUT1- 20 20 19 19 VGA_TXOUT1- 18
18 18 17 17 VGA_TXOUT1 18
18 VGA_TZOUT2 16 16 15 15
C 100K_0402_5% R345 14 13 C
18 VGA_TZOUT2- 14 13 VGA_TXOUT2 18
12 11 VGA_TXOUT2- 18
2

12 11
18 VGA_TZCLK- 10 10 9 9
18 VGA_TZCLK 8 8 7 7 VGA_TXCLK- 18
6 6 5 5 VGA_TXCLK 18
R759 1 2 0_0402_5% USB20_CMOS_N3 4 3
24 USB20_N3 4 3
R760 1 2 0_0402_5% USB20_CMOS_P3 2 1 R761 1 2 0_0603_5% 3VS
24 USB20_P3 2 1
L77 ACES_88242-4001
4 3 CONN@ 1 1
4 3
C768 C426
1 1 2 2
2 2
EC_INVT_PWM 1 2 INVT_PWM @ WCM2012F2S-900T04_0805 0.1U_0402_16V4Z 1000P_0402_25V8J
34 EC_INVT_PWM
R764 0_0402_5%

18 VGA_VARIBL 2 1
R561 0_0402_5%
VARY@

3VS INVPWR_B

B L20 2 B
1 B
W=40mils FBMA-L11-201209-221LMA30T_0805

1
VARYBRIGHT FUNCTION R1 L15 2 1
@ FBMA-L11-201209-221LMA30T_0805
1 2 4.7K_0402_5% 1 1
R763 0_0402_5% C379 C362

2
3VS 3VS BKOFF# 1 2 DISPOFF# 680P_0402_50V7K 68P_0402_50V8J
34 BKOFF# 2 2
D2 RB751V_SOD323
@
1

2
R769 0_0402_5%
EC_INVT_PWM 2 VARY@ 1 R30 R39 R414
VARY@ VARY@
2

4.7K_0402_5% 4.7K_0402_5% 100K_0402_5% LCDVDD

1 VARY@ 2
2

1
R21 4.7K_0402_5% 1 6 1 VARY@ 2 INVT PWM
R768 0_0402_5%
Q52A VARY@ DAC BRIG C371 1 2 220P 0402 50V7K 1 1
1

R770 0_0402_5% 2N7002DW-T/R7_SOT363-6 D @ C383 C382

VGA VARIBL 2 VARY@1 2 Q69 INVT PWM C372 1 2 220P 0402 50V7K
G 2N7002_SOT23-3 10U_0805_10V4Z 0.1U_0402_16V4Z
5

VARY@ DISPOFF# C377 1 2 2

S 2 220P 0402 50V7K
3

1 VARY@ 2
R23 4.7K_0402_5% 4 3
Q52B VARY@
2N7002DW-T/R7_SOT363-6
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2009/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 30 of 55
5 4 3 2 1
 5 4 3 2 1

1 8114@ 2 1.8_VDD/LX
Place Close to Chip
R820 0_0603_5% Layout Notice : Close to chip
1 2 LAN_MIDI0 R843 2 1 49.9_0402_1% C978 1 2 0.1U_0402_16V4Z
L88 8132@ 4.7UH_1008HC-472EJFS-A_5%_1008 3V_LAN
LAN_MIDI0- R845 2 1 49.9_0402_1%
AVDD_CEN 1 2 0.1U_0402_16V4Z
LAN_MIDI1 R846 2
+3VALW
1 49.9_0402_1% C979 1 2 0.1U_0402_16V4Z R830 0_1206_5%

R8441 2 0 0603 5% 1 2 2.5V VDDH/VDD17 1 2 2.5V VDDH LAN MIDI1- R847 2 1 49.9 0402 1% 1 1 1 1
1 R824 8132@ 0_0603_5% R825 8114@ 0_0603_5% Trace 10mil C944 C941 C942
D C933 C934 10U_0805_10V4Z C945 D
1U_0603_10V4Z
4.7U_0805_10V4Z 0.1U_0402_16V4Z 2 2 2 2
8132@ 2 8132@

0.1U_0402_16V4Z

U85

2 1 1.8_VDD/LX 1 29 TWSI_SCL
C936 8114@ 1U_0603_10V4Z VDD18O TWSI_CLK TWSI_SDA
TWSI_DATA 30
3V_LAN 2 VDD33
8114@ LAN_ACTIVITY#
WAKEn C935 2 1 1U_0603_10V4Z 2.5V_VDDH/VDD17 6
LED_ACTn 47
48 LAN_LINK#
LAN_ACTIVITY# 32 Place Close to Pin 28、32、45、46
VDDHO LED_10_100n LAN_LINK# 32
8114 Internal PU C982 2 1 0.1U_0402_16V7K CTR12 5 CTR12 LED_DUPLEXn 27 1 2 LAN_CLKREQ# 16
C953 C955
8132 OD 8132@ R261 0_0402_5% 1.2_DVDDL 0.1U_0402_16V4Z 0.1U_0402_16V4Z
PLT_RST# 3 13 LAN_MIDI0 LAN_MIDI0 32 1 1 1 1 1
13,15,17,23,34,37 PLT_RST# PERSTn TRXP0
34 EC_PME# 4 14 LAN_MIDI0- LAN_MIDI0- 32
8114@ WAKEn TRXN0 LAN_MIDI1 C952
TRXP1 17 LAN_MIDI1 32
3V_LAN 1 2 2 1 7 18 LAN_MIDI1- LAN_MIDI1- 32 close PIN46 8132@ 81 4@ 0.1U_0402_16V4Z
R829 4.7K_0402_5% C937 1000P_0402_50V7K VBG1P18V TRXN1 2 2 2 2 2
16 CLK_PCIE_LAN 2 1 CLK_PCIE_LAN_C 41 11 AVDDVCO1 C983 C954
C938 0.1U_0402_16V7K REFCLKP AVDDL_REG AVDDVCO2 1U_0603_10V4Z 0.1U_0402_16V4Z
AVDDL/AVDDL_REG 42
16 CLK_PCIE_LAN# 2 1 CLK PCIE LAN# C 40 REFCLKN

A
t
h
e
r
o
s
C939 0.1U_0402_16V7K
12 PCIE_ITX_C_PRX_P1 43 RX_P
28 1.2 DVDDL
DVDDL0
12 PCIE_ITX_C_PRX_N1 44 RX_N DVDDL1 32
C 45 C
PCIE PTX IRX P1 DVDDL2
12 PCIE_PTX_C_IRX_P1 2
C940
1
0.1U_0402_16V7K
38 TX_P AR8114A 10/100 LAN DVDDL3 46 Place Close to Pin15、19、25
12 PCIE_PTX_C_IRX_N1 2 1 PCIE PTX IRX N1 37 8 1.2 AVDDL
C943 0.1U 0402_16V7K TX_N AVDDL0 C960
AVDDL1 16
2.5V_VDDH 0.1U_0402_16V4Z
Place Close to Chip LAN_X1 9
AVDDL2 22
36
XTLO AVDDL3 1 1 1
LAN_X2 10 39 C961
XTLI AVDDL4
31 15 2.5V_VDDH close PIN15 0.1U_0402_16V4Z
Y8 SMCLK AVDDH0 2 2 2
33 SMDATA AVDDH1 19
LAN_X1 1 2 LAN_X2 25 C959
AVDDH2 1U_0603_10V4Z
NC_0 20
1 25MHZ_20P 1 2 1 12 21
R831 2.37K_0402_1% RBIAS NC_1
34 TESTMODE NC_2 23
C946 C947 24
27P_0402_50V8J 27P_0402_50V8J NC_3
NC_4 26
2 2
49 GND NC_5 35

AR8114-AL1E_QFN48_6X6
Place Close to Pin8、16、22、36、39
change to AR8132L-AL1E Add 10/26
C984 C963 C965
1.2 AVDDL 1U 0603 10V4Z 0.1U 0402 16V4Z 0.1U 0402 16V4Z
PLT RST# 1 1 1 1 1 1
C966
B
1 B
C191 8132@ 0.1U_0402_16V4Z
1.2_AVDDL 180P_0402_50V8J 2 2 2 2 2 2
L89 FBMA-L11-201209-221LMA30T_0805 close PIN8 C962 C964
1.2_DVDDL 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2
8114@

3V_LAN

R835 0_0603_5% 1
1

1 2 1 2 AVDDVCO1 3V_LAN 3V_LAN

R834 @ 1 1 C948 R832 1 8132@ 2 2.5V_VDDH
0_0603_5% C956 0.1U_0402_16V4Z 10K_0402_1% R833 0_0402_5%
3

1000P_0402_50V7K C957 8114@ 2 Q73 8114@

1
1U_0603_10V4Z 1
2

2 2 CTR12 C932 R821 R822

1
1
C949 0.1U_0402_16V4Z 4.7K_0402_5% 4.7K_0402_5%
NJT4030PT1G_SOT223 0.1U_0402_16V4Z 2
4
2

2
8114@ 8132@
1.2 AVDDL 2 U84
R546 1 2 0 0805 5% AVDDVCO2 1 1 1 8
C950 C951 A0 VCC
1 2 A1 WP 7
10U_0805_10V4Z 0.1U_0402_16V4Z 3 6 TWSI SCL
C958 8114@ 8114@ A2 SCL TWSI SDA
4 GND SDA 5
2 2
0.1U_0402_16V4Z
2 AT24C02BN-SH-T_SO8
@
A A
8114: R546 need change to bead

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 31 of 55
5 4 3 2 1
 5 4 3 2 1

C967
1 2
AVDD_CEN
C993 220P_0402_50V7K
2 1
1U_0603_10V4Z JRJ1

2
31 LAN_ACTIVITY# 2 1 LAN_ACTIVITY#_R 12 Amber LED+
R836 R837 510_0402_5%
0_0603_5% Close T1 2 1 11 Amber LED-
R14 5.11K_0402_1% 16
SHLD2
D 8 D

1
T1 PR4-
SHLD1 15
7 PR4+
31 LAN_MIDI0 LAN MIDI0 1 16 RJ45 MIDI0
LAN MIDI0- RD+ RX+ RJ45 MIDI0- RJ45 MIDI1-
31 LAN_MIDI0- 2 RD- RX- 15 6 PR2-
3 CT CT 14
4 NC NC 13 5 PR3-
5 12

31 LAN_MIDI1 LAN_MIDI1
LAN_MIDI1-
6
7
8
NC
CT
TD+
NC
CT
TX+
11
10
9
RJ45_MIDI1
RJ45_MIDI1-
close JRJ1 RJ45_MIDI1
4

3
PR3+
31 LAN_MIDI1- TD- TX- PR2+
RJ45_MIDI0- 2
350uH_NS0013LF PR1-
SHLD2 14
RJ45_MIDI0 1 PR1+
SHLD1 13

1
LAN_LINK# 10
31 LAN_LINK# Green LED-
LAN_TCT R839 R 40 2 1 9
3V_LAN Green LED+
75_0402_ % 7 _0402_1% R838 510_0402_5%
FOX_JM36113-L2R8-7F

2
1 1 1 CONN@
C969 C970
Trace 10mil C968
0.1U_0402_16V4Z RJ45 GND 220P_0402_50V7K
2 2 2

0.1U_0402_16V4Z

C LAN LINK# RJ45 GND 1 2 LANGND C

1 1
LAN ACTIVITY# R C973
LAN ACTIVITY# R 1 2 1000P_1206_2KV7K C974 C975

2
C976 Trace 10mil 4.7U_0805_10V4Z
@ 68P_0402_50V8J D16 2 2
@
0.1U_0402_16V4Z
LAN_LINK# 1 2
C977 PJDLC05_SOT23-3
@ 68P_0402_50V8J

1
For ESD request

Screw Hole PCB Fedical Mark PAD

B B

H1 H14 H19 H26 H25 H24 H23 H17 FD1 FD2 FD3 FD4
H_3P4 H_3P4 H_3P4 H_3P4 H_3P4 H_3P4 H_3P4 H_3P4

@ @ @ @

1
@ @ @ @ @ @ @ @
1

FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

H7 H9 H4 H18 H16
H_3P4 H_3P4 H_3P4 H_3P4 H_4P2

@ @ @ @ @
1

H11 H10 H15 H20 H6 H21

H_4P2 H_4P2 H_4P2 H_3P4 H 2P3 H_4P6X4P0N

@ @ @ @ @ @
1

H5 H8 H28 H29 H12 H22 H27

H_2P8 H_4P0N H_3P8 H_3P8 H_5P1X4P1N H_3P3 H_2P3
A A

@ @ @ @ @ @ @
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 32 of 55
5 4 3 2 1
 5 4 3 2 1

2 1
R675 0_0402_5%

U77

2 1 1 AV_PLL
C851 0.1U_0402_16V4Z 3
@ +3V_CARD NC
+3VALW 1 2 7 NC
R548 0_0805_5% +XDPWR_SDPWR_MSPWR 9 CARD_3V3
+3VS 1 2 11 D3V3
R547 0_0805_5% 33 10 1 2
D3V3 VREG
D 1 1 C853 MS_D4 22 C860 1U_0402_6.3V4Z D
+3V CARD C852 30
@ 0.1U_0402_16V4Z NC
8 3V3_IN
4.7U_0603_6.3V6K RST# 44 RST#
2

2 2 MODE_SEL 45 MODE_SEL
XTLO 47 43 XDCLE
@ R674 XTLI XTLO XD_CLE_SP19 XDCE#
48 XTLI XD_CE#_SP18 42
100K_0402_5% 41 XDALE
USB20_N4 XD_ALE_SP17 SDDAT2_XDRE#
24 USB20_N4 4 40
1

USB20_P4 DM SD_DAT2/XD_RE#_SP16 SDDAT3_XDWE#

24 USB20_P4 5 DP SD_DAT3/XD_WE#_SP15 39
1 2 RST# 14 38 XD RDY
40 5IN1_LED# GPIO0 XD_RDY_SP14
R335 0_0402_5% 37 SDDAT4 XDWP# MSD7
MODE SEL SD_DAT4/XD_WP#/MS_D7_SP13 SDDAT5 XDD0 MSD6
SD_DAT5/XD_D0/MS_D6_SP12 35
1 34 SDCLK_XDD1_MSCLK_L 2 1 SDCLK_XDD1_MSCLK
SD_CLK/XD_D1/MS_CLK_SP11 SDDAT6_XDD7_MSD3 R671 0_0402_5%
SD_DAT6/XD_D7/MS_D3_SP10 31

1
C854 1 29 MS INS#
1U_0402_6.3V4Z R680 MS_INS#_SP9 SDDAT7 XDD2 MSD2
SD_DAT7/XD_D2/MS_D2_SP8 28
2 @ C855 SDDAT0 XDD6 MSD0
0_0402_5% SD_DAT0/XD_D6/MS_D0_SP7 27
47P_0402_50V8J 26 SDDAT1_XDD3_MSD1
2 SD_DAT1/XD_D3/MS_D1_SP6 XDD5_MSBS
25
2
XD_D5_SP5 XDD4_SDDAT1
XD_D4/SD_DAT1_SP4 23
21 SDCD
SD_CD#_SP3 SDWP
SD_WP_SP2 20
19 XDCD
XD_CD#_SP1
EEDI 18
XTAL_CTR
2 13 XTAL_CTR 2 1 +3VS If Open , use 12MHz. crystal
RREF XTAL_CTR R681 0_0603_5%
C MS_D5 24 C
1 2 12
If Pull high , use CLKGEN 48MHz.
16 CLK_48M_SD DGND
R676 0_0402_5% 32 15
DGND EEDO
EECS 16
@ 6 17
XTLI AGND EESK SD CMD
1 2 46 AGND SD_CMD 36
C856 6P_0402_50V8D
1

2
R673 R678
10_0402_5% 6.19K_0402_1% RTS5159-GR_LQFP48_7X7
1

R672
@ Y7 0_0402_5%
2

1
1 12MHZ_16PF_6X12000012
C858
2

10P_0402_50V8J
2 @
1 2 XTLO
C857 6P_0402_50V8D

For EMI request JREAD1 +CARDPWR

MS-VCC 10
+CARDPWR 34 12 SDCLK_XDD1_MSCLK
XDCD XD-VCC MS-SCLK MS_INS#
1 XD-CD-SW MS-INS 16
B XD RDY 2 23 XDD5 MSBS B
+XDPWR_SDPWR_MSPWR SDDAT2 XDRE# XD-R/B MS-BS SDDAT0 XDD6 MSD0
3 XD-RE MS-DATA0 19
+CARDPWR XDCE# 4 21 SDDAT1_XDD3_MSD1
XDCLE XD-CE MS-DATA1 SDDAT7_XDD2_MSD2
5 XD-CLE MS-DATA2 18
XDALE 6 14 SDDAT6_XDD7_MSD3
SDDAT3 XDWE# XD-ALE MS-DATA3 SDCLK XDD1 MSCLK
7 XD-WE
1 2 SDDAT4 XDWP# MSD7 8 20
XD-WP SD-VCC

1
R318 0_0603_5% 22 SDCLK XDD1 MSCLK
SDDAT5_XDD0_MSD6 SD-CLK SD_CMD R564
9 XD-D0 SD-CMD 15
SDCLK_XDD1_MSCLK 24 30 SDDAT0_XDD6_MSD0 10_0402_5%
XD-D1 SD-DAT0
2

1 SDDAT7_XDD2_MSD2 25 32 XDD4_SDDAT1 @
SDDAT1 XDD3 MSD1 XD-D2 SD-DAT1 SDDAT2 XDRE#
27 11

2
R295 C348 XDD4 SDDAT1 XD-D3 SD-DAT2 SDDAT3 XDWE#
28 XD-D4 SD-DAT3 13
100K_0402_5% 0.1U_0402_16V4Z XDD5_MSBS 29 35 SDWP 1
2 SDDAT0_XDD6_MSD0 XD-D5 SD-WP-SW SDCD
31 36
1

SDDAT6_XDD7_MSD3 XD-D6 SD-CD-SW C479

Close to CLK_SD_48M via 33 XD-D7 @ 22P_0402_50V8J
2
4in1-GND 17
4in1-GND 26
+5VS 37
+CARDPWR 4in1-GND
4in1-GND 38 For EMI request

1 1 1 1 C859 TAITW_R015-300-LM_36P_NR-T
CONN@
C477 C342 C480 0.1U_0402_16V4Z
A 0.1U_0402_16V4Z A
2 2 2 2

10U_0805_10V4Z 0.1U_0402_16V4Z

Security Classification Compal Secret Data Compal Electronics, Inc.

For EMI request Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 33 of 55
5 4 3 2 1
 5 4 3 2 1

CLK_PCI_EC 3VALW

1
L48
R633 0.1U 0402_16V4Z 0.1U_0402_16V4Z 1 2 EC_VCCA
@ 10_0402_5% 1 1 C567 1 1 2 2 FBMA-L11-160808-800LMT_0603
C569
C476 C557 C568 C561
1
Please close to EC pin

2
1 000P_0402_50V7K 1000P_0402_50V7K C566
2 2 2 2 1 1
C689 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z BATT_OVP C672 1 100P_0402_50V8J
2

ECAGND
@ 22P_0402_50V8J
2 BATT TEMP C673 1 100P 0402 50V8J
2
D
For EC Tools D
ACIN C676 1 2 100P 0402 50V8J

111
125
For EMI request KSI[0..7]

22
33
96

67
35,40 KSI[0..7] Place on MiniCard

9
U27 3VALW
KSO[0..17] JP37

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
35,40 KSO[0..17]
1 1
3VALW 2 E51RXD P80CLK
2 E51RXD_P80CLK 37
R632 47K_0402_5% 3 E51TXD P80DATA
3 E51TXD_P80DATA 37
2 1 ECRST# 1 21 4
24 EC_GA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F 4
24 EC_KBRST# 2 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 23 BEEP# 41
2 1 3 26 ACES_85205-0400
23 SERIRQ SERIRQ# FANPWM1/GPIO12 FANPWM 6
C549 0.1U_0402_16V4Z 4 27 CONN@
23 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 46,52
23 LPC_AD3 5 LAD3
23 LPC_AD2 7 LAD2 PWM Output
8 63 BATT_TEMP
23 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 47
3VALW BATT_OVP
23 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP 46
ADP_I/AD2/GPIO3A 65 ADP_I 46
12 AD Input 66 AD_BID0
23,27 CLK_PCI_EC PCICLK AD3/GPIO3B
R514 2 @ 1 10K_0402_5% EC_PME# 13 75 R656
13,15,17,23,31,37 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
ECRST# 37 76 AD_PID0 1 2 0_0402_5%
R729 1 ECRST# SELIO2#/AD5/GPIO43
2 2.2K_0402_5% EC_SMB_CK1
24 EC_SCI# 20 SCI#/GPIO0E
23 PM_CLKRUN# 38 CLKRUN#/GPIO1D
R730 1 2 2.2K_0402_5% EC_SMB_DA1 68 3VALW
DAC_BRIG/DA0/GPIO3C DAC_BRIG 30
EN_DFAN1/DA1/GPIO3D 70 EN_DFAN1 6
R19 1 2 100K 0402 5% LID SW# DA Output 71 U45
IREF/DA2/GPIO3E IREF 46

5
KSI0 55 72
KSI0/GPIO30 DA3/GPIO3F CALIBRATE# 46
KSI1 56 2

P
R634 2 KSI1/GPIO31 B
1 47K 0402 5% KSO1 KSI2 57 KSI2/GPIO32 Y 4 RSMRST#
RSMRST# 24
KSI3 58 83 EC MUTE# EC RSMRST# 1
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# 42 A

G
C R639 2 1 47K 0402 5% KSO2 KSI4 59 84 C
KSI4/GPIO34 PSDAT1/GPIO4B

1
KSI5 60 85 TP LOCK LED# 1 @ NC7SZ08P5X_NL_SC70-5
TP_LOCK_LED# 40

3
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C R657
EC test-mode issue 61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86
KSI7 62 87 TP CLK @ C762 R740 10K_0402_5%
3VS KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 35
KSO0 39 88 TP DATA 0.1U_0402_16V4Z @
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 35 2
KSO1 40 10K_0402_5%

2
KSO2 KSO1/GPIO21
41 KSO2/GPIO22
R731 1 2 2.2K_0402_5% EC_SMB_CK2 KSO3 42 97
KSO3/GPIO23 SDICS#/GPXOA00 3S/4S# 46
KSO4 43 98
KSO4/GPIO24 SDICLK/GPXOA01 65W/90W# 46
R732 1 2 2.2K_0402_5% EC_SMB_DA2 KSO5
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW#
EC_VLDT_EN 39
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW# 40
KSO7 46 SPI Device Interface
5VS KSO8 KSO7/GPIO27
47 KSO8/GPIO28
KSO9 48 119
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO 36
R208 2 1 4.7K_0402_5% TP_CLK KSO10 49 120 Project ID
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI 36 3VALW
KSO11 50 SPI Flash ROM 126
KSO11/GPIO2B SPICLK/GPIO58 EC_SPICLK 36 Please see page 3.
R207 2 1 4.7K_0402_5% TP_DATA KSO12 51 128
KSO12/GPIO2C SPICS# EC_SPICS#/FSEL# 36
KSO13 52 KSO13/GPIO2D

2
KSO14 53
KSO15 KSO14/GPIO2E 17@ R186
R519 1
54 KSO15/GPIO2F CIR_RX/GPIO40 73 0--NDWG2
2 10K 0402 5% ENBKL KSO16 81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 Ra
KSO17 82 89 FSTCHG
FSTCHG 46
100K_0402_5% 7--NDWH1
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50
90 BATT_GRN_LED# 40

1
BATT_CHGI_LED#/GPIO52 AD PID0
CAPS_LED#/GPIO53 91 CAPS_LED# 40
EC SMB CK1 77 GPIO 92
47 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_AMB_LED# 40

2
EC SMB DA1 78 93 1
47 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_LED 40
EC SMB CK2 79 SM Bus 95 15@ R534 @ C309
8,22 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 43,50
EC SMB DA2 80 121 Rb
8,22 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 53
R460 0_0402_5% 127 ACIN 0_0402_5% 0.1U_0402_16V4Z
B AC_IN/GPIO59 ACIN 18,25,44 2 B
1 2 EC THERM# R
25 EC_THERM#

1
6 100 EC_RSMRST#
24 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03
24 PM_SLP_S5# 14 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 101 EC_LID_OUT# 24
24 EC_SMI# 15 EC_SMI#/GPIO08 EC_ON/GPXO05 102 EC_ON 39
16 LID_SW#/GPIO0A EC_SWI#/GPXO06 103 EC_SWI# 24
17 SUSP#/GPIO0B ICH_PWROK/GPXO06 104 EC_PWROK 39
18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# 30 3VALW Board ID <VB support>
19 EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09 106 WL_OFF# 37
30 EC_INVT_PWM 25 107 Please see page 3.
EC_THERM#/GPIO11 GPXO10
6 FAN_SPEED1 28 FAN_SPEED1/FANFB1/GPIO14 GPXO11 108

2
29 FANFB2/GPIO15
E51TXD_P80DATA 30 R219
E51RXD_P80CLK 31 EC_TX/GPIO16 @
EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 VGATE 53 Ra
EC_CRY1 EC_CRY2 32 112 100K_0402_5%
39 ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL 18
40 PWR_SUSP_LED 34 114 EAPD 41

1
PWR_LED#/GPIO19 GPXID3 EC THERM# R AD BID0
1 1 40 NUM_LED# 36 NUMLED#/GPIO1A GPI GPXID4 115
C344 C343 116
GPXID5 SUSP# 39,43,46,49
1

2
GPXID6 117 PBTN_OUT# 24 1
15P_0402_50V8J 15P_0402_50V8J 118 R215 C306
OUT
IN

2 2 GPXID7 EC_PME# 31
EC CRY1 122 Rb @ @
EC CRY2 XCLK1 8.2K_0402_5% 0.1U_0402_16V4Z
123 XCLK0 V18R 124
2
1

1
AGND

C674
NC

NC

GND
GND
GND
GND
GND

4.7U_0805_10V4Z
2

KB926QFD2_LQFP128_14X14 2
11
24
35
94
113

69

Y1 20mil L69
A
32.768KHZ_12.5P_MC-306 Chagne to D3 version ECAGND 1 2
A

FBMA-L11-160808-800LMT_0603

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 34 of 55
5 4 3 2 1
 For 17" For 15"
Left Right Left Right
SW4 SW5 SW2 SW3
17@ SMT1-05-A_4P 17@ SMT1-05-A_4P 15@ SMT1-05-A_4P 15@ SMT1-05-A_4P
BTN_L 3 1 BTN_R 3 1 BTN_L 3 1 BTN_R 3 1

4 2 4 2 4 2 4 2

5
6

5
6

5
6

5
6
TP_DATA C169 1 2 100P_0402_50V8J

TP_CLK C174 1 2 100P_0402_50V8J

TP_CLK BTN_R

TP_DATA BTN_L

2
D15
D14
TP/B Conn.
PJDLC05_SOT23-3 PJDLC05_SOT23-3

JTP1
5VS

1
5VS TP CLK 6
34 TP_CLK 5
TP DATA For ESD request For ESD request
34 TP_DATA 4
BTN L C137
BTN R 3
2 0.1U_0402_16V4Z
1 Change to SCA00000200
ACES_85201-0605
CONN@

KB1 for 15"

KSI[0..7]
KSI[0..7] 34,40 INT_KBD Conn.
KSO[0..17]
KSO[0..17] 34,40
KB2 for 17"

(Left) JKB1 (Left) JKB2

KSO15 C243 1 2 100P 0402 50V8J KSO7 C231 1 2 100P 0402 50V8J KSO0 26 28 KSO0 26 28
KSO1 KSO0 G2 KSO1 KSO0 G2
25 KSO1 G1 27 25 KSO1 G1 27
KSO14 C242 1 2 100P 0402 50V8J KSO6 C230 1 2 100P 0402 50V8J KSO2 24 KSO2 24
KSO3 KSO2 KSO3 KSO2
23 KSO3 23 KSO3
KSO13 C241 1 2 100P_0402_50V8J KSO5 C229 1 2 100P_0402_50V8J KSO4 22 KSO4 22
KSO5 KSO4 KSO5 KSO4
21 KSO5 21 KSO5
KSO12 C240 1 2 100P_0402_50V8J KSO4 C228 1 2 100P_0402_50V8J KSO6 20 KSO6 20
KSO7 KSO6 KSO7 KSO6
19 KSO7 19 KSO7
KSO8 18 KSO8 18
KSI0 C239 1 100P_0402_50V8J KSO3 C227 1 100P_0402_50V8J KSO9 KSO8 KSO9 KSO8
2 2 17 KSO9 17 KSO9
KSO10 16 KSO10 16
KSO11 C238 1 100P_0402_50V8J KSI4 C226 1 100P_0402_50V8J KSO11 KSO10 KSO11 KSO10
2 2 15 KSO11 15 KSO11
KSO12 14 KSO12 14
KSO10 C237 1 100P_0402_50V8J KSO2 C225 1 100P_0402_50V8J KSO13 KSO12 KSO13 KSO12
2 2 13 KSO13 13 KSO13
KSO14 12 KSO14 12
KSI1 C236 1 100P_0402_50V8J KSO1 C224 1 100P_0402_50V8J KSO15 KSO14 KSO15 KSO14
2 2 11 KSO15 11 KSO15
KSO16 10 KSO16 10
KSO17 KSO16 KSO17 KSO16
9 KSO17 9 KSO17
KSI2 C235 1 2 100P 0402 50V8J KSO0 C223 1 2 100P 0402 50V8J KSI0 8 KSI0 8
KSI1 KSI0 KSI1 KSI0
7 KSI1 7 KSI1
KSO9 C234 1 2 100P 0402 50V8J KSI5 C222 1 2 100P 0402 50V8J KSI2 6 KSI2 6
KSI3 KSI2 KSI3 KSI2
5 KSI3 5 KSI3
KSI3 C233 1 2 100P 0402 50V8J KSI6 C221 1 2 100P 0402 50V8J KSI4 4 KSI4 4
KSI5 KSI4 KSI5 KSI4
3 KSI5 3 KSI5
KSO8 C232 1 2 100P 0402 50V8J KSI7 C220 1 2 100P 0402 50V8J KSI6 2 KSI6 2
KSI7 KSI6 KSI7 KSI6
1 KSI7 1 KSI7
(Right) ACES_88747-2601
(Right) ACES_88747-2601
KSO16 C245 1 2 100P_0402_50V8J CONN@ CONN@

KSO17 C244 1 2 100P_0402_50V8J

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 35 of 55
 SPI Flash ROM 16M*1

3VALW 1 2 C675 1 2 0.1U 0402 16V4Z

R618 0_0603_5%

SPI VCC
U17

34 EC_SPICS#/FSEL# 1 CE# VDD 8

2 1 SPI WP# 3 6 EC SPICLK R R620 1 2 0 0402 5%
WP# SCK EC_SPICLK 34
3VALW R619 2 1 4.7K 0402 5% SPI HOLD# 7 5 EC SO SPI SI R R622 1 2 0 0402 5%
HOLD# SI EC_SO_SPI_SI 34
R621 4.7K_0402_5% 4 2 EC SI SPI SO R R623 1 2 0 0402 5%
VSS SO EC_SI_SPI_SO 34
MX25L8005M2C-15G_SOP8

SA00000XT00 : S IC FL 8M MX25L8005M2C-15G SOP 8P

ENE suggestion SPI Frequency over 66MHz
SST: 50MHz R257 C296
MXIC: 70MHz EC_SPICLK_R 1 2 1 2
ST: 40MHz @ 22_0402_5% @ 10P_0402_50V8J
ONLY MXIC used in this project (66MHz)
For EMI request
U44
EC SPICS#/FSEL# 1 8 SPI VCC
SPI WP# CS# VCC EC SPICLK R
3 WP# SCLK 6
SPI HOLD# 7 5 EC SO SPI SI
HOLD# SI EC SI SPI SO
4 GND SO 2
MX25L512AMC-12G_SO8
@
Reserved for BIOS simulator.
Footprint SO8
SPI ROM Footprint 150mil

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 36 of 55
 A B C D E

3VS_WLAN 1.5VS 3VALW

1 1 1 1 1 1
C442 C441 C439 C438 C440 C437
Mini Card Power Rating 4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2
1 Power Primary Power (mA) Auxiliary Power (mA) 1

Peak Normal Normal

+3VS 1000 750
+3VALW 330 250 250 (wake enable) For Wireless LAN
+1.5VS 500 375 5 (Not wake enable) 3VS_WLAN R487 1 2 0 1206 5% 3VS
R653 0_0402_5% JMINI2
24 SB_PCIE_WAKE# 1 2 1 1 2 2 3VS_WLAN
@ 3 4
3 4
5 5 6 6 1.5VS
16 MINI1_CLKREQ# 7 7 8 8
9 9 10 10
16 CLK_PCIE_MINI1# 11 11 12 12
16 CLK_PCIE_MINI1 13 13 14 14
15 15 16 16

17 18 R655 0_0402_5%
17 18 WL_OFF#_R 1
19 19 20 20 2 WL_OFF# 34
21 22 PLT_RST#
21 22 PLT_RST# 13,15,17,23,31,34
23 24 R246 1 2 0 0603 5% 3VS
12 PCIE_PTX_C_IRX_N0 23 24
25 26 R243 1 2 0 0603 5% 3VALW
12 PCIE_PTX_C_IRX_P0 25 26
27 28 @
27 28
29 29 30 30 SB_CK_SCLK 10,11,16,24
12 PCIE_ITX_C_PRX_N0 31 31 32 32 SB_CK_SDAT 10,11,16,24
12 PCIE_ITX_C_PRX_P0 33 33 34 34
2 35 36 2
35 36 USB20_N5 24
37 37 38 38 USB20_P5 24
3VS_WLAN 39 39 40 40
41 41 42 42
43 44 (MINI1_LED#) 1 2
43 44 WL_ON_LED# 40
45 45 46 46
47 48 R752 0_0402_5%
47 48

1
E51TXD_P80DATA R654 1 2 0_0402_5% E51TXD_P80DATA_R 49 50
34 E51TXD_P80DATA 49 50
E51RXD_P80CLK 51 52 R550
34 E51RXD_P80CLK 51 52 @100K_0402_5%
1

G1
G2
G3
G3
For MINICARD Port80 Debug

2
100K_0402_5% FOX_AS0B226-S99N-7F

53
54
55
56
R594 CONN@
2

3VALW

H:9.9mm

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 37 of 55
A B C D E
 A B C D E

USB CONN. 1 & 2

USB_VCCA USB_VCCA
1 W=80mils W=80mils 1

1 1
1 1
C478+ C474 C1 + C2
@
150U_D2_6.3VM 470P_0402_50V7K 150U_D2_6.3VM 470P_0402_50V7K
2 2 2 2
JUSB1 JUSB2
1 VCC 1 VCC
USB20_N0 @ R598 1 2 0_0402_5% USB20_N0_R 2 USB20_N1 @ R599 1 2 0_0402_5% USB20_N1_R 2
24 USB20_N0 D- 24 USB20_N1 D-
USB20_P0 @ R600 1 2 0_0402_5% USB20_P0_R 3 USB20_P1 @ R601 1 2 0_0402 5% USB20_P1_R 3
24 USB20_P0 D+ 24 USB20_P1 D+
4 GND 4 GND
5 GND1 5 GND1
L96 6 L95 6
GND2 GND2
4 4 3 3 7 GND3 4 4 3 3 7 GND3
8 GND4 8 GND4
1 2 SUYIN_020173MR004G565ZR 1 2 SUYIN_020173MR004G565ZR
1 2 CONN@ 1 2 CONN@
WCM2012F2S-900T04_0805 WCM2012F2S-900T04_0805

For EMI request For EMI request

2 2

3VALW

Add 10/26
1

R42 D31 R602

5VALW USB_VCCA USB20_N0_R USB20_N1_R_R USB20_N1_R
6 CH3 CH2 3 2
U4 100K_0402_5%
1 8 0_0402_5%
2

GND OUT
2 IN OUT 7 2 1 USB_OC#1 24
3 6 R171 10K_0402_5% R677 0_0402_5% USB_VCCA 5 2
IN OUT Vp Vn
1 4 EN# FLG 5 1 2 USB_OC#0 24
C111 1
TPS2061DRG4_SO8 C133 R603
4.7U_0805_10V4Z USB20_P1_R 1 2 USB20_P1_R_R 4 1 USB20_P0_R
2 0.1U_0402_16V4Z CH4 CH1
2 0_0402_5% CM1293-04SO_SOT23-6

For ESD request

43,49 SYSON# Add 10/26

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 38 of 55
A B C D E
 A B C D E

Power ON Circuit For South Bridge

3VS

3VALW 3VALW note:T1 minimum 15ms,T2 minimum 33ms/maximum 500ms,

SUSP# goes to low after SB_PWRGD goes to low for power

1
U13A U13B
R192 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 down.

14

14
1 180K_0402_5% T1 1

P
2
1 I O 2 3 I O 4 1 2 SB_PWRGD 24
R191 @ 0_0402_5% VLDT_EN

G
D
1
2 C322
43 SUSP

7
G NB_PWRGD
Q11 S 1U_0603_10V4Z
3
2N7002_SOT23 2
34 EC_PWROK 1 2
R198 0_0402_5% SB_PWRGD
T2
3VS SUSP#
For +1.2HT
3VALW 3VALW
+1.8VS

1
R195
U13C U13D

14

14
10K_0402_1% SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
D12

P
2
SUSP# 1 2 5 6 9 8 1 2
34,43,46,49 SUSP# I O I O VLDT_EN 43,48
2 R180 @ 0_0402_5%

G
CH751H-40PT_SOD323-2 C321

7
0.1U_0402_16V4Z 1 2
1 34 EC_VLDT_EN
R183 0_0402_5%

2 2

3VALW 3VALW
C565
1 2 0.1U_0402_16V4Z

U13E U13F
For +VGA_CORE
14

14

SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
R230 200K_0402_5% @
TOP Side
P

SUSP# 1 2 11 10 13 12 1 2 3VALW
I O I O VGA_ON 51
R231 0_0402_5% 2 @ 1
Power Button
G

2
1 2 C563 R765 10K_0603_5%
7

2
2 0.1U_0402_16V4Z
D23 @ 2 @ 1 R281
RB751V_SOD323 C564 SUSP# 1
1 2
0.22U_0603_16V4Z R229 0_0402_5% R766 10K_0603_5% 100K_0402_5%
1
Bottom Side

1
D10
2 ON/OFF 34
ON/OFFBTN# 1
40 ON/OFFBTN#
3 51ON#
51ON# 44
DAN202UT106_SC70-3

1
3 3
2
C358 D11
1000P_0402_50V7K RLZ20A_LL34
1

2
1
D Q17
EC_ON 2
34 EC_ON
G 2N7002_SOT23
R290 S

3
10K_0402_5%

SW10
SMT1-05-A 4P
1 3
ON/OFFBTN#
2 4

6
5
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 39 of 55
A B C D E
 To PWR LED/B
PWR_LED#
5VS 3VALW 5VALW 3VS

JP14
1

3
5VALW 5VS 3VS 3VALW
2
Q68B 3
2N7002DW-T/R7_SOT363-6 4
34 PWR_LED 5 5 LID SW# C435 C436 C444 C445
6 LID_SW# 34

1
TP LOCK LED#
TP_LOCK_LED# 34

4
R291 7 KSO0 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
8 KSO0 34,35
KSI2
9 KSI2 34,35
100K_0402_5% PWR SUSP LED#
10 PWR LED#

2
11 ON/OFFBTN#
12 ON/OFFBTN# 39
KSI1
13 KSI1 34,35
WL_ON_LED#
14 WL_ON_LED# 37
MEDIA_LED#
PWR_SUSP_LED# 15 NUM_LED#
16 NUM_LED# 34
CAPS_LED#
17 CAPS_LED# 34
18
19

6
20
Q68A ACES_85201-20051
2 2N7002DW-T/R7_SOT363-6 CONN@
34 PWR_SUSP_LED
1

1 3VS
R292 KSO0 Q67A

2
100K_0402_5% KSI1 WL_BTN# 2N7002DW-T/R7_SOT363-6
2

KSI2 TP_LOCK_BTN# 6 1 5IN1_LED# 33

KSI3 MEDIA LED# 3 4 SATA_LED# 25

LED1
KSI4 Q67B

5
R251 1K_0402_5% KSI5 2N7002DW-T/R7_SOT363-6 3VS
5VS 1 2 2 YG 1 PWR_LED#

R250 1.2K_0402_5%
KSI6
5VALW 1 2 4 A 3 PWR_SUSP_LED#

HT-297UD/CB BLUE/AMB
HARVATEK
LED2
R253 1K_0402_5%
5VALW 1 2 2 YG 1 BATT_GRN_LED# BATT_GRN_LED# 34
R252 1.2K_0402_5%
5VALW 1 2 4 A 3 BATT AMB LED# BATT_AMB_LED# 34

HT-297UD/CB BLUE/AMB
HARVATEK

BLUE/AMB LED

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 40 of 55
 A B C D E F G H

HD Audio Codec
1 2
L82 R784 0_0805_5%
MBK1608121YZF_0603
10mil 0.1U_0402_16V4Z 3VS_DVDD 1 2 3VS 5VAMP
U81
1
C905
1
C906
1
C907 5VS L80 1 2 60mil 1 IN
40mil
AVDD_HDA FBMA-L11-201209-221LMA30T_0805
1
OUT 5 VDDA 4.75V 1

C106

C899

C900
10U_0805_10V4Z 2
2 2 2 L81 1 GND
L83 1 2 0.1U 0402 16V4Z 40mil 2
FBMA-L11-201209-221LMA30T_0805
1 1 1
3 4 1 2
VDDA SHDN BYP
FBM-L11-160808-800LMT_0603 1 1 1 0.1U_0402_16V4Z C901

22U_0805_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C909 C910 @ @ G9191-475T1U_SOT23-5 @ 0.01U_0402_25V7K
C908 2 2 2
10U_0805_10V4Z

25

38

9
2 2 2 U82
0.1U_0402_16V4Z
(output = 300 mA)

AVDD1

AVDD2

DVDD_IO
DVDD
14 35 AMP_LEFT
LINE2_L LOUT1_L AMP_LEFT 42
AMP_RIGHT 3VS VDDA
15 LINE2_R LOUT_R 36 AMP_RIGHT 42
16 MIC2_L LOUT2_L 39

1
17 MIC2_R LOUT2_R 41

1
R783
23 45 D38 20K_0402_5%
LINE1_L SPDIFO2 R789
24 46 RB751V_SOD323 10K_0402_5%

2
LINE1_R DMIC_CLK1/2 C902
For EMI Request

2
18 43 1 2 MONO IN
LINE1_VREFO NC 1U_0402_6.3V4Z
20 LINE2_VREFO DMIC_CLK3/4 44 1 2 1 2 C914
R792 0_0402_5% 22P_0402_50V8J 1 2
2 19 R786 2
MIC2_VREFO

1
6 C 2.4K_0402_1%
BITCLK HDA_BITCLK_AUDIO 24 R787
MIC1 L 1 2 MIC1 C L 21 C903 1 2 1 2 2 Q72
42 MIC1_L MIC1_L 34 BEEP# B
C915 4.7U_0805_6.3V6K 1U_0402_6.3V4Z
MIC1 R 1 2 MIC1 C R 22 8 HDA SDIN0 R 1 2 560_0402_5% E
42 MIC1_R HDA_SDIN0 24

3
C916 4.7U_0805_6.3V6K MIC1_R SDATA_IN R793 33_0402_5% 2SC2411KT146_SOT23-3
MONO_IN 12 37
PCBEEP_IN MONO_OUT
MIC1_VREFO_L C904 1 R788
CBP 29 24 SB_SPKR 2 1 2
11 2.2U_0402_6.3V6M 1U_0402_6.3V4Z
24 HDA_RST_AUDIO# RESET#

1
31 C917 1 2 2 560_0402_5%
CPVEE R44 @
24 HDA_SYNC_AUDIO 10 SYNC 10mil 1
C990 10K_0402_5%
MIC1_VREFO 28 MIC1_VREFO_L
24 HDA_SDOUT_AUDIO 5 C918 1U_0402_6.3V4Z RB751V_SOD323 D37
SDATA_OUT HP_RIGHT 1
32 HP_RIGHT 42 2 2.2U_0402_6.3V6M

2
HPOUT_R
2 GPIO0/DMIC_DATA1/2
3 GPIO1/DMIC_DATA3/4 CBN 30
R794 2 1 20K_0402_1% SENSE_A 13 10mil
42 MIC_PLUG# SENSE A
R795 2 1 5.11K_0402_1% SENSE_B 34 27 CODEC_VREF
42 HP_PLUG# SENSE B VREF
1 1

10U_0805_10V4Z

0.1U_0402_16V4Z
34 EAPD 1 2 47 EAPD JDREF 40

20K_0402_1%

C919

C920
R796 0_0402_5%

1
48 33 HP LEFT
SPDIFO1 HPOUT_L HP_LEFT 42 2 2
Sense Pin Impedance Codec Signals
R797
4 DVSS1 AVSS1 26
7 DVSS2 AVSS2 42
39.2K PORT-A (PIN 39, 41)
ALC272-VA2-GR_LQFP48_7X7 2
3 Change to ALC272X 3
AGND 20K PORT-B (PIN 21, 22)
DGND SENSE A
10K PORT-C (PIN 23, 24)

5.1K PORT-D (PIN 35, 36)

1 2 1 2
R798 0_0805_5% R799 0_0805_5%
39.2K PORT-E (PIN 14, 15)
1 2 1 2
R800 0_0805_5% R801 0_0805_5% 20K PORT-F (PIN 16, 17)
C992 C991
SENSE B
1 2 1 2 10K PORT-G (PIN 43, 44)
0.1U_0402_16V4Z 0.1U_0402_16V4Z
5.1K PORT-H (PIN 45, 46)

GND GNDA GND GNDA

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 41 of 55
A B C D E F G H
 A B C D E

TPA6017 Medium Range Amplifier

5VAMP
0.1U_0402_16V4Z
Left Connector
JSPK1
SPKL R804 1 2 0_0603_5% SPK_L 1
SPKL- R805 1 1
1 1 2 0_0603_5% SPK_L- 2 2
20mil Left

2
C921 C922
10U_0805_10V4Z D39 3
2 2 G1
4 G2
@
ACES_88266-02001
1 10 dB PJDLC05_SOT23-3 CONN@ 1
5VAMP

1
16
15

1
6
U83 R809 @ R806
100K_0402_5% 100K_0402_5%

VDD
PVDD1
PVDD2
Right Connector For ESD request

2
C923 1 2 0.47U_0603_10V7K 7 2 GAIN0
RIN+ GAIN0
JSPK2
3 GAIN1 SPKR R810 1 2 0_0603_5% SPK_R 1
GAIN1 SPKR- R807 1 1
2 0_0603_5% SPK_R- 2 2

1
1 2 1 2 AMP_C_RIGHT 17 20mil
41 AMP_RIGHT RIN- Right

2
C924 3900P_0402_50V7K R808 0_0603_5% 18 SPKR @ R811 R812
ROUT+ 100K_0402_5% 100K_0402_5% D40 3 G1
4 G2
14 SPKR- @

2
C925 1 ROUT-
2 0.47U_0603_10V7K 9 LIN+
ACES_88266-02001
PJDLC05_SOT23-3 CONN@
4 SPKL
LOUT+
1 2 1 2 AMP_C_LEFT 5

1
41 AMP_LEFT C971 3900P_0402_50V7K R813 0_0603_5% LIN- SPKL-
LOUT- 8

For ESD request

NC 12
2 2

EC MUTE# BYPASS 10 Keep 10 mil width

34 EC_MUTE# 19 SHUTDOWN
2

GND5
GND1
GND2
GND3
GND4
C927
0.47U_0603_10V7K
1
21
20
13
11
1
TPA6017A2_TSSOP20
LINE Out/Headphone Out
JHP1
8
7
2 2
C928 C929
HP_PLUG# 5
41 HP_PLUG#
20mil 330P_0402_50V7K 330P_0402_50V7K
1 1
4

41 HP_RIGHT HP RIGHT 1 2 HPOUT R 1 1 2 HPOUT R 2 3

R814 56.2_0402_1% L84 FBM-11-160808-700T_0603 6
41 HP_LEFT HP LEFT 1 2 HPOUT L 1 1 2 HPOUT L 2 2
R815 56.2_0402_1% L85 FBM-11-160808-700T_0603 1
SINGA_2SJ-E351-S03
CONN@
3 3

MIC1_VREFO_L MIC1_VREFO_L

LINE IN/Ext.MIC JACK

2
RB751V_SOD323 RB751V_SOD323 JMIC1
D41 D42 8
7

1 1

1 1
MIC PLUG# 5
41 MIC_PLUG#
R816 R817
4.7K_0402_5% 4.7K_0402_5% 4

2
41 MIC1_R 1 2 1 2 FBM 11-160808-700T 0603 MIC2 R 1 3
R818 1K_0603_1% L86 6
41 MIC1_L 1 2 1 2 FBM 11-160808-700T 0603 MIC2 L 1 2
R819 1K_0603_1% L87 1
1 1
SINGA_2SJ-E351-S01
C930 C931 CONN@
220P_0402_50V7K 220P_0402_50V7K
4 2 2 4
(HDA Jack)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 42 of 55
A B C D E
 A B C D E

5VALW

+3VALW TO +3VS +5VALW TO +5VS

2
3VS R167
10K_0402_5%
5VALW 5VS
1 1 U7

1
3VALW C559 C562 8 1 SUSP
D S 39 SUSP
7 D S 2
U41 10U_0805_10V4Z 1U_0603_10V4Z 6 3 1 1
2 2 D S C166 C165
8 D S 1 5 D G 4

1
R508 D Q12
1 7 D S 2 1
6 3 100K_0402_5% 1 AO4468_SO8 10U_0805_10V4Z 1U_0603_10V4Z 2
D S 2 2 34,39,46,49 SUSP#
5 4 1 2 5VS GATE 1 2 VSB G 2N7002_SOT23
D G

1
R562 20K_0402_1% C143 S

3
AO4468_SO8 4.7U_0805_10V4Z R586

6
2 10K_0402_5%
1 R728 0_0402_5%
2

C560 1 2 5VS GATE

2
C570 2 SUSP
10U_0805_10V4Z 0.1U_0603_25V7K Q14A
1

2
2 2N7002DW-T/R7_SOT363-6

1
C658
0.1U_0603_25V7K

1
5VALW

2
R31
10K_0402_5%

1
SYSON#
38,49 SYSON#

+1.2VALW TO +1.2V_HT

1
D Q5
SYSON 2
+1.8V TO +1.8VS 1.2V_HT 34,50 SYSON
G 2N7002_SOT23

1
2 S 2

3
1.8V
1.2VALW R589
U37 1 1 100K_0402_5%
8 1 1.8VS C756 C757

2
D S

2
7 D S 2
6 3 U46 1U_0603_10V4Z 10U_0805_10V4Z R698 1.2VALW
D S 2 2 470_0805_5%
5 D G 4 1 1 8 D S 1
C447 C446 7 2
AO4430_SOIC8 D S
6 3 1

1
10U_0805_10V4Z 1U_0603_10V4Z D S
1 5 D G 4 1 2 VSB
2 2 R699 + C30
1
C443 AO4430_SOIC8 33K_0402_5% 220U_B2_2.5VM_R25M 5VALW

3
4.7U_0805_10V4Z 1
2 C759 2

2
R549 0.1U_0603_25V7K 2
100K_0402_5% C758 VLDT_EN# 2N7002DW-T/R7_SOT363-6 R725
2 5
2 Q63A Q63B
1 R563 2 1 2 VSB For PWR request 10K_0402_5%
60.4K_0402_1% 4.7U_0805_ 0V4Z 2N7002DW-T/R7_SOT363-6

1
2

VLDT EN#
C632 Q30
1

0.1U_0603_25V7K D
1

3
2 SUSP
G
S 2N7002_SOT23-3 2N7002DW-T/R7_SOT363-6
3

VLDT EN 5
39,48 VLDT_EN Q10B

4
3 3
R726
100K_0402_5%

2
0.9V 2.5VS 1.5VS 1.8V 3VS 1.8VS 5VS NB_CORE 1.1VS
2

2
2

2
R224 R270 R181 R184
R604 R587 R588 R26 470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5% R185
470_0805_5% 470_0402_5% 470_0402_5% 470_0805_5% 470_0805_5%
1

1
1

1
3

6
1

1
D D D
2 SYSON# 5 SUSP 2 SUSP 2 SYSON# 5 SUSP 5 SUSP 2 SUSP 2 VLDT EN# 2 SUSP
G G G
S Q34 Q13B S Q36 Q6A Q14B Q6B Q10A Q13A S Q16
3

3
2N7002_SOT23 2N7002DW-T/R7_SOT363-6 2N7002_SOT23 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002_SOT23

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 43 of 55
A B C D E
 A B C D

DC231000500
<BOM
PJP1 Structure> PR1
SINGA_2DC-G756I200 ADPIN PL1 VIN 1M_0402_5%
SMB3025500YA_2P 1<BOM Structure>
2
1 1 2 VIN VIN
VS
@ PR2

1
G 2 10K_0402_5%

560P_0402_50V7K

12P_0402_50V8J
G PR3
46,52 PACIN

560P_0402_50V7K
84.5K_0402_1%

12P_0402_50V8J
3

1
PC1
PR5

8
PC2

PC3

PC4
PR6 PR4 22K_0402_5%

2
0_0402_5% 10K_0402_5% 3 1 2

P
2

2
+
1<BOM Structure>
2 1 2 1 0
18,25,34 ACIN

20K_0402_1%
- 2

1
PR7
PU1A

1
PC6
0.1U_0603_25V7K
LM358DT_SO8 PC5

4
PR8 PD1 1000P_0402_50V7K

2
10K_0402_5% GLZ4.3B_LL34-2

2
2

2
PR9
10K_0402_5%
1 2
RTCVREF

- PBJ1 +
RTCBATT
2 1
RTCBATT
Vin Dectector
Min. Typ Max.
ML1220T13RE H-->L 16.976V 17.525V 17.728V
2 45@ 2

L-->H 17.430V 17.901V 18.384V

VIN

2 PD2
LL4148_LL34-2 PJ1 PJ2
+3VALWP 2 2 1 1 +3VALW +1.5VSP 2 2 1 1 +1.5VS
PD3
1

LL4148_LL34-2 JUMP_43X118 JUMP_43X118

BATT+ 2 1
1

PR10 PR11
PQ1 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3 PJ3 PJ4
PR12 2 1 2 1
+5VALWP +5VALW +0.9VP +0.9V
2

200_0603_5% 2 1 2 1
CHGRTCP 1 2 N1 3 1 JUMP_43X118 JUMP_43X79
VS
1

3 PR13 PC8 3
PJ5
100K_0402_1% PC7 0.1U_0603_25V7K PJ6
0.22U_0603_25V7K 2 1 +1.8VP 2 1 +1.8V
+VSBP +VSB
2

PR14 2 1 2 1
2

22K_0402_1% JUMP_43X39 JUMP_43X118

1 2
39 51ON#
PJ9
2 2 1 1
PJ7
2 1 JUMP_43X118
+1.2VALWP 2 1 +1.2VALW
RTCVREF
1

JUMP_43X118
PR15
PU2 200_0603_5%
PR16 PR17 G920AT24U_SOT89-3
560_0603_5% 560_0603_5% 3.3V PJ21 PJ8
2

1 2 1 2 3 2 N2 2 1 +1.1VSP 2 1 +1.1VS
OUT IN +NB COREP 2 1 +NB CORE 2 1
+CHGRTC
JUMP_43X118 JUMP_43X118
1

GND PC10
PC9 1U_0805_25V4Z
10U_0805_10V4Z 1
2

PJ17 PJ15
+VGA COREP 2 2 1 1 +VGA CORE +2.5VSP 2 2 1 1 +2.5VS
JUMP_43X118 JUMP_43X118
PJ18
2 2 1 1
4 4

JUMP_43X118

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 44 of 55
A B C D
 A B C D

ISL6237_B+
ISL6237_B+
PJ10 PR36
JUMP 43X118 0_0805_5%
2 2 1 1 1 2
B+

2200P_0402_50V7K

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
1

5
6
7
8
PC20

PC21

PC22
@ PC126

8
7
6
5

1
PC25
680P_0402_50V7K VL

PC23

PC24
1U_0603_10V6K
2

2
PQ6

2
2
PQ5 PC26 AO4466_SO8

2
AO4466_SO8 0.1U_0603_25V7K

4.7U_0805_6.3V6K
4

1
PC27
4

PC28
1
+5VALWP

3
2
1
PL3

1
2
3
PL4 10UH_MSCDRI-104A-100M-E_4.6A_20%

7
10UH_MSCDRI-104A-100M-E_4.6A_20% PC29 2 1
1 2 1U_0603_10V6K

LDO
VIN

VCC
+3VALWP 33 19 1 2
TP PVCC

5
6
7
8

1
4.7_1206_5%
1

8
7
6
5

PR41
DH3 26 15 DH5
PR37 PR38 UGATE2 UGATE1 PR39 2.2_0603_5% PQ8
4.7_1206_5% PQ7 2 1 BST3A 24 17 BST5A 2 1 AO4712_SO8
BOOT2 BOOT1
2

1 AO4712_SO8 2.2_0603_5%

2
2

63.4K_0402_1%
PR40 PC32 4

2
PC30 + 0_0402_5% 4 PC31 0.1U_0603_25V7K

2
680P_0402_50V7K
330U_6.3V_M 0.1U_0603_25V7K

1
1

PR42
<BOM Structure> LX3 25 16 LX5 1
1

2 PHASE2 PHASE1

PC34
PC33

3
2
1

2
680P_0402_50V7K + PC35

1
2
3
DL3 23 18 DL5 330U_6.3V_M

1
LGATE2 LGATE1
2
2 2
2

10K_0402_1%
PGND 22

2
FB3 30 OUT2

PR44
@ PR43
10K_0402_1% 10
OUT1
VL 32
1

REFIN2

1
11 FB5
2VREF ISL6237 FB1

1 2 1 REF
PC36 0.22U_0603_10V7K
BYP 9
8 LDOREFIN
+3.3VALWP Ipeak=4.26A ; Then set Imax=4.26A @ PR45 0_0402_5%
29 2 1 VL
Choke DCRmax=26.5m ohm, DCRtyp=23m ohm SKIP
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) PR46 0_0402_5%
1 2
Vlimit=(5E-06 * 316K)/10=158mV 20 28
PD6 PR47 NC POK2
Ilimit=158mV/(18m*1.2) ~ 158mV/15m
GLZ5.1B_LL34-2 100K_0402_1%
=7.31A~10.53A 1 2 1 2 4 13 SPOK 47,50
Iocp=Ilimit+Delta I/2 VS EN_LDO POK1 PR49
2
200K_0402_5%

365K_0402_1%
=7.76A~10.98A
2
PR48

14 12 ILM1 2 1
EN1 ILIM1
Delta I=0.908A (Freq=300KHz) PC37
0.22U_0603_25V7K
1

27 31 ILIM2 2 1

GND
3 3

TON
1

EN2 ILIM2
1

NC
2

0_0402_5%
PD7 PR50
VL
2
@ PR51 PU4 316K_0402_1%

21
PR52
0_0402_5% ISL6237IRZ-T_QFN32_5X5
2

1SS355_SOD323-2
2

PR53
1

1
1U_0603_10V6K
806K_0603_1%
2VREF_ISL6237 1

@ PR56
check this part PR55 PR54
+5VALWP Ipeak=6.87A ; Imax=4.81A
1

2
0_0402_5% 47K_0402_5% PC38 0_0402_5%
2 1 1 2 Choke DCRmax=26.5m ohm, DCRtyp=23m ohm

2VREF ISL6237 2
1
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
0.047U_0603_16V7K

8,47,52 MAINPWON
Vlimit=(5E-06 * 365K)/10=182.5mV
1

PC39

Ilimit=182.5mV/(18m*1.2) ~ 182.5mV/15m
2

=8.44A ~ 12.16A
1

@ PC40 Iocp=Ilimit+Delta I/2

3

0.047U_0402_16V7K
2

=8.90A ~ 12.62A
Delta I=0.921A (Freq=400KHz)
2 PQ9
TP0610K-T1-E3_SOT23-3

4 4
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 45 of 55
A B C D
 A B C D

P2
PQ10 PQ11
P3 B+ CHG B+ B+
AO4407A_SO8 AO4407A_SO8 PR57 0.02_2512_1%
VIN 8 1 1 8 PJ24
7 2 2 7 1 4 2 2 1 1
6 3 3 6
5 5 2 3 JUMP_43X118 CSIN
PQ12 AO4407A_SO8

5600P_0402_25V7K

2200P_0402_25V7K
10U_1206_25V6M

10U_1206_25V6M

0.1U_0603_25V7K
4

4
CSIP 1 8

1
PC354

PC357
2 7

PC355

PC356

PC358
PQ58 TP0610K-T1-E3_SOT23-3 3 6
1

2
1
PR358 3 1 DCIN
P3

0.1U_0603_25V7K
47K_0402_1% PR361

4
1

1
100K_0402_1%
PR359 47K_0402_1%
VIN

PC359
200K_0402_1% PQ60 1 2
2

1
PR360
PDTC115EU_SOT323

2
PD12

2
PD11 1SS355_SOD323-2

2
3

PR362 2 FSTCHG PR363 1 2 ACOFF

2
47K PQ61 2 1 2 1 10K_0402_1%
PDTA144EU_SOT323 3 3 SUSP#
2 47K PD13 100K_0402_1% SUSP# 34,39,43,49 PR364

1 1
1SS355_SOD323-2 BAS40CW_SOT323-3 200K_0402_1%
1 2 1 2 VIN

3
6251VDD PD14
1

2.2U_0603_6.3V6K
1SS355_SOD323-2

PC360
PQ62 PR366 PQ63
1

1
PDTC1 5EU_SOT323 10K_0402_5% PDTC115EU_SOT323 2 1 2
FSTCHG 2 1 PU19 PC362
2 PR365 34 FSTCHG 0.1U_0603_25V7K

2
150K_0402_1% 1 2 1 24 DCIN 2 1
VDD DCIN

100K_0402_1%

0.1U_0603_25V7K
PR367 47K_0402_5% PC361
2

3
1

1
PQ64 D 6251VDD .1U_0402_16V7K PQ66D
1 2

1
PR368

PC363
2 <BOM Structure> 2 23 2 PACIN
3

ACSET ACPRN

1
G 2N7002W-T R7_SOT323-3 PR369 2N7002W-T/R7_SOT323-3
G
S PQ65 20_0402_5% S
3

3
PDTC115EU_SOT323 6251 EN 3 22 1 2 CSON
EN CSON

2
PC364

5
6
7
8
2 0.047U_0402_16V7K
34 3S/4S#
1

PQ67 D CSOP PQ68

4 CELLS CSOP 21 1 2
2 PR370 AO4466_SO8
G 2N7002W-T/R7_SOT323-3 PC365 6800P_0402_25V7K 20_0402_5%
S 1 2 5 20 2 1
3

3
ICOMP CSIN

2
PR371
ACON PC367 20_0402_5%
4 <40,41>
52 ACON
2
1 2 1 PR372 2 10K 0402 1% 6 19 0.1U 0603 25V7K
1 2 TCR=50ppm / C 2

1
PR375 VCOMP CSIP PR373 PL23
PR374 PC366 1 2 100_0402_1% 2_0402_5% 10UH_PCMB104T-100MS_6A_20% BATT+

3
2
1
22K_0402_5% 0.01U_0402_25V7K @ PC368 1 2 7 18 LX_CHG 1 2 CHG 1 4 PR64
ICM PHASE

4.7_1206_5%
PACIN 1 2 100P_0402_50V8J
44,52 PACIN

5
6
7
8

1
34 ADP I 2 3 0.02_2512_1%

PR377
PC369 6251VREF 8 17 DH_CHG
VREF UGATE
1

PQ69 PR378 1 2 PR379 PC370

10U_1206_25V6M

10U_1206_25V6M
PDTC115EU_SOT323 80.6K_0402_1% 0_0603_5% 0.1U_0603_25V7K
2 1 .1U_0402_16V7K 9 16 BST_CHG 1 2 BST_CHGA 2 1 PQ70 @

2
34 IREF CHLIM BOOT
0.01U_0402_25V7K

4 AO4466_SO8
1

1
PC372

PC374
ACOFF 2 PR381 PD15
34,52 ACOFF

680P_0402_50V7K
PC371

PR380 6251VREF 1 2 6251ACLIM 10 15 6251VDDP RB751V-40_SOD323-2

ACLIM VDDP

PC373
C373
100K_0402_1%
2

2
1
2.55K_0402_1%
PR383
12.1K_0402_1% 20K_0402_1% 1 26251VDD

3
2
1

2
PR384 11 14 DL_CHG @
@P
3

VADJ LGATE

2
PR382
4.7_0603_5%
12 13 PC375
2

1
GND PGND 4.7U_0603_6.3V6M
PQ71
2
1

2N7002W-T/R7_SOT323-3 D ISL6251AHAZ-T_QSOP24
2
34 65W/90W# G
S
3

3
PR385 3

15.4K_0402_1%
CP mode 34 CALIBRATE#
1 2 LI-3S :13.5V----BATT-OVP=2.007V
2

Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) PR386
BATT-OVP=0.1487*VMB
where Vaclm=1.502V, Iinput=4.07A VMB
31.6K_0402_1% Per cell=3.5V
VS
1

1
Ki

0.01U_0402_25V7K
Vchlim=Iref*(PR374/(PR372+PR374)) PR79
CC=0.6~4.48A =Iref*(100K/(80.6K+100K)) Input OVP : 22.3V 340K_0402_1%
=Iref*0.5537
Iref=0.7224*Ichanrge

2
1
Ichanrge=(165mV/PR369)*(Vchlim/3.3V)

PC67
=(165m/20m)*(1/3.3V)*Iref*0.5537
Input UVP : 17.26V
=>Ki=0.7224

1
=1.3842*Iref
Fsw : 300KHz

2
Iref=0.7224*Ichanrge =>Ki=0.7224 PU1B PR83
IREF=0.43V~3 24V LM358DT_SO8 499K_0402_1%
Kv

8
Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K PR85

2
R=514K//31.6K//(15.4K+3k)=11.372K 10K_0402_5% 5

P
34 BATT OVP +

105K_0402_1%
r=514K//514K//31.6K=28.14K

0.01U_0402_25V7K
1 2 7 0

1
Vcell=0.175*Vadj+3.99v 6
-

1
G
4.2V=0.175*Vadj+3.99V =>Vadj=1.2V

PR91

PC69
Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K))

4
1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899

2
1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv

2
A=Vref*(R/(R+514K))=0.052
Kv=9.451
Charging Voltage
BATT Type CV mode
4
(0x15) 4

Normal 3S LI-ON Cells

12600mV 12.60V
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date Thursday, March 18, 2010 Sheet 46 of 55
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 92 degree C

VL
VL
VL
VMB

2
PJP2
SUYIN_250133MR007G115ZL PL2 PR18

1
SMB3025500YA_2P 47K_0402_1%
1 1 BATT_S1 1 2 BATT+ PC11
MAINPWON 8,45,52
2 PH1 0.1U_0603_25V7K PR19

1
2 100K_0402_1%_NCP15WF104F03RC 47K_0402_1%
3 3

1
4 EC_SMCA 1 2

2
4 EC SMDA PC12 PC13 PR20
5 5

8
6 1000P_0402_50V7K 0.01U_0402_25V7K 12.4K_0402_1%

2
6

1
PD4 PQ21 D
7 1 2 3

P
7 +
8 8 O 1 2 1 2
9 TM REF1 2 G 2N7002W-T/R7_SOT323-3
9 -

2
PU3A LL4148_L 34-2 S

3
PR25 LM393DG_SO8 PR92

4
6.49K_0402_1% 1M_0402_1%
2

0.22U_0603_16V7K
2 1 3VALWP
PR21 PR22

1
15.8K_0402_1%
100_0402_1% 100_0402_1%

1
PC14
PR24
1

1000P_0402_50V7K
PR23
100K_0402_1%
1

PR27 2 1 VL

1
1K_0402_1%

PC15
2
2

1
2 2
BATT_TEMP 34
PR26
EC_SMB_CK1 34
100K_0402_1%
EC_SMB_DA1 34

2
PJP3

1 1 2 2

3 3 4 4

5 5 6 6

7 7 8 8 PH2 near main Battery CONN :

EC SMCA 9 9 10 10 BAT. thermal protection at 75 degree C
11 12 EC SMDA
11 12
13 13 14 14
VL
15 15 16 16

2
17 17 18 18
@ PR28
19 20 VL 47K_0402_1%
19 20 @ PR29
SUYIN_200109MS020G209ZR 47K_0402_1%

1
1 2

1
3 PQ3 3

TP0610K-T1-E3_SOT23-3 @ PH2
100K_0402_1%_NCP15WF104F03RC
VL

B+ 3 1 +VSBP

2
0.22U_0603_25V7K

0.1U_0603_25V7K

@ PR31
1

8
6.49K_0402_1% @ PD5
1

1
PC16

PC17

PR30 1 2 5 LL4148_LL34-2

P
100K_0402_1% +
O 7 2 1
@ @ TM REF1 6
2

G
PR32 PU3B
2

1
VL 22K_0402_1% LM393DG_SO8

4
1 2 @ PC18 @ PR33
0.22U_0603_16V7K 22.1K_0402_1%

2
2

PR34
100K_0402_1%

PR35
1

0_0402_5% D
1 2 2 PQ4
45,50 SPOK G 2N7002W-T/R7_SOT323-3
0.1U_0402_16V7K

S
3
1

PC19

@
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 47 of 55
A B C D
 5 3 2 1

PJ16
NB 51117 B+ 2 1
2 1
B+

10U_1206_25VAK
JUMP_43X118

D D

PC206
5

2
PR246 4
267K_0402_1%
1 2
PQ35
SIS412DN-T1-GE3_POWERPAK8-5

3
2
1
BST_NBCOREP
PC209
PR247 PR248 0.1U_0603_25V7K PL13

15

14
+NB_COREP

1
1.3K_0402_5% PU12 0_0603_5% 1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
1 2 1 2BST_NBCOREP_11 2 1 2

BOOT
NC
EN/DEM
39,43 VLDT_EN 1

PR249 2 13 DH NBCOREP
TON UGATE

1
47K_0402_5% PC208
0.1U_0402_16V7K 3 12 LX NBCOREP PR250
2

VOUT PHASE

5
4.7_1206_5%
2

4 11 +5VALW
VDD CS PQ36 + PC210

2
5 10 SI7686DP-T1-E3_SO8 330U_D2E_6.3VM_R25M
FB VDDP

1
DL NBCOREP 2
6 PGOOD LGATE 9 4

PGND
PC211

GND
PR251 680P_0603_50V8J

2
1
<BOM Structure>
100_0603_1%

1
+5VALW 1 2 @ PC213
@PC213 RT8209BGQW_WQFN14_3P5X3P5 PC212

3
2
1
C 47P_0402_50V8J 4.7U_0805_10V6K C

2
1 2 PR252
1

6.81K_0402_1%
PC214

2
4.7U_0603_6.3V6K
Rds=4m ohm(typ)
2

PR253 4.8m ohm(max)

3.57K_0402_1%
1 2
1

PR255
PR254 30K_0402_1% +3VS
10K_0402_1%
2

2
PR256
PR257 10K_0402_5%
1

D 10K_0402_1%

1
PQ31 2 1 2
2N7002W-T/R7_SOT323-3 G
2

VFB=0.75V S +1.2VALW
3

B @ PR258 B
Rton=267K, Freq=298KHz 10K_0402_1% +3VS
PC215
2

2
0.1U_0402_16V7K +5VALW
Ipeak=8.9A Imax=6.23A
1

1
Delta I=((19-1.1)*(1.1/19))/(1.8U*298K)=1.93A @ PR259
@PR259 PJ22

1
Rtrip=6.81K 10K_0402_5% JUMP_43X79
1/2DeltaI=0.96A @
1

2
Rdson=4.5m~5.6m BOM control (R*C>1ms) PC227

2
Iocp=10.79A~17.59A PR260 1U_0402_6.3V6K

2
1

D
10K_0402_1%
PQ32 2 1 2 POWER SEL
POWER SEL 13

1
2N7002W-T/R7_SOT323-3 G PC230
S 4.7U_0805_6.3V6K
3

6
PU15

2
@PR261
@ PR261 5

VCNTL
10K_0402_1% VIN
7 POK
VOUT 4 +1.1VSP

H 1.017V
1

0.01U_0402_25V7K
PR273 3
VOUT

22U_0805_6.3V6M
PC226
12_0402_5%

PC229
VLDT_EN 1 2 8 2
39,43 VLDT_EN EN FB

1
PR272

GND

2
1
9 1.3K_0402_1%
L 1.1V PC228 PR270 VIN

2
1U_0603_10V6K 10K_0402_5% APL5912-KAC-TRL_SO8

1
2

1
A PR271 A
3.24K_0402_1%

2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date Thursday March 18 2010 Sheet 48 of 55
5 3 2 1
 5 4 3 2 1

+1.8V

1
PJ14

1
D JUMP_43X79 D

2
PU9

2
1 VIN VCNTL 6 +3VALW
2 GND NC 5

1
1
PC91 3 7 PC92
4.7U_0805_6.3V6K PR118 REFEN NC 1U_0402_6.3V6K

2
1K_0402_1% 4 8
VOUT NC
9

2
GND
RT9173DPSP_SO8
@ PR119 @ PQ30
+0.9VP

1
0_0402_5% 2N7002W-T/R7_SOT323-3 D

38,43 SYSON# 1 2 2 PR120

1
G 1K_0402_1% PU7

2
1
S PC93 PC95 APL5508-25DC-TRL_SOT89-3

3
@ PC94 0.1U_0402_ 6V7K 10U_0805_6.3V6M

2
0.1U_0402_16V7K 2 3
+3VS

2
IN OUT
+2.5VSP

1
GND

1
PC78
1U_0402_6.3V6K 1 PC79 @ PR93
4.7U_0805_6.3V6K 150_1206_5%

2
C C

2
+1.8V

+5VALW

11
PJ19
JUMP_43X79
1

2
PC83
1U_0402_6.3V6K

2
2
6

5 1 PC84
VCNTL

VIN 4.7U_0805_6.3V6K
7 POK
4
2

VOUT
PR94 3
100K_0402_5% VOUT
+1.5VSP
1
34,39,43,46 SUSP# 1 2 8 EN FB 2

1
GND

9 PR102 PC85
VIN
1

1.54K_0402_1% 0.01U_0402_25V7K

1
B PR103 PC86 PC87 B
1

47K_0402_5% 0.1U_0402_16V7K PU8 22U_0805_6.3V6M

2

APL5915KAI-TRL_SO8

2
1
2

PR104
1.74K_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 49 of 55
5 4 3 2 1
 5 4 3 2 1

PJ12
1.8_51117_B 2 1
2 1
B+

5
6
7
8
JUMP_43X118

1
PC70
10U_1206_25VAK

2
PR95
267K_0402_1% 4
PR96 1 2 PQ24
0_0402_5% AO4466_SO8
1 2
D 34,43 SYSON D

3
2
1
PR97 PC71 PL8
0_0603_5% 0.1U_0603_25V7K 1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%

15

14
1

1
VFB=0.75V @PC72
@PC72
PU6 BST 1.8V 1 2BST 1.8V-1 1 2 1 2 +1.8VP

EN/DEM

BOOT
NC
Vo=VFB*(1+PR111/PR112)=0.75*(1+14K/10K)=1.8V 0.1U_0402_16V7K

2
2 13 DH 1.8V
Rton=267K=>Faw=297KHz TON UGATE

1
3 12 LX_1.8V 1
VOUT PHASE

5
6
7
8
@ PR160
VFB=0.75V PQ25 4.7_1206_5% + PC73
4 VDD CS 11 +5VALW AO4456_SO8 330U_6.3V_M
5 10

2
FB VDDP 2
6 9 DL_1.8V 4
PGOOD LGATE

PGND
PR98

GND

1
100_0603_1% @ PC119
1 2 @ PC75 PC74 680P_0402_50V7K
+5VALW 47P_0402_50V8J RT8209BGQW_WQFN14_3P5X3P5 4.7U_0805_10V6K

3
2
1

2
1 2
1 PR99

2
PC76 9.76K_0402_1%
4.7U_0603_6.3V6K
2

Cout ESR=15m ohm

Ipeak=11.96A, Imax=8.372A PR100
2.87K_0402_1%
Delta I=((19-1.8)*(1.8/19))/(L*Fsw)
1 2
((19-1.8)*(1.8/19))/(1.8u*297000)=3.048A
C =>1/2DeltaI=1.524A C
1

Rtrip=9.76K
Iocp=15.20A~24.71A PR101
2.05K_0402_1%
2

PJ25
1.2 51117 B 2 2 1 1 B+
JUMP_43X118

1
PC90
PQ26 10U_1206_25VAK
SI7686DP-T1-E3_SO8

2
PR114
B 267K_0402_1% B
PR115 1 2 4
0_0402_5%
1 2
45,47 SPOK

3
2
1
PR116 PC97 PL9
0_0603_5% 0.1U_0603_25V7K 1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
15

14
1

@PC96
@PC96
PU10 BST_1.2V 1 2BST_1.2V-1 1 2 1 2 +1.2VALWP
EN/DEM

BOOT
NC

0.1U_0402_16V7K
2

1
2 13 DH_1.2V
TON UGATE @ PR203
VFB=0.75V 3 12 LX_1.2V 4.7_1206_5% 1
VOUT PHASE

5
Vo=VFB*(1+PR119/PR120)=0.75*(1+6.04K/10K)=1.203V +
4 VFB=0.75V 11 +5VALW PQ27 PC98

1 2
Rton=267K=>Fsw=298KHz VDD CS SI7636DP-T1-E3_SO8 330U_D2E_2.5VM
5 10 @ PC172
FB VDDP 680P_0402_50V7K 2
6 9 DL 1.2V 4

2
PGOOD LGATE G
PGND

PR117
GND

100_0603_1%

S
S
S
1 2 @ PC100 PC99
+5VALW 47P_0402_50V8J RT8209BGQW_WQFN14_3P5X3P5 4.7U_0805_10V6K
7

3
2
1
1 2
1

PR105
2

PC101 8.66K_0402_1%
4.7U_0603_6.3V6K
Rds=4m ohm(typ)
2

A 4.8m ohm(max) A
1.2VP Ipeak=7.4A ; Imax=5.180A PR106
3.24K_0402_1%
Delta I=((19-1.2)*(1.2/19))/(L*Fsw) 1 2
((19-1.2)*(1.2/19))/(1.8u*298000)=2.10A
=>1/2DeltaI=1.05A
1

Rdson=15m/18m ohm Security Classification Compal Secret Data Compal Electronics, Inc.
set Rtrip=8.66K PR107 2009/09/25 2010/09/25 Title
5.11K_0402_1% Issued Date Deciphered Date
Icop_min=4.77A SCHEMATIC MB A5992
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
Iocp_max=7.74A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 50 of 55
5 4 3 2 1
 5 3 2 1

PJ26
2 1 B+_core
VGA_CORE
B+ 2 1
JUMP_43X118
fsw=331.675kHz
Ipeak=11.62A (from HW pwr budget)

10U_1206_25V6M

10U_1206_25V6M
LX_VCORE

1
Imax=8.134A

1
PC132
DH_VCORE 1 PR164 2 DH_VCORE-1

PC133
0_0603_5%
1.2*Ipeak=13.944A

2
BST VCORE
1 PR165 2 1 2

2
0_0603_5% PC134 0.1U_0603_25V7K
Iocp setting must higher than 13.944A
D D
+5VS Cesr=9 mOHM

5
Low side Rds(on)=4.8 mOHM
PR166 PQ37
0_0603_5% SI7686DP-T1-E3_SO8 DCR=3m OHM

16

15
8

1
PU11 PR167

2
1 2 6269 VCORE 4

BOOT
GND

PGOOD

PHASE

UG
4.7_0603_5%
3 VIN PVCC 14 1 2 PC135
+3VS

3
2
1
6269 VCORE 2.2U_0603_6.3V6K
PL18
DCR=3m OHM
4 13 DL VCORE
2 VCC LG 0.56UH_ETQP4LR56WFC_21A_20%

1
PC136 1 2 +VGA_COREP
@ PR168 2.2U_0603_6.3V6K ISL6268CAZ-T_SSOP16

1
10K_0402_5% 12

2
PGND PQ39 @ PQ38 PR172

2
39 VGA_ON PR169
@4.7_1206_5% PC137
1

8.06K_0402_1%
PR170 SI7636DP-T1-E3_SO8 SI7636DP-T1-E3_SO8
+

PR171
1 2 5 11 ISEN
1 VCORE 2

1 2
EN ISEN 330U_V_2.5VM_R9M
4 4

COMP
100K_0402_1% 7.5K_0402_1% G G PC138

FSET

1
1

VO
FB

S
S
S

S
S
S
PC139 EVT (for OCP setting) @680P_0603_50V7K

2
0.1U_0402_16V7K
2

10

3
2
1

3
2
1
C C

VFB=0.6V

1
Rds=4m ohm(typ)

1
22P_0402_50V8J
1

1
PR174 4.8m ohm(max) +3VS
PC140

2200P_0402_25V7K
33K_0402_1% PC141

2
0.01U_0402_25V7K PR177
2

2
PR175
80.6K_0402_1%

2
PR176

1
PC142
14K_0402_1% PR337
40.2K_0402_1%

1
2N7002W-T/R7_SOT323-3 10K_0402_5%
2

1
PQ40 PR179

1
D 10K_0402_1%
2 1 2
PR197 G

2
EVT (for Compensation setting) 2K_0402_1% S

1
@ PR180

2
PC143 10K_0402_1%
0.022U_0402_25V7K

1
B B

2
PR190 +3VS
20K_0402_1% +3VS

2
M92-S2 XT @ PR181

2
PQ41
VGA_PWRSEL_0 VGA_PWRSEL_1 Core Voltage Level PR193 2N7002W-T/R7_SOT323 3 10K_0402_5%
PQ42 PR191 PR182

1
D 10K_0402_1% 10K_0402_5% D 10K_0402_1% VGA_PWRSEL1 18
0 0 1.20V 2 1 2 21 2

1
G G

2
S 2N7002W T/R7_SOT323-3 S

3
0 1 1.14V @ PR192 +3VS @ PR183
10K_0402_1% 10K_0402_1%

1
1 0 0.96V

1
2
PC149
0.022U_0402_25V7K

2
1 1 0.90V PR194 PR195 @

1
D 10K_0402_1% 10K 0402 5%
PQ43 2 1 2 VGA_PWRSEL0 18
G
S 2N7002W-T/R7_SOT323-3

2
@ PR196
10K_0402_1%
A A

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/09/25 Deciphered Date 2009/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date Thursday March 18 2010 Sheet 51 of 55
5 3 2 1
 5 4 3 2 1

VS
D D

PU20A
+ 3 B+
P

1 O
2 PR412
-
G

VL 2.2M_0402_5%
LM393DG_SO8 2 1
4

PR417
1K_1206_5%
1 2

1
PR407 TP0610K-T1-E3_SOT23-3
499K_0402_1% PR408 PQ77
PD19
VS VIN 1K_1206_5%
B+
1
2 1 1 2 3 1

2
PR416
100K_0402_1% PR418
PU20B LL4148_LL34-2 1K_1206_5%

8
LM393DG_SO8 1 2
2

100K_0402_5%

100K_0402_5%
8,45,47 MAINPWON PD18 5

P
+

1
PR415
2 7 PR420
O

PR414
0.01U_0402_25V7K
1 6 1K_1206_5%

2
-

1
46 ACON 3 1 2

PC381
4

1000P_0402_50V7K

32.8
C BAS40CW_SOT323-3 PR410 C

2
1

1
191K_0402_1% PR413

2
PC382
PC383 499K_0402_1%

2
0.1U_0603_25V7K
2

1
PRG
PR409

1
100K_0402_5%
PR411 PR406 PQ79

1
34K_0402_1% PQ78D 47K_0402_5% PDTC115EU_SOT323

1 2
2 1 2 2 1
RTCVREF 2N7002W-T/R7_SOT323-3
G PACIN 44,46 34,46 ACOFF 2

1
S PQ81

3
PQ80 PDTC115EU_SOT323
1
PDTC115EU_SOT323
@ PR419 2

3
66.5K_0402_1% 2 +5VALW
2

3
3
ACIN
Precharge detector
Min. typ. Max
B H-->L 14.589V 14.84V 15.243V B

L-->H 15.562V 15.97V 16.388V

BATT ONLY
Precharge detector
Min. typ. Max
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 52 of 55
5 4 3 2 1
 5 3 2 1

CPU_B+ PL21
HCB4532KF-800T90_1812
PC301 1 2 B+

2200P_0402_50V7K
10U_1206_25V6M

0.01U_0402_25V7K
33P_0402_50V8J

220U_25V_M
2
<BOM 1
Structure> PQ49 1

1
AO4932_SO8

PC303

PC304

PC305

PC306
+
2 1 2 1 UGATE NB 8 1
G2 D2
7 2

2
PR275 PC302 S2/D1 D2 2
6 S2/D1 G1 3
44.2K_0402_1% 1200P_0402_50V7K 5 4
PR276 S2/D1 S1
2_0603_5%
D +5VS 1 2 PC307 PL22 D
1000P_0402_50V7K 3.3UH_SIQB74B-3R3PF_5.9A_20% +CPU_CORE_NB
2 1 PHASE NB 1 2
PR277

1
PC308 PR278 0_0603_5%
0.1U_0603_25V7K 22K_0402_1% BOOT NB 1 2 1 2 PR279 +VDDNB
4.7_1206_5%
2 1 1 Design Current: 3.5A

2
PR280 PC309
10_0402_5% 0.22U_0603_10V7K + PC310 Max current: 5A

1 2
1 2 +CPU CORE_NB LGATE NB 220U_D2_4VM
CPU_B+ 1 2 PR282
0_0402_5%
PC311
680P_0603_50V7K 2 OCP_min:6A
PR281 2 1 CPU_VDDNB_FB_H 8

2
2_0603_5% PR283
+5VS +3VS 13.7K_0402_1%
2 1 PHASE NB

LGATE_NB

1
PC312 CPU_B+
0.1U_0603_25V7K PHASE NB
1

2200P_0402_50V7K
0.01U_0402_25V7K
PR284 PR285 UGATE NB

10U_1206_25V6M

10U_1206_25V6M
0_0402_5% @ 105K_0402_1%

5
2 1 CPU_VDDNB_FB_L 8
PR286
2

2
1

1
PC313

PC314

PC315

PC316
0_0402_5%
PR288
1

PR287 @ 10K_0402_1% PR289

2
105K_0402_1% PR290 10_0402_5% UGATE0 4
@ 105K_0402_ %

48

47

46

45

44

43

42

41

40

39

38

37
2

1
PU16
PHASE0 PQ50

VIN

PGND_NB

LGATE_NB

PHASE_NB

UGATE_NB
VCC

FB_NB

COMP_NB

FSET_NB

VSEN_NB

RTN_NB

OCSET_NB
2

C PR291 TPCA8030-H_SOP-ADV8-5 PL19 C

3
2
1
2.2_0603_5% 0.36UH_PCMC104T-R36MN1R17_30A_20%
1 36 BOOT NB BOOT0 1 2 1 2 1 4 +CPU_CORE_0
34 VGATE OFS/VFIXEN BOOT_NB
PR292 0_0402_5%
1 2 2 35 BOOT0 PC317 2 3
23 H_PWRGD_L PGOOD BOOT0

2
1 2 0.22U_0603_10V7K 2009-0414 update

1
PR293 0_0402_5% @ 3 34 UGATE0 PR295
PWROK UGATE0 PR294 16.2K_0402_1%
2 1 4 33 PHASE0 4.7_1206_5%
8 CPU_SVD SVD PHASE0
PR296 0_0402_5% PR297

1
5 32 4 4 1 2

1 2
SVC PGND0 +5VS 4.02K_0402_1%
8 CPU_SVC 2 1
PR298 0_0402_5% 6 31 LGATE0 PC318 PC319
ENABLE LGATE0 680P_0603_50V7K 2 1
7 30 PQ44

3
2
1

3
2
1

2
RBIAS PVCC TPCA8028-H_SOP-ADVANCE8-5 0.1U_0402_16V7K
34 VR_ON
8 29 LGATE1 @ PQ45
@PQ45
OCSET LGATE1

1
PR299 PR301 ISL6265IRZ-T_QFN48_6X6~D PC320 TPCA8028-H_SOP-ADVANCE8-5 @ PR300 2
@PR300 1 2 1 @PH3
@ PH3
2 1 2 1 9 28 1U_0603_16V6K LGATE0 10_0402_5% 0K_0603_5%_TSM1A103J4302RE
21.5K_0402_1% 95.3K_0402_1% VDIFF0 PGND1

ISN0
ISP0
10 27 PHASE1
FB0 PHASE1
2009-0414 update 11 26 UGATE1
COMP0 UGATE1 CPU_B+
12 25 BOOT1
VW0 BOOT1
COMP1

+VCC_CORE0
VDIFF1
VSEN0

VSEN1

2200P_0402_50V7K
0.01U_0402_25V7K
RTN0

RTN1
ISN0

ISN1
ISP0

ISP1
VW1
FB1

10U_1206_25V6M

10U_1206_25V6M
Design Current: 17.5A
TP

5
Max current: 25A
13

14

15

16

17

18

19

20

21

22

23

24

49

1
PC321

PC322

PC323

PC324
B
PR302
ISP0
ISN0
OCP_min:30A B

2
ISN1
ISP1

0_0402_5% UGATE1 4
2 1 VSEN0
8 CPU_VDD0_FB_H
PR303
+CPU CORE 0 2 1 PHASE1 PQ46
PR304 10_0402_5% PR305 TPCA8030-H_SOP-ADV8-5 PL20

3
2
1
8 CPU_VDD0_FB_L 2 1 RTN0 2.2_0603_5% 0.36UH_PCMC104T-R36MN1R17_30A_20%
0_0402_5% BOOT1 1 2 1 2 1 4 +CPU_CORE_1
2 1 RTN1
8 CPU_VDD1_FB_L
PR306 PC325 2 3
2

2
10_0402_5%

10K_0402_5%

0_0402_5% 2009-0404 update 0.22U_0603_10V7K 2009-0414 update

1
PR308

PR309

PR311
+1.8V 2 1 PR310 16.2K_0402_1%
@ PR307
@PR307 PQ47 4.7_1206_5%
1K_0402_5% TPCA8028-H_SOP-ADVANCE8-5 1 PR312 2
1

1
PR313 4 4 4.02K_0402_1%

1 2
0_0402_5%
2 1 VSEN1 PC326 PC327
8 CPU_VDD1_FB_H
680P_0603_50V7K 2 1
+CPU_CORE_1 2 PR314 1 @PQ48
@ PQ48

3
2
1

3
2
1

2
10_0402_5% TPCA8028-H_SOP-ADVANCE8-5 0.1U_0402_16V7K

DIFF_0 VW0 DIFF_1 VW1 @PR315

@ PR315 2 1 2 1
LGATE1 10_0402_5% @PH4
@ PH4
PR316 PC328 PR317 PC331 0K_0603_5%_TSM1A103J4302RE

ISN1
ISP1
255_0402_1% 4700P_0402_25V7K 255_0402_1% 4700P_0402_25V7K
2 1 2 1 FB 0 2 1 COMP0 2 1 2 1 2 1 FB 1 2 1 COMP1 2 1

PC329 PC330 PC332 PC333

180P_0402_50V8J 1000P_0402_50V7K 180P_0402_50V8J 1000P_0402_50V7K +VCC_CORE1
A
PR318 PR320 PR321 PR323
Design Current: 17.5A A

1K_0402_5% PR319 PC334 6.81K_0402_1% 1K_0402_5% PR322 PC335 6.81K_0402_1% Max current: 25A
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1

54.9K_0402_1% 1200P_0402_50V7K 54.9K_0402_1% 1200P_0402_50V7K

OCP_min:30A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401836 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date Thursday March 18 2010 Sheet 53 of 55
5 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

D HW required to adjust from 1.14V to HW required to adjust from 1.14V to Change PR271 from SD034300180 (S RES 1/16W 3K +-1% D

1 1.12V 1.12V 0.1 42 0402) to SD034324180 (S RES 1/16W 3.24K 0402 1%) 09, 05/07 to PVT

2 Power sequense adjust. HW required to adjust power sequense. 0.1 42 Add PC208 SE076104K80 (S CER CAP .1U 16V K X7R 0402) 09, 05/07 to PVT

Change PR247 from SD028000080 (S RES 1/16W 0 +-5%

3 Power sequense adjust. HW required to adjust power sequense. 0.1 42 0402) to SD028130180 (S RES 1/16W 1.3K 0402 5%) 09, 05/07 to PVT

4 NB_COREP working frequency has

Because NB_COREP working frequency will be gitter
while system at heavy loading. Change to larger ESR
Change PC210 from SGA19331D00 (S POLY C 330U 2.5V M
D2 TPE LESR15M H1.8) to SGA00002B00 (S POLY C 330U
issue. 0.1 42 09, 05/07 to PVT
Cap will be solve. 6.3V M D2E ESR25M TPE H1.8)

5 BOM error BOM error 0.1 42 Add PR270 SD28100280(S RES 1/16W 10K 0402 5%) 09, 05/07 to PVT

Change PR103 from SD028470280(S RES 1/16W 47K 0402 5%)

6 BOM error BOM error 0.1 42 to SD028100280(S RES 1/16W 10K 0402 09, 05/07 to PVT
5%)

7
C C

Change R550 to +3VALW

8 Change Power Source For WLAN wakeup 1.0 37 09, 05/07 Pre-MP

10

11

B 12 B

13

14

15

16

17

18
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401836 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date Thursday, March 18, 2010 Sheet 54 of 55
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) for HW

Item Reason for change Modify List PG# Date Item Reason for change Modify List Rev. PG#
1 PWR update circuit 4/9 26
2 27
D D

BOM change R118 reserve P 18 4/9

3 BOM change Change R178 R179 to 90 9/158 ohm P 16 4/9 28
4 BOM change R30 R39 reserve P 24 4/9 29
5 BOM change Add C30 P 38 4/9 30
6 BOM change Add R634 R639 P 28 4/9 31
7 BOM change C383 Reserve P 24 4/9 32
8 Pop R419 P 20 4/10 33
9 PWR update circuit 5/15
10 For Panel flash issue R1 D2 Reserve pop R763 P 24 5/18
11 For Panel flash issue Add R414 and non-pop P 24 5/18
C C

12 Lid_SW intial issue Add R19 P 28 5/18

13 HPET timer issue Change C288 C290 to 33P P 16 5/18
14 BOM change change C276 C279 10P to 27P P 19 5/19
15
16
17
18
19
20
B 21 B

22
23
24
25

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/09/25 Deciphered Date 2010/09/25 Title
SCHEMATIC MB A5992
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401836
Date: Thursday, March 18, 2010 Sheet 55 of 55
5 4 3 2 1
www.s-manuals.com