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    Visoth Phal
    Construction of Half-Adder and Full-Adder by using Logic Gate lab report

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    Lab 02 Digital

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    Visoth Phal
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    Construction of Half-Adder and Full-Adder by using Logic Gate lab report

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    Construction of Half-Adder and Full-Adder by using Logic Gate lab report

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    5 views4 pages

    Lab 02 Digital

    Uploaded by

    Visoth Phal
    Construction of Half-Adder and Full-Adder by using Logic Gate lab report

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 4

    Institute of Technology of Cambodia Electrical and Energy Engineering Department

    DIGITAL ELECTRONIC LAB

    Lab 2:
    Construction of Half-Adder and Full-Adder by using
    Logic Gate

    LECTURED by: SENG Dararaksmey


    Group: GEE-C1
    Students Name: PHAL Visoth ID: e20200158

    Academic year
    2022-2023
    1. Introduction
    Adders are important in computers and also in other types of digital systems in which
    numerical data are processed. An understanding of the basic adder operation is fundamental
    to the study of digital system.

    2. Objective
    This lab has the following objective:
    • Implementing and simulating the operation of half-adder
    • Implementing and simulating the operation of 1-bit full-adder
    • Implementing and simulating the operation of 4-bits full-adder

    3. Half-Adder
    The Half-Adder is a basic building block of adding two numbers as two inputs and produce
    out two outputs. The adder is used to perform OR operation of two single bit binary numbers.
    The A and B are two input states, and 'carry' and 'sum 'are two output states of the half
    adder.
    Practice:

    a. Implementing this half-adder from both formula by using logic gate

    b. Using truth table to verify the operation.

    Input Output
    A B SUM Carry
    0 0 0 0
    0 1 1 0
    1 0 1 0
    1 1 0 1

    c. Implementing and simulating the operation of half-adder

    1
    4. Full-Adder
    A Full adder is a digital circuit that performs the addition of three binary inputs and produce
    two outputs. A full adder logic is designed in such a manner that can take eight inputs
    together to create a byte-wide adder and cascade the carry bit from one adder to the another.
    Practice:

    a. Implementing this Full-adder from both formula by using logic gate

    b. Using truth table to verify the operation

    Input Output
    Cin A B SUM Carry
    0 0 0 0 0
    0 0 1 1 0
    0 1 0 1 0
    0 1 1 0 1
    1 0 0 1 0
    1 0 1 0 1
    1 1 0 0 1
    1 1 1 1 1

    c. Implementing and simulating the operation of Full-adder

    By comparing both the truth table and simulating, thus verified as should be.

    2
    5. 4-bits Full Adder

    A 4-bits full adder is a digitals circuit that adds two binary numbers of 4 bits each. It is a
    combinational circuit, which mean that its output depends only on its inputs and not its
    previous state.

    Practice:
    Implementing the 4- bits parallel full-adder through simulation software.

    Simulating the waveform.

    The first full adder adds the least significant bits of the two numbers, and the carry out bit
    from the first full adder is used as the carry in bit for the second full adder. This process
    continues until the last full adder, which produces the sum of the two numbers and a carry out
    bit.

    6. Conclusion
    4-Bit adder are used in variety of circuits. it is simple, fast and reliable. But it also requires a
    large number of logic gate, expensive to manufacture and consume a lot of power.

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