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    Lab 12 Voltage Divider

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    kunwalsindhi405
    This document describes a lab experiment on studying the operation of a voltage divider bias configuration with different NPN transistor models. The experiment involves connecting transistors in a voltage divider bias circuit and measuring the base current, collector current, and collector-emitter voltage for different transistors and supply voltages. Tables are included to record readings and a graph is to be plotted from the data.

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    Download as DOCX, PDF, TXT or read online from Scribd

    Lab 12 Voltage Divider

    Uploaded by

    kunwalsindhi405
    8 views4 pages
    This document describes a lab experiment on studying the operation of a voltage divider bias configuration with different NPN transistor models. The experiment involves connecting transistors in a voltage divider bias circuit and measuring the base current, collector current, and collector-emitter voltage for different transistors and supply voltages. Tables are included to record readings and a graph is to be plotted from the data.

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    This document describes a lab experiment on studying the operation of a voltage divider bias configuration with different NPN transistor models. The experiment involves connecting transistors in a voltage divider bias circuit and measuring the base current, collector current, and collector-emitter voltage for different transistors and supply voltages. Tables are included to record readings and a graph is to be plotted from the data.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    8 views4 pages

    Lab 12 Voltage Divider

    Uploaded by

    kunwalsindhi405
    This document describes a lab experiment on studying the operation of a voltage divider bias configuration with different NPN transistor models. The experiment involves connecting transistors in a voltage divider bias circuit and measuring the base current, collector current, and collector-emitter voltage for different transistors and supply voltages. Tables are included to record readings and a graph is to be plotted from the data.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 4

    Department of Electronic Engineering

    Faculty of Engineering and Technology


    University of Sindh, Jamshoro
    Electronic Devices and Circuits (EE-123)

    LAB # 12
    Name: Roll No:

    Score _Signature of the Lab Tutor: Date:

    Dr. Mudasir Ahmed Memon

    Selection of Utilization of Experimental Experimental Lab Safety Teamwork Technical


    Equipment Lab Tools & Data Collection Data Analysis Precautions During Lab cleanliness and 𝒔𝒄𝒐𝒓𝒆 = 𝟐
    ×𝐎𝐛𝐭𝐚𝐢𝐧ed marks
    (0 to 5) Calibration (0 to 5) (0 to 5) (0 to 5) Task Organization 𝟑𝟓
    (0 to 5) (0 to 5) (0 to 5)

    Object: To study the operation of voltage divider bias configuration with different models of NPN
    transistors

    Apparatus Required:
    1. Regulated Power supply, Breadboard and Connecting wires
    2. Transistor (NPN, PNP), Resistors, Capacitor
    3. Oscilloscope and Multimeter (MM), Function Generator

    Theory: [30 minutes]

    In the fixed bias configurations, the bias current ICQ and voltage VCEQ were a function of the current gain 𝛽
    of the transistor. However, because 𝛽 is temperature sensitive, especially for silicon transistors, and the
    actual value of 𝛽 is usually not well defined, it would be desirable to develop a bias circuit that is less
    dependent on, or in fact is independent of, the transistor 𝛽. The voltage-divider bias configuration of Fig.
    12.1 is such a network. If analyzed on an exact basis, the sensitivity to changes in 𝛽 is quite small. If the
    circuit parameters are properly chosen, the resulting levels of ICQ and VCEQ can be almost totally
    independent of 𝛽. The level of IBQ will change with the change in 𝛽, but the operating point on the
    characteristics defined by ICQ and VCEQ can remain fixed if the proper circuit parameters are employed.

    1
    Department of Electronic Engineering
    Faculty of Engineering and Technology
    University of Sindh, Jamshoro
    Electronic Devices and Circuits (EE-123)

    Fig.12.1: Voltage divider bias configuration


    Base Current (𝐼𝐵):

    𝐸𝑇𝐻 − 𝑉𝐵𝐸
    𝐼𝐵 =
    𝑅𝑇𝐻 + (𝛽 + 1)𝑅𝐸 Voltage

    collector-Emitter (𝑉𝐶𝐸):

    𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶(𝑅𝐶 + 𝑅𝐸)

    Load-Line Analysis

    𝑉𝐶𝐶
    𝐼𝐶(𝑆𝑎𝑡) =
    𝑅 𝐶 + 𝑅𝐸

    𝑉𝐶𝐸 (𝐶𝑢𝑡𝑡𝑜𝑓𝑓) = 𝑉𝐶𝐶

    Procedure [150 minutes]


    Voltage divider bias configuration with different model numbers (different transistors are selected because
    each have different 𝜷 values)

    1. Select any NPN Transistor available in the laboratory and make the circuit shown in figure 12.2.
    2. Write down the readings of IB, IC, and VCE in Table 12.1.
    3. Choose another NPN transistor with different model number and write down the readings of I B, IC,
    and VCE in Table 12.1

    Load line analysis.

    1. Connect the circuit as shown in Fig. 12.2.


    2. Select and fix any value of IB through VBB, vary VCC1 and write down the values of IC and VCE in table
    12.2.

    2
    Department of Electronic Engineering
    Faculty of Engineering and Technology
    University of Sindh, Jamshoro
    Electronic Devices and Circuits (EE-123)
    3. Slightly increase the value of IB and repeat step 2.

    𝐼𝐶(𝑆𝑎𝑡) = ______________________

    𝑉𝐶𝐸(𝐶𝑢𝑡𝑡𝑜𝑓𝑓) = ______________________________

    Table 12.1

    NPN (Model No:_______________) NPN (Model No:_______________)

    𝐼𝐵 𝐼𝐶 𝑉𝐶𝐸 𝐼𝐵 𝐼𝐶 𝑉𝐶𝐸

    Fig 12.2: voltage divider bias circuit

    Table 12.2
    Output characteristics
    VCC (V) IC VCE VCC (V) IC VCE VCC (V) IC VCE
    I B=______________

    I B=________________

    I B=________________

    1 1 1
    2 2 2
    3 3 3
    4 4 4
    5 5 5
    6 6 6
    7 7 7

    3
    Department of Electronic Engineering
    Faculty of Engineering and Technology
    University of Sindh, Jamshoro
    Electronic Devices and Circuits (EE-123)
    8 8 8
    9 9 9
    10 10 10
    11 11 11
    12 12 12

    Graph:

    1. Plot the graph as per the data given in Table 12.2 over the load line.

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