Proceedings of the Third International Conference on Electronics Communication and Aerospace Technology [ICECA 2019]

IEEE Conference Record # 45616; IEEE Xplore ISBN: 978-1-7281-0167-5

A 0.5 V LNA Design for 2.4 GHz Wireless

Body Area Network Applications

Vandana Reddy1, Poojitha Sammeta1, Ruchita Kumari1, Nasir Abdul Quadir1 and Amit Jain1
1
Department of Electronics and Communication Engineering
1
CMR Institute of Technology
Bangalore, India

Abstract—Low noise amplifier is a very important part complexity of the design as it requires extra supply
of the receiver and must ensure power constrained voltages. To solve this issue we have used low
amplification with proper impedance matching. The threshold voltage MOS devices, which allows us to
designed circuit can work at supply voltage of 0.5 V and use the casocde topology without using FBB
was designed for wireless body area network technique. Also the PCSNIM technique [10] is used
applications using 130nm CMOS technology. Post layout
simulation results of the proposed LNA shows a power
for our design to obtain simultaneous input and noise
gain of 16.27 dB and a noise figure of 1.7 dB, while matching considering power consumption as the main
dissipating only 1.44 mW power. The design shows constraint. The LC tank circuit is used as output
excellent input matching with the input reflection co- matching circuit to lessen the effect of parasitic
efficient (S11) obtained as -27.71 dB. The proposed work capacitance of the cascode device.
also features very good linearity with -0.87 dBm IIP3.
II. CIRCUIT DESIGN AND ANALYSIS
Index Terms— Low Noise Amplifier (LNA), Source
Degenerated Common Source LNA (SD-CLNA), Wireless
Cascode is a widely accepted topology for low noise
Body Area Network, Noise Factor (NF), Forward Gain. amplifer design due to its advantages like impedance
matching, isolation, gain and stability. The actual
I. INTRODUCTION topology considered is the source degenerated
common source low noise amplifier (SD-CLNA). The
The wireless body area network offers the most typical schematic of the SD-CLNA topology is shown
favorable solution for wearable medical devices. It is in Fig. 1. The SD-CLNA circuit is well known for its
very crucial to have receiver with very low power optimized noise performance with good gain at very
consumption, while meeting the specification with low drain current[1].
enough margins [1]. Being the first block of a typical The typical SD-CLNA technique requires two
receiver, the low noise amplifier design includes inductors for simultaneous input and noise matching
trade-offs between impedance matching, noise figure, [11] as depicted in Fig. 1.
linearity, gain and power consumption [2]. A number
of low noise amplifier circuit techniques like cascade
[3], cascode [4], folded-cascode [5] and the current re-
use [6] topologies have been reported in the literature.
For cascade topology the power consumption is very
high due to multi-stage structure. The current re-use
topology involves a matching network to re-use the
current which increases the complexity of the design.
The cascode topology is widely used for narrowband
LNA design [7]-[9]. It improves the isolation
between output port and input port which improves
the stability of the circuit. It also provides very good
gain with very low power consumption. But cascode
topology reduces the voltage headroom due to its
architecture. Though the folded cascode design
requires lesser voltage compared to cascode topology,
it demands higher current flow due to multiple gain
stages. In cascode topology, usually forward body
biasing [7] is used to handle the issue of the voltage
head room. But this technique increases the Fig 1. Typical circuit of the SD-CLNA

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Proceedings of the Third International Conference on Electronics Communication and Aerospace Technology [ICECA 2019]
IEEE Conference Record # 45616; IEEE Xplore ISBN: 978-1-7281-0167-5

In conventional SDCLNA it is not possible to obtain a

very good impedance matching at optimum noise and
power [7]. Different optimization techniques have
been reported in the literature [10-13] to solve this
issue. The most popular one is power constrained
input and noise matching where an capacitor ( Cext ) is
added between gate and source terminal of the
common source device.
The proposed circuit including the bias circuit and
Fig. 3. Small signal equivalent circuitl of the input stage
output matching circuit is shown in Fig. 2. Input
matching network consists of the gate inductor L g ,
1 L
source inductor Ls , and the capacitor Cext . The
Zin   j Lt  g m S (1)
jCt Ct
capacitor Cext along with good matching helps in
reducing the value of the source inductor [14]. M1 The resonant frequency value is calculated from (1) as
performs as a common source device and M2 as 1
cascode device. The input device is biased in the 0  (2)
saturation region using the current mirror as Lt  Ct
demonstrated in Fig. 2. The size of the input transistor
determines the optimum noise match [15]. The
cascode configuration reduces the impact of gate- Where,
drain overlap capacitance which helps in decoupling Lt  Lg  Ls (3)
the input and output port and improves the output
impedance [16]. An LC tank circuit has been used as And
the output matching network. The output tank circuit
along with resonating at the designed frequency help Ct  Cgs  Cext (4)
in reducing the parasitic effect of the cascode device.
It is clear from the above equations that at resonant
In order to provide useful insight in the proposed frequency the input impedance is pure resistive in
circuit, theoretical analysis is provided regarding nature and the value of the input impedance is
input matching technique and noise effect. Analyzing
the small signal model of the input device (Fig. 3) the
calculated as  gm Ls Ct 
input impedance of the SD-CLNA is given as [1] Being the first block of receiver, it is very crucial for
low noise amplifier to achieve a low noise factor. As
the noise power of MOSFETs are greater than that of
the inductors and capacitors, the capacitor and the
inductor noise is ignored for simplicity [17]. The
small signal model of the input stage considering
noise sources is shown in Fig. 4. ind2 is expressed as
[18]
2
ind  4kT  gd 0f (5)

Fig 2. The proposed LNA circuit Fig. 4 Small signal equivalent circuit for noise analysis

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Proceedings of the Third International Conference on Electronics Communication and Aerospace Technology [ICECA 2019]
IEEE Conference Record # 45616; IEEE Xplore ISBN: 978-1-7281-0167-5

Where g d 0 is the drain to source conductance at Zero

Vds and f is the bandwidth. The value of  is 2/3
for long channel devices and more than 2 for short
channel MOSFETs. The fluctuating channel potential
couples with the gate terminal and results into noisy
current. The mean squared value of the noisy gate
current is expressed as [18]

 2Ct2
ing2  4kT  eff f (6)
5gd 0

Where  eff    Cgs2 Ct2  and the value of  is

Fig. 6 The post layout simulation results of S11 and S22
4/3. The noise factor of the SD-CLNA is expressed as
[3] It can be noticed from the figure that the value of the
NF is 1.7 dB which is very close to the minimum NF
2 achievable for the designed circuit. A two–tone IIP3
 0  simulation is performed using periodic steady state
NF  1   g m RS  
 g m  Cgs  Cext  
(PSS) analysis, to assess the linearity of the designed
  (7)
circuit. The output power corresponding to the
operating frequency is shown in Fig. 8. The value of
RS   Cgs  Cext 
2 2
0
the IIP3 is obtained as -0.87 dBm, which signifies
 1 excellent linearity for the designed circuit. The power
gm consumption of the designed circuit is 1.44 mW as
demonstrated in Fig. 9.
So it can be referred from the above expression that
the value of the transconductance need to be very high
to ensure lower value of the noise factor.

III. SIMULATION RESULTS AND DISCUSSIONS

The designed low noise amplifier is implemented with
130nm RF-CMOS technology for 2.4 GHz applictions
at a supply voltage of 0.5 V. the simulation work is
carried out in cadence virtuoso environment. As
shown in Fig. 5, the LNA shows the forward gain of
16.27 dB and reverse gain of -33.45 dB at 2.4 GHz.
The design shows very good input matching with the
value of S11 obtained as -27.71 dB as depicted in Fig.
6. The value of the output reflection co-efficient is -
15.33 dB. The plot regarding NF and NFmin is given Fig. 7 NF and NFmin for the designed circuit
in Fig. 7.

Fig. 8 IIP3 result considering 2.4 GHz as the fundamental

Fig. 5 The extracted result for S21 and S12 frequency and 2.48 GHz as the third order frequency

978-1-7281-0167-5/19/$31.00 ©2019 IEEE 21

Proceedings of the Third International Conference on Electronics Communication and Aerospace Technology [ICECA 2019]
IEEE Conference Record # 45616; IEEE Xplore ISBN: 978-1-7281-0167-5

Fig. 9 the power consumption of the designed circuit Fig. 10 the stability factors of the designed LNA

The plots regarding stability of the designed circuit is

shown in Fig. 10.It is noticed, that the value of Kf is
greater than 1 and the value for B1f is less than 1
which signifies unconditional stability for the
designed circuit.
The physical design of the designed circuit is depicted
in Fig. 11. MIM (metal-insulator-metal) capacitor and
poly resistor are used in the design as they have less
variations with respect to process and temperature.
The top metal is used as the ground as it has the least
resistivity among all the metal options. A performance
comparison has been shown in table 1 to validate our
design with respect to the existing work reported in
the literature.
CONCLUSION
In this work a LNA is proposed to work at a supply
voltage of 0.5V without using forward body biasing.
The LNA shows very good gain of 16.27 dB, while
dissipating only 1.44 mW of power. The reverse
voltage gain is obtained as -33.45 dB, which signifies Fig. 11 The physical design of the proposed LNA
very good isolation between output and input port.
The designed circuit also shows very good linearity
along with very low NF of 1.7 dB. The proposed
circuit is unconditionally stable for the designed
frequency.

TABLE I. PERFORMANCE COMPARISON WITH THE EXISTING WORK IN THE LITERATURE

.
Parameters This [6] [18] [19] [20] [21] [22] [23] [24]
Work
Freq (GHz) 2.4 2.4 2.4 2.4 3.5 2.4 2.4 5 5.2
Vdd (V) 0.5 0.5 0.5 1 1 0.6 0.6 0.6
Pdc (mW) 1.44 2.1 1.5 0.98 6.5 12 3 1.3 1.1
Gain (dB) 16.27 18.7 14.13 15.2 11 15 15 12.5 10
S11 (dB) -27.72 -12
IIP3 (dBm) -0.87 -4.9 -19 -9 -7 -2 -8.6
NF (dB) 1.7 1.5 2 5.2 4.6 2 3 3.5 3.7

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Proceedings of the Third International Conference on Electronics Communication and Aerospace Technology [ICECA 2019]
IEEE Conference Record # 45616; IEEE Xplore ISBN: 978-1-7281-0167-5

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