IETE Journal of Research

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A Low Power CMOS UWB LNA with Dual-band

Notch Filter Using Forward Body Biasing

Maryam Babasafari & Mostafa Yargholi

To cite this article: Maryam Babasafari & Mostafa Yargholi (2018): A Low Power CMOS UWB
LNA with Dual-band Notch Filter Using Forward Body Biasing, IETE Journal of Research, DOI:
10.1080/03772063.2018.1487341

To link to this article: https://doi.org/10.1080/03772063.2018.1487341

Published online: 02 Jul 2018.

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IETE JOURNAL OF RESEARCH
https://doi.org/10.1080/03772063.2018.1487341

A Low Power CMOS UWB LNA with Dual-band Notch Filter Using Forward Body
Biasing
Maryam Babasafari and Mostafa Yargholi
Department of Electrical Engineering, University of Zanjan, Zanjan, Iran

ABSTRACT KEYWORDS
In this paper, two ultra-wide band (UWB) low noise amplifiers (LNAs) with out-of-band rejection Cascade; dual-band notch
between 2.4–10.2 GHz and forward body biasing technique for wideband application are designed filter; forward body biasing;
and simulated in a standard 0.18 µm CMOS process. Simulation results of two types of LNA exhibit a ultra wide bands
maximum power gain of 13.6 and 14.9 dB with the input return loss lower than −9.8 and −11.3 dB
from 3.1 to 10 GHz for a cascode and a cascade topologies, respectively. A minimum noise figure of
3.4 dB at frequency of 4.3 GHz and 3.1 dB at frequency of 4.1 GHz, IIP3 of −3.3 and −12.3 dBm are
obtained for the cascode and the cascade topologies, respectively. The power consumption of the
cascode LNA with an output buffer is 17.5 mW from a 1.8 V voltage supply, while the cascade LNA
with an output buffer dissipates 9.29 mW from a 0.9 V supply.

1. INTRODUCTION the same time, which makes its design and implementa-
The federal communications commission (FCCs) ruling tion challenging. The signals coming from the receiver
in February 2002 in the USA has approved the stan- antenna are very small; therefore, signal amplification is
dard of ultra-wideband (UWB) technology to use a large required before feeding it into the mixer. This proce-
bandwidth of 7.5 GHz from 3.1 to 10.6 GHz for commer- dure sets the requirement of a certain gain to the LNA.
cial applications [1]. This standard provides low com- The received signal should has a certain Signal to Noise
plexity, high data rate, low cost, low power dissipation, Ratio (SNR) to allow suitable detection. Consequently,
and high-security wireless telecommunication which can the noise which added via the LNA circuit should be
used for short-range purposes. The most important rea- reduced as much as possible. A large interference signal
sons for quick growth in the designing of these circuits or blocker can happen at the input of the LNA. The mod-
are request of these modules for medical imaging sys- ules should be appropriately linear to have a logical signal
tems, wireless personal area networks (WPAN), ground reception. For mobile and portable applications, moder-
and vehicular penetrating radars, and sensor nodes for ate power dissipation is another restriction. Until now,
wireless networks [2]. Literatures illustrate that an UWB published CMOS-based wideband amplifiers are imple-
system can effectively transmit information at a rate of mented in numerous topologies [6]. In this paper, we pro-
110 Mbps at a distance of 10 m [3]. Recently, high speed posed a cascode configuration that improves the input-
and high data rate wireless communication are interested output reverse isolation and the frequency response of the
in the portable device and equipment. For example, data CMOS UWB LNA utilizing input stage common source
rates of 54 and 11 Mbps at an operation frequency of (CS), input passive filtering structures, and forward body
2.4 GHz are attracted in the IEEE 802.11g and 802.11b biasing technique for the wideband applications. In addi-
standard, respectively. However, the operation frequency tion, a dual-band notch filter (with active inductors)
of 5.7/5.2 GHz is established in the IEEE 802.11a to avoid is employed after the LNA core to frequency attenua-
from interfering and crowding at 2.4 GHz. Thus, an UWB tion purposes. furthermore, a notch filter eliminates the
system is considered except for 2.4, 5.2, and 5.7 GHz. The WLAN interferers from 2.4 to 10.2 GHz frequency bands.
CMOS technology is a suitable select for the implemen-
tation of low band UWB system when considering the This paper is organized as follows. In section 2, a pri-
hardware cost, time to market, and the level of difficulty mary schematic of the LNA will be described includ-
[4,5]. The low noise amplifier (LNA) is the first gain stage ing the wideband input matching and proposed cir-
of a receiver. It must satisfy numerous specifications at cuit. In section 3, notch filter and forward body biasing

© 2018 IETE
2 M. BABASAFARI AND M. YARGHOLI: LOW POWER CMOS UWB LNA

techniques will be presented. In section 4, the optimized 3. NOTCH FILTER AND ANALYSIS OF FORWARD
schematic of the LNA with low power dissipation will be BODY BIASING TECHNIQUES
presented. Section 5 is presented simulation results of the
3.1. Notch Filter Technique Analysis
proposed techniques; and finally, Section 6 provides the
conclusion. Figure 2 shows a dual-band notch filter structure to atten-
uate the interference. The filter stage is located next to the
source follower stage to avoid the degrade in NF because
2. DESIGN OF UWB LNA of the loss of this notch filter [8]. Dual-band notch filter
The schematic of the UWB LNA is illustrated in Figure 1. contains inductor and two series capacitors combination
A high pass filter is used to achieve resonance in the reac- in parallel [9]. They are employed after the LNA core
tive part of the input impedance over the whole frequency due to suppression of the WLAN interferers at 2.4 and
range of 3.1–10 GHz. The proposed solution expands the 10.2 GHz without changing the noise figure of the LNA.
fundamental inductively degeneration common-source In the notch filter, considered frequencies for notching
amplifier by inserting an input multi-section reactive net- can be attained as [10]:
work, so the overall reactance can be resonated over a 1
f = √ . (2)
wide bandwidth. The input matching network is shown 2π LC
in Figure 1 with a dot-dash square. A high pass filter-
ing structure, including inductive source degeneration, Figure 3 illustrates the active inductors which are used
is used to perform a wideband input impedance match- in the scheming of L3 and L4 . It is based on the cascode
ing [7], where the inductor employs as a shunt element gain boosting stage with a resistor in a feedback structure
in the RF input path. The cascode connection of M 1 and [11]. The input impedance (Zin ) of Figure 3 is described
M 2 improves the input–output reverse isolation and the as [10]:
frequency response of the amplifier. The source follower  
1 1
stage (M 3 and M 4 ) is used for simulation purposes. The Zin = Rin + jXin = || ||Geq . (3)
input impedance is expressed as following [7]: jωCeq R eq + jωLeq

 
1 1 The quality factor (Q) of the inductor also influence
Zin (s) = + sL1 || sLs + + Req , (1)
sC1 sCgs1 the performance of the filter. Figure 4 demonstrates the
transmission coefficients of the filter for various Q fac-
g L tors. As depicted in Figure 4, the low quality factor will
where g m1 , Cgs1 , and Req = Cm1gs1 s represent the transcon-
decline the maximum attenuation of the notch filter.
ductance, the gate-source capacitance, and the source
degeneration effect of the common-source transistor From Equation (3), the Q factor can be derived as [10]:
(M 1 ), respectively.
Xin ω0 (Leq − Geq R2
eq − ω0 Leq Ceq )
2 2
Q= = . (4)
Rin R eq + Geq R2
eq + ω0 Leq Ceq
2 2

The values of the equivalent circuit is given by:

Cgs7 (1 + gds5 RF )
Leq ≈ , (5)
gm5 gm7

Figure 1: Schematic of the UWB LNA with high pass filter Figure 2: Dual-band notch filter circuit
 M. BABASAFARI AND M. YARGHOLI: LOW POWER CMOS UWB LNA 3

stage composed of transistors M 5 and M 8 (replaced to

the only common-source transistor M 5 ), we can have a
gain boosting technique to reach a small value of DC
current whereas maintaining a satisfactory Q value [8].
As a result, a low power active inductor is simply adept
due to the apply of the cascode gain boosting module
with a resistor in a feedback. In addition, it is evident
in Equation (5) that the inductance of an active induc-
tor is dependent to the bias currents of transistors (and
transconductances of transistors), therefore, the frequen-
cies of notch filter will be efficiently tuned by changing the
bias currents of the active inductor. The applied bias volt-
age in Figures 6 and 7 (i.e. V G1 and V G2 ), are considered
Figure 3: (a) Schematic of active inductor (b) equal circuit of the for fine-tuning the bias currents to compensate the pro-
active inductor with a resistor feedback cess variation lead to frequency shift [8]. To improve the
designed LNA, the control voltage of V G1 and V G2 can
be utilized with a feedback mechanism for calibration of
the frequency change of the notch filters [10,11].

3.2. Forward Body Biasing Technique Analysis

In a long-channel enhancement mode n-MOSFET, where
body, source, and drain terminals are connected to
ground; suppose that an external voltage is connected
to the gate terminal, which is initially zero. As the gate-
source voltage (V GS ) becomes positive, the hole in the
P-substrate is repelled from the gate area, leaving nega-
tive ions behind, so as to mirror the charge on the gate.
In other words, a depletion region is created. In this sit-
uation, no current flows; because, no charge carries are
Figure 4: Simulated transmission coefficient (S21 ) of the notch established. When the gate-source voltage increases, the
filter for different values of Q
width of the depletion region and the potential reaches
a adequately positive value, thus the electrons flow from
gm5 the source to the interface and finally to the drain [6]. The
Geq ≈ gds7 + ,
(1 + gds5 RF ) main problem with a low voltage design is the restriction
of the threshold voltage (V th ), since it is not expected
1 gds5 gds8
Req ≈ = , to reduce much lower what is existing today [12]. For-
(gm7 Av5 Av8 ) (gm7 gm5 gm8 ) ward body biasing technique is announced to solve this
restriction problem and further reduce V th . Besides, for
Ceq ≈ Cgs5 ,
a standard CMOS technology without the multiple gate-
oxide options, the threshold voltage can be manipulated
where Cgsi , gdsi , and gmi are the gate-source capacitance, by the DC biasing at the body terminal, adding one more
output conductance, and transconductance of the related degree of freedom in the circuit design. Typically, the
transistors, respectively. According to Equation (4), the Q threshold voltage of channel MOSFET can be defined
factor of the mentioned active inductor can be improved as [6]:
by declining the parameters Geq and R eq . As illustrated    
in Equation (5), by using the feedback resistor (RF ), the Vth = Vth0 + γ 2φf − vbs − 2φf , (6)
amount of parallel conductance (Geq ) is reduced by the
factor of (1 + gds5 RF ). Also, a larger gm7 , gm5 , and gm8 where V bs is the body-source voltage, V th0 is the thresh-
are required to obtain the lower value of R eq , because old voltage for V bs = 0, γ is a process dependent param-
R eq inversely related to them; therefore the total DC eter, and finally φ f is a semiconductor parameter with
current of the circuit and consequently its power con- a typical value in the range of 0.3–0.4 V [6]. Accord-
sumption can be increased. Thus, by using a cascode ing to the above equation, increasing the V bs can reduce
4 M. BABASAFARI AND M. YARGHOLI: LOW POWER CMOS UWB LNA

Figure 5: Small signal model of the cascode LNA with inductive source degeneration and noise sources

Figure 6: Schematic of the proposed cascode UWB LNA

the V th , which can reduce the power supply and power resistance (in,Rs ), the thermal noise of the channel cur-
consumption [6,13,14]. It is noted that, as the forward rent (in,d ), the gate-induced current noise (in,g ) and the
body bias turns on the source to body connection of the thermal noise of the output resistance (in,out ).
MOSFET, a DC current flows across the junction with
an exponential dependence on the body voltage, leading The entire noise factor of the cascode topology at ω0
to extra power dissipation and possibly latch-up failure. (resonance frequency of input matching network) is cal-
To avoid the excessive junction conduction, a current- culated as follows:
limiting resistor, Rb , attendant with a parallel capacitor
at the body terminal. It could be simply found that the
large bias resistor leads to little noise figure. The general 2 2 2
in,out,Rs + in,out,d + in,out,g
model of the small signal of the cascode topology with
2 2
noise sources is demonstrated in Figure 5. Four sources of +in,out,Rout + in,out,c
Ffirst−stage = 2
. (7)
noise have been considered: the thermal noise of source in,out,Rs
 M. BABASAFARI AND M. YARGHOLI: LOW POWER CMOS UWB LNA 5

After simplification of the above equation, it can be 4. A SOLUTION FOR POWER OPTIMIZATION
derived as (see appendix):
Improving the significant figure of merits such as power
  2  g  and noise in the design of UWB LNA is a continuous
gm
gg1 Q2 + 14 P2 gdn + γ1 4dn challenge. The CS and common gate (CG) topologies are

g 1 two popular architecture choices for the narrow band
+ γ1 4g1 cPgm + Rout
Ffirst−stage = 1 + , (8) LNA design, for example, a cascode topology; but, sup-
Rs Q2 gm
2
plying the cascode topology normally needs a high volt-
age to bias both stages, subsequently increasing power
where γ is a process dependent parameter of transistor
C dissipation. In contrast with traditional designs using the
M 1 , P = Cgst , gdn = γ gdo , and
cascode topology, we propose in part of this paper a cas-
cade topology as a solution for low supply voltage and
1 1
Q=    = . (9) low power dissipation. The cascade stages are based on a
Rs + gm Ls
ω0 Ct 2Rs ω0 Ct simple common-source transistor. The common-source
Ct
topology with the source inductor degeneration estab-
lished the input impedance matching with the noiseless
The long-channel value for gg 1 and γ 1 are 8/45 and devices, which leads to a small NF. The input impedance
1, respectively. Parameter P always is less than unity, of the LNA should be close to 50  across the entire bands
because Ct always is bigger than Cgs due to a supplemen- of 3.1–10 GHz. Therefore, passive circuits are mainly
tary capacitance. According to Friis equation, the entire established to attain the input matching and bandwidth
noise factor of the designed CMOS LNA is considered as aims, simultaneously. To achieve ultra-low power per-
[14]: formance, the cascade LNA is designed with the NMOS
transistors (M 1 and M 2 in Figure 7). The transistors’ sizes
Fsubsequent − 1 (W/L ratios) are increased and optimized to improve the
Ftotal = Ffirst−stage + , (10)
G gain of the LNA and help to match the input impedance
to 50 . A source degeneration inductor (LS ), also facil-
Vd2 Vs2 itates the input matching to 50 , and established better
G= . , (11) linearity and high reverse isolation, which helps with the
Vs2 Vg1
amplifier stability and forward body biasing technique for
where F first−stage is the noise factor of the LNA topolo- wideband applications. All transistors are biased so that
gies, F subsequent is the noise factor of the subsequent stage the supply voltage (V dd ) is reduced to a 0.9 V. The pro-
of LNA, and G is the total voltage gain of the first stage posed cascade LNA is illustrated in Figure 7. It contains
(LNA). As a result, with the high gain (G), the dom- transistors M 1 and M 2 which acts as a CS amplifier stages
inant noise source of the LNA is the first stage noise. and dual-band notch filter with a series combination of
Therefore, NF is minimized at the first stage with the inductance and capacitor for notching at the considered
source inductive degeneration and inserting Lm . Accord- frequency. In order to avoid the extreme junction con-
ing to Equation (8), it can be seen that by increasing gm , duction, a current-limiting resistor, Rb , attendant with
the NF of the first stage can be enhanced. The complete a shunt capacitor consist at the body terminal. To sup-
schematic of the proposed wideband LNA is shown in ply the desired matching conditions, the input network
Figure 6. It consists of LNA, and dual-band notch filter should contain the source degeneration inductor. Fur-
with a series combination of inductance and capacitor. thermore, the noise performance should be considered
A passive inductor, Lm , is used with a shunt connection. in this design. Because of the cascade topology features,
Lm , Cgd of M 1 , and Cgs of M 2 constitute a broadband π the second stage noise effect is degraded by the previ-
section LC network. Proper selecting of inductor (Lm ) ous stage gain, leading to an entire noise contribution
can resonate with the parasitic capacitor and demonstrate dominating by the first stage. Also, the first stage noise
a broadband operating property. The peaking load of the performance is fundamentally based on the input match-
inductor and the shunt insertion inductor together can ing network losses and the noise source of the transistor
established the best flatness of the LNA gain. Besides, an M 1 . Therefore, the high pass filtering configuration is
inductor Lg is connected between the drain of M 2 and chosen as an amplifier input matching to decrease the
gate of M 3 for further bandwidth expansion due to a inductor loss effect on the noise contribution over the
series LC resonance with the gate capacitance of M 3 . The favorite wideband. In this design a shunt peaking induc-
total DC power of the cascode LNA with an output buffer tor Ld1 is selected to resonate with the entire parasitic
is 17.5 mW from a 1.8 V supply voltage. capacitance of the transistor M 1 , CP1 , at the vicinity of
6 M. BABASAFARI AND M. YARGHOLI: LOW POWER CMOS UWB LNA

Figure 7: Schematic of the proposed cascade low power UWB LNA

Table 1: Comparison of the proposed technique with other published CMOS UWB LNAs
Ref. [8]d [10]b [15]b [16]d [17]b [18]b [19]b Cascode LNA Cascade LNA
Technology 0.18 μm 0.18 μm 0.18 μm 0.18 μm 0.18 μm 0.18 μm 0.18 μm 0.18 μm 0.18 μm
S11 (dB) < −9 < −7 < −9 < −7 < −9 < −17.5 < −10 < −9.8 < −11.3
S22 (dB) N/A N/A < −15 N/A < −13 < −14.4 N/A < −11 < −12.2
Gmax (dB) 11.5 16.57 15 16 16.8 8.1 19.7 13.6b 14.9b
12.75c 14c
Bw (GHz) 2.8–6.2 3–5 3.1–10.6 3–4.8 3.1–10.6 1.3–12.1 3–4.8 3.1–10 3.1-10
NFmin (dB) 3.8 2.4 2.7 2.7 3.1 2.5 4 3.4b 3.1b
4c 3.82c
Pdiss (mW) 2.5a 15.75 7 11.9 33.2 10.68 24 17.5 9.29
IIP3 (dBm) N/A −27 N/A N/A N/A −4 N/A −3.3 −12.3
FOM N/A N/A N/A N/A N/A 0.74 N/A 1.4 3.3
Out-band rejection 25dB@ 20.3dB@ 15dB@ 51.5dB@ 84.2dB@
1.8 GHz 2.4 GHz 2.4 GHz 2.4 GHz 2.4 GHz
32dB@ 44.1dB@ – 19dB@ − – − 40.8dB@ 39.5dB@
8.5 GHz 5.2 GHz 5.3 GHz 0.2 GHz 10.2GHz
a Only core LNA
b Simulation results
c Post-layout results
d Measurement results

the low frequency of 3.1 GHz. At high frequency, the LNA, the capacitance Cgd and the output resistance Rds
coupling capacitor (Cc ) is ideally short which permits to of the CS transistors are neglected.
simply feed the second stage with RF signals; further-
more, the series Lg inductor and Cgs2 intrinsic capaci- The general voltage gain [15] is derived as:
tance are selected to resonate in the center of the band to
Vout Vgs1 Vgs2 Vout
improve the amplifier gain response at these frequencies. Gain = = = H1 H 2 H 3 , (12)
The transistor M 3 is used as a source follower (output Vin Vin Vgs1 Vgs2
buffer) to provide a 50  output impedance matching
over the whole bandwidth. To compensation of the gain 1
H1 (s) = L1 (Cgs +C1 )+LS Cgs
, (13)
roll off at the output of M 2 , a shunt peaking inductor (Ld2 ) 1
+
Cgs Req
+
is used to resonate with the entire parasitic capacitances, L1 C1 S2 L1 C1 S L1 C1

CP2 , at the drain of M 2 . Also, the inductor Lm is attached +Cgs Req S + Ls Cgs S2
between the second stage and the output buffer for addi-
−gm1 Ld1 s
tional bandwidth extension due to a series LC resonance H2 (s) = , (14)
with the total parasitic capacitances CL , at the buffer Lg Cgs2 Ld1 Cp1 S4
input. To determine the voltage gain of the proposed +(Lg Cgs2 + Ld1 (Cp1 + Cgs2 ))S2 + 1
 M. BABASAFARI AND M. YARGHOLI: LOW POWER CMOS UWB LNA 7

Figure 8: Simulation result of S11 and S22 for the cascode topol-
ogy Figure 9: Simulation result of S11 and S22 for the cascade topol-
ogy

−gm2 Ld2 S
H3 (s) = , (15)
Lm CL Ld2 Cp2 S4
+(Lm CL + Ld2 (CP2 + CL ))S2 + 1

where H 1 , H2, and H 3 represent the transfer functions of

the input matching network, inter-stage and the output
stage, respectively.

In this section, the cascade topology is reserved as a solu-

tion for low supply voltage and low power consumption.
In the cascade topology, only one transistor is used for
each stage. Thus, the supply voltage will reduce to the Figure 10: Simulation of S21 for the cascode topology
overdrive V sat . In Figure 7, with a low voltage supply
of a 0.9 V, the total DC power with an output buffer is
9.29 mW. To evaluate the performance of the UWB LNAs
for their maximum power gain, 3-dB bandwidth, excess
NF and power dissipation, the figure of merit (FOM) is
defined as:

Gainmax (dB) × BW(GHz)

FOM = . (16)
NFmin × Pdc (mW)

The FOM includes the most related parameters to esti-

mate an UWB LNA for low power and low cost applica-
tions.

Table 1 summarizes the performance of recently pub- Figure 11: Simulation of S21 for the cascade topology
lished UWB LNAs in a 0.18 μm CMOS technology. The
maximum power gain is 13.6 and 14.9 dB, the minimum
5. SIMULATION RESULTS
noise figure is 3.4 and 3.1 dB for the cascode and the
cascade topologies, respectively. The FOM of the offered The simulation results of the proposed circuits com-
circuits is evaluated to 1.4 and 3.3 for the cascode and the posed of UWB LNA with optimization techniques for
cascade topologies, respectively. 3.1–10 GHz bandwidth in a standard 0.18 μm CMOS
8 M. BABASAFARI AND M. YARGHOLI: LOW POWER CMOS UWB LNA

Figure 15: Simulation of IIP3 at 5 GHz for the cascade topology

Figure 12: Noise figure of the cascode topology

Figure 16: Simulation and post-layout results of S21 for the cas-
code topology with all inductors

Figure 13: Noise Figure of the cascade topology

Figure 17: Simulation and post-layout results of S21 for the cas-
cade topology with all inductors

technology is presented. With Agilent ADS 2009A, sim-

ulation results are achieved. The LNA with an out-
put buffer consumes 17.5 mW from a 1.8 V supply and
9.29 mW from a 0.9 V supply for the cascode and the
cascade topologies, respectively. As demonstrated in Fig-
Figure 14: Simulation of IIP3 at 5 GHz, for the proposed cascode ures 8 and 9, the input return loss (S11 ) from 3.1 to
topology 10 GHz is lower than −9.8 and −11.3 dB, the output
return loss (S22 ) is less than −11 and −12.2 dB for the
 M. BABASAFARI AND M. YARGHOLI: LOW POWER CMOS UWB LNA 9

Figure 18: Simulation and post-layout results of noise figure with

Rb and C2 for the cascode topology

Figure 21: Layout of the cascade LNA

cascode and the cascade topologies, respectively. Figures

10 and 11 are depicted power gain versus frequency; as
illustrated, the peak gain is 13.6 dB while the maximum
attenuation of 51.5 and 40.8 dB can be accomplished at
2.4 and 10.2 GHz, respectively, for the cascode topol-
ogy. For the cascade topology, the peak gain is 14.9 dB
Figure 19: Simulation and post-layout results of noise figure with
Rb and C for the cascade topology
while the maximum attenuation of 84.2 and 39.5 dB can
be achieved at 2.4 and 10.2 GHz, respectively. Figures 12
and 13 are depicted the simulation results of NF ver-
sus frequency; as illustrated the minimum NF is 3.4 dB
at 4.3 GHz and 3.1 dB at 4.1 GHz for the cascode and
the cascade topologies, respectively. As demonstrated in
Figures 12 and 13, by using Rb with a parallel capaci-
tor, the NF is smaller than the case without using them.
As shown in Figures 14 and 15, the third order input
intercept point (IIP3 ) of the LNA at 5 GHz are −3.3
and −12.3 dBm, Input Referred 1 dB Compression Point
(IP1–dB ) are −15 and −20 dBm for the cascode and the
cascade topologies, respectively. Figures 16 and 17 show
simulation and post-layout results of S21 with all induc-
tors, which proper choice of inductors Lm and Lg can be
attained the best flatness of the LNA gain. As demon-
strated in Figures 16 and 17, post-layout results of the
peak gain are 12.75 and 14 dB for the cascode and the
cascade topologies, respectively. Also, Figures 18 and 19
show simulation and post-layout results of noise figure
with Rb and C, the noise figure with Rb parallel to a
capacitor is smaller than the case of without them. The
post-layout results of the NF are 4 and 3.82 dB for the
Figure 20: Layout of the cascode LNA cascode and the cascade topologies, respectively. It could
be easily to see that the larger bias resistor will result to
10 M. BABASAFARI AND M. YARGHOLI: LOW POWER CMOS UWB LNA

smaller amplifier noise figure. To confirm the schemat- expressed as following:

ics performances of the designed LNAs and its capability 2
in,d = 4KTγ gd0 f , (A3)
for implementation, the complete layouts of the pro-
posed LNAs are carried out which are illustrated in Fig-
ures 20 and 21. It occupies 990.45 μm × 1009.26 μm and 2
in,g = 4KTδgg f , (A4)
1048.3 μm×1120.65 μm silicon die areas for the cascode
where gg is the equivalent shunt gate conductance, which is
and the cascade topologies, respectively. Figures 16–19 given by [21]:
illustrate the good matching between simulation and
post-layout results. The performance summary and com- (ωCgs )2
gg = , (A5)
parison to other CMOS UWB LNAs are listed in Table 5gd0
1. Compared to recently reported designs, the obtained where gd0 is the drain conductance for zero drain-source volt-
LNA performance achieves acceptable results. age, and γ is a process dependent parameter which has a value
of around 2/3 for long-channel devices in saturation region (in
short channel devices, γ is larger and its value is between 2
6. CONCLUSION and 3) [22,23]. δ is technology dependent parameter and repre-
sent the gate noise coefficient; Its value is 4/3 for long-channel
Two optimization techniques have been designed and devices and made greater in quantity by a factor of 2 in short
simulated for the UWB LNA for 3.1–10 GHz bandwidth channel devices.
by using dual-band notch filter configuration with out-
of-band rejection ability and forward body biasing based
OUTPUT NOISE OF THE FIRST STAGE
on the 0.18 μm CMOS technology. Besides, to substan-
tially reduce the DC power dissipation, a cascade topol- The output noise (in,out ) of the four noise sources (shown in
Figure 5) are represented as:
ogy with only one transistor is used for the LNA. Conse-
quently, the cascade LNA is designed that uses oversized gm
in,out,Rs = in,Rs , (A6)
NMOS transistors. It provides low noise figure, good out- j2ω0 Ct
put and input matching, and high gain and linearity with
a dual-band notch filter. The dual-band notch filter has in,out,Rout = in,Rout , (A7)
the rejection of about 51.5 and 84.2 dB at 2.4 GHz, and
40.8 and 39.5 at 10.2 GHz interferers for the cascode and 1
in,out,d = in,d , (A8)
the cascade topologies, respectively. The LNA consumes 2
17.5 mW from a 1.8 V supply for the cascode topology
with an output buffer, and 9.29 mW from a 0.9 V supply gm jRs ω0 Ct − 1
in,out,g = in,g . (A9)
for the cascade topology with an output buffer. jω0 Ct j2Rs ω0 Ct
Here, the correlation coefficient between in,d and in,g can be
express as [24,25]:
ACKNOWLEDGEMENTS
in,g · i∗n,d
The authors would like to express our sincere gratitude to c=  . (A10)
2 2
authors of references [8], [14], [15], and [20]. in,g · in,d

For the long-channel devices, c = −0.395j, and its magnitude

APPENDIX decreases as the channel length scales down [21].

NOISE ANALYSIS OF THE CASCODE LNA The PSD of output current due to in,d and in,g can be express as:
In this part, noise analysis of the cascode LNA, according to 2
Figure 5, is presented. The small signal model of the cascode in,out,g+d = (Hin,g + Kin,d )(Hin,g + Kin,d )∗
topology with noise sources is shown in Figure 5. The power 2 2
2 2 = |H|2 in,g + |K|2 in,d + HK ∗ in,g .i∗n,d
spectral densities (PSDs) of in,Rs and in,Rout are established by:
+ H ∗ Ki∗n,g .in,d , (A11)
2 1
in,Rs = 4KT f , (A1)
Rs where K and H are the transfer function of (A8) and (A9),
respectively. The last two terms are output noise due to corre-
lation and can be re-expressed by using (A8)–(A10) as follows:
2 1
in,Rout = 4KT f , (A2) 
Rout 2 2 2
in,out,c = (jcHK ∗ −jcH ∗ K) in,g in,d
where T is the absolute temperature in Kelvin, K is the Boltz- 
mann constant, and f is the noise bandwidth in Hertz. The gm c 2 2
= i i , (A12)
PSDs of channel current thermal and gate-induced noises are 2ω0 Ct n,g n,d
 M. BABASAFARI AND M. YARGHOLI: LOW POWER CMOS UWB LNA 11

According to Equation (7), the total noise factor [20] of the 6. B. Razavi, Design of Analog CMOS Integrated Circuits.
cascode topology at ω0 is calculated as follows: Boston: McGrawHill, 2001, pp. 192–256.
2 2 2 2
in,out,d + in,out,g + in,out,Rout + in,out,c 7. A. Bevilacqua and A. M. Niknejad, “An ultra-wideband
Ffirst−stage = 1 + 2
= CMOS LNA for 3.1 to 10.6 GHz wireless receiver,” IEEE J.
in,out,Rs
Solid State Circuit, Vol. 39, no. 12, pp. 2259–68, Dec. 2004.
1 2 2 2 2
4 in,d + in,out,g + in,Rout + in,out,c
1+ 2
. (A13) 8. Ch. Liang, P. Rao, T. Huang, and Sh. Chung, “Analy-
in,out,Rs sis and design of two low-power ultra-wideband CMOS
low-noise amplifiers with out-band rejection,” IEEE Trans.
By using Equations (A2), (A3), (A9), and (A12), F first−stage can
Micro Wave Theory Tech., Vol. 58, no. 2, pp. 277–86, Feb.
be derived as:
  2010.
1 gm jRs ω0 Ct −1 2
4 × 4KTγ gd0 f + jω0 Ct . j2Rs ω0 Ct
9. A. Vallese, A. Bevilacqua, C. Sandner, M. Tiebout, A.
4KTf
×(4KTδgg f ) + Rout + . . . Gerosa, and A. Neviani, “Analysis and design of an inte-
Ffirst−stage = 1 +  2 grated notch filter for the rejection of interference in UWB
4KTf gm
Rs × j2ω0 Ct systems,” IEEE J. Solid-State Circuits, Vol. 44, no. 2, pp.
g c 331–43, Feb. 2009.
+ 2ωm0 Ct 4KTδgg f × 4KTγ gd0 f
, (A14)
1 10. M. Yargholi and A. P. Tarighat, “Resistive feedback LNA
with dual band notch filter for suppressing WLAN signals
  2
γ gm in UWB receivers,” in IEEE International Conference on
4KTf 4 gd0 + 2jω0 Ct δgg UltraWideband, NCC, Kharagpur, India, 2012, pp. 1–4.

1 gm c
+ Rout + 2ω0 Ct δgg γ gd0
Ffirst−stage = 1 + 11. A. Bevilacqua, A. Maniero. A. Gerosa, and A. Neviani, “An
 2
4KTf gm integrated solution for suppressing WLAN signals in UWB
Rs × j2ω0 Ct receivers,” IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 54,
  2 no. 8, pp. 1617–25, Aug. 2007.
γ gm 1
4 gd0 + 2jω0 Ct δgg + Rout
 12. A. Srivastava and D. Govindarajan, “A fast ALU design in
g c
+ 2ωm0 Ct δgg γ gd0 CMOS for low voltage operation,” J. VLSI, pp. 315–27, Dec.
=1+  2 . (A15) 2002.
1 gm
Rs × j2ω0 Ct

C
13. Gh. R. Karimi and S. B. Sedaghat, “Ultra low voltage, ultra
By using P = Cgst , gdn = γ gdo , Equations (A5), and (9), after low power LNA for 2 GHz applications,” Int. J. Electron.
simplification of the equation (A15), it can be derived as Commun, Vol. 66, pp. 18–22, 2012.
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14. H. Rastegar, S. Saryazdi and A. Hakimi, “A low power and
high linearity UWB low noise amplifier (LNA) for 3.1-
10.6 GHz wireless applications in 0.13μm CMOS process,”
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Authors Mostafa Yargholi received the B.Sc.

degree in Communication Engineering
Maryam Babasafari received the B.Sc.
from Iran University of Science and Tech-
degree in Communication Engineering
nology (IUST), Iran in 2002, and the
from Iran University of Karaj (KU), Iran in
M.Sc. and Ph.D. degree in Electronics
2009. The M.Sc. degree and Ph.D. candi-
Engineering from Tarbiat Modares Uni-
date in Electronics Engineering from Zan-
versity (TMU), Iran in 2004 and 2009,
jan University (ZNU), Iran in 2014 and
respectively. He has been working with
2017, respectively. She has been working
the Department of Electrical Engineering, University of Zan-
in Standard Research Institute of Iran as
jan, since 2009, where he is now an associate professor and
an engineer since 2012. Her main interests include Design and
serves as the Head of the Electrical engineering group. His
Analysis of Analog Integrated Circuits and UWB systems.
current research interests include designing of RF Integrated
Circuits, ADCs, UWB systems, and CMOS Integrated Circuits.
Corresponding author. Email: [email protected]
Email: [email protected]