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    Ece DLD Set Ii

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    kisnamohan
    The document is an exam paper for a Digital Logic Design course. It contains 11 questions across 5 units on topics like Boolean algebra, logic gates, encoders, decoders, multiplexers, latches, flip-flops, counters, and memory devices like ROM. Students are required to simplify Boolean expressions, implement logic functions using gates, explain sequential circuits and their operations, and design basic digital components like adders and shift registers.

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    Ece DLD Set Ii

    Uploaded by

    kisnamohan
    18 views2 pages
    The document is an exam paper for a Digital Logic Design course. It contains 11 questions across 5 units on topics like Boolean algebra, logic gates, encoders, decoders, multiplexers, latches, flip-flops, counters, and memory devices like ROM. Students are required to simplify Boolean expressions, implement logic functions using gates, explain sequential circuits and their operations, and design basic digital components like adders and shift registers.

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    ECE-DLD-SET-II

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    The document is an exam paper for a Digital Logic Design course. It contains 11 questions across 5 units on topics like Boolean algebra, logic gates, encoders, decoders, multiplexers, latches, flip-flops, counters, and memory devices like ROM. Students are required to simplify Boolean expressions, implement logic functions using gates, explain sequential circuits and their operations, and design basic digital components like adders and shift registers.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    18 views2 pages

    Ece DLD Set Ii

    Uploaded by

    kisnamohan
    The document is an exam paper for a Digital Logic Design course. It contains 11 questions across 5 units on topics like Boolean algebra, logic gates, encoders, decoders, multiplexers, latches, flip-flops, counters, and memory devices like ROM. Students are required to simplify Boolean expressions, implement logic functions using gates, explain sequential circuits and their operations, and design basic digital components like adders and shift registers.

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    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    of 2

    CODE: 20CA04201

    CHADALAWADA RAMANAMMA ENGINEERING COLLEGE


    (AUTONOMOUS)
    Chadalawada Nagar, Renigunta Road, Tirupati – 517 506
    B. Tech I Year II Semester (R20) Regular Examinations, Sept/Oct - 2021
    Digital Logic Design
    (ECE)
    Time: 3 hours Max Marks: 70
    PART – A
    1. Answer any ten questions (10 x 2 = 20 Marks)
    (a) What do you understand by universal gate?
    (b) Using 10’s complement subtract 72532-3250.
    (c) Convert following hexadecimal number to decimal. i) F2816 ii) BC216.
    (d) What is meant by ‘Don’t care’ conditions? What are its uses ?
    (e) Define PLA.
    (f) What is meant by encoder? Write its functions.
    (g) Differentiate between latch and flip-flop?
    (h) What is counter? what are the types of counters?
    (i) Convert JK Flip flop to T Flip flop.
    (j) Explain clear and preset inputs.
    (k) What is race around condition?
    (l) How does static RAM cell differ from dynamic RAM cell?
    PART - B
    Answer all five units (5 x 10 = 50 Marks)

    UNIT-I
    Simplify the following Boolean expression: (i) F = (A+B)(A’+C)(B+C).
    2.
    (ii) F = A+B+C’+D(E+F)’ .
    OR

    3. Convert the following:


    (i) (163.789)10 = ( )8 (ii) (101101110001.00101) 2= ( ) 8 (iii) (292)16 = ( )2
    (iv) (23.92)10 = ()2

    Continued in Page 2
    Page 1 of 2
    CODE: 20CA04201

    UNIT-II
    4. (a) Reduce the following function using K-Map Technique and implement using universal
    gate.
    F(P, Q,R, S) = Σm(0,1,4,8,9,10) + d(2,11) .
    (b) Use the tabular procedure to simplify the given expression:
    F(A,B,C,D) = Σm (0,4,12,16,19,24,27,28,29,31) in SOP form.

    OR
    5. (a) Simplify the following expression using the K-map for the 4-variable:
    Y = AB’C+A’BC+A’B’C+A’B’C’+AB’C’ .
    (b) Implement the following Boolean function using NOR gates Y=(AB’+A’B)(C+D’).

    UNIT-III
    6. (a) Draw and explain the operation of 3 to 8 decoder.
    (b) Design a full subtractor and implement it using NAND gates. Explain its operation with
    the help of truth table.
    OR
    7. (a) Briefly explain the operation of Multiplexer and Demultiplexer.

    (b) Realize the function using F (A,B,C,D) = ∑m(0,1,2,5,9,11,13,15) using 8:1 MUX.

    UNIT-IV
    8. (a) Compare combinational circuits and sequential circuits.
    (b) Explain the clocked JK flip-flop with truth table
    OR

    9. (a) Draw the logic diagram of a 4-bit shift resister. Explain how shift -left and shift -right
    operations are performed.
    (b) Distinguish between asynchronous and synchronous counters. Write the design steps of
    synchronous counters.

    UNIT-V
    (a) Implement the following Boolean function using PLA:
    10.
    F1(A,B,C) = ∑m(3,5,6,7), F2(A,B,C) = ∑m(0,2,4,7)
    (b) Explain in detail about ROM and types of ROM.

    OR

    11. Explain in details about PAL and PLA.

    *****
    Page 2 of 2

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