COA BIT BANK

1. During Binary multiplication the multiplier bits are stored in ______[ C]

A) Register ‘A’ B) Register ‘B’
C) Shift register ‘Q’ D) None of the above
2. The method of accessing the I/O devices by repeatedly checking the status flags is a [ A]
A) Program-controlled I/O B) I/O mapped
C) Memory-mapped I/O D) None
3. The method which offers higher speeds of I/O transfers is [ C]
A) Interrupts B) Program-controlled I/O
C) DMA D) Memory mapping
4. Both the CISC and RISC architectures have been developed to reduce the _____ [ C]
A) Cost B) Time delay
C) Semantic gap D) All of the mentioned
5. The fastest data access is provided using _______[ D]
A) Cache Memory B) DRAM
C) SRAM D) Registers
6. Which is used to speed-up the processing: [ A]
A) Pipeline B) Vector processing
C) Both D) None
7. Which are the types of array processor? [ C]
A) Attached array processor B) SIMD array processor
C) Both D) None
8. The product of 1101 & 1011 is ______ [ A]
A) 10001111 B) 10101010
C) 11110000 D) 11001100
9. A method of executing one instruction in one CPU clock cycle of time is used in [ C]
A)RISC B)CISC
C)pipelining D)Multiprocessing
10. Variable length of Instruction Size is used in [ B]
A)RISC B)CISC
C)pipelining D)Multiprocessing
11. The primary memory (also called main memory) of a personal computer consists of [A ]
A) RAM only B) ROM only
C) both RAM and ROM D)Cache memory
12. The Boot sector files of the system are stored in which computer memory? [A]
A) ROM B) RAM
C) Cache D) Register
13. Which of the following statements are not correct about cache memory? [B]
A) it stores data temporarily
B) It holds that data and program which has to be executed within a short period of time.
C) It consumes less access time as compared to the RAM.
D) All the above
14. Primary storage is __________ as compared to secondary storage. [ C]
A) Slow and inexpensive B) Fast and inexpensive
C) Fast and expensive D) Slow and expensive
15. The process of dividing the disk into tracks and sectors is called [ D]
A) Tracking B) Crashing
C) Dicing D) Formatting
16. The method which offers higher speeds of I/O transfers is ___________ [ D]
A) Interrupts B) Memory mapping
C) Program-controlled I/O D) DMA
17. In memory-mapped I/O ____________ [ B]
A) The I/O devices have a separate address space
B) The I/O devices and the memory share the same address space
C) A part of the memory is specifically set aside for the I/O operation
D) The memory and I/O devices have an associated address space
18. What does MIMD stand for? [ B]
A)Multiple Instruction Memory Data
B)Multiple Instruction Multiple Data
C)Memory Instruction multiple Data
D)Memory Information Memory Data
19. The process wherein the processor constantly checks the status flags is called as ____ [ A]
A) Polling B) Inspection
C) Reviewing D) Echoing
20. In which of the following term the performance of cache memory is measured? [B ]
A) Chat ratio B)Hit Ratio
C) Copy Ratio D)Data Ratio
21. The process where in the processor constantly checks the status flags is called as [ A]
a) Polling b) Inspection
c) Reviewing d) Echoing
22. The method which offers higher speeds of I/O transfers is[D]
a) Interrupts b) Memory mapping c)
Program-controlled I/O d) DMA
23. SIMD stands for: [D ]
a)System instruction multiple data b) Scale instruction multiple data
c)Symmetric instruction multiple data d) Single instruction multiple data
24. To increase the speed of memory access in pipelining, we make use of [D]
a)Special memory locations b) Special purpose registers
 c) Cache d) Buffers
25. Both the CISC and RISC architectures have been developed to reduce the _____ [C]
a)Cost b) Time delay c) Semantic gap d) All of the mentioned
26. The pipelining process is also called as ______ [ B]
a) Superscalar operation b) Assembly line operation
c) Von Neumann d) None
27. Size of the ________ memory mainly depends on the size of the address bus [A]
a) Main b) Virtual c) Secondary d) Cache
28. To increase the speed of memory access in pipelining, we make use of [C]
a)Special memory locations b) Special purpose registers
c) Cache d) Buffers
29. MIMD stands for: [ C]
a)Multiple input multiple data b) Memory input multiple data
c)Multiple instruction multiple data d) Memory instruction multiple data
30. The effectiveness of the cache memory is based on the property of [ A]
a)Locality of reference b) Memory localization
c) Memory size d) None of the above
31.Cache Hit Ratio=(cache hits/total requests)*100
32. Another name for BCD adder ________4bit adder___
33. MemoryMappings used in Cache_____direct,set associative,fully associative
34. The last type of memory on the memory hierarchy is ____secondary storage________
35. Average Time to Access the Cache memory is hit ratio×cache access time+(1-hit
ratio)×misspenality
36. Example for Auxiliary memory________HDD_______
37. Types of pipelining_______instruction,data,vector___________.
38. Expand RISC Reduced Instruction Set ComputingCISC Complex Instruction Set Computing
39. A ___parallel processing___system can carry out simultaneous data-processing to achieve
faster execution time.
40. Example for RISC processor ARM(Acron Risc Machine)
41. RAM is volatile and temporary storage
42. In pipelining the task which requires the least time is performed
first._____False____(True/false)
43. _Daisy Chaining __ method is used to establish priority by serially connecting all devices that
request an interrupt __handling___
44. In the pipeline___stalling____ is a method used to prevent data hazard and structural hazards.
45. The problem where process concurrency becomes an issue is called as_concurrency controller
46. The CISC stands for ___Complex Instruction Set Computing____
47. Both the CISC and RISC architectures have been developed to reduce the imstruction cycle
time
48. In CISC architecture most of the complex instructions are stored in _memory_
49. Sign magnitude is a representation of ___numeric values
50. The 8 bit 2’s complement form of the number -14 is__11110010_____
51. The digital information is stored on the hard disk by _magnetic storage___
52. The product of -13 & 11 is in binary form is _11101______
53. The pipelining process is also called as _instruction pipelining___
54. The DMA controller has ___3___ registers
55. The DMA transfer is initiated by __DMA Controller__
56. Auxiliary memory example _HDD___
57. Secondary memory also called as__Auxiliary Memory____
58. Cache memory is of type____volatile (volatile, Non-volatile)
59. RAM is of type__volatile (volatile, Non-volatile)
60. ROM is of type__non volatile_ (volatile, Non-volatile)