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 application UC1625
INFO UC2625
available
UC3625
Brushless DC Motor Controller
FEATURES DESCRIPTION
• Drives Power MOSFETs or Power Darlingtons The UC3625 family of motor controller ICs integrate most of the
Directly functions required for high-performance brushless DC motor con-
trol into one package. When coupled with external power
• 50V Open Collector High-Side Drivers
MOSFETs or Darlingtons, these ICs perform fixed-frequency PWM
• Latched Soft Start motor control in either voltage or current mode while implementing
closed loop speed control and braking with smart noise rejection,
• High-speed Current-Sense Amplifier with Ideal
Diode safe direction reversal, and cross–conduction protection.
Although specified for operation from power supplies between 10V
• Pulse-by-Pulse and Average Current Sensing
and 18V, the UC1625 can control higher voltage power devices
• Over-Voltage and Under-Voltage Protection with external level-shifting components. The UC1625 contains fast,
high-current push-pull drivers for low-side power devices and 50V
• Direction Latch for Safe Direction Reversal
open-collector outputs for high-side power devices or level shifting
• Tachometer circuitry.

• Trimmed Reference Sources 30mA The UC1625 is characterized for operation over the military tem-
perature range of –55°C to +125°C, while the UC2625 is charac-
• Programmable Cross-Conduction Protection
terized from –40°C to +105°C and the UC3625 is characterized
• Two-Quadrant and Four-Quadrant Operation from 0°C to 70°C. (NOTE: ESD Protection to 2kV)

TYPICAL APPLICATION

+5V TO HALL +15V VMOTOR

VREF
SENSORS

3kΩ +
100nF 100nF + 100µF
2N3904
20µF 20µF
10Ω
10kΩ
3kΩ 10kΩ
ROSC 2 19 11
QUAD 33kΩ 2N3906
IRF9350
22 3kΩ
DIR
16
6 TO
1k 17 MOTOR
1 TO OTHER
CHANNELS
18
100nF 28 UC3625
4kΩ
14 REQUIRED
27 TO OTHER FOR BRAKE
CHANNELS AND FAST
13
25 10Ω REVERSE
2200pF IRF532
12
COSC
15 20

BRAKE 21 26 3 24 23 8 9 10 4 5 7 10kΩ

100nF
3nF 68kΩ REQUIRED
CT 5nF 100nF 240Ω
RT FROM FOR
HALL AVERAGE
2nF SENSORS 0.02Ω CURRENT
5nF 240Ω RS SENSING
2nF
0.02Ω
2nF RD

UDG-99045

SLUS353A - NOVEMBER 1999

 UC1625
UC2625
UC3625
ABSOLUTE MAXIMUM RATINGS
CONNECTION DIAGRAM
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20V
Pwr VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . +20V DIL-28 (TOP VIEW)
PWM In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 6V
E/A IN(+), E/A IN(–) . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 12V J or N PACKAGE
ISENSE1, ISENSE2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.3 to 6V
OV–Coast, Dir, Speed-In, SSTART, Quad Sel . . . . . . –0.3 to 8V
H1, H2, H3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 12V
PU Output Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 50V
PU Output Current . . . . . . . . . . . . . . . . . . +200 mA continuous
PD Output Current . . . . . . . . . . . . . . . . . . ±200 mA continuous
E/A Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
ISENSE Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . –10 mA
Tach Out Output Current . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
VREF Output Current . . . . . . . . . . . . . . . . . . –50 mA continuous
Operating Temperature Range UC1625. . . . . . –55°C to 125°C
Operating Temperature Range UC2625. . . . . . –40°C to 105°C
Operating Temperature Range UC3625. . . . . . . . . 0°C to 70°C

Note 1: Currents are positive into and negative out of the spec-
ified terminal.
Note 2: Consult Unitrode Integrated Circuits databook for infor-
mation regarding thermal specifications and limitations
of packages.

Note 3: This pinout applies to the SOIC (DW), PLCC (Q), and
LCC (L) packages (ie. pin 22 has the same function on all
packages.)

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for: TA = 25°C; Pwr VCC = VCC = 12V;
ROSC = 20k to VREF; COSC = 2nF; RTACH = 33k; CTACH = 10nF; and all outputs unloaded. TA = TJ.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Overall
Supply current Over Operating Range 14.5 30.0 mA
VCC Turn-On Threshold Over Operating Range 8.65 8.95 9.45 V
VCC Turn-Off Threshold Over Operating Range 7.75 8.05 8.55 V
Overvoltage/Coast
OV-Coast Inhibit Threshold Over Operating Range 1.65 1.75 1.85 V
OV-Coast Restart Threshold 1.55 1.65 1.75 V
OV-Coast Hysteresis 0.05 0.10 0.15 V
OV-Coast Input Current –10 –1 0 µA
Logic Inputs
H1, H2, H3 Low Threshold Over Operating Range 0.8 1.0 1.2 V
H1, H2, H3 High Threshold Over Operating Range 1.6 1.9 2.0 V
H1, H2, H3 Input Current Over Operating Range, to 0V -400 -250 –120 µA
Quad Sel, Dir Thresholds Over Operating Range 0.8 1.4 2.0 V
Quad Sel Hysteresis 70 mV
Dir Hysteresis 0.6 V
Quad Sel Input Current –30 50 150 µA
Dir Input Current –30 –1 30 µA
PWM Amp/Comparator
E/A In(+), E/A In(–) Input Current To 2.5V –5.0 –0.1 5.0 µA
PWM In Input Current To 2.5V 0 3 30 µA
Error Amp Input Offset 0V < VCOMMON-MODE < 3V –10 10 mV
Error Amp Voltage Gain 70 90 dB
2
 UC1625
UC2625
UC3625
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for: TA = 25°C; Pwr VCC = VCC = 12V;
ROSC = 20k to VREF; COSC = 2nF; RTACH = 33k; CTACH = 10nF; and all outputs unloaded. TA = TJ.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
PWM Amp/Comparator (cont.)
E/A Out Range 0.25 3.50 V
SSTART Pull-up Current To 0V –16 –10 –5 µA
SSTART Discharge Current To 2.5V 0.1 0.4 3.0 mA
SSTART Restart Threshold 0.1 0.2 0.3 V
Current Amp
Gain ISENSE1 = .3V, ISENSE2 = .5V to .7V 1.75 1.95 2.15 V/V

Level Shift ISENSE1 = .3V, ISENSE2 = .3V 2.4 2.5 2.65 V

Peak Current Threshold ISENSE1 = 0V, Force ISENSE2 0.14 0.20 0.26 V
Over Current Threshold ISENSE1 = 0V, Force ISENSE2 0.26 0.30 0.36 V
ISENSE1, ISENSE2 Input Current To 0V –850 –320 0 µA
ISENSE1, ISENSE2 Offset Current To 0V ±2 ±12 µA
Range ISENSE1, ISENSE2 –1 2 V
Tachometer/Brake
Tach-Out High Level Over Operating Range, 10k to 2.5V 4.7 5 5.3 V
Tach-Out Low Level Over Operating Range, 10k to 2.5V 0.2 V
On Time 170 220 280 µs
On Time Change With Temp Over Operating Range 0.1 %
RC-Brake Input Current To 0V –4.0 –1.9 mA
Threshold to Brake, RC-Brake Over Operating Range 0.8 1.0 1.2 V
Brake Hysteresis, RC-Brake 0.09 V
Speed-In Threshold Over Operating Range 220 257 290 mV
Speed-In Input Current –30 –5 30 µA
Low-Side Drivers
Voh, –1mA, Down From VCC Over Operating Range 1.60 2.1
V Voh, –50mA, Down From VCC Over Operating Range 1.75 2.2 V
Vol, 1mA Over Operating Range 0.05 0.4 V
Vol, 50mA Over Operating Range 0.36 0.8 V
Rise/Fall Time 10% to 90% Slew Time, into 1nF 50 ns
High-Side Drivers
Vol, 1mA Over Operating Range 0.1 0.4 V
Vol, 50mA Over Operating Range 1.0 1.8 V
Leakage Current Output Voltage = 50V 25 µA
Fall Time 10% to 90% Slew Time, 50mA Load 50 ns
Oscillator
Frequency 40 50 60 kHz
Frequency Over Operating Range 35 65 kHz
Reference
Output Voltage 4.9 5.0 5.1 V
Output Voltage Over Operating Range 4.7 5.0 5.3 V
Load Regulation 0mA to –20mA Load –40 –5 mV
Line Regulation 10V to 18V VCC –10 –1 10 mV
Short Circuit Current Over Operating Range 50 100 150 mA

3
 UC1625
UC2625
UC3625

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for: TA = 25°C; Pwr VCC = VCC = 12V;
ROSC = 20k to VREF; COSC = 2nF; RTACH = 33k; CTACH = 10nF; and all outputs unloaded. TA = TJ.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Miscellaneous
Output Turn-On Delay 1 µs
Output Turn-Off Delay 1 µs

BLOCK DIAGRAM

Quad Sel 22
5V
2 VREF
RC-Osc 25 OSC S Q REFERENCE
PWM CLOCK
PWM In 26 R

E/A Out 27

E/A In(+) 1 2.9V

E/A In (–) 28
10µA
SSTART 24

ISENSE 3 R Q Q1
ABS VALUE 0.2V
2.5V 250Ω
ISENSE1 4 S
2X
ISENSE2 5 3.1V

VCC 19
9V
PWM
OV-Coast 23 CLOCK
1.75V 18 PUA

Dir 6 17 PUB
DIRECTION
Speed-In 7 LATCH

0.25V 16 PUC

+5V PWM CLOCK

DIR COAST CHOP QUAD 11 Pwr Vcc

H1 8 D Q H1 CROSS
14 PDA
CONDUCTION
+5V L PROTECTION
LATCHES

H2 9 D Q H2 DECODER
13 PDB
+5V L

H3 9 D Q H3

BRAKE 12 PDC
L
EDGE
DETECT 15 GND
+5V
2k
RC-Brake 21 ONE 20 Tach-Out
SHOT

1V
UDG-99044

4
 UC1625
UC2625
UC3625
PIN DESCRIPTIONS
Dir, Speed-In: The position decoder logic translates the H1, H2, H3: The three shaft-position sensor inputs con-
Hall signals and the Dir signal to the correct driver sig- sist of hysteresis comparators with input pull-up resis-
nals (PUs and PDs). To prevent output stage damage, tors. Logic thresholds meet TTL specifications and can
the signal on Dir is first loaded into a direction latch, be driven by 5V CMOS, 12V CMOS, NMOS, or
then shifted through a two-bit register. open-collectors.
As long as Speed-In is less than 250mV, the direction Connect these inputs to motor shaft position sensors
latch is transparent. When Speed-In is higher than that are positioned 120 electrical degrees apart. If noisy
250mV, the direction latch inhibits all changes in direc- signals are expected, zener clamp and filter these inputs
tion. Speed-In can be connected to Tach-Out through a with 6V zeners and an RC filter. Suggested filtering
filter, so that the direction latch is only transparent when components are 1kΩ and 2nF. Edge skew in the filter is
the motor is spinning slowly, and has too little stored en- not a problem, because sensors normally generate
ergy to damage power devices. modified Gray code with only one output changing at a
Additional circuitry detects when the input and output of time, but rise and fall times must be shorter than 20µs
the direction latch are different, or when the input and for correct tachometer operation.
output of the shift register are different, and inhibits all Motors with 60 electrical degree position sensor coding
output drives during that time. This can be used to allow can be used if one or two of the position sensor signals
the motor to coast to a safe speed before reversing. is inverted.
The shift register guarantees that direction can't be ISENSE1, ISENSE2, ISENSE: The current sense amplifier
changed instantaneously. The register is clocked by the has a fixed gain of approximately two. It also has a
PWM oscillator, so the delay between direction changes built-in level shift of approximately 2.5V. The signal ap-
is always going to be between one and two oscillator pe- pearing on ISENSE is:
riods. At 40kHz, this corresponds to a delay of between
I SENSE = 2 .5V + (2 • ABS (I SENSE 1 – I SENSE 2 ))
25µs and 50µs. Regardless of output stage, 25µs dead
time should be adequate to guarantee no overlap ISENSE1 and ISENSE2 are interchangeable and can be
cross-conduction. Toggling DIR will cause an output used as differential inputs. The differential signal applied
pulse on Tach-Out regardless of motor speed. can be as high as ±0.5V before saturation.
E/A In(+), E/A In(–), E/A Out, PWM In: E/A In(+) and If spikes are expected on ISENSE1 or ISENSE2, they are
E/A In(–) are not internally committed to allow for a wide best filtered by a capacitor from ISENSE to ground. Fil-
variety of uses. They can be connected to the ISENSE, to tering this way allows fast signal inversions to be cor-
Tach-Out through a filter, to an external command volt- rectly processed by the absolute value circuit. The
age, to a D/A converter for computer control, or to an- peak-current comparator allows the PWM to enter a cur-
other op amp for more elegant feedback loops. The rent-limit mode with current in the windings never ex-
error amplifier is compensated for unity gain stability, so ceeding approximately 0.2V/RSENSE. The over current
E/A Out can be tied to E/A In(–) for feedback and major comparator provides a fail-safe shutdown in the unlikely
loop compensation. case of current exceeding 0.3V/RSENSE. Then, soft start
is commanded, and all outputs are turned off until the
E/A Out and PWM In drive the PWM comparator. For
high current condition is removed. It is often essential to
voltage-mode PWM systems, PWM In can be connected
use some filter driving ISENSE1 and ISENSE2 to reject ex-
to RC-Osc. The PWM comparator clears the PWM latch,
treme spikes and to control slew rate. Reasonable start-
commanding the outputs to chop.
ing values for filter components might be 250Ω series
The error amplifier can be biased off by connecting E/A resistors and a 5nF capacitor between ISENSE1 and
In(–) to a higher voltage than E/A In(+). When biased ISENSE2. Input resistors should be kept small and
off, E/A Out will appear to the application as a resistor to matched to maintain gain accuracy.
ground. E/A Out can then be driven by an external am-
plifier. OV-Coast: This input can be used as an over-voltage
shutdown in put, as a coast input, or both. This input
GND: All thresholds and outputs are referred to the can be driven by TTL, 5V CMOS, or 12V CMOS.
GND pin except for the PD and PU outputs.

5
 UC1625
UC2625
UC3625
PIN DESCRIPTIONS (cont.)
PDA, PDB, PDC: These outputs can drive the gates of ground. Recommended values for RT are 10kΩ to
N-Channel power MOSFETs directly or they can drive 500kΩ, and recommended values for CT are 1nF to
the bases of power Darlingtons if some form of current 100nF, allowing times between 5µs and 10ms. Best ac-
limiting is used. They are meant to drive low-side power curacy and stability are achieved with values in the cen-
devices in high-current output stages. Current available ters of those ranges.
from these pins can peak as high as 0.5A. These out-
RC-Brake also has another function. If RC-Brake pin is
puts feature a true totem-pole output stage. Beware of
pulled below the brake threshold, the IC will enter brake
exceeding IC power dissipation limits when using these
mode. This mode consists of turning off all three
outputs for high continuous currents. These outputs pull
high-side devices, enabling all three low-side devices,
high to turn a “low-side” device on (active high).
and disabling the tachometer. The only things that in-
PUA, PUB, PUC: These outputs are open-collector, hibit low-side device operation in braking are
high-voltage drivers that are meant to drive high-side low-supply, exceeding peak current, OV-Coast com-
power devices in high-current output stages. These are mand, and the PWM comparator signal. The last of
active low outputs, meaning that these outputs pull low these means that if current sense is implemented such
to command a high-side device on. These outputs can that the signal in the current sense amplifier is propor-
drive low-voltage PNP Darlingtons and P-channel tional to braking current, the low-side devices will brake
MOSFETs directly, and can drive any high-voltage de- the motor with current control. (See applications) Sim-
vice using external charge-pump techniques, trans- pler current sense connections will result in uncontrolled
former signal coupling, cascode level-shift transistors, or braking and potential damage to the power devices.
opto-isolated drive (high-speed opto devices are recom-
RC-Osc: The UC3625 can regulate motor current using
mended). (See applications).
fixed-frequency pulse width modulation (PWM). The
PWR VCC: This supply pin carries the current sourced RC-Osc pin sets oscillator frequency by means of timing
by the PD outputs. When connecting PD outputs directly resistor ROSC from the RC-Osc pin to VREF and capaci-
to the bases of power Darlingtons, the PWR VCC pin can tor COSC from RC-Osc to Gnd. Resistors 10kΩ to
be current limited with a resistor. Darlington outputs can 100kΩ and capacitors 1nF to 100nF will work best, but
also be "Baker Clamped" with diodes from collectors frequency should always be below 500kHz. Oscillator
back to PWR VCC. (See Applications) frequency is approximately:
Quad Sel: The IC can chop power devices in either of 2
F =
two modes, referred to as “two-quadrant” (Quad Sel low) (ROSC • COSC )
and “four-quadrant” (Quad Sel high). When
two-quadrant chopping, the pull-down power devices Additional components can be added to this device to
are chopped by the output of the PWM latch while the cause it to operate as a fixed off-time PWM rather than
pull-up drivers remain on. The load will chop into one a fixed frequency PWM, using the RC-Osc pin to select
commutation diode, and except for back-EMF, will ex- the monostable time constant.
hibit slow discharge current and faster charge current. The voltage on the RC-Osc pin is normally a ramp of
Two-quadrant chopping can be more efficient than about 1.2V peak-to-peak, centered at approximately
four-quadrant. 1.6V. This ramp can be used for voltage-mode PWM
When four-quadrant chopping, all power drivers are control, or can be used for slope compensation in cur-
chopped by the PWM latch, causing the load current to rent-mode control.
flow into two diodes during chopping. This mode exhibits
SSTART: Any time that VCC drops below threshold or the
better control of load current when current is low, and is
sensed current exceeds the over-current threshold, the
preferred in servo systems for equal control over accel-
soft-start latch is set. When set, it turns on a transistor
eration and deceleration. The Quad Sel input has no ef-
that pulls down on SSTART. Normally, a capacitor is con-
fect on operation during braking.
nected to this pin, and the transistor will completely dis-
RC-Brake: Each time the Tach-Out pulses, the capaci- charge the capacitor. A comparator senses when the
tor tied to RC-Brake discharges from approximately NPN transistor has completely discharged the capacitor,
3.33V down to 1.67V through a resistor. The tachometer and allows the soft-start latch to clear when the fault is
pulse width is approximately T = 0.67 RT CT, where RT removed. When the fault is removed, the soft-start ca-
and CT are a resistor and capacitor from RC-Brake to pacitor will charge from the on-chip current source.

6
 UC1625
UC2625
UC3625
PIN DESCRIPTIONS (cont.)
SSTART clamps the output of the error amplifier, not al- tation cycle, additional commutations are not possible.
lowing the error amplifier output voltage to exceed Although this will effectively set a maximum rotational
SSTART regardless of input. The ramp on RC-Osc can speed, the maximum speed can be set above the high-
be applied to PWM In and compared to E/A Out. With est expected speed, preventing false commutation and
SSTART discharged below 0.2V and the ramp minimum chatter.
being approximately 1.0V, the PWM comparator will
VCC: This device operates with supplies between 10V
keep the PWM latch cleared and the outputs off. As
and 18V. Under-voltage lockout keeps all outputs off be-
SSTART rises, the PWM comparator will begin to
low 7.5V, insuring that the output transistors never turn
duty-cycle modulate the PWM latch until the error ampli-
on until full drive capability is available. Bypass VCC to
fier inputs overcome the clamp. This provides for a safe
ground with an 0.1µF ceramic capacitor. Using a 10µF
and orderly motor start-up from an off or fault condition.
electrolytic bypass capacitor as well can be beneficial in
Tach-Out: Any change in the H1, H2, or H3 inputs loads applications with high supply impedance.
data from these inputs into the position sensor latches.
VREF: This pin provides regulated 5 volts for driving
At the same time data is loaded, a fixed-width 5V pulse
Hall-effect devices and speed control circuitry. VREF will
is triggered on Tach-Out. The average value of the volt-
reach +5V before VCC enables, ensuring that Hall-effect
age on Tach-Out is directly proportional to speed, so
devices powered from VREF will become active before
this output can be used as a true tachometer for speed
the UC3625 drives any output. Although VREF is current
feedback with an external filter or averaging circuit
limited, operation over 30mA is not advised. For proper
which usually consists of a resistor and capacitor.
performance VREF should be bypassed with at least a
Whenever Tach-Out is high, the position latches are in- 0.1µF capacitor to ground.
hibited, such that during the noisiest part of the commu-

APPLICATION INFORMATION
Cross Conduction Prevention cleared two PWM oscillator cycles after that drive signal
is turned off. The output of each flip flop is used to inhibit
The UC3625 inserts delays to prevent cross conduction
drive to the opposing output (see below). In this way, it is
due to overlapping drive signals. However, some thought
impossible to turn on driver PUA and PDA at the same
must always be given to cross conduction in output stage
time. It is also impossible for one of these drivers to turn
design because no amount of dead time can prevent fast
on without the other driver having been off for at least
slewing signals from coupling drive to a power device
two PWM oscillator clocks.
through a parasitic capacitance.
The UC3625 contains input latches that serve as noise
blanking filters. These latches remain transparent
through any phase of a motor rotation and latch immedi-
ately after an input transition is detected. They remain
latched for two cycles of the PWM oscillator. At a PWM EDGE SHIFT
S Q
FINDER REG
oscillator speed of 20kHz, this corresponds to 50µs to
PWM R Q PUA
100µs of blank time which limits maximum rotational CLK
speed to 100kRPM for a motor with six transitions per ro- PULL UP

tation or 50kRPM for a motor with 12 transitions per rota- S Q

FROM
tion. DECODER
R Q
This prevents noise generated in the first 50µs of a tran- PULL PDA
sition from propagating to the output transistors and DOWN

causing cross–conduction or chatter.

The UC3625 also contains six flip flops corresponding to
the six output drive signals. One of these flip flops is set
every time that an output drive signal is turned on, and Figure 1. Cross conduction prevention.

7
 UC1625
UC2625
UC3625
TYPICAL CHARACTERISTICS

1MHz

100kHz
Oscillator Frequency

Ro
sc
- 10k
Ro
10kHz sc
- 30k
Ro
sc
- 100
k

1kHz

100Hz
0.001 0.01 0.1

COSC (µF)

Figure 2. Oscillator frequency vs. COSC and ROSC. Figure 4. Supply current vs. temperature.

100ms

10ms k
500
RT -

k
100
RT -
On Time

1ms

30k
RT -
100µs 10k
RT -

10µs

1µs
0.001 0.01 0.1
CT (µF)

Figure 3. Tachometer on time vs RT and CT. Figure 5. Soft start pull-up current vs temperature.

8
 UC1625
UC2625
UC3625
TYPICAL CHARACTERISTICS (cont.)

Figure 6. Soft start discharge current vs. Figure 7. Current sense amplifier transfer function.
temperature.

APPLICATION INFORMATION (cont.)

Power Stage Design cases, RD is not needed. The low-side circulating di-
odes go to ground and the current sense terminals of
The UC3625 is useful in a wide variety of applications,
the UC3625 (ISENSE1 and ISENSE2) are connected to RS
including high-power in robotics and machinery. The
through a differential RC filter. The input bias current of
power output stages used in such equipment can take a
the current sense amplifier will cause a common mode
number of forms, according to the intended perfor-
offset voltage to appear at both inputs, so for best accu-
mance and purpose of the system. Below are four differ-
ent power stages with the advantages and racy, keep the filter resistors below 2k and matched.
disadvantages of each shown. The current that flows through RS is discontinuous be-
For high-frequency chopping, fast recovery circulating cause of chopping. It flows during the on time of the
diodes are essential. Six are required to clamp the wind- power stage and is zero during the off time. Conse-
ings. These diodes should have a continuous current quently, the voltage across RS consists of a series of
rating at least equal to the operating motor current, pulses, occurring at the PWM frequency, with a peak
since diode conduction duty-cycle can be high. For value indicative of the peak motor current.
low-voltage systems, Schottky diodes are preferred. In To sense average motor current instead of peak cur-
higher voltage systems, diodes such as Microsemi rent, add another current sense resistor (RD in Fig. D) to
UHVP high voltage platinum rectifiers are recom- measure current in the low-side circulating diodes, and
mended. operate in four quadrant mode (pin 22 high). The nega-
In a pulse-by-pulse current control arrangement, current tive voltage across RD is corrected by the absolute
sensing is done by resistor RS, through which the tran- value current sense amplifier. Within the limitations im-
sistor's currents are passed (Fig. A, B, and C). In these posed by Table 1, the circuit of Fig. B can also sense
average current.

9
 UC1625
UC2625
UC3625
APPLICATION INFORMATION (cont.)

FIGURE A FIGURE B

TO TO
MOTOR MOTOR

RS RS

FIGURE C FIGURE D

TO TO
MOTOR MOTOR

RS RS RD

2 4 SAFE POWER CURRENT SENSE

QUADRANT QUADRANT BRAKING REVERSE PULSE BY PULSE AVERAGE
FIGURE A YES NO NO NO YES NO
FIGURE B YES YES NO IN 4-QUAD MODE ONLY YES YES
FIGURE C YES YES YES IN -4QUAD MODE ONLY YES NO
FIGURE D YES YES YES IN-4QUADMODE ONLY YES YES

10
 UC1625
UC2625
UC3625
APPLICATION INFORMATION (cont.)

Figure 8. Fast high-side P-channel driver.

Figure 11. Power NPN low-side driver.

For drives where speed is critical, P-Channel MOSFETs

can be driven by emitter followers as shown in Fig. 8.
Here, both the level shift NPN and the PNP must with-
stand high voltages. A zener diode is used to limit
gate-source voltage on the MOSFET. A series gate re-
sistor is not necessary, but always advisable to control
overshoot and ringing.
High-voltage optocouplers can quickly drive high-voltage
MOSFETs if a boost supply of at least 10 volts greater
Figure 9. Optocoupled N-channel high-side driver. than the motor supply is provided (See Fig. 9.) To protect
the MOSFET, the boost supply should not be higher than
18 volts above the motor supply.
For under 200V 2-quadrent applications, a power NPN
driven by a small P-Channel MOSFET will perform well
as a high-side driver as in Fig. 10. A high voltage
small-signal NPN is used as a level shift and a high volt-
age low-current MOSFET provides drive. Although the
NPN will not saturate if used within its limitations, the
base-emitter resistor on the NPN is still the speed limiting
component.
Fig. 11 shows a power NPN Darlington drive technique
using a clamp to prevent deep saturation. By limiting sat-
uration of the power device, excessive base drive is mini-
mized and turn-off time is kept fairly short. Lack of base
series resistance also adds to the speed of this ap-
proach.
Figure 10. Power NPN high-side driver.

11
 UC1625
UC2625
UC3625
APPLICATION INFORMATION (cont.)
+12V VMOTOR
3
33kΩ 6 7
PUA 2
7 UC3724N UC3725N
4
4 8
1:2
8 1 2 5 1 6 3

5kΩ 1nF 100nF

TO MOTOR UDG-99047

Figure 12. Fast high-side N-channel driver with transformer isolation.

Fast High-Side N-Channel Driver with Transformer These ICs operate with position sensor encoding that
Isolation has either one or two signals high at a time, never all low
A small pulse transformer can provide excellent isolation or all high. This coding is sometimes referred to as “120°
between the UC3625 and a high-voltage N-Channel Coding” because the coding is the same as coding with
MOSFET while also coupling gate drive power. In this position sensors spaced 120 magnetic degrees about
circuit (shown in Fig. 12), a UC3724 is used as a trans- the rotor. In response to these position sense signals,
former driver/encoder that duty-cycle modulates the only one low-side driver will turn on (go high) and one
transformer with a 150kHz pulse train. The UC3725 recti- high-side driver will turn on (pull low) at any time.
fies this pulse train for gate drive power, demodulates the
signal, and drives the gate with over 2 amp peak current. Table I. Computational truth table.
Both the UC3724 and the UC3725 can operate up to INPUTS OUTPUTS
500kHz if the pulse transformer is selected appropriately.
To raise the operating frequency, either lower the timing DIR H1 H2 H3 Low-Side High-Side
resistor of the UC3724 (1kΩ min), lower the timing ca- 6 8 9 10 12 13 14 16 17 18
pacitor of the UC3724 (500pF min) or both. 1 0 0 1 L H L L H H
If there is significant capacitance between transformer 1 0 1 1 L L H L H H
primary and secondary, together with very high output 1 0 1 0 L L H H L H
slew rate, then it may be necessary to add clamp diodes 1 1 1 0 H L L H L H
from the transformer primary to +12V and ground. Gen- 1 1 0 0 H L L H H L
eral purpose small signal switching diodes such as 1 1 0 1 L H L H H L
1N4148 are normally adequate. 0 1 0 1 L L H H L H
0 1 0 0 L L H L H H
The UC3725 also has provisions for MOSFET current
0 1 1 0 L H L L H H
limiting. Consult the UC3725 data sheet for more infor-
0 0 1 0 L H L H H L
mation on implementing this.
0 0 1 1 H L L H H L
Computational Truth Table 0 0 0 1 H L L H L H
This table shows the outputs of the gate drive and open X 1 1 1 L L L H H H
collector outputs for given hall input codes and direction X 0 0 0 L L L H H H
signals. Numbers at the top of the columns are pin
numbers.

12
 UC1625
UC2625
UC3625
APPLICATION INFORMATION (cont.)

+5V TO HALL +15V VMOTOR

VREF
SENSORS

3kΩ +
100nF 100nF + 100µF
2N3904
20µF 20µF
10Ω
10kΩ
3kΩ 10kΩ
ROSC 2 19 11
QUAD 33kΩ 2N3906
IRF9350
22 3kΩ
DIR
16
6 TO
1k 17 MOTOR
1 TO OTHER
CHANNELS
18
100nF 28 UC3625
4kΩ
14 REQUIRED
27 TO OTHER FOR BRAKE
CHANNELS AND FAST
13
25 10Ω REVERSE
2200pF IRF532
12
COSC
15 20

BRAKE 21 26 3 24 23 8 9 10 4 5 7 10kΩ

100nF
3nF 68kΩ REQUIRED
CT 5nF 100nF 240Ω
RT FROM FOR
HALL AVERAGE
2nF SENSORS 0.02Ω CURRENT
5nF 240Ω RS SENSING
2nF
0.02Ω
2nF RD

UDG-99045

Figure 13. 45V/8A brushless DC motor drive circuit.

N–Channel power MOSFETs are used for low–side driv- steady–state motor speed is closely related to applied
ers, while P–Channel power MOSFETs are shown for voltage.
high–side drivers. Resistors are used to level shift the Pin 20 (Tach-Out) is connected to pin 7 (SPEED IN)
UC3625 open–collector outputs, driving emitter follow- through an RC filter, preventing direction reversal while
ers into the MOSFET gate. A 12V zener clamp insures the motor is spinning quickly. In two–quadrant opera-
that the MOSFET gate–source voltage will never exceed tion, this reversal can cause kinetic energy from the mo-
12V. Series 10Ω gate resistors tame gate reactance, tor to be forced into the power MOSFETs.
preventing oscillations and minimizing ringing.
A diode in series with the low-side MOSFETs facilitates
The oscillator timing capacitor should be placed close to PWM current control during braking by insuring that
pins 15 and 25, to keep ground current out of the capac- braking current will not flow backwards through low–side
itor. Ground current in the timing capacitor causes oscil- MOSFETs. Dual current–sense resistors give continu-
lator distortion and slaving to the commutation signal. ous current sense, whether braking or running in
The potentiometer connected to pin 1 controls PWM four–quadrant operation, an unnecessary luxury for
duty cycle directly, implementing a crude form of speed two–quadrant operation.
control. This control is often referred to as “voltage The 68kΩ and 3nF tachometer components set maxi-
mode” because the potentiometer position sets the aver-
mum commutation time at 140µs. This permits smooth
age motor voltage. This controls speed because
operation up to 35,000 RPM for four–pole motors, yet
UNITRODE CORPORATION gives 140µs of noise blanking after commutation.
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460

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