Third International Conference on Devices, Circuits and Systems (ICDCS'16) 281

Design of 10T SRAM Cell for High SNM and Low

Power
P. Shiny Grace1, N. M. Sivamangai2
1, 2
School of Electrical sciences, Karunya University, Coimbatore, Tamil Nadu, India.

Abstract–Objective: In this paper, a 10-T (Transistor) static random In this paper, we have designed a 10T SRAM cell that
access memory (SRAM) cell with reduced power and with improved operates at ultra low voltages and also exhibits high SNM. This
static noise margin (SNM) is proposed. The 10-T SRAM employs a 10T SRAM cell has reduced the bitline to one instead of two,
single bitline with dynamic feedback control which enhances the SNM Since bit lines, word lines, and datalines are the largest
at ultra low power. Further, the power consumption is trimmed down by
the use of sleep transistors. The experimental results shows that the
capacitive parts in the memory which leads to more dynamic
proposed 10T SRAM cell achieves SNM of 2.91x as that of power consumption. Hence, reducing it to single bit line reduces
conventional 6T SRAM and it has achieved 20.49% power reduction the power drastically and sleep transistors to reduce the static
that of the 8T SE dynamic feedback loop using 45nm process. power consumption and it also has dynamic feedback loop to
improve the SNM by separating the true storing nodes from the
Keywords- Single-ended, SRAM, Sleep transistors, Static noise bitlines during SRAM cell operation. The experimental results
margin (SNM) , low power. show that the proposed 10T SRAM cell exhibits 2.91x as that of
Conventional 6T SRAM and the power consumption is 20.49%
I.INTRODUCTION
lesser than that of 8T SE dynamic feedback loop.
All battery operated devices require primary memory that
responds faster. So for that we need SRAM’s which are faster
and need not be refreshed. Hence, SRAM’s occupy most of the II. DESIGN METHODODLOGY
area and dominates the power and performance of a device. It is
thus necessary to reduce the power consumption of SRAM. A. Conventional 6T SRAM
Reducing the supply voltage of SRAM is one of the effective
ways to reduce the power consumption because reducing supply
voltage reduces dynamic and leakage power drastically. Though
it has many advantages, designing a robust SRAM cell is
extremely challenging because of increased stability problems.
There has been many efforts during the past decades to
understand and model the stability of the SRAM. The basic 6T
SRAM is deceptively simple, yet attempts to analytically model
the cell stability have achieved only limited success at ultra low
power supplies[2-4]. To overcome this data stability problems
researchers have considered different configurations for SRAM
and adopted various methods which includes negative bitline
voltage [5], write back schemes [6-7], Dual rail supply power Figure 1. Conventional 6T SRAM
[8-9], isolating read path from storage node [10-12], whereas
they all have two complementary bitlines which consumes more In 6T SRAM as shown in Fig. 1, during write mode BL is
power during switching. The SRAM cell shown in [13-16] charged ‘1’ or lowered to ‘0’ depending upon the data to be
eliminates the stability problem by separating the storage nodes stored .BLB is charged complement to the bitline (BL). To write
from the bitlines yet leakage power is high. ‘1’ BL is charged to Vdd and WL is made high such that the
Furthermore, to reduce power there are many 5T – 10T current passes through M3 and M4 transistors and gets stored in
SRAM cells [17-22] have been explored. They use single node Q and the complement of it, gets stored in the node QB.
bitlines to reduce power and to minimize the area. However, That makes the transistors M1 and M6 ON. During precharge
write 1 signal is weakened by the NMOS pass transistor logic. phase WL is lowered to zero and hence the transistors M3 and
Hence those SRAM cells have higher stability problems. M4 are turned OFF. Then both the bit lines are forced to Vdd.
During read phase WL is made high such that the transistors M3

978-1-5090-2309-7/16/$31.00©2016 IEEE
Third International Conference on Devices, Circuits and Systems (ICDCS'16) 282

and M4 turns ON. Thus the BLB gets discharged to ground Transistors N1, N2 decouples the storage node from the bitline
through the M6 transistor. BL is not discharged and remains in thereby increasing the SNM. Sleep transistors are introduced to
Vdd since the M5 transistor is OFF. And hence this condition reduce the power consumption further. These sleep transistors
represents that data ‘1’ is been stored in the SRAM. And it is are ON when the circuit is ON and switch OFF when the circuit
read through the sense amplifiers. is idle. By cutting of the power supply it reduces the leakage
power.SL and SLB signals are used to control the sleep
B. SE with dynamic feedback loop 8T SRAM transistors.

Figure 2. SE with dynamic feedback loop 8T SRAM

8T SE dynamic feedback loop SRAM is shown in the Fig.

2. Here single bitline is used to write data in the SRAM.
Transistors M6 and M2 are used to separate the true storing Figure 3. Proposed 10T SRAM
nodes from the bitline and thereby increasing the SNM of the
SRAM. During write phase WWL is made high, WBL is made The transistors P2, P3, N3 and N4 forms the cross
high and low if data ‘1’ and ‘0’ is to be written respectively. coupled inverters to store the data. The write word line (WWL)
FCS1 is made high if ‘0’ is written and lowered if ‘1’ is written controls the transistor N6 which transfers the data from word bit
since it has to separate the node from the bitline. FCS2 is made line (WBL). Where, read bit line (RBL) transfers the stored data
high if 1 is written in Q node and lowered if 0 is written in node to the output when the read word line (RWL) is activated.
Q. Now consider 1 is written in node Q, and hence makes the Transistors N1, N2 are used for the dynamic feedback control.
M4 and M8 transistors ON. RBL and RWL are lowered since it FC1, FC2 are the lines used to control the N1 and N2 transistors,
gets involved only in read operation. During precharge phase respectively.
RBL is precharged to Vdd, WWL is lowered to ‘0’. During read
phase, RWL is made high hence the RBL which is precharged A. Write operation
gets discharged through the M4 transistor. This RBL is then During write, read and precharge phase of the SRAM
connected to the inverting sense amplifier to read the data. cell, SL is made low and SLB is made high otherwise SL is
Hence here RBL is discharged to zero and when it is given to the made high and SLB is made low to turn off the transistors P1
inverting sense amplifier it is read that data 1 is stored in the and N5. To write 1, SL is lowered to zero and SLB is charged to
SRAM cell. vdd, FC1 is made low, FC2 is made high which makes the
transistor N1 ON and N2 OFF. Data is given to the WBL as 1
and WBL is made high. Then current flows from WBL to Q
III.PROPOSED 10T SRAM CELL DESIGN node and the complement of it is store in QB node. Since, FC2 is
Single ended SRAM with dynamic feedback loop and sleep high, N2 is ON and hence the nodal voltage gets transferred to
cells is shown in Fig. 3. The single ended design is used to the virtual QB node, whereas to write 0, FC1 and FC2 are made
minimize the power consumption during the read and write high and low, respectively. WBL is made low and WWL is
operation of the SRAM. The power consumed in 10T SRAM is made high. Hence, 0 is stored in Q and the complement data is
lesser than the SRAM that uses differential bit line pair. stored in QB. Since FC1 is high N1 transistor is ON and the Q
Moreover, it uses single nmos to write data in SRAM. node is connected to the ground and even if there are any
Third International Conference on Devices, Circuits and Systems (ICDCS'16) 283

charges present in node Q gets discharged through it, whereas stored in node Q, the transistor N4 is not activated and hence
N2 is OFF since FC2 is lowered to zero. Therefore, 0 is stored in does not have a connection to ground. Therefore, the RWL
the node Q and ‘1’ is stored in the node QB. which is made high does not gets discharged to the ground and
this can be sensed through the inverting sense amplifier.
TABLE I
OPERATION OF 10T SRAM CELL
IV. SIMULATION RESULTS
Write Write
Precharge Read
‘1’ ‘0’ Static noise margin (SNM), static power, dynamic power and
WBL ‘0’ ‘0’ ‘1’ ‘0’ total power consumption of the proposed 10T SRAM cell in a
45nm technology is discussed in this section.
RWL ‘0’ ‘1’ ‘0’ ‘0’
FC1 ‘1’ ‘0’ ‘0’ ‘0’ A. Static noise margin (SNM)
FC2 ‘1’ ‘0’ ‘1’ ‘0’ SNM is the term used to characterize the stability of the
SRAM cells. The SNM is the minimum DC noise necessary to
WWL ‘1’ ‘1’ ‘1’ ‘1’
toggle the state of an SRAM cell and also used to quantify the
RBL ‘1’ Discharge ‘1’ ‘1’ SRAM cell immunity to noise.
SL ‘1’ ‘1’ ‘1’ ‘1’

SLB ‘1’ ‘1’ ‘1’ ‘1’

Figure 5. VTC of conventional 6T SRAM

Figure 4. Write ‘1’ waveform of proposed 10 T SRAM cell

B . Read operation
For both read and precharge phase, SL is made low and
SLB is made high. Before reading the data, RBL is precharged
to VDD. When the read operation starts the RWL is made high,
both FC1 and FC2 is made low. If 1 is stored in node Q, the
transistor N4 which is connected to the ground through N5
Figure 6. VTC of proposed 10T SRAM cell.
transistor is activated. Hence, the RWL which is made high, gets
discharged to ground through the N4, N5 transistors. If ‘0’ is
Third International Conference on Devices, Circuits and Systems (ICDCS'16) 284

When the node Q is at 1 and QB is at 0, the dc noise is `V. CONCLUSION

introduced at the node QB and the corresponding Q node values Thus the power consumption is reduced by 20.49% than that of
are noted. Whereas, if the node Q is at 0 and the node QB is at 1, 8T SE dynamic feedback loop SRAM along with high SNM of
DC noise introduced in the node Q and the corresponding QB 350 mV by implementing sleep transistors in the SRAM
node values are noted there by obtaining the so-called Butterfly memory cell which employs single bit line and dynamic
curves. Graphically, the SNM is determined by the length of the feedback loop. It provides advantage for the battery operated
square embedded in the butterfly curve as shown in the Fig. 5 devices like mobiles, laptops etc., to save the battery usage.
and Fig. 6. Eventhough, the area is little bit higher it offers ultra low power
The SNM of conventional 6T SRAM obtained from Fig. 5 consumption with high stability.
is 120 mV and the SNM for the proposed 10T SRAM cell
obtained from the Fig. 7 is 350 mV..
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