Counter Type ADC

Counter type ADC
The counter type ADC is constructed using a binary counter, DAC and a comparator. The
output voltage of a DAC is VD which is equivalent to the corresponding digital input to
DAC.
The following figure shows the n-bit counter type ADC.
Operation:
The n-bit binary counter is initially set to 0 by using the reset command. Therefore, the digital
output is zero and the equivalent voltage VD is also 0V. When the reset command is
removed, the clock pulses are allowed to go through AND gate and are counted by the binary
counter. The D to A converter (DAC) converts the digital output to an analog voltage and is
applied as the inverting input to the comparator. The output of the comparator enables the
AND gate to pass the clock. The number of clock pulses increases with time and the analog
input voltage VD is a rising staircase waveform as shown in the figure below. The counting
will continue until the DAC output VD, equals and just rises more than the unknown analog
input voltage VA. Then the comparator output becomes low and this disables the AND gate
from passing the clock. The counting stops at the instance VA< VD, and at that instant, the
counter stops its progress and the conversion is said to be complete.
The numbers stored in the n-bit counter is the equivalent n-bit digital data for the given
analog input voltage.
Advantages:
1 Simple construction.
2 Easy to design and less expensive.
3 Speed can be adjusted by adjusting the clock frequency.
4 Faster than dual slope type ADC.
Dual Slope type ADC

In dual slope type ADC, the integrator generates two different ramps, one with the known
analog input voltage VA and another with a known reference voltage –Vref. Hence it is
called an s dual-slope A to D converter. The logic diagram for the same is shown below.
Operation:
The binary counter is initially reset to 0000; the output of the integrator is reset to 0V and the
input to the ramp generator or integrator is switched to the unknown analog input voltage
VA.
The analog input voltage VA is integrated by the inverting integrator and generates a negative
ramp output. The output of the comparator is positive and the clock is passed through the
AND gate. This results in the counting up of the binary counter.
The negative ramp continues for a fixed period t1, which is determined by a count detector
for the period t1. At the end of the fixed period t1, the ramp output of the integrator is given
by
∴VS=-VA/RC×t1
When the counter reaches the fixed count at period t1, the binary counter resets to 0000 and
switches the integrator input to a negative reference voltage –Vref.
Now the ramp generator starts with the initial value –Vs and increases in a positive direction
until it reaches 0V and the counter gets advanced. When Vs reaches 0V, comparator output
becomes negative (i.e., logic 0) and the AND gate is deactivated. Hence no further clock is
applied through AND gate. Now, the conversion cycle is said to be completed and the
positive ramp voltage is given by
∴VS=Vref/RC×t2
Where Vref & RC are constants and period t2 is variable.
The dual ramp output waveform is shown below.
Since ramp generator voltage starts at 0V, decreases down to –Vs and then increases to 0V,
the amplitude of negative and positive ramp voltages can be equated as follows.
∴Vref/RC×t2=-VA/RC×t1
∴t2=-t1×VA/Vref
∴VA=-Vref×t1/t2
Thus, the unknown analog input voltage VA is proportional to the time period t2, because
Vref is a known reference voltage and t1 is the predetermined time period.
The actual conversion of analog voltage VA into a digital count occurs during time t2. The
binary counter gives the corresponding digital value for the time period t2. The clock is
connected to the counter at the beginning of t2 and is disconnected at the end of t2. Thus, the
counter counts digital output as
Digital output=(counts/sec) t2
∴Digital output=(counts/sec) [t1×VA/Vref ]
For example, consider the clock frequency is 1 MHz, the reference voltage is -1V, the fixed
time period t1 is 1ms and the RC time constant is also 1 ms. Assuming the unknown analog
input voltage amplitude as VA = 5V, during the fixed time period t1, the integrator output Vs
is
∴VS=-VA/RC×t1= (-5)/1ms×1ms=-5V
During the time period t2, the ramp generator will integrate all the way back to 0V.
∴t2=VS/Vref ×RC= (-5)/(-1)×1ms=5ms=5000μs
Hence the 4-bit counter value is 5000, and by activating the decimal point of MSD seven-
segment displays, the display can directly read as 5V.
Flash Type ADC

Flash Type ADC is based on the principle of comparing analog input voltage with a set of
reference voltages. To convert the analog input voltage into a digital signal of n-bit output,
(2n – 1) comparators are required.
The following figure shows 2- bit flash type ADC
The three op-amps are used as comparators. The non-inverting inputs of all the three
comparators are connected to the analog input voltage. The inverting terminals are connected
to a set of reference voltages (V/4), (2V/4) and (3V/4) respectively which are obtained using
a resistive divider network and power supply +V.
The output of the comparator is in positive saturation (i.e. logic 1), when voltage at non-
inverting terminal is greater than voltage at inverting terminal and is in negative saturation
otherwise.
The following table shows the comparator outputs for different ranges of analog input
voltages and their corresponding digital outputs.
Consider the first condition, where analog input voltage VA is less than (V/4). In this case,
the voltage at the non-inverting terminals of all the three comparators is less than the
respective voltages at inverting terminals and hence the comparator outputs are C1C2C3 =
000. These comparator outputs are applied to the further coding circuit to get the digital
outputs as B1B0 = 00. Similarly, the digital outputs are calculated for the other three
conditions also.
Advantages:
1)It is the fastest type of ADC because the conversion is performed simultaneously through a
set of comparators, hence referred to as flash type ADC. The typical conversion time is 100ns
or less.
2)The construction is simple and easier to design.
Disadvantages:
1)It is not suitable for a higher number of bits.
2)To convert the analog input voltage into a digital signal of n-bit output, (2n – 1)
comparators are required. The number of comparators required doubles for each added bit.
Successive Approximation type ADC

Successive Approximation type ADC is the most widely used and popular ADC method. The
conversion time is maintained constant in successive approximation type ADC, and is
proportional to the number of bits in the digital output, unlike the counter and continuous
type A/D converters. The basic principle of this type of A/D converter is that the unknown
analog input voltage is approximated against an n-bit digital value by trying one bit at a time,
beginning with the MSB. The principle of the successive approximation process for a 4-bit
conversion is explained here. This type of ADC operates by successively dividing the voltage
range by half, as explained in the following steps.
(1) The MSB is initially set to 1 with the remaining three bits set as 000. The digital
equivalent voltage is compared with the unknown analog input voltage.
(2) If the analog input voltage is higher than the digital equivalent voltage, the MSB is
retained as 1 and the second MSB is set to 1. Otherwise, the MSB is set to 0 and the second
MSB is set to 1. Comparison is made as given in step (1) to decide whether to retain or reset
the second MSB.
The above steps are more accurately illustrated with the help of an example.
Let us assume that the 4-bit ADC is used and the analog input voltage is VA = 11 V. when
the conversion starts, the MSB bit is set to 1.
Now VA = 11V > VD = 8V = [1000]2
Since the unknown analog input voltage VA is higher than the equivalent digital voltage VD,
as discussed in step (2), the MSB is retained as 1 and the next MSB bit is set to 1 as follows
VD = 12V = [1100]2
Now VA = 11V < VD = 12V = [1100]2
Here now, the unknown analog input voltage VA is lower than the equivalent digital voltage
VD. As discussed in step (2), the second MSB is set to 0 and the next MSB is set to 1 as
VD = 10V = [1010]2
Now again VA = 11V > VD = 10V = [1010]2
Again, as discussed in step (2) VA>VD, hence the third MSB is retained to 1 and the last bit
is set to 1. The new code word is
VD = 11V = [1011]2
Now finally VA = VD, and the conversion stops.
The functional block diagram of the successive approximation type of ADC is shown below.
It consists of a successive approximation register (SAR), DAC and comparator. The output of
SAR is given to n-bit DAC. The equivalent analog output voltage of DAC, VD is applied to
the non-inverting input of the comparator. The second input to the comparator is the
unknown analog input voltage VA. The output of the comparator is used to activate the
successive approximation logic of SAR.
When the start command is applied, the SAR sets the MSB to logic 1 and other bits are made
logic 0 so that the trial code becomes 1000.
Advantages:
1 Conversion time is very small.
2 Conversion time is constant and independent of the amplitude of the analog input signal
VA.
Disadvantages:
1 Circuit is complex.
2 The conversion time is more compared to flash type ADC.

Counter Type ADC

Uploaded by

Copyright:

Available Formats

Counter Type ADC

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Counter Type ADC

Uploaded by

Copyright:

Available Formats

Counter type ADC

Dual Slope type ADC

Flash Type ADC

Successive Approximation type ADC

You might also like