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D
Enrico/Caruso 15" UMA Schematics Document D

Sandy Bridge
Intel PCH
2011-06-02
C

REV : A00 C

B B

A DV15 HR Vos GIGA HDMI NoSurge A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Cover Page
Size Document Number Rev
A3

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Thursday, June 02, 2011 Sheet
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SYSTEM DC/DC
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DV15 Huron River UMA Block Diagram INPUTS
DCBATOUT
TPS51461
OUTPUTS
0D85V_S0
48

CPU DC/DC
ISL95831HRTZ 42~44
Project code : 91.4IP01.001 INPUTS OUTPUTS
4 DCBATOUT VCC_CORE
D
PCB P/N : 48.4IP16.0SB GFX DC/DC
D

Revision : 10316-1 ISL95831HRTZ 44

Intel CPU INPUTS OUTPUTS
DCBATOUT VCC_GFXCORE
DDRIII 1066/1333 Channel A DDRIII DIMM 1
Sandy Bridge 1066/1333 14 SYSTEM DC/DC
TPS51218 45
INPUTS OUTPUTS
DDRIII 1066/1333 Channel B DDRIII DIMM 2 DCBATOUT 1D05V_VTT
15
1066/1333
SYSTEM DC/DC
TPS51123RGER 41
4,5,6,7,8,9,10,11,12,13
INPUTS OUTPUTS
5V_AUX_S5
3D3V_AUX_S5
DCBATOUT 5V_S5
3D3V_S5
Giga NIC 15V_S5
C C
FDIx4x2 DMIx4 Realtek
RTL8111E-VB SYSTEM DC/DC
31 46
RGB CRT
TPS51216RUKR
CRT 55
10/100/NIC INPUTS OUTPUTS
Intel PCIE x 1 Realtek
RJ45 1D5V_S3
RTL8105E CONN DCBATOUT 0D75V_S0
31 DDR_VREF_S3
LCD LVDS(Single Channel)
49
PCH
MAXIM CHARGER
Cougar Point Mini-Card BQ24707 40
HDMI HDMI PCIE x 1; USB 2.0 x 1
57
14 USB 2.0/1.1 ports 802.11b/g/n INPUTS OUTPUTS
BT V3.0+HS 65
ETHERNET (10/100/1000Mb) +DC_IN_S5
+PBATT DCBATOUT
High Definition Audio
Right Side: USB 2.0 x 2 26
USB x2
SATA ports (6)
CardReader SD/MMC/MS
SYSTEM DC/DC
61 47
PCIE ports (8) USB 2.0 x 1 TPS51311RGTR
Realtek Slot 74
Left Side: USB 2.0 x 1
LPC I/F
32
INPUTS
26 OUTPUTS
RTS5138
B USB x1 61
ACPI 1.1
3D3V_S5 1D8V_S0 B

54 USB 2.0 x 1 Switches

CAMERA
17,18,19,20,21,22,23,24,25,26 SATA x 2 HDD INPUTS OUTPUTS
56 1D5V_S3 1D5V_S0
HDA
5V_S5 5V_S0
3D3V_S5 3D3V_S0
ODD
SPI

56
PCB LAYER
LPC Bus

L1:Top L4:Signal
Internal Analog MIC
HDA Flash ROM LPC debug port
L2:GND L5:VCC
L3:Signal L6:Bottom
SPI

71
CODEC 4MB 60
HP
IDT 92HD87B129 KBC
MIC IN Thermal
A
NUVOTON P2800 DV15 HR Vos GIGA HDMI NoSurge A
D/A 28
NPCE795P 27
Thermal Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2CH SPEAKER G709 28 Taipei Hsien 221, Taiwan, R.O.C.
(1CH 2W/4ohm) 58
Title
Touch Int. Fan Control Block Diagram
Size Document Number Rev
PAD KB P2793

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28 A3
69 69 Enrico/Caruso 15 HR X01
Date: Thursday, June 02, 2011 Sheet 2 of 104
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Huron River Platform

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Power Sequence
(AC mode) red word: KBC GPIO
(DC mode) red word: KBC GPIO

+RTC_VCC
+RTC_VCC t01 >9ms
t01 >9ms
RTC_RST#
RTC_RST#
DCBATOUT
DCBATOUT

Within logic high level and disable if

3D3V_AUX_S5
it is less than the logic low level.
3D3V_AUX_S5
KBC GPIO34 control power on by 3V_5V_EN
D D
S5_ENABLE Sense the power button status
Press Power button
KBC_PWRBTN# Platform to KBC PSL_IN2
5V_S5
V5REF_Sus must be powered up before EC_ENABLE#_1(GPIO31) keep low
VccSus3_3, or after VccSus3_3 within 3D3V_S5 Ta 3D3V_AUX_KBC
0.7 V. Also, V5REF_Sus must power
down after VccSus3_3, or before KBC GPIO34 control power on by 3V_5V_EN
VccSus3_3 within 0.7 V.
+5VA_PCH_VCC5REFSUS S5_ENABLE
KBC GPIO43 to PCH
PM_RSMRST#(EC Delay 40ms) t05 >10ms 5V_S5
PCH to KBC GPIO00 V5REF_Sus must be powered up before
+5V_ALW & +3.3V_ALW need meet 0.7V difference
PCH_SUSCLK_KBC t07>5ms VccSus3_3, or after VccSus3_3 within 3D3V_S5
0.7 V. Also, V5REF_Sus must power
KBC GPO84 to PCH down after VccSus3_3, or before
+5V_ALW & +3.3V_ALW need meet 0.7V difference
Not floating. VccSus3_3 within 0.7 V.
AC_PRESENT 0ms<t08a<90ms +5VA_PCH_VCC5REFSUS Ta

KBC GPIO20 to PCH

Press Power button
3D3V_AUX_KBC PM_PWRBTN#
Platform to KBC PSL_IN2
Sense the power button status
AC KBC_PWRBTN#
KBC GPIO43 to PCH
This signal has an internal PM_RSMRST# t05 >10ms
pull-up resistor and has an KBC GPIO20 to PCH
internal 16 ms de-bounce on the PCH to KBC GPIO00
input. AC PM_PWRBTN#
PCH_SUSCLK_KBC t07>5ms

AC PM_PWRBTN# DC PCH_RSMRST#

PCH to KBC GPIO44 PCH to KBC GPIO44

PM_SLP_S4# PM_SLP_S4#
t10 PCH to KBC GPIO01 t10 PCH to KBC GPIO01
PM_SLP_S3# >30us PM_SLP_S3# >30us
KBC GPIO23 to LAN KBC GPIO23 to LAN
PM_LAN_ENABLE PM_LAN_ENABLE
Enable by PM_SLP_S4# Enable by PM_SLP_S4#
1D5V_S3 1D5V_S3

DDR_VREF_S3(0.75V) DDR_VREF_S3(0.75V)
C
+5V_RUN & +3.3V_RUN need meet 0.7V difference +5V_RUN & +3.3V_RUN need meet 0.7V difference C

5V_S0 5V_S0
Tb
V5REF must be powered up before 3D3V_S0 V5REF must be powered up before 3D3V_S0
Vcc3_3, or after Vcc3_3 within 0.7 V. Vcc3_3, or after Vcc3_3 within 0.7 V.
Also, V5REF must power down after Also, V5REF must power down after
Vcc3_3, or before Vcc3_3 within 0.7 V. Vcc3_3, or before Vcc3_3 within 0.7 V.
+5VS_PCH_VCC5REF Tb +5VS_PCH_VCC5REF Tb

1D5V_S0 1D5V_S0

1D8V_S0 1D8V_S0

0D75V_S0 0D75V_S0
1D8V_S0 & 1D5V_S3 power ready 1D8V_S0 & 1D5V_S3 power ready
RUNPWROK RUNPWROK

1D05V_VTT 1D05V_VTT
TPS51218 PGOOD TPS51218 PGOOD
1.05VTT_PWRGD 1.05VTT_PWRGD

0D85V_S0 0D85V_S0

0D85V_S0 0D85V_S0
TPS51461RGER PGOOD TPS51461RGER PGOOD
D85V_PWRGD D85V_PWRGD

CPU SVID BUS SetVID ACK SetVID ACK

50us< t36 <2000us CPU SVID BUS 50us< t36 <2000us

VCC_CORE VCC_CORE

VCC_GFXCORE VCC_GFXCORE
t37 t37
<5ms
ISL95831 PGOOD to system <5ms
ISL95831 PGOOD to system
IMVP_PWRGD IMVP_PWRGD

CLK_EXP_P CLK_EXP_P
ALL_SYS_PWRGD=D85V_PWRGD ALL_SYS_PWRGD=D85V_PWRGD
B This signal represents the Power t14 >99ms KBC GPIO77 to PCH This signal represents the Power t14 >99ms KBC GPIO77 to PCH B
Good for all the non-CORE and Good for all the non-CORE and
non-graphics power rails.
PWROK non-graphics power rails.
PWROK
t18 >0us t18 >0us
D85V_PWRGD D85V_PWRGD
2ms< t17 <650ms PCH to CPU 2ms< t17 <650ms PCH to CPU
VDDPWRGOOD VDDPWRGOOD
t19 >1ms t19 >1ms
t20 >2ms t20 >2ms
1D8V_S0 1D8V_S0
5ms< t13 <650ms PCH to CPU 5ms< t13 <650ms PCH to CPU
H_CPUPWRGD H_CPUPWRGD

SYS_PWROK SYS_PWROK
t21+t22 >1ms+60us t21+t22 >1ms+60us
1ms< t25 <100ms PCH to all system 1ms< t25 <100ms PCH to all system
PLT_RST# PLT_RST#
t39 <200us t39 <200us
DMI DMI

A A

DV15 HR Vos GIGA HDMI NoSurge

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

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Size
A1

Date:
Document Number
Power Sequence
Enrico/Caruso 15 HR
Thursday, June 02, 2011
1
Sheet 98 of 104
Rev
X01
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Wistron HURON RIVER POWER UP SEQUENCE DIAGRAM
5V_S5 DCBATOUT
-6
AC AD+
Adapter in
Page38
-3a -3a -3a 3a
VDDP VIN 1D5V_S3
D PWR_5V3D3V_ENC 3V_5V_EN S5_ENABLE VOUT D

3
PM_SLP_S4#
EN
-3b -3c DDR_VREF_S3 3b
PWR_CHG_ACOK REF
SWITCH ENC 5V_S5 15V_S5
LL1 PUMP
Page40
3D3V_S5 TPS51216RUKR
LL2
SWITCH 5a 0D75V_S0
Page40 5V_AUX_S5 VTT
TPS51123RGER VREG5 1.05VTT_PWRGD
DC/DC 3D3V_AUX_S5 -4 VTT_EN
-5 (3V/5V) VREG3 3 RUNPWROK
PGD
DCBATOUT 3V_5V_POK PM_SLP_S4# Page46
VIN PGOOD 5
Page41

4 5V_S5 3D3V_S5
DC BQ24707 5V_S0
BT+ PM_SLP_S3#
Battery Charger SWITCH
Page39 -3 Page37
3D3V_AUX_KBC -3a VDD VIN 1D8V_S0
VOUT
Page40 ACOK 3D3V_S0 4
S5_ENABLE SWITCH
-6a Page37 PM_SLP_S3# TPS53311RGTR
EN
RUNPWROK
AC_IN# GPIO34 PGD
GPIO70 1D5V_S0
Page47
C SWITCH C

Page37 5
1 SLP_S4# SLP_S3#
-1 KBC
KBC_PWRBTN#
GPIO6 NPCE795P -2
9 AND GATE
Power Button PM_RSMRST# 0D75V_EN
PM_SLP_S4# GPIO43 RSMRST# B VDDPWRGOOD
GPIO44 PM_PWRBTN# PM_DRAM_PWRGD Y SM_DRAMPWROK
PM_SLP_S3# GPIO20 PWRBTN# DRAMPWRGD A
GPIO01
2 H_CPUPWRGD H_CPUPWRGD_R
PROCPWRGD UNCOREPWRGOOD
Page27 Cougar Point 10
GPIO77 PCH Sandy Bridge
8
15 CPU
S0_PWR_GOOD
APWROK
PWROK PLT_RST# BUF_CPU_RST#
PLTRST# RSTIN#
SYS_PWROK SVID
SYS_PWROK

SVID
14
11
5V_S5 DCBATOUT

B V5IN VIN 1D05_VTT 5a B

VOUT
5
RUNPWROK TPS51218DSCR
EN 1.05VTT_PWRGD
Page45 PGOOD
14
5V_S5 DCBATOUT 5b IMVP_PWRGD SYS_PWROK

VDDP VIN 0D85_S0 5c -4

VOUT
5b -7 3D3V_AUX_S5
1.05VTT_PWRGD TPS51461RGER RTC_AUX_S5
EN D85V_PWRGD
Page48 PGOOD -8
+RTC_VCC
6
DCBATOUT
RTC battery

11 VIN VCC_CORE
OUTPUT
SVID 12
SVID VCC_GFXCORE
A VR OUTPUT A

6 7 ISL95831HRTZ
D85V_PWRGD IMVP_VR_ON 13 DV15 HR Vos GIGA HDMI NoSurge
VR_ON IMVP_PWRGD
Page42 & 43 & 44 PGOOD
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Power Up Sequence: -8 ~ 15 Title

Size Document Number

Power Sequence Diagram
Rev
A2
Enrico/Caruso 15 HR X01

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D D

AD+
AO4407A DCBATOUT TPS51216RUKR
Adapter
40

ISL95831HRTZ TPS51218DSCR TPS51461RGER

DDR_VREF_S3 0D75V_S0 1D5V_S3
BT+ AO4407A
Battery Charger
40
BQ24707 VCC_CORE VCC_GFXCORE 1D05V_VTT 0D85V_S0
TPCA8062
+PBATT

TPS51123RGER 1D5V_S0

C C

3D3V_AUX_S5
3D3V_S5
15V_S5 5V_AUX_S5 5V_S5

G547F2P81U G547F2P81U AO4468 AO4468 PA102FMG

DMP2130L TPS51311RGTR

5V_USB2_S3 5V_USB1_S3 5V_S0 3D3V_S0 3D3V_LAN_S5

3D3V_AUX_KBC 1D8V_S0

LDO
AO6402A RTS5138 RTL8111E
B B

LCDVDD 3D3V_CARD_S0 CTRL10A_R

Power Shape

Regulator LDO Switch

A DV15 HR Vos GIGA HDMI NoSurge A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Size
Power Block Diagram
Document Number Rev
A3

5 4
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Thursday, June 02, 2011 Sheet
1
100 of 104
X01