Task Switching:

The 80386 switches execution to another task in any of four cases:

1. The current task executes a JMP or CALL that refers to a TSS descriptor.
2. The current task executes a JMP or CALL that refers to a task gate.
3. An interrupt or exception vectors to a task gate in the IDT.
4. The current task executes an IRET when the NT flag is set.

JMP, CALL, IRET, interrupts, and exceptions are all ordinary mechanisms of the
80386 that can be used in circumstances that do not require a task switch. Either the
type of descriptor referenced or the NT (nested task) bit in the flag word distinguishes
between the standard mechanism and the variant that causes a task switch.

To cause a task switch, a JMP or CALL instruction can refer either to a TSS
descriptor or to a task gate. The effect is the same in either case: the 80386 switches to
the indicated task.

An exception or interrupt causes a task switch when it vectors to a task gate in the
IDT. If it vectors to an interrupt or trap gate in the IDT, a task switch does not occur .
Refer to Chapter 9 for more information on the interrupt mechanism.

Whether invoked as a task or as a procedure of the interrupted task, an interrupt

handler always returns control to the interrupted procedure in the interrupted task. If
the NT flag is set, however, the handler is an interrupt task, and the IRET switches
back to the interrupted task.

A task switching operation involves these steps:

1. Checking that the current task is allowed to switch to the designated task. Data-
access privilege rules apply in the case of JMP or CALL instructions. The DPL
of the TSS descriptor or task gate must be numerically greater (e.g., lower
privilege level) than or equal to the maximum of CPL and the RPL of the gate
selector. Exceptions, interrupts, and IRET are permitted to switch tasks
regardless of the DPL of the target task gate or TSS descriptor.
2. Checking that the TSS descriptor of the new task is marked present and has a
valid limit. Any errors up to this point occur in the context of the outgoing task.
Errors are restartable and can be handled in a way that is transparent to
applications procedures.
3. Saving the state of the current task. The processor finds the base address of the
current TSS cached in the task register. It copies the registers into the current
TSS (EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI, ES, CS, SS, DS, FS, GS,
 and the flag register). The EIP field of the TSS points to the instruction after the
one that caused the task switch.
4. Loading the task register with the selector of the incoming task's TSS
descriptor, marking the incoming task's TSS descriptor as busy, and setting the
TS (task switched) bit of the MSW. The selector is either the operand of a
control transfer instruction or is taken from a task gate.
5. Loading the incoming task's state from its TSS and resuming execution. The
registers loaded are the LDT register; the flag register; the general registers
EIP, EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI; the segment registers ES,
CS, SS, DS, FS, and GS; and PDBR. Any errors detected in this step occur in
the context of the incoming task. To an exception handler, it appears that the
first instruction of the new task has not yet executed.

Paging:

Advantages :
 Allocating memory is easy and cheap
 Any free page is ok, OS can take first one out of list it keeps
 Eliminates external fragmentation
 Data (page frames) can be scattered all over PM
 Pages are mapped appropriately anyway
 Allows demand paging and pre paging
 More efficient swapping
 No need for considerations about fragmentation
 Just swap out page least likely to be used

Disadvantages :
 Longer memory access times (page table lookup)
 Can be improved using TLB
 Guarded page tables
 Inverted page tables
 Memory requirements (one entry per VM page)
 Improve using Multilevel page tables and variable page sizes (super-pages)
 Guarded page tables
 Page Table Length Register (PTLR) to limit virtual memory size
 Internal fragmentation
Segment descriptors:
There is a segment descriptor used to describe each segment in the system. There are
regular descriptors and system descriptors. Here's a descriptor in all its glory. The
strange format is essentially to maintain compatibility with the 286. Note that it takes
8 bytes.

63-54 55 54 53 52 51-48 47 46 45 44-40 39-16 15-0

Base G D R U Limit P DPL S TYPE Segment Base Segment Limit
31-24 19-16 23-0 15-0

Explanation:

R reserved (0)

DPL 0 means kernel, 3 means user

G 1 means 4K granularity (Always set in Linux)

D 1 means default operand size 32bits

U programmer definable

P 1 means present in physical memory

S 0 means system segment, 1 means normal code or data segment.

Type
There are many possibilities. Interpreted differently for system and normal descriptors.

Pentium Architecture:
The Pentium family of processors originated from the 80486 microprocessor. The term ''Pentium processor'' refers to a family of
microprocessors that share a common architecture and instruction set. The first Pentium processors were introduced in 1993. It runs
at a clock frequency of either 60 or 66 MHz and has 3.1 million transistors. Some of the features of Pentium architecture are
 Complex Instruction Set Computer (CISC) architecture with Reduced Instruction Set Computer (RISC) performance.
 64-Bit Bus
 Upward code compatibility.
 Pentium processor uses Superscalar architecture and hence can issue multiple instructions per cycle.
 Multiple Instruction Issue (MII) capability.
 Pentium processor executes instructions in five stages. This staging, or pipelining, allows the processor to overlap multiple
instructions so that it takes less time to execute two instructions in a row.
 The Pentium processor fetches the branch target instruction before it executes the branch instruction.
  The Pentium processor has two separate 8-kilobyte (KB) caches on chip, one for instructions and one for data. It allows the
Pentium processor to fetch data and instructions from the cache simultaneously.
 When data is modified, only the data in the cache is changed. Memory data is changed only when the Pentium processor
replaces the modified data in the cache with a different set of data
 The Pentium processor has been optimized to run critical instructions in fewer clock cycles than the 80486 processor.

Fig 35.1 Superscalar Architecture of Pentium

The Pentium processor has two primary operating modes -

1. Protected Mode - In this mode all instructions and architectural features are available, providing the highest performance
and capability. This is the recommended mode that all new applications and operating systems should target.
2. Real-Address Mode - This mode provides the programming environment of the Intel 8086 processor, with a few extensions.
Reset initialization places the processor in real mode where, with a single instruction, it can switch to protected mode

The Pentium's basic integer pipeline is five stages long, with the stages broken down as follows:
1. Pre-fetch/Fetch : Instructions are fetched from the instruction cache and aligned in pre-fetch buffers for decoding.
2. Decode1 : Instructions are decoded into the Pentium's internal instruction format. Branch prediction also takes place at this
stage.
3. Decode2 : Same as above, and microcode ROM kicks in here, if necessary. Also, address computations take place at this
stage.
4. Execute : The integer hardware executes the instruction.
5. Write-back : The results of the computation are written back to the register file.
 Fig 35.2 Pentium pipeline stages

Floating Point Unit :

There are 8 general-purpose 80-bit Floating point registers. Floating point unit has 8 stages of pipelining. First five are similar to integer
unit. Since the possibility of error is more in Floating Point unit (FPU) than in integer unit, additional error checking stage is there in
FPU. The floating point unit is shown as below

Fig 35.3 Floating Point Unit

FRD - Floating Point Rounding

FDD - Floating Point Division
FADD - Floating Point Addition
FEXP - Floating Point Exponent
FAND - Floating Point And
FMUL - Floating Point Multiply
 RISC & CISC Features:
RISC (Reduced Instruction Set Computer)
RISC stands for Reduced Instruction Set Computer. To execute each instruction, if there is separate electronic circuitry
in the control unit, which produces all the necessary signals, this approach of the design of the control section of the
processor is called RISC design. It is also called hard-wired approach.
Examples of RISC processors:
 IBM RS6000, MC88100
 DEC’s Alpha 21064, 21164 and 21264 processors

Features of RISC Processors:

The standard features of RISC processors are listed below:
 RISC processors use a small and limited number of instructions.
 RISC machines mostly uses hardwired control unit.
 RISC processors consume less power and are having high performance.
 Each instruction is very simple and consistent.
 RISC processors uses simple addressing modes.
 RISC instruction is of uniform fixed length.

CISC (Complex Instruction Set Computer)

CISC stands for Complex Instruction Set Computer. If the control unit contains a number of micro-electronic circuitry to
generate a set of control signals and each micro-circuitry is activated by a micro-code, this design approach is called
CISC design.
Examples of CISC processors are:
 Intel 386, 486, Pentium, Pentium Pro, Pentium II, Pentium III
 Motorola’s 68000, 68020, 68040, etc.

Features of CISC Processors:
The standard features of CISC processors are listed below:
 CISC chips have a large amount of different and complex instructions.
 CISC machines generally make use of complex addressing modes.
 Different machine programs can be executed on CISC machine.
 CISC machines uses micro-program control unit.
 CISC processors are having limited number of registers.

Performance issues in pipelining:

Pipelining increases the CPU instruction throughput - the number of instructions
completed per unit of time. But it does not reduce the execution time of an individual
instruction. In fact, it usually slightly increases the execution time of each instruction
due to overhead in the pipeline control.
The increase in instruction throughput means that a program runs faster and has lower
total execution time.

Limitations on practical depth of a pipeline arise from:

Pipeline latency. The fact that the execution time of each instruction does not decrease
puts limitations on pipeline depth;
Imbalance among pipeline stages. Imbalance among the pipe stages reduces
performance since the clock can run no faster than the time needed for the slowest
pipeline stage;
Pipeline overhead. Pipeline overhead arises from the combination of pipeline register
delay (setup time plus propagation delay) and clock skew.
Once the clock cycle is as small as the sum of the clock skew and latch overhead, no
further pipelining is useful, since there is no time left in the cycle for useful work.

Simple example
Consider a nonpipelined machine with 6 execution stages of lengths 50 ns, 50 ns, 60
ns, 60 ns, 50 ns, and 50 ns.
- Find the instruction latency on this machine.
- How much time does it take to execute 100 instructions?

Solution:

Instruction latency = 50+50+60+60+50+50= 320 ns

Time to execute 100 instructions = 100*320 = 32000 ns

Suppose we introduce pipelining on this machine. Assume that when introducing

pipelining, the clock skew adds 5ns of overhead to each execution stage.

- What is the instruction latency on the pipelined machine?

- How much time does it take to execute 100 instructions?

Solution:
Remember that in the pipelined implementation, the length of the pipe stages must all
be the same, i.e., the speed of the slowest stage plus overhead. With 5ns overhead it
comes to:

The length of pipelined stage = MAX(lengths of unpipelined stages) + overhead = 60

+ 5 = 65 ns
Instruction latency = 65 ns
Time to execute 100 instructions = 65*6*1 + 65*1*99 = 390 + 6435 = 6825 ns

- What is the speedup obtained from pipelining?

Solution:
Speedup is the ratio of the average instruction time without pipelining to the average
instruction time with pipelining.
(here we do not consider any introduced by different types of hazards which we will
look at in the next section)
Average instruction time not pipelined = 320 ns
Average instruction time pipelined = 65 ns
Speedup for 100 instructions = 32000 / 6825 = 4.69

The Programming Model:

The programming model of the 8086 through the Pentium II’s considered to be program visible because its
registers are used during application programming and are specified by the instructions. Other registers, detailed later
in this chapter, are considered to be program invisible because they are not addressable directly during applications
programming, but may be used indirectly during system programming. Only the 80286 and above contain the
program-invisible registers used to control and operate the protected memory system.

Figure 2-1 illustrates the programming model of the 8086 through the Pentium II microprocessor. The earlier
8086, 8088, and 80286 contain 16-bit internal architectures, a subset of the registers. The 80386, 80486, Pentium,
Pentium Pro, and Pentium II microprocessors contain full 32-bit internal architectures. The architectures of the earlier
8086 through the 80286 are fully upward-compatible to the 80386 through the Pentium II. The shaded areas in this
illustration represent registers that are not found in the 8086, 8088, or 80286 microprocessors.
The programming model contains 8-, 16-, and 32-bit registers. The 8-bit registers
are AH, AL, BH, BL, CH, CL, DH, and DL and are referred to when an instruction is formed using these two-letter
designations. The 16-bit registers are AX, BX, CX, DX, SP, BP, DI, SI, IP, FLAGS, CS, DS, ES, SS, FS, and GS.
The extended 32-bit registers are EAX, EBX, ECX, EDX, ESP, EBP, EDI, ESI, EIP, and EFLAGS. These 32-bit
extended registers, and 16-bit registers ES and GS are available only in the 80386 and above.

Some registers are general-purpose or multipurpose registers, while some have special purposes.
The multipurpose registers include EAX, EBX, ECX, EDX, EBP, EDI, and ESI. These registers hold various data
sizes (bytes, words, or doublewords) and are used for almost any purpose, as dictated by a program.

Data Transfer Instruction:

1.CMPXCHG: This instruction compares the accumulator (AL/AX/EAX) (8-32 bits)
with the operand "dest". If equal the "dest" is loaded with the operand "src",
otherwise the accumulator is loaded with "dest".
Usage CMPXCHG dest,src
Flags AF PF OF CF ZF SF
Example: Assume AX = 0010H, CX = 0010H, DX = 0012H
CMPXCHG CX, DX; CX = AX so CX = 0012H

2.LAHF: This instruction copies the low byte of the flag register to AH. Only five
flags are copied; the remaining bits are undefined. After copying, AH looks like this: AH
= SF ZF xx AF xx PF xx CF
Usage LAHF
Flags None

3.LAR: LOAD ACCESS RIGHT (286+ protected) – The high byte of the destination
register is overwritten by the value of access rights byte and the low order byte is
zeroed depending on selection in the source operand. The zero flag is set if the load
operation is successful.

USAGE:LAR dest,src
FLAGS: ZF

4.LDS/LES: This instruction copies a word from two memory locations into the register
specified in the instruction. It then copies a word from the next two memory locations
into the DS(ES) register. It is useful for pointing to SI(DI) and DS(ES) at the start of a
string before using a string instruction.
Usage LDS dest, src
FLAGS: None
Example: LDS BX,[4326];

5.LEA: Transfers offset address of "src" to the destination register. LEA is very similar
to MOV, except that math can be done on the original value before it is used.
Usage LEA dest, src
Flags None
Example: lea eax, [eax+eax] ;
lea edi, [esi+0Bh] ;
6.MOV: The MOV instruction copies a word or byte of data from a specified source to a
specified destination. The source and destination in an instrcution cannot both be
memory locations. For the MOV instruction, the src and dest addresses must both be of
type byte or both of type word.
Usage MOV dest, src
Flags None.
Example: mov eax, ebx
mov byte ptr [var], 5

Data Movement Instruction:

Data movement instructions move data from one place, called the source operand, to
another place, called the destination operand. Data movement instructions can be
grouped into loads, stores, moves, and immediate loads.

 Load instructions move data from memory to registers.

 Store instructions move data from registers to memory.
 Move instructions move data from one register to another.
 Immediate load instructions move constants, including addresses, to registers.

Load Instructions

Load instructions move data from memory to registers.

Instruction Operation
lb Rd, addr load byte sign extended
lbu Rd, addr load byte zero extended
lh Rd, addr load halfword sign extended
lhu Rd, addr load halfword zero extended
lw Rd, addr load word
l.d Fd, addr load double
l.s Fd, addr load float
Store Instructions

Store instructions move data from registers to memory.

Instruction Operation
sb Rs, addr store byte
sh Rs, addr store halfword
sw Rs, addr store word
s.d Fs, addr store double
s.s Fs, addr store float
Move Instructions

Move instructions move data from one register to another.

Instruction Operation
mfc0 Rd, Cs load from control register
mfc1 Rd, Fs load from floating point register
move Rd, Rs move integer data
move.d Fd, Fs move double
move.s Fd, Fs move float
mtc0 Rs, Cd store to control register
mtc1 Rs, Fd store to floating point register
Immediate Load Instructions

Immediate load instructions move constants to registers.

Instruction Operation
la Rd, label load address
li Rd, const load immediate
li.d Fd, const load double immediate
li.s Fd, const load float immediate

Segment Register:

Additional registers, called segment registers, generate memory addresses when combined with other registers in the
microprocessor. There are either four or six segment registers in various versions of the microprocessor. A segment
register functions differently in the real mode when compared to the protected mode operation of the microprocessor.
Following is a list of each segment register, along with its function in the system:

CS (code)

The code segment is a section of memory that holds the code (programs and procedures) used by the microprocessor.
The code segment register defines the starting address of the section of memory holding code. In real
mode operation, it defines the start of a 64K-byte section of memory; in protected mode, it selects a
descriptor that describes the starting address and length of a section of memory holding code. The code segment is
limited to 64K bytes in the 8088-80286, and 4G bytes in the 80386 and above when these microprocessors operate
in the protected mode.

DS (data)

The data segment is a section of memory that contains most data used by a program. Data are accessed in the data
segment by an offset address or the contents of other registers that hold the offset address. As
with the
code segment and other segments, the length is limited to 64K bytes in the 8086-80286,
and 4G bytes in the 80386 and above.
ES (extra)

The extra segmentis an additional data segment that is used by some of the string instructions
to hold destination data.
SS (stack)

The stack segment defines the area of memory used for the stack. The stack entry point is
determined by the stack segment and stack pointer registers. The BP register also addresses data within the stack
segment.

FS and GS

The FS and GS segments are supplemental segment registers available in

the 80386, 80486, Pentium. and Pentium
Pro microprocessors to allow two additional memory segments for access by programs.

8051 Microcontroller architecture:

The 8051 Microcontroller is one of the basic type of microcontroller, designed by Intel in 1980’s. This
microcontroller was based on Harvard Architecture and developed primarily for use in embedded
systems technology. Normally, this microcontroller was developed using NMOS technology, which requires more
power to operate. Therefore, Intel redesigned Microcontroller 8051 using CMOS technology and their updated
versions came with a letter C in their name, for instance an 80C51 it is an 8 bit microcontroller. These
latest Microcontrollers requires less power to operate as compared to their previous versions. The 8051
Microcontroller has two buses and two memory spaces of 64K X 8 size for program and data units. It has an 8 bit
processing unit and 8 bit accumulator units.
Central Processor Unit (CPU)

As we know that the CPU is the brain of any processing device of the microcontroller. It monitors and
controls all operations that are performed on the Microcontroller units. The User has no control over the
work of the CPU directly . It reads program written in ROM memory and executes them and do the expected
task of that application.

Interrupts

As its name suggests, Interrupt is a subroutine call that interrupts of the microcontrollers main operations
or work and causes it to execute any other program, which is more important at the time of operation. The
feature of Interrupt is very useful as it helps in case of emergency operations. An Interrupts gives us a
mechanism to put on hold the ongoing operations, execute a subroutine and then again resumes to another
type of operations.

The Microcontroller 8051 can be configured in such a way that it temporarily terminates or pause the main
program at the occurrence of interrupts. When a subroutine is completed, Then the execution of main
program starts. Generally five interrupt sources are there in 8051 Microcontroller. There are 5 vectored
interrupts are shown in below

 INTO
 TFO
 INT1
 TF1
 R1/T1

Out of these, (INT0) ̅ and (INT1) ̅ are external interrupts that could be negative edge triggered or low
level triggered. When All these interrupts are activated, set the corresponding flogs except for serial
interrupt,.The interrupt flags are cleared when the processor branches to the interrupt service routine
(ISR). The external interrupt flags are cleared when the processor branches to the interrupt service
routine, provides the interrupt is a negative edge triggered whereas the timers and serial port
interrupts two of them are external interrupts, two of them are timer interrupts and one serial port
interrupt terminal in general.

Memory

Microcontroller requires a program which is a collection of instructions. This program tells microcontroller
to do specific tasks. These programs require a memory on which these can be saved and read by
Microcontroller to perform specific operations of a particular task. The memory which is used to store
the program of the microcontroller is known as code memory or Program memory of applications. It is
known as ROM memory of microcontroller also requires a memory to store data or operands temporarily
of the micro controller. The data memory of the 8051 is used to store data temporarily for operation is
known RAM memory. 8051 microcontroller has 4K of code memory or program memory,that has 4KB
ROM and also 128 bytes of data memory of RAM.

BUS

Basically Bus is a collection of wires which work as a communication channel or medium for transfer of
Data. These buses consists of 8, 16 or more wires of the microcontroller. Thus, these can carry 8 bits,16
bits simultaneously. Hire two types of buses that are shown in below
  Address Bus
 Data Bus

Address Bus: Microcontroller 8051 has a 16 bit address bus for transferring the data. It is used to address
memory locations and to transfer the address from CPU to Memory of the microcontroller. It has four
addressing modes that are

 Immediate addressing modes.

 Bank address (or) Register addressing mode.
 Direct Addressing mode.
 Register indirect addressing mode.

Data Bus: Microcontroller 8051 has 8 bits of the data bus, which is used to carry data of particular
applications.

Oscillator

Generally, we know that the microcontroller is a device, therefore it requires clock pulses for its operation
of microcontroller applications. For this purpose, microcontroller 8051 has an on-chip oscillator which
works as a clock source for Central Processing Unit of the microcontroller. The output pulses of oscillator
are stable. Therefore, it enables synchronized work of all parts of the 8051 Microcontroller.

Input/Output Port

Normally microcontroller is used in embedded systems to control the operation of machines in the
microcontroller. Therefore, to connect it to other machines, devices or peripherals we require I/O
interfacing ports in the microcontroller interface. For this purpose microcontroller 8051 has 4 input, output
ports to connect it to the other peripherals

Timers/Counters

8051 microcontroller has two 16 bit timers and counters. These counters are again divided into a 8 bit
register. The timers are used for measurement of intervals to determine the pulse width of pulses.

Applications of 8051 Microcontroller

Some of the applications of 8051 is mainly used in daily life & industrial applications also some of that
applications are shown below

 Light sensing and controlling devices

 Temperature sensing and controlling devices
 Fire detections and safety devices
 Automobile applications
 Defense applications
Data Memory (RAM) of 8051 Microcontroller:
The Data Memory or RAM of the 8051 Microcontroller stores temporary data and intermediate
results that are generated and used during the normal operation of the microcontroller. Original
Intel’s 8051 Microcontroller had 128B of internal RAM.

But almost all modern variants of 8051 Microcontroller have 256B of RAM. In this 256B, the first
128B i.e. memory addresses from 00H to 7FH is divided in to Working Registers (organized as
Register Banks), Bit – Addressable Area and General Purpose RAM (also known as Scratchpad
area).

In the first 128B of RAM (from 00H to 7FH), the first 32B i.e. memory from addresses 00H to
1FH consists of 32 Working Registers that are organized as four banks with 8 Registers in each
Bank.

The 4 banks are named as Bank0, Bank1, Bank2 and Bank3. Each Bank consists of 8 registers
named as R0 – R7. Each Register can be addressed in two ways: either by name or by
address.

To address the register by name, first the corresponding Bank must be selected. In order to
select the bank, we have to use the RS0 and RS1 bits of the Program Status Word (PSW)
Register (RS0 and RS1 are 3rd and 4th bits in the PSW Register).
When addressing the Register using its address i.e. 12H for example, the corresponding Bank
may or may not be selected. (12H corresponds to R2 in Bank2).

The next 16B of the RAM i.e. from 20H to 2FH are Bit – Addressable memory locations. There
are totally 128 bits that can be addressed individually using 00H to 7FH or the entire byte can
be addressed as 20H to 2FH.

For example 32H is the bit 2 of the internal RAM location 26H.

The final 80B of the internal RAM i.e. addresses from 30H to 7FH, is the general purpose RAM
area which are byte addressable.

These lower 128B of RAM can be addressed directly or indirectly.

The upper 128B of the RAM i.e. memory addresses from 80H to FFH is allocated for Special
Function Registers (SFRs). SFRs control specific functions of the 8051 Microcontroller. Some of
the SFRs are I/O Port Registers (P0, P1, P2 and P3), PSW (Program Status Word), A
(Accumulator), IE (Interrupt Enable), PCON (Power Control), etc.

.
Program Memory:
The first models of the 8051 microcontroller family did not have internal program
memory. It was added as an external separate chip. These models are recognizable
by their label beginning with 803 (for example 8031 or 8032). All later models have
a few Kbyte ROM embedded. Even though such an amount of memory is sufficient
for writing most of the programs, there are situations when it is necessary to use
additional memory as well. A typical example are so called lookup tables. They are
used in cases when equations describing some processes are too complicated or
when there is no time for solving them. In such cases all necessary estimates and
approximates are executed in advance and the final results are put in the tables
(similar to logarithmic tables).

How does the microcontroller handle external memory depends on the EA pin logic
state:
EA=0 In this case, the microcontroller completely ignores internal program
memory and executes only the program stored in external memory. EA=1 In this
case, the microcontroller executes first the program from built-in ROM, then the
program stored in external memory. In both cases, P0 and P2 are not available for
use since being used for data and address transmission. Besides, the ALE and PSEN
pins are also used.

Interrupt structure:
The most powerful and important features are interrupts in 8051 microcontroller. In most of the
real-time processes, to handle certain conditions properly, the actual task must be halt for some time
– it takes required action – and then must return to the main task. For executing such type of
programs, interrupts are necessary. It entirely differs from the polling method wherein the processor
must check sequentially each device and ask whether the service is required or not while consuming
more processor time.

Types of Interrupts in 8051 Microcontroller

The 8051 microcontroller can recognize five different events that cause the main program to
interrupt from the normal execution. These five sources of interrupts in 8051are:
1. Timer 0 overflow interrupt- TF0
2. Timer 1 overflow interrupt- TF1
3. External hardware interrupt- INT0
4. External hardware interrupt- INT1
5. Serial communication interrupt- RI/TI
Interrupt Structure of 8051 Microcontroller

Upon ‘RESET’ all the interrupts get disabled, and therefore, all these interrupts must be enabled by a
software. In all these five interrupts, if anyone or all are activated, this sets the corresponding
interrupt flags as shown in the figure. All these interrupts can be set or cleared by bit in some special
function register that is Interrupt Enabled (IE), and this in turn depends on the priority, which is
executed by IP interrupt priority register.

Interrupt structure of 8051 microcontroller

Interrupt Enable (IE) Register: This register is responsible for enabling and disabling the interrupt.
It is a bit addressable register in which EA must be set to one for enabling interrupts. The
corresponding bit in this register enables particular interrupt like timer, external and serial inputs.
In the below IE register, bit corresponding to 1 activates the interrupt and 0 disables the interrupt.

Interrupt Enable (IE) Register

Interrupt Priority Register (IP): It is also possible to change the priority levels of the interrupts by
setting or clearing the corresponding bit in the Interrupt priority (IP) register as shown in the figure.
This allows the low priority interrupt to interrupt the high-priority interrupt, but prohibits the
interruption by another low-priority interrupt. Similarly, the high-priority interrupt cannot be
interrupted. If these interrupt priorities are not programmed, the microcontroller executes in
predefined manner and its order is INT0, TF0, INT1, TF1, and SI.
 IP register

TCON Register: In addition to the above two registers, the TCON register specifies the type of
external interrupt to the 8051 microcontroller, as shown in the figure. The two external interrupts,
whether edge or level triggered, specify by this register by a set, or cleared by appropriate bits in it.
And, it is also a bit addressable register.

TCON Register