Differential Amplifiers

Half-Circuit Analysis
• Half-circuits are constructed by first drawing
the differential amplifier in a fully
symmetrical form: power supplies are split
into two equal halves in parallel, the emitter
resistor is separated into two equal resistors
in parallel.
• None of the currents or voltages in the circuit
are changed.
• For differential-mode signals, points on the
line of symmetry are virtual grounds and
connected to ground for ac analysis
• For common-mode signals, points on the line
of symmetry are replaced by open circuits.

Jaeger/Blalock Microelectronic Circuit Design, 5E Chap 15-16

5/6/15 McGraw-Hill
Differential Amplifiers
BJT Differential-mode Half-circuits
Direct analysis of the half-circuit yields:

vid
vc1 = −gm ( RC ro )
2
v
vc2 = +gm ( RC ro ) id
2
vod = vc1 − vc2
vod = −gm ( RC ro ) vid
Applying rules for drawing half-
circuits, the two power supply vid
Rid = = 2rπ
lines and emitter become ac ib
grounds. The half-circuit
represents a C-E amplifier stage. Rod = 2 ( RC ro )

Jaeger/Blalock Microelectronic Circuit Design, 5E Chap 15-17

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Differential Amplifiers
BJT Common-mode Half-circuits

• All points on line of symmetry become open circuits.

• DC circuit with VIC set to zero is used to find amplifier’s Q-point.
• Last circuit is used for for common-mode signal analysis and
represents the C-E amplifier with emitter resistor 2REE.

Jaeger/Blalock Microelectronic Circuit Design, 5E Chap 15-18

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Differential Amplifiers
BJT Common-mode Half-circuits (cont.)

−VBE − (−VEE ) VEE −VBE βo RC R

vc1 = vc2 = − vic ≅ − C vic
IE = = rπ + 2 ( βo +1) REE 2REE
2REE 2REE
βo
IC = α F I E = IE IC ≅ I E 2 ( βo +1) ib REE
βo +1 ve = vic ≅ vic
rπ + 2 ( βo +1) REE
VCE = VCC − I C RC +VBE

Jaeger/Blalock Microelectronic Circuit Design, 5E Chap 15-19

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Differential Amplifiers
BJT Common-mode Input Voltage Range
VCB = VCC − I C RC −VIC
VIC −VBE +VEE
VCB ≥ 0 → I C ≤ α F
2REE
& RC )& VEE −VBE )
1− α F ( +( +
2R
' EE *' V CC *
∴VIC ≤ VCC
& RC )
1+ α F ( +
2R
' EE *

For symmetrical power supplies, VEE >> VBE, and RC = REE,

VCC
VIC ≤
3

Jaeger/Blalock Microelectronic Circuit Design, 5E Chap 15-20

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Differential Amplifiers
Biasing with Electronic Current Sources
• Differential amplifiers are biased using electronic
current sources to stabilize the operating point and
increase the effective value of REE to improve CMRR
• An electronic current source has a Q-point current of
ISS and an output resistance of RSS as shown.
• The dc model of the electronic current source is a dc
current source ISS while ac model is a resistance RSS.
SPICE model includes both ac
and dc models.

VO
I DC = I SS −
RSS

Jaeger/Blalock Microelectronic Circuit Design, 5E Chap 15-21

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MOSFET Differential Amplifiers
dc Analysis

Kn 2
ID = (VGS −VTN )
2
2I D I
VGS = VTN + = VTN + SS
Kn Kn

Op amps with MOSFET inputs have a VD1 = VD2 = VDD − I D RD and VO = 0

high input resistance and much higher
slew rate that those with bipolar input
VDS = VD −VS = VDD − I D RD +VGS
stages.
Using half-circuit analysis method, we
see that IS = ISS /2.

Jaeger/Blalock Microelectronic Circuit Design, 5E Chap 15-22

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 MOSFET Differential Amplifiers
dc Analysis Using the Unified Model
The Unified model replaces (VGS-VTN) with VMIN,
VMIN=min{(VGS-VTN),VDS,VSAT}
For values of gate drive and VDS exceeding VMIN, the drain current and
transconductance become
Kn " VSAT %
ID = $VGS −VTN − ' VSAT and gm = K nVSAT
2 # 2 &
Assuming the current bias is unchanged, the required VGS will change as
required to support the current.
VSAT ID
VGS = VTN + +
2 K nVSAT
The drain voltage, VD, and VDS remain the same since the current is unchanged.

Jaeger/Blalock Microelectronic Circuit Design, 5E Chap 15-23

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MOSFET Differential Amplifiers
Small-Signal Transfer Characteristic
MOS differential amplifier gives improved linear input signal range and
distortion characteristics over that of a single transistor.

Kn " 2 2$
iD1 − iD2 = #( GS1 TN ) ( GS 2 TN ) %
v −V − v −V
2
For a symmetrical differential amplifier with purely differential-mode input
vid v
vGS1 = VGS + vGS 2 = VGS − id
2 2
∴ id1 − id 2 = K n (VGS −VTN ) vid = gm vid
Second-order distortion is eliminated and distortion is greatly reduced.
However, some distortion prevails as MOSFETs are nor perfect square law
devices, and some distortion arises through the voltage dependence of
output impedances of the transistors.

Jaeger/Blalock Microelectronic Circuit Design, 5E Chap 15-24

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MOSFET Differential Amplifiers
dc Analysis (Example)
• Problem: Find Q-points of transistors in the differential amplifier.
• Given data: VDD = VSS = 12 V, ISS =1 mA, RSS = 100 kW, RD = 13 kW,
l = 0.0133 V-1, Kn = 500 µA/ V2, VTN = 0.7 V
I
• Analysis: I D = SS = 1 mA
2
2I D 1mA
VGS = VTN + = 0.7V + 2
= 2.11 V
Kn 0.5mA V
VDS = VDD − I D RD − (−VGS ) = 12V − 500µ A (13kΩ) + 2.11 = 7.61 V
Q-pt: ( 500 µ A, 7.61 V )

To maintain pinch-off operation of M1 for nonzero VIC ,

VGD = VIC − (VDD − I D RD ) ≤ VTN or VIC ≤ VDD − I D RD + VTN
∴VIC ≤ 6.20 V

Jaeger/Blalock Microelectronic Circuit Design, 5E Chap 15-25

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MOSFET Differential Amplifiers
dc Analysis (Example)
Unified model calculations (VMIN = VSAT):
VSAT ID 1V 500 µA
VGS = VTN + + = 0.7V + + = 2.20 V
2 K nVSAT 2 (500 µA / V 2)(1V )
VDS = VDD − I D RD − (−VGS ) = 12V − 6.5V + 2.2.0 = 7.70 V

ID and VIC are unchanged.

Jaeger/Blalock Microelectronic Circuit Design, 5E Chap 15-26

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MOSFET Differential Amplifiers
Differential-mode Input Signals
Source node in differential amplifier represents virtual
ground. Differential-mode gain for balanced output is
vod
Add = = −gm ( RD ro )
vid vic

Gain for single-ended output is

vd1 gm ( RD ro ) Add
Add1 = =− =
vid vid 2 2
vd1 = −gm ( RD ro ) vic
2
v vd1 gm ( RD ro ) Add
vd 2 = +gm ( RD ro ) id Add 2 = =+ =−
2 vid vic
2 2
∴vod = −gm ( RD ro ) vid Rid = ∞ Rod = 2 ( RD ro )
Jaeger/Blalock Microelectronic Circuit Design, 5E Chap 15-27
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MOSFET Differential Amplifiers
Common-mode Input Signals
Electronic current source is modeled by twice its small-
signal output resistance representing output resistance of
the current source.
Common-mode half-circuit is similar to inverting
amplifier with 2RSS as source resistor.

gm RD 2gm Rss
vd 2 = vd1 = − vic vs = + vic ≅ vic
1+ 2gm RSS 1+ 2gm RSS
vod = vd1 − vd 2 = 0. Thus, Acd = 0

voc gm RD R
Acc = =− ≅− D
vic 1+ 2gm RSS 2RSS Due to infinite current gain
vid =0
of FET, ro can be neglected.
Ric = ∞

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MOSFET Differential Amplifiers
Common-Mode Rejection ratio (CMRR)
• For purely common-mode input signal, the output of a balanced MOS
amplifier is zero, and the CMRR is infinite. For a single-ended output,
Adm Add 2 gm RD 2
Acc = = ≅ = gm RSS
Acm Acc RD 2RSS
• RSS (which is much > REE and thus provides more Q-point stability) should
be maximized.
• To compare MOS amplifier directly to BJT amplifier, assume that MOS
amplifier is biased by resistor RSS
VSS −VGS 2I D RSS I R V −V
RSS = CMRR = = SS SS = SS GS
I SS VGS −VTN VGS −VTN VGS −VTN
• From given data in example, MOS amplifier’s CMRR = 54 or 35 dB
(almost 10 dB worse than BJT amplifier).To increase CMRR in BJT and
FET amplifiers, current sources with higher RSS or REE are used.

Jaeger/Blalock Microelectronic Circuit Design, 5E Chap 15-29

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Differential Amplifiers
Two-port Model

gm vcm
idm = gm vdm icm = vcm ≅
1+ 2gm REE 2REE
Rod = 2ro Roc ≅ 2µ f REE
• Two-port model simplifies circuit analysis of differential amplifiers.
• Expressions for FET are obtained by substituting RSS for REE.

Jaeger/Blalock Microelectronic Circuit Design, 5E Chap 15-30

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Differential Amplifier
Design Example
Problem: Find Q-points for transistors in BJT & MOSFET differential
amplifiers.
Given data: Adm= 40 dB, Rid ≥ 250 kW, single-ended CMRR > 80 dB, VIC
at least ±5 V; MOSFETs have l = 0.0133 V-1, Kn’ = 50 µA/ V2, VTN = 1 V;
BJTs have bF = 100, VA = 75 V, IS = 0.5 fA
Assumptions: Active-region operation, symmetrical power supplies, bo =
bF, vid maximum of ±30 mV; VT = 25 mV
Analysis:
Adm= 40 dB = 100. To achieve this gain with a resistively loaded amplifier,
we use the BJT. For Adm = gm RC = 40 IC RC , the required gain can be
obtained with a voltage drop of 2.5 V across RC.
βoVT
For the bipolar amplifier: Rid = 2rp , and rp ≥ 125 kW. ∴ I C ≤ = 20 µ A
rπ

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Differential Amplifier
Design Example (cont.)
Choose IC = 15 µA to provide safety margin. So RC = 2.5 V/15 µA = 167 kW.
Choose RC = 180 kW as the nearest value with 5% tolerance and also to
compensate for neglecting ro in the analysis.
VIC of 5 V requires collector voltage to be at least 5 V at all times. We also
know that vid can be a maximum of ±30 mV for linearity. So the ac
component of the differential output will not be greater than 100(0.03 V) =
3V, half of which appears at each collector. Thus total signal across RC
won’t exceed 4 V ( 2.5 V dc + 1.5 V ac) and the positive power supply
must fulfill
VCC ≥ VIC + 4V = 5V + 4V = 9 V

Choose VCC = 10 V to provide a margin of 1 V.

For symmetrical supplies, VEE = -10 V.

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Differential Amplifier
Design Example (cont.)

A single-ended CMRR of 80 dB requires

CMRR 10 4
REE ≥ = = 16.7 MΩ
gm 40 (15µ A)

So, choose a current source with I EE = 30µ A and REE = 20 MΩ

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