HEF4013BT

HEF4013B
Dual D-type flip-flop

Rev. 9 — 10 December 2015 Product data sheet
1. General description
The HEF4013B is a dual D-type flip-flop that features independent set-direct input (SD),
clear-direct input (CD), clock input (CP) and outputs (Q, Q). Data is accepted when CP is
LOW and is transferred to the output on the positive-going edge of the clock. The active
HIGH asynchronous CD and SD inputs are independent and override the D or CP inputs.
The outputs are buffered for best system performance. The clock input’s Schmitt-trigger
action makes the circuit highly tolerant of slower clock rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits

 Tolerant of slow clock rise and fall times
 Fully static operation
 5 V, 10 V, and 15 V parametric ratings
 Standardized symmetrical output characteristics
 Specified from 40 C to +125 C
 Complies with JEDEC standard JESD 13-B
3. Applications
 Counters and dividers
 Registers
 Toggle flip-flops
4. Ordering information
Table 1. Ordering information
All types operate from 40 C to +125 C
Type number Package
Name Description Version
HEF4013BT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
HEF4013BTT TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
NXP Semiconductors HEF4013B
5. Functional diagram

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&3 &3 4 4
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Fig 1. Functional diagram
&3 &
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& &
&
&
& &
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4
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Fig 2. Logic diagram (one flip-flop)
HEF4013B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 9 — 10 December 2015 2 of 16

6. Pinning information
6.1 Pinning
4 9''
4 4
&3 4
&' +()% &3
' &'
6' '
966 6'
DDJ
Fig 3. Pin configuration
6.2 Pin description

Table 2. Pin description
Symbol Pin Description
1Q, 2Q 1, 13 true output
1Q, 2Q 2, 12 complement output
1CP, 2CP 3, 11 clock input (LOW to HIGH edge-triggered)
1CD, 2CD 4, 10 asynchronous clear-direct input (active HIGH)
1D, 2D 5, 9 data input
1SD, 2SD 6, 8 asynchronous set-direct input (active HIGH)
VSS 7 ground (0 V)
VDD 14 supply voltage
7. Functional description
Table 3. Function table[1]
Control Input Output
nSD nCD nCP nD nQ nQ
H L X X H L
L H X X L H
H H X X H H
L L  L L H
L L  H H L
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; = LOW-to-HIGH clock transition.

8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +18 V
IIK input clamping current VI < 0.5 V or VI > VDD + 0.5 V - 10 mA
VI input voltage 0.5 VDD + 0.5 V
IOK output clamping current VO < 0.5 V or VO > VDD + 0.5 V - 10 mA
II/O input/output current - 10 mA
IDD supply current - 50 mA
Tstg storage temperature 65 +150 C
Tamb ambient temperature 40 +125 C
Ptot total power dissipation Tamb = 40 C to +125 C
SO14 [1] - 500 mW
TSSOP14 [2] - 500 mW
P power dissipation per output - 100 mW
[1] For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K.
[2] For TSSOP14 packages: above Tamb = 60 C, Ptot derates linearly with 5.5 mW/K.
9. Recommended operating conditions

Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 3 15 V
VI input voltage 0 VDD V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate VDD = 5 V - 3.75 s/V
VDD = 10 V - 0.5 s/V
VDD = 15 V - 0.08 s/V

10. Static characteristics

Table 6. Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 C Unit
Min Max Min Max Min Max Min Max
VIH HIGH-level IO < 1 A 5V 3.5 - 3.5 - 3.5 - 3.5 - V
input voltage 10 V 7.0 - 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - 11.0 - V
VIL LOW-level IO < 1 A 5V - 1.5 - 1.5 - 1.5 - 1.5 V
input voltage 10 V - 3.0 - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 - 4.0 V
VOH HIGH-level IO < 1 A 5V 4.95 - 4.95 - 4.95 - 4.95 - V
output voltage 10 V 9.95 - 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - 14.95 - V
VOL LOW-level IO < 1 A 5V - 0.05 - 0.05 - 0.05 - 0.05 V
output voltage 10 V - 0.05 - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 - 0.05 V
IOH HIGH-level VO = 2.5 V 5V - 1.7 - 1.4 - 1.1 - 1.1 mA
output current VO = 4.6 V 5V - 0.64 - 0.5 - 0.36 - 0.36 mA
VO = 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA
VO = 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA
IOL LOW-level VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA
output current VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA
VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA
II input leakage 15 V - 0.1 - 0.1 - 1.0 - 1.0 A
current
IDD supply current all valid input 5V - 1.0 - 1.0 - 30 - 30 A
combinations; 10 V - 2.0 - 2.0 - 60 - 60 A
IO = 0 A
15 V - 4.0 - 4.0 - 120 - 120 A
CI input - - - - 7.5 - - - - pF
capacitance

11. Dynamic characteristics

Table 7. Dynamic characteristics
Tamb = 25 C; unless otherwise specified. For test circuit see Figure 6.
Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit
tPHL HIGH to LOW nCP to nQ, nQ; 5V [1] 83 + 0.55  CL - 110 220 ns
propagation delay see Figure 4 10 V 34 + 0.23  CL - 45 90 ns
15 V 22 + 0.16  CL - 30 60 ns
nSD to nQ 5V [1] 73 + 0.55  CL - 100 200 ns
10 V 29 + 0.23  CL - 40 80 ns
15 V 22 + 0.16  CL - 30 60 ns
nCD to nQ 5V [1] 73 + 0.55  CL - 100 200 ns
10 V 29 + 0.23  CL - 40 80 ns
15 V 22 + 0.16  CL - 30 60 ns
tPLH LOW to HIGH nCP to nQ, nQ; 5V [1] 68 + 0.55  CL - 95 190 ns
propagation delay see Figure 4 10 V 29 + 0.23  CL - 40 80 ns
15 V 22 + 0.16  CL - 30 60 ns
nSD to nQ 5V [1] 48 + 0.55  CL - 75 150 ns
10 V 24 + 0.23  CL - 35 70 ns
15 V 17 + 0.16  CL - 25 50 ns
nCD to nQ 5V [1] 33 + 0.55  CL - 60 120 ns
10 V 19 + 0.23  CL - 30 60 ns
15 V 12 + 0.16  CL - 20 40 ns
tt transition time see Figure 4 5V [1] 10 + 1.00  CL - 60 120 ns
10 V 9 + 0.42  CL - 30 60 ns
15 V 6 + 0.28  CL - 20 40 ns
tsu set-up time nD to nCP; 5V 40 20 - ns
see Figure 4 10 V 25 10 - ns
15 V 15 5 - ns
th hold time nD to nCP; 5V 20 0 - ns
15 V 15 0 - ns
tW pulse width nCP input LOW; 5V 60 30 - ns
15 V 20 10 - ns
nSD input HIGH; 5V 50 25 - ns
15 V 20 10 - ns
nCD input HIGH; 5V 50 25 - ns
15 V 20 10 - ns

Table 7. Dynamic characteristics …continued

Tamb = 25 C; unless otherwise specified. For test circuit see Figure 6.
Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit
trec recovery time nSD input; 5V +15 5 - ns
15 V 15 0 - ns
nCD input; 5V 40 25 - ns
15 V 25 10 - ns
fclk(max) maximum clock see Figure 4 5V 7 14 - MHz
frequency 10 V 14 28 - MHz
15 V 20 40 - MHz
[1] Typical values of the propagation delays and output transition times can be calculated with the extrapolation formulas. CL is given in pF.
Table 8. Dynamic power dissipation

VSS = 0 V; tr = tf  20 ns; Tamb = 25 C.
Symbol Parameter VDD Typical formula Where
PD dynamic power dissipation 5V PD = 850  fi + (fo  CL)  VDD W 2 fi = input frequency in MHz;
10 V PD = 3600  fi + (fo  CL)  VDD2 W fo = output frequency in MHz;
15 V PD = 9000  fi + (fo  CL)  VDD2 W CL = output load capacitance in pF;
(fo  CL) = sum of the outputs;
VDD = supply voltage in V.

12. Waveforms
IFON PD[ W:
9,
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9
WVX WVX
WI WU
WK WK
9,
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9
W3/+ W3+/
WW WW
92+
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RXWSXWQ4 90
92/ 9;
DDK
Set-up and hold times are shown as positive values but may be specified as negative values.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Measurement points are given in Table 9.
Fig 4. Set-up time, hold time, minimum clock pulse width, propagation delays and transition times
9,
LQSXWQ&3 90
9
WUHF WUHF
9,
LQSXWQ6' 90
9 W:
9,
LQSXWQ&' 90
9 W:
92+
RXWSXWQ4
92/ DDJ
Recovery times are shown as positive values but may be specified as negative values.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Measurement points are given in Table 9.
Fig 5. nSD, nCD recovery time and pulse width
Table 9. Measurement points

Supply voltage Input Output
VDD VM VM VX VY
5 V to 15 V 0.5VDD 0.5VDD 0.1VDD 0.9VDD

9''
9, 92
* '87
57 &/
DDJ
Test and measurement data is given in Table 10;

Definitions test circuit:
DUT = Device Under Test.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Fig 6. Test circuit for measuring switching times
Table 10. Test data

Supply voltage Input Load
VDD VI tr, tf CL
5 V to 15 V VSS or VDD  20 ns 50 pF

13. Application information
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Fig 7. N-stage shift register
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7W\SHIOLSIORS DDJ
Fig 8. Binary ripple up-counter; divide-by-2n
' 4 ' 4 ' 4 4
)) )) ))

Q
&3 4 &3 4 &3 4
FORFN
DDJ
Fig 9. Modified ring counter; divide-by-(n + 1)

14. Package outline
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Fig 11. Package outline SOT402-1 (TSSOP14)

15. Abbreviations
Table 11. Abbreviations
Acronym Description
DUT Device Under Test
16. Revision history

Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF4013B v.9 20151210 Product data sheet - HEF4013B v.8
Modifications: • Type number HEF4013BP (SOT27-1) removed.
Modifications: • Legal pages updated.
• Changes in “General description”, “Features and benefits” and “Applications”.
HEF4013B v.4 20080515 Product data sheet - HEF4013B_CNV v.3
HEF4013B_CNV v.3 19950101 Product specification - HEF4013B_CNV v.2
HEF4013B_CNV v.2 19950101 Product specification - -

17. Legal information
17.1 Data sheet status

Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Draft — The document is a draft version only. The content is still under
malfunction of an NXP Semiconductors product can reasonably be expected
internal review and subject to formal approval, which may result in
to result in personal injury, death or severe property or environmental
modifications or additions. NXP Semiconductors does not give any
damage. NXP Semiconductors and its suppliers accept no liability for
representations or warranties as to the accuracy or completeness of
inclusion and/or use of NXP Semiconductors products in such equipment or
information included herein and shall have no liability for the consequences of
applications and therefore such inclusion and/or use is at the customer’s own
use of such information.
risk.
Short data sheet — A short data sheet is an extract from a full data sheet
Applications — Applications that are described herein for any of these
with the same product type number(s) and title. A short data sheet is intended
products are for illustrative purposes only. NXP Semiconductors makes no
for quick reference only and should not be relied upon to contain detailed and
representation or warranty that such applications will be suitable for the
full information. For detailed and full information see the relevant full data
specified use without further testing or modification.
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the Customers are responsible for the design and operation of their applications
full data sheet shall prevail. and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
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NXP Semiconductors and its customer, unless NXP Semiconductors and products planned, as well as for the planned application and use of
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deemed to offer functions and qualities beyond those described in the applications and products.
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
17.3 Disclaimers customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Limited warranty and liability — Information in this document is believed to
Semiconductors products in order to avoid a default of the applications and
be accurate and reliable. However, NXP Semiconductors does not give any
the products or of the application or use by customer’s third party
representations or warranties, expressed or implied, as to the accuracy or
customer(s). NXP does not accept any liability in this respect.
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no Limiting values — Stress above one or more limiting values (as defined in
responsibility for the content in this document if provided by an information the Absolute Maximum Ratings System of IEC 60134) will cause permanent
source outside of NXP Semiconductors. damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
In no event shall NXP Semiconductors be liable for any indirect, incidental,
the Recommended operating conditions section (if present) or the
punitive, special or consequential damages (including - without limitation - lost
Characteristics sections of this document is not warranted. Constant or
profits, lost savings, business interruption, costs related to the removal or
repeated exposure to limiting values will permanently and irreversibly affect
replacement of any products or rework charges) whether or not such
the quality and reliability of the device.
damages are based on tort (including negligence), warranty, breach of
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Notwithstanding any damages that customer might incur for any reason products are sold subject to the general terms and conditions of commercial
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authorization from competent authorities. liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
Non-automotive qualified products — Unless this data sheet expressly
standard warranty and NXP Semiconductors’ product specifications.
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested Translations — A non-English (translated) version of a document is for
in accordance with automotive testing or application requirements. NXP reference only. The English version shall prevail in case of any discrepancy
Semiconductors accepts no liability for inclusion and/or use of between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer 17.4 Trademarks
(a) shall use the product without NXP Semiconductors’ warranty of the
Notice: All referenced brands, product names, service names and trademarks
product for such automotive applications, use and specifications, and (b)
are the property of their respective owners.
whenever customer uses the product for automotive applications beyond
18. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]

19. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
13 Application information. . . . . . . . . . . . . . . . . . 10
14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13
17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
17.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
18 Contact information. . . . . . . . . . . . . . . . . . . . . 15
19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 10 December 2015
Document identifier: HEF4013B

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HEF4013B

Dual D-type flip-flop

It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS

2. Features and benefits

Fig 1. Functional diagram

Fig 2. Logic diagram (one flip-flop)

Product data sheet Rev. 9 — 10 December 2015 2 of 16

&'  +()%  &3

Fig 3. Pin configuration

6.2 Pin description

Product data sheet Rev. 9 — 10 December 2015 3 of 16

9. Recommended operating conditions

Product data sheet Rev. 9 — 10 December 2015 4 of 16

10. Static characteristics

Product data sheet Rev. 9 — 10 December 2015 5 of 16

11. Dynamic characteristics

Product data sheet Rev. 9 — 10 December 2015 6 of 16

Table 7. Dynamic characteristics …continued

Table 8. Dynamic power dissipation

Product data sheet Rev. 9 — 10 December 2015 7 of 16

Table 9. Measurement points

Product data sheet Rev. 9 — 10 December 2015 8 of 16

Test and measurement data is given in Table 10;

Table 10. Test data

Product data sheet Rev. 9 — 10 December 2015 9 of 16

13. Application information

' ' 4 ' 4 ' 4 4

)) )) ))

&3 4 &3 4 &3 4

Fig 7. N-stage shift register

' 4 ' 4 ' 4 4

)) )) ))

FORFN &3 4 &3 4 &3 4

Fig 8. Binary ripple up-counter; divide-by-2n

' 4 ' 4 ' 4 4

)) )) ))

&3 4 &3 4 &3 4

Fig 9. Modified ring counter; divide-by-(n + 1)

Product data sheet Rev. 9 — 10 December 2015 10 of 16

14. Package outline

287/,1( 5()(5(1&(6 (8523($1

Fig 10. Package outline SOT108-1 (SO14)

Product data sheet Rev. 9 — 10 December 2015 11 of 16

287/,1( 5()(5(1&(6 (8523($1

Fig 11. Package outline SOT402-1 (TSSOP14)

Product data sheet Rev. 9 — 10 December 2015 12 of 16

16. Revision history

Product data sheet Rev. 9 — 10 December 2015 13 of 16

17. Legal information

17.1 Data sheet status

Product data sheet Rev. 9 — 10 December 2015 14 of 16

18. Contact information

Product data sheet Rev. 9 — 10 December 2015 15 of 16

© NXP Semiconductors N.V. 2015. All rights reserved.

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