Architecture of TMS320C5X 71

C8X: video telephony, 3D computer graphics, virtual reality and a number of multimedia applications
The TI DSP chips have IC numbers with the prefix TMS320. If the next letter is C (e.g. TMS320C5X),
it indicates that CMOS technology is used for the IC and the on-chip non-volatile memory is a ROM.
If it is E (e.g. TMS320E5X) it indicates that the technology used is CMOS and the on-chip non-volatile
memory is an EPROM. If it is neither (e.g. TMS3205X), it indicates that NMOS technology is used
for the IC and the on-chip non-volatile memory is a ROM. Under C5X itself there are three processors,
‘C50, ‘C51 and ‘C5X, that have identical instruction set but have differences in the capacity of on-chip
ROM and RAM. The characteristics of some of the TMS320 family DSP chips are given in Table 3.1.
The instruction set of TMS320C5X and other DSP chips is superior to the instruction set of
conventional microprocessors such as 8085, Z80, etc., as most of the instructions require only a single
cycle for execution. The multiply accumulate operation used quite frequently in signal processing
applications such as convolution requires only one cycle in DSP.

Table 3.1 Characteristics of some of the TMS320 family DSP chips

¢C15 ¢C25 ¢C30 ¢C50 ¢C541

Cycle time (ns) 200 100 60 50 25
on chip RAM 4K 4K 4K 2K 5K
Total memory 4K 128K 16M 128K 128K
Parallel ports 8 16 16M 64K 64K

Architecture of TMS320C5X DSPs The block diagram of the internal architecture of C5X is shown
in Fig. 3.1. The 320C5X DSPs are said to have advanced Harvard architecture because they have sepa-
rate memory bus structures for program and data and have instructions that enable data transfer between
the program and data memory area.

BUS STRUCTURE 3.2

Separate program and data buses allow simultaneous access to program instructions and data, providing
a high degree of parallelism. For example, while data is multiplied, a previous product can be loaded
into, added to or subtracted from the accumulator and, at the same time, a new address can be generated.
Such parallelism supports a powerful set of arithmetic, logic and bit-manipulation operations that can
all be performed in a single machine cycle. In addition, the ¢C5X includes the control mechanisms to
manage interrupts, repeated operations and function calling. The ¢C5X architecture has four buses and
their functions are as follows:
Program bus (PB) It carries the instruction code and immediate operands from program memory
space to the CPU.
Program address bus (PAB) It provides addresses to program memory space for both reads and
writes.
Data read bus (DB) It interconnects various elements of the CPU to data memory space.
Data read address bus (DAB) It provides the address to access the data memory space. The program
and data buses can work together to transfer data from on-chip data memory and internal or external
program memory to the multiplier for single-cycle multiply/accumulate operations.
72 Digital Signal Processors

Fig. 3.1 Internal architecture of C5X

CPU registers (except STO and ST1), peripheral registers and I/O ports occupy data memory space.
Some of the registers/execution units in the CPU of C5X DSP processors and their functions are as
follows.

CENTRAL ARITHMETIC LOGIC UNIT (CALU) 3.3

It consists of the following elements: (16xl6)-bit parallel multiplier, arithmetic logic unit (ALU),
accumulator (ACC), accumulator buffer (ACCB), product register (PREG) each with 32 bits and 0-16-
bit left barrel shifter and right barrel shifter.
One of the operands for the ALU operation comes from ACC. The result of operations performed in
central ALU are stored in ACC. Either the higher order word or lower order word of ACC can be loaded
from memory. A 32-bit register denoted as ACCB is used for temporary storage of ACC. The hardware
 Architecture of TMS320C5X 73
multiplier unit in the C5X processors performs 16 x 16 multiplication of numbers represented in 2’s
complement form. The 32-bit PREG holds the result of multiplication. The 16-bit temporary register 0
(TREG0) holds the multiplicand. The other operand for the multiplication can be specified using one of
the addressing modes.
0-16-bit left barrel shifter and right barrel shifter in CALU permit the contents of memory to be
left shifted by 0 to 16 bits before they are either fed to ALU or stored from ALU to memory. The CPU
registers ACC and PREG can also be shifted using these shifters. In this case they require two cycles.
A 5-bit register TREG1 specifies the number of bits by which the scaling shifter should shift either the
incoming data to one of the CPU registers or vice versa. When the incoming data to CPU is left shifted
by the scaling shifter the LSBs are filled with 0.

AUXILIARY REGISTER ALU (ARAU) 3.4

It consists of eight 16-bit auxiliary registers (ARs) AR0-AR7, a 3-bit auxiliary register pointer (ARP)
and an unsigned 16-bit ALU. ARAU calculates indirect addresses by using inputs from ARs, 16-bit index
register (INDX) and auxiliary register compare register (ARCR). The ARAU can autoindex the current
AR while the data memory location is being addressed and can index either by ± 1 or by the contents of
the INDX. As a result, accessing data does not require the CALU for address manipulation; therefore,
the CALU is free for other operations in parallel. This makes the instructions to be executed faster
compared to the conventional microprocessors. For example, let us consider the following sequence of
8085 instructions:
M0V A,M
INX H
These instructions enable the accumulator to be loaded using indirect addressing mode and HL
register used as the address pointer is incremented. These two instructions can be replaced by a single
5X instruction LACC *+, 0.
Further, any one of the auxiliary registers can be used as the address pointer and incremented by the
above instruction. The register that will be used is specified by the content of the ARP.
The auxiliary registers AR0-AR7 may also be used as the general purpose registers for holding the
operands for arithmetic and logical operations in CALU. Some of the other registers of ARAU and their
functions are as follows:

INDEX REGISTER (INDX) 3.5

The 16-bit INDX is used by the ARAU as a step value (addition or subtraction by more than 1) to
modify the address in the ARs during indirect addressing. For example, when the ARAU steps across
a row of a matrix, the indirect address is incremented by 1. However, when the ARAU steps down a
column, the address is incremented by the dimension of the matrix. The ARAU can add or subtract the
value stored in the INDX from the current AR as part of the indirect address operation. INDX can also
map the dimension of the address block used for bit-reversal addressing.

AUXILIARY REGISTER COMPARE REGISTER (ARCR) 3.6

The 16-bit ARCR is used for address boundary comparison. The CMPR instruction compares the ARCR
to the selected AR and places the result of the compare in the TC bit of ST1.
74 Digital Signal Processors

BLOCK MOVE ADDRESS REGISTER (BMAR) 3.7

The 16-bit BMAR holds an address value to be used with block moves and multiply/accumulate
operations. This register provides the 16-bit address for an indirect-addressed second operand.

BLOCK REPEAT REGISTERS (RPTC, BRCR, PASR, PAER) 3.8

All these registers are 16-bit wide. Repeat counter register (RPTC) holds the repeat count in a repeat
single-instruction operation and is loaded by the RPT and RPTZ instructions. Block repeat counter
register (BRCR) holds the count value for the block repeat feature. This value is loaded before a block
repeat operation is initiated. Block repeat program address start register (PASR) indicates the 16-bit
address where the repeated block of code starts. The block repeat program address end register (PAER)
indicates the 16-bit address where the repeated block of code ends. The PASR and PAER are loaded by
the RPTB instruction.

PARALLEL LOGIC UNIT (PLU) 3.9

It performs Boolean operations or the bit manipulations required of high-speed controllers. The PLU
can set, clear, test or toggle bits in a status register control register, or any data memory location. The
PLU allows logic operations to be performed on data memory values directly without affecting the
contents of the ACC or PREG. Results of a PLU function are written back to the original data memory
location.

MEMORY-MAPPED REGISTERS 3.10

The ‘C5X has 96 registers mapped into page 0 of the data memory space. All ‘C5X DSPs have 28 CPU
registers and 16 input/output (I/O) port registers but have different numbers of peripheral and reserved
registers. Since the memory-mapped registers are a component of the data memory space, they can be
written to and read from in the same way as any other data memory location. The memory-mapped
registers are used for indirect data address pointers, temporary storage, CPU status and control, or
integer arithmetic processing through the ARAU.

PROGRAM CONTROLLER 3.11

The program controller contains logic circuitry that decodes the instructions, manages the CPU pipeline,
stores the status of CPU operations and decodes the conditional operations. Parallelism of architecture lets
the ¢C5X perform three concurrent memory operations in any given machine cycle: fetch an instruction,
read an operand and write an operand. The program controller consists of the following elements:
16-bit program counter (PC)
16-bit status registers ST0, ST1, processor mode status register (PMST) and circular buffer control
register (CBCR)
(8 x 16)-bit hardware stack
Address generation logic
Instruction register
Interrupt flag register and interrupt mask register
 Architecture of TMS320C5X 75
15 – 13 12 11 10 9 8–0

ARP OV OVM 1 INTM DP

Fig. 3.2(a) Status register 0 (ST0) bit assignment

SOME FLAGS IN THE STATUS REGISTERS 3.12

The status registers can be stored into data memory and loaded from data memory, thereby allowing the
‘C5X status to be saved and restored for subroutines. The ST0 and ST1 each have an associated 1-level
deep shadow register stack for automatic context-saving when an interrupt trap is taken. These registers
are automatically restored upon a return from interrupt.
The bit assignment details for ST0 and ST1 are given in Fig. 3.2. Significance of the various bits of
ST0 and ST1 are as follows:
ARP (Auxiliary Register Pointer) These bits select the AR to be used in indirect addressing. When the
ARP is loaded, the previous ARP value is copied to the auxiliary register buffer (ARB) in ST1.
OV (Overflow) flag bit This bit indicates that an arithmetic operation overflow in the ALU.
OVM (Overflow Mode) bit This bit enables/disables the accumulator overflow saturation mode in the
ALU.
INTM (Interrupt Mode) bit This bit globally masks or enables all interrupts. The INTM bit has no ef-
—– ——
fect on the non-maskable R S and NMI interrupts.
DP (Data Memory Page Pointer) bits These bits specify the address of the current data memory page.
The DP bits are concatenated with the 7 LSBs of an instruction word to form a direct memory address
of 16 bits.

Fig. 3.2(b) Status register 1 (ST1) bit assignment

ARB Auxiliary Register Buffer

This 3-bit field holds the previous value contained in the ARP in ST0. Whenever the ARP is loaded, the
previous ARP value is copied to the ARB, except when using the LST #0 instruction. When the ARB
is loaded using the LST #1 instruction, the same value is also copied to the ARP. This is useful when
restoring context (when not using the automatic context save) in a subroutine that modifies the current
ARP.
CNF On-chip RAM configuration control bit This 1-bit field enables the on-chip dual-access RAM
block 0 (DARAM B0) to be addressable in data memory space or program memory space. The CNF bit
can be modified by the LST #1 instruction. If CNF is 0, the on-chip DARAM block 0 is mapped into
data memory space. The CNF bit can be cleared by a reset or the CLRC CNF instruction. When CNF is
1, the on-chip DARAM block 0 is mapped into program memory space. The CNF bit can be set by the
SETC CNF instruction.
76 Digital Signal Processors
TC Test/control flag bit This 1-bit flag stores the results of the ALU or parallel logic unit (PLU) test
bit operations. The status of the TC bit determines if the conditional branch, call and return instructions
are to be executed.
SXM Sign-extension mode bit This 1-bit field enables/disables sign extension of an arithmetic opera-
tion. The SXM bit does not affect the operations of certain arithmetic or logical instructions; the ADDC,
ADDS, SUBB or SUBS instruction suppresses sign extension, regardless of SXM.
C Carry bit This 1-bit field indicates an arithmetic operation carry or borrow in the ALU. The single-
bit shift and rotate instructions affect the C bit.
HM Hold mode bit This 1-bit field determines whether the central processing unit (CPU) stops or
— ——
continues execution when acknowledging an active HOLD signal.
XF pin status bit This 1-bit field determines the level of the external flag (XF) output pin.
PM Product shift mode bits This 2-bit field determines the product shifter (P-SCALER) mode and
shift value for the PREG output into the ALU. Table 3.2 gives the PM bits and the function performed.

Table 3.2 PM bits and the function performed

PM bits Function
b1 b0 P-SCALER mode for PREG output
00 No shift
01 Left-shifted 1 bit; LSB zero-filled
10 Left-shifted 4 bits; 4 LSBs zero-filled
11 Right-shifted 6 bits; sign extended; 6 LSBs lost. The product is always sign extended, regard-
less of the value of the SXM bit

ON-CHIP MEMORY 3.13

The ¢C5X architecture contains a considerable amount of on-chip memory to aid in system performance
and integration:
Program Read-Only Memory (ROM)
Data/Program Dual-Access RAM (DARAM)
Data/Program Single-Access RAM (SARAM)
The ¢C5X has a total address range of 224K words x 16 bits. The memory space is divided into
four individually selectable memory segments: 64K-word program memory space, 64K-word local data
memory space, 64K-word I/O ports and 32K-word global data memory space.

3.13.1 Program ROM

All ‘C5X DSPs carry a 16-bit on-chip maskable programmable ROM (see Fig. 3.1 for sizes). Some of
the ‘C5X DSPs have boot loader code resident in the on-chip ROM, and the other ¢C5X DSPs offer
the boot loader code as an option. This memory is used for booting program code from slower external
ROM or EPROM to fast on-chip or external RAM. Once the custom program has been booted into
RAM, the boot ROM space can be removed from program memory space by setting the MP/ MC bit
in the processor mode status register (PMST). The on-chip ROM is selected at reset by driving the
MP/ MC pin low. If the on-chip ROM is not selected, the ‘C5X devices start execution from off-chip
memory.
 Architecture of TMS320C5X 77
3.13.2 Data/Program Dual-Access RAM
All ¢C5X DSPs carry a 1056-word x 16-bit on-chip dual-access RAM (DARAM). The DARAM is
divided into three individually selectable memory blocks: 512-word data or program DARAM block
B0, 512-word data DARAM block B1 and 32-word data DARAM block B2. The DARAM is primarily
intended to store data values but, when needed, can be used to store programs as well. DARAM blocks
B1 and B2 are always configured as data memory; however. DARAM block B0 can be configured by
software as data or program memory.
DARAM improves the operational speed of the ‘C5X CPU. The CPU operates with a 4-deep pipeline.
In this pipeline, the CPU reads data on the third stage and writes data on the fourth stage. Hence, for
a given instruction sequence, the second instruction could be reading data at the same time the first
instruction is writing data. The dual data buses (DB and DAB) allow the CPU to read from and write to
DARAM in the same machine cycle.

3.13.3 Data/Program Single-Access RAM

Almost all ¢C5X DSPs carry a 16-bit on-chip single-access RAM (SARAM) of sizes varying from
1-9K (16–bits) words. Code can be booted from an off-chip ROM and then executed at full speed once
it is loaded into the on-chip SARAM. The SARAM can be configured by software as data memory, as
program memory or combination of both data memory and program memory. The SARAM is divided
into 1K- and/or 2K-word blocks contiguous in address memory space. All ¢C5X CPUs support parallel
accesses to these SARAM blocks. However, one SARAM block can be accessed only once per machine
cycle. In other words, the CPU can read from or write to one SARAM block while accessing another
SARAM block.

3.13.4 On-Chip Memory Protection

The ¢C5X DSPs have a maskable option that protects the contents of on-chip memories. When the
related bit is set, no externally originating instruction can access the on-chip memory spaces.

ON-CHIP PERIPHERALS 3.14

All ¢C5X DSPs have the same CPU structure; however, they have different on-chip peripherals connected
to their CPUs. The ‘C5X DSP on-chip peripherals available are as follows:
Clock Generator
Hardware Timer
Software-Programmable Wait-State Generators
Parallel I/O Ports
Host Port Interface (HPI)
Serial Port
Buffered Serial Port (BSP)
Time-Division Multiplexed (TDM) Serial Port
User-Maskable Interrupts

3.14.1 Clock Generator

The clock generator consists of an internal oscillator and a phaselocked loop (PLL) circuit. The clock
generator can be driven internally by a crystal resonator circuit or driven externally by a clock source.
78 Digital Signal Processors
The PLL circuit can generate an internal CPU clock by multiplying the clock source by a specific factor
and so a clock source with a frequency lower than that of the CPU can be used.

3.14.2 Hardware Timer

A 16-bit hardware timer with a 4-bit prescaler is available. This programmable timer clocks at a rate
that is between 1/2 and 1/32 of the machine cycle rate (CLKOUT1), depending upon the timer’s divide-
down ratio. The timer can be stopped, restarted, reset or disabled by specific status bits. Three registers
control and operate the timer. The timer counter register (TIM) gives the current count of the timer. The
timer period register (PRD) defines the period for the timer. The 16-bit timer control register (TCR)
controls the operations of the timer.

3.14.3 Software-Programmable Wait-State Generators

Software-programmable wait-state logic is incorporated in ‘C5X DSPs allowing wait-state generation
without any external hardware for interfacing with slower off-chip memory and I/O devices. This
feature consists of multiple wait-state generating circuits. Each circuit is user-programmable to operate
in different wait states for off-chip memory accesses.

3.14.4 Parallel I/O Ports

A total of 64K I/O ports are available, 16 of these ports are memory-mapped in data memory space.
Each of the I/O ports can be addressed by the IN or the OUT instruction. The memory-mapped I/O ports
can be accessed with any instruction that reads from or writes to data memory. The IS signal indicates
a read or write operation through an I/O port. The ¢C5X can easily interface with external I/O devices
through the I/O ports while requiring minimal off-chip address decoding circuits.

3.14.5 Host Port Interface (HPI)

The HPI is available on the ¢C57S and ¢LC57. It is an 8-bit parallel I/O port that provides an interface
to a host processor. Information is exchanged between the DSP and the host processor through on-chip
memory that is accessible to both the host processor and the ‘C57.

3.14.6 Serial Port

Three different kinds of serial ports are available: a general-purpose serial port, a time-division
multiplexed (TDM) serial port and a buffered serial port (BSP). Each ¢C5X contains at least one general-
purpose, high-speed synchronous, full-duplexed serial port interface that provides direct communication
with serial devices such as codecs, serial analog-to-digital (A/D) converters and other serial systems.
The serial port is capable of operating at up to one-fourth the machine cycle rate (CLKOUT1). The
serial port transmitter and receiver are double-buffered and individually controlled by maskable external
interrupt signals. Data is framed either as bytes or as words.
Five 16-bit registers (SPC, DRR, DXR, XSR, RSR) control and operate the serial port interface. The
serial port control (SPC) register contains the mode control and status bits of the serial port. The data
receive register (DRR) holds the incoming serial data, and the data transmit register (DXR) holds the
outgoing serial data. The data transmit shift register (XSR) controls the shifting of the data from the
DXR to the output pin. The data receive shift register (RSR) controls the storing of the data from the
input pin to the DRR.
 Architecture of TMS320C5X 79
3.14.7 Buffered Serial Port (BSP)
The BSP is available on the ¢C56 and ¢C57 devices. It is a full-duplexed, double-buffered serial port and
an autobuffering unit (ABU). The BSP provides flexibility on the data stream length. The ABU supports
high-speed data transfer and reduces interrupt latencies. The BSP has a 2K-word buffer, which resides
in the ‘C5X internal memory. Five BSP registers control and operate the BSP.

3.14.8 TDM Serial Port

The TDM serial port available on the ‘C50, ‘C51 and ‘C53 devices is a full-duplexed serial port that can
be configured by software either for synchronous operations or for time-division multiplexed operations.
The TDM serial port is commonly used in multiprocessor applications.

3.14.9 User-Maskable Interrupts

—— ——
Four external interrupt lines (INT1 – INT4) and five internal interrupts, a timer interrupt and four serial
port interrupts are user maskable. When an interrupt service routine (ISR) is executed, the contents
of the program counter are saved on an 8-level hardware stack, and the contents of 11 specific CPU
registers, ACC, ACCB, PREG, ST0, ST1, PMST, TREG0, TREG1, TREG2, INDX and ARCR, are
saved in one deep stack (shadow registers). When a return from interrupt instruction is executed, the
CPU registers’ contents are restored.

Review Questions
3.1 Mention few applications of each of the families of 3.6 List status register bits of 5X and their functions.
TI DSPs 3.7 Distinguish between the dual-access RAM and
3.2 What are the different buses of TMS320C5X and single-access RAM used in the on-chip memory of 5X.
their functions? 3.8 List the on-chip peripherals in 5X and their
3.3 List the functional units in CALU of 5X and explain functions.
the source and destination of operands of each of these 3.9 What are the various interrupt types supported by
units. 5X?
3.4 List the various registers used with the ARAU and 3.10 Draw the internal architecture diagram of 5X and
their functions. indicate the various blocks.
3.5 What is meant by memory mapped register? How
is it different from a memory?

Self Test Questions

3.1 The 320C5X DSPs are said to have advanced Harvard 3.2 The central ALU of C5X DSP processors have ———
architecture because bit ALU and one of the operands for the ALU operation
(a) they have separate memory bus structures for comes from ———.
program and data (a) 32,ACC (b) 16,ACC (c) 32,ACCB (d) 16,ACCB
(b) they have instructions that enable data transfer 3.3 The result of operations performed in central ALU
between the program and data memory area are stored in ———.
(c) they have same memory bus structures for program (a) ACC (b) ACCB (c) TREG0 (d) PREG
and data
3.4 The ALU register whose either higher order word
(d) the contents of program memory cannot into the
or lower order word can be loaded from memory is.
data memory or vice versa
80 Digital Signal Processors
(a) ACC (b) ACCB (c) TREG0 (d) PREG 3.16 The bit of ST0 that determines whether the ACC is
3.5 The ——— bit register used for temporary storage replaced with either largest positive or negative number
of accumulator is ———. or left unmodified is ———.
(a) 32, PREG (b) 32, ACCB (c) 16, TREG0, (d) 32, ACC (a) SXM (b) OV (c) OVM (d) TC (e) C
3.6 The ——— permits execution of logical operations 3.17 The bit of ST1 that is used for testing whether a
on data without affecting the contents of ACC. particular memory is zero or not or for comparing one
(a) parallel logic unit (b) auxiliary ALU register against another register memory is ———.
(c) central ALU (a) SXM (b) OV (c) OVM (d) TC (e) C
3.7 The hardware multiplier unit in the C5X processors 3.18 The bit of ST1 that becomes 1 if either addition
perform multiplication of ——— times ——— bit generates a carry or subtraction results in borrow is
represented in ——— complement form. ———.
(a) 16, 16, 1s (b) 8,8 1s (c) 16, 16, 2s (d) 8, 8, 2s (a) SXM (b) OV (c) OVM (d) TC (e) C
3.8 ——— holds the result of multiplication and is 3.19 The status register bit that determines whether
——— bit wide. multiplier’s 32-bit product is left shifted by 0, 1, 4 or right
(a) PREG, 32 (b) PREG, 16 shifted by 6 with sign extension before it is transferred/
(c) TREG0, 16 (d) TREG0, 32 added to the ACC is ———.
3.9 The register in which the multiplicand is stored (a) PM (b) CNF (c) HM (d) XF
before multiplication is performed is ——— and is ——— (e) INTM
bit wide. 3.20 The RAM configuration control bit that indicates
(a) PREG, 32 (b) PREG, 16 whether the on-chip reconfigurable dual-access RAM is
(c) TREG0, 16 (d) TREG0, 32 mapped to data space or program space is ———.
3.10 ——— permits the contents of memory to be left (a) PM (b) CNF (c) HM (d) XF
shifted by 0-16 bits before they are either fed to ALU or (e) INTM
stored from ALU to memory. 3.21 The bit of status register that determines whether
(a) Scaling shifter (b) ALU the processor halts the internal operation while
(c) PLU (d) Auxiliary ALU acknowledging a hold or not is ———.
3.11 The register that specifies the number of bits by (a) PM (b) CNF (c) HM (d) XF
which the scaling shifter should shift either the incoming (e) INTM
data to one of the CPU registers or vice versa is ——— 3.22 The ——— bit of the status register indicates the
and is ——— bit wide. status of the general purpose output pin.
(a)TREG1,4 (b) TREG1, 5 (c) TREG2, 5 (d) TREG2, 4 (a) PM (b) CNF (c) HM (d) XF
3.12 When the incoming data to CPU is left shifted by (e) INTM
the scaling shifter the LSBs are filled with ——— 3.23 The pointers that are contained in the status
(a) 0 (b) 1 (c) LSB before shifting register 0 are ———.
3.13 The bit of status register ST1, which determines (a) ARP (b) DP (c) ARB (d) IPTR
whether the MSBs of the bits left shifted by the scaling (e) INTM
shifter is zero, are sign extended is ———. 3.24 The pointers that are contained in the status
(a) SXM (b) TC (c) OV (d) OVM register 1 are ———.
3.14 In the hardware stack of C5X processors ——— bit (a) ARP (b) DP (c) ARB (d) IPTR
numbers can be stored. (e) INTM
(a) 16, 16 (b) 16, 8 (c) 8, 8 (d) 8, 16 3.25 If ——— bit is set to 0, all unmasked interrupts
3.15 The bit of status register 0 (ST0) that becomes 1 if are enabled. Otherwise all the maskable interrupts are
overflow occurs from an ALU operation is ——— disabled.
(a) SXM (b) OV (c) OVM (d) TC (e) C (a) ARP (b) DP (c) ARB (d) IPTR
(e) INTM
 TMS320C5X ASSEMBLY
LANGUAGE INSTRUCTIONS
4
The ¢C5X instruction set supports numerically intensive signal processing operations as well as general-
purpose applications, such as multiprocessing and high-speed control. The C5X instruction set is
a superset of the ¢C1X and ¢C2X instruction sets and is source-code upward compatible with both
devices.

ASSEMBLY LANGUAGE SYNTAX 4.1

For programming in the assembly language the C5X assembler assumes the following assembly language
syntax. A source statement can contain four ordered fields. The general syntax for source statements is
as follows:
[ label ] [:] mnemonic [ operand list ][;comment ]
They in turn follow these guidelines:
∑ All statements must begin with a label, a blank, an asterisk or a semicolon.
∑ Labels are optional; if used, they must begin in column 1.
∑ Labels may be placed either before the instruction mnemonic on the same line or on the
preceding line in the first column.
∑ One or more blanks must separate each field. Tab characters are equivalent to blanks.
∑ Comments are optional. Comments that begin in column 1 can begin with an asterisk or a
semicolon (* or ;), but comments that begin in any other column must begin with a semicolon.
The following types of operands are permitted:
0 £ dma £ 127 dma: Data Memory Address
0 £ pma £ 65535 pma: Program Memory Address
0 £ shift £ 15
0 £ shift2 £ 7
0£n£7 n:AR no.
0 £ k £ 255 k: Short Constant
0 £ lk £ 65535 lk: Long Constant
ind: {**+*–*0+ *0– *BR0+ *BR0–}
Operands can be constants or assembly-time expressions that refer to memory, I/O ports, register
addresses, pointers, shift counts and a variety of other constants.
82 Digital Signal Processors
The complete list of the mnemonics of the various instructions supported by 5X and a brief
description of each of these instructions are given in Appendix A4. More detailed explanation of these
instructions with examples is given in the TMS30C5X user reference manual. In this chapter, in Section
4.2 the various addressing modes supported by C5X are discussed. In Sections 4.3-4.5 some of the most
commonly used C5X instructions are explained individually with examples. In chapter 6 application
programs which make use of the instructions explained in the above sections are presented.

ADDRESSING MODES 4.2

C5X processors can address 64K words of program memory and 96K words of data memory. C5X
supports the following six addressing modes:
Direct addressing
Memory-mapped register addressing
Indirect addressing
Immediate addressing
Dedicated-register addressing
Circular addressing
The details of each of these addressing modes are considered next.

4.2.1 Direct Addressing

The data memory used with C5X processors is split into 512 pages each of 128 words long. The data
memory page pointer (DP) in ST0 holds the address of the current data memory page. In the direct
addressing mode of C5X, only lower-order 7 bits of the address are specified in the instruction. The
upper 9 bits are taken from the DP as shown in Fig. 4.1.

DP(9) Instruction Register (16)

9 MSBs 7 LSBs
15 6 0

DP Direct Memory Address

Fig. 4.1 16-bit data memory address bus (DAB)

4.2.2 Memory-Mapped Register Addressing

The RAM area in page 0 is used for storing some of the registers, interrupt vector addresses and so on.
These locations can be accessed by specifying the actual address or by the register name, (e.g., the AR0
can either be denoted by the actual memory location (10h) used for storing its value or by the symbol
AR0). Since these memory locations can be interchangeably used with the register names, the registers
corresponding to page 0 are referred to as memory-mapped registers (MMRs).
With memory-mapped register addressing, the MMRs can be modified without affecting the current
data page pointer value. In addition, any scratch pad RAM (DARAM B2) location or data page 0 can
also be modified. The memory-mapped register addressing mode operates like the direct addressing
mode, except that the 9 MSBs of the address are forced to 0 instead of being loaded with the contents
 TMS320C5X Assembly Language Instructions 83
of the DP. This allows the memory-mapped registers of data page 0 to be modified directly without the
overhead of changing the DP or auxiliary register. The following instructions operate in the memory-
mapped register addressing mode. Using these instructions does not affect the contents of the DP:
LAMM—Load accumulator with memory-mapped register
LMMR—Load memory-mapped register
SAMM—Store accumulator in memory-mapped register
SMMR—Store memory-mapped register

Example 4.1 The instruction LMMR AR0, #1500h loads AR0 with the content of the location
1500h as shown in Fig. 4.2. Let the content of AR0 and the data memory location
1500h be 2345h and 6789h, respectively, before executing the instruction. After executing the instruction
their contents become 6789h and 6789h.

Before execution of LMMR AR0, # 1500 h after execution.

Fig. 4.2 Memory-mapped register addressing example 4.1

Before execution of SMMR ARO, #1500h After execution.

Fig. 4.3 Memory-mapped register addressing example 4.2

The SMMR does the reverse operation.

Example 4.2 Let the content of AR0 and the data memory location be 2345h and 6789h,
respectively, before executing the instruction SMMR AR0, # 1500h. After executing
the instruction their contents become 2345h and 2345h as shown in Fig. 4.3.

LAMM * loads lower 16 bits of ACC, i.e., ACCL from the location pointed by the lower-order 7 bits of
the current AR. The higher 16 bits ACCH is filled with 0.

Example 4.3 Let the content of ARP, AR1, ACC, the value of data memory locations 25h and
825h be as shown in Fig. 4.4. After execution of the LAMM * instructions, the
register contents are as shown on the right hand column in Fig. 4.4. It can be seen that the value in data
memory location 25h is loaded into ACC. 25h corresponds to the lower-order 7 bits of AR1 and the higher
bits of PAB are made to be 0 as the MMR corresponds to page 0.
84 Digital Signal Processors
Before execution of LAMM * After execution

ARP 1 ARP 1

325 h 325 h

Data mem. Data mem.

6789 h 6789 h
825 h 825 h

Data mem. Data mem.

8345 h 8345 h
25 h 25 h

ACC 2345 h ACC 8345 h

Fig. 4.4 Memory-mapped register addressing example 4.3

4.2.3 Immediate Addressing

The immediate addressing mode can be used to load either a 16-bit constant or a constant of length 13, 9
or 7. Accordingly it is referred to as long immediate or short immediate addressing mode. This mode is
indicated by the symbol #. For e.g., ADD # 56h adds 56h to ACC. Similarly ADD # 4567h adds 4567h
to ACC.

4.2.4 Indirect Addressing

The ARs AR0-AR7 are used for accessing data, using indirect addressing mode. In the indirect addressing
mode, out of the eight ARs the one which is currently used for accessing data is denoted by the register
ARP. The contents of ARP can be temporarily stored in the ARB register. The indirect addressing mode
of C5X permits the AR used for the addressing to be updated automatically either after or before the
operand is fetched. Hence a separate instruction is not required to update the AR. However, if required,
the contents of an AR can be incremented or decremented by any 8-bit constant using SBRK and ADRK
instructions, (e.g., SBRK #k, ADRK #k subtracts, adds the constant k from/ to the AR pointed by
ARP).
In the indirect addressing mode, the manner in which the memory address is computed and the
manner in which the AR is altered after the instruction depends on the instruction. This is indicated to
the assembler by the symbols *, *+, *–,*0+ , *0–, *BR0+ and *BR0–. The symbol used to indicate the
indirect addressing mode and the action taken after executing the instruction are given in Table 4.1.
Table 4.1 Various options in the indirect addressing mode of 5X
Symbol Value of AR pointed by ARP after instruction execution
* AR unaltered
*+ AR incremented by 1
*– AR decremented by 1
*0+ AR incremented by the content of INDX
*0– AR decremented by the content of INDX
*BR0+ AR incremented by the content of INDX with reverse carry propagation
*BR0– AR decremented by the content of INDX with reverse carry propagation