Department of Electrical Engineering

Faculty Member: Sir Mughees Ahmad Dated:06/03/2024

Course/Section: BEE-13-B Semester: 6th semester

EE-421 Digital System Design

Lab 5: Counters and Shift Registers

PLO4 PLO5 PLO8 PLO9

Name Reg. No Viva / Quiz Analysis of Modern Ethics and Individual
/ Lab data in Tool Usage Safety and Team
Performanc Lab Work
e Report

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks

Muhammad Omais 390616

Ahmed Razi Ullah 366191

Department of Electrical Engineering, SEECS, NUST

Department of Electrical Engineering, SEECS, NUST

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1. Objective

The purpose of these laboratory exercises is to design counters and shift registers in Verilog.

2. Introduction to Countersliegisters

A 4-bit counter in Verilog is a digital circuit that counts in binary from 0 to 15 and then wraps
around back to 0. It consists of four flip-flops, each storing a single bit of the binary count.
Here's a simple example of a 4-bit synchronous up counter with an asynchronous reset. This
counter will increment its value on every rising edge of the clock if the enable signal is high,
and it will reset to 0 if the reset signal is high, regardless of the clock.

Counters can be designed using a combination of flip flops. A 4-bit counter can be designed
using instances of d-flip flops. To create a 4-bit counter in Verilog using instances of D flip-
flops, you need to manually instantiate each D flip-flop and connect them to form a counter.
A D flip-flop captures the value at its D input at the rising edge of the clock and transfers it to
the Q output.

The counter we'll design is a simple synchronous up counter that increments on each clock
cycle. We'll use the output of each flip-flop as the input to the next to achieve the counting
behaviour. For simplicity, this example does not include an asynchronous reset or enable
functionality, but those features can be added similarly to the previous example.

module four_bit_counter(
input clk,
input reset,
output [3:0] count
);

wire d_ff0_d, d_ff1_d, d_ff2_d, d_ff3_d;

assign d_ff0_d = ~count[0]; // LSB toggles every clock

assign d_ff1_d = count[0] ? ~count[1] : count[1];
assign d_ff2_d = (count[0] & count[1]) ? ~count[2] : count[2];
assign d_ff3_d = (count[0] & count[1] & count[2]) ? ~count[3] : count[3];

d_ff d_ff0(.clk(clk), .reset(reset), .d(d_ff0_d), .q(count[0]));

d_ff d_ff1(.clk(clk), .reset(reset), .d(d_ff1_d), .q(count[1]));
d_ff d_ff2(.clk(clk), .reset(reset), .d(d_ff2_d), .q(count[2]));
d_ff d_ff3(.clk(clk), .reset(reset), .d(d_ff3_d), .q(count[3]));

endmodule

Similarly a counter can easily be described but just writing its behaviour specification in HDL

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Task 1 : Simulation and Implementation of Counter

● Create a test bench of the 4-bit counter written at behaviour level and implement it on
the FPGA board. The clock source will come from a push button. Observe the results
on Leds.
● module counter_4bit(
● input clk, // Clock input
● input reset, // Asynchronous reset input
● input enable, // Enable input for counting
● output [3:0] out // 4-bit output
● );
●
● reg [3:0] count_value;
●
● // Assign the internal register to the output
● assign out = count_value;
●
● // Counter logic
● always @(posedge clk or posedge reset) begin
● if (reset) begin
● // Asynchronously reset the counter to 0
● count_value <= 4'b0000;
● end else if (enable) begin
● // Increment the counter on each clock edge if enabled
● count_value <= count_value + 1;
● end
● end
●
● endmodule

TESTBENCH
module testbench_4bit_cpunter;
reg clk,reset,enable;
wire [3:0] count;

counter_4bit c4b(.clk(clk),.reset(reset),.enable(enable),.out(count));
initial begin
reset = 1;
clk = 0;
enable = 1;
#100 reset = 0;
end
always #30 clk = ~clk;

endmodule

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 SIMULATION

DIAGRAM

HARDWARE (Double click to watch)

3. Shift Registers

A shift register is a type of digital circuit using a cascade of flip-flops where the output of one
flip-flop is connected to the input of the next. They share a single clock signal. Figure 1
shows a 4-bit serial in serial out shift register that right shifts a bit through each flip flop.

Figure 1: 4-bit Serial In Serial Out Shift Register

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Task 2 : 10-bit Shift Register

Design, simulate and Implement a 10-bit shift register that takes a single Data bit and shift
control bit as input from switches, along with clock and reset from the push buttons. Display
the shift register's data on Seven Segment displays and LEDs.

module task2 (
input data_in,
input control,
input clk,
input reset,
output wire [5:0] leds,
output wire [6:0] anode
);
wire [9:0] data_out;
shift_register s1(data_in,control,clk,reset,data_out);
assign leds[5:0]=data_out[9:4];
sevenseg_ca s2(data_out[3:0],anode);

endmodule

module shift_register (
input data_in,
input control,
input clk,
input reset,
output reg [9:0] data_out
);

always @(posedge clk or negedge reset) begin

if(~reset) data_out<=10'b0000000000;
else if (control)begin
data_out<=data_out<<1;
data_out[0]<=data_in;
end
end
endmodule

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module sevenseg_ca (input [3:0] digit, output reg [6:0] anode);

always @* begin
case(digit)
//////////////////gfedcba
4'b0000: anode = 7'b1000000; // digit 0
4'b0001: anode = 7'b1111001; // digit 1
4'b0010: anode = 7'b0100100; // digit 2
4'b0011: anode = 7'b0110000; // digit 3
4'b0100: anode = 7'b0011001; // digit 4
4'b0101: anode = 7'b0010010; // digit 5
4'b0110: anode = 7'b0000010; // digit 6
4'b0111: anode = 7'b1111000; // digit 7
4'b1000: anode = 7'b0000000; // digit 8
4'b1001: anode = 7'b0001000; // digit 9
4'b1010: anode = 7'b0010000; // digit 10
4'b1011: anode = 7'b0000011; // digit 11
4'b1100: anode = 7'b1000110; // digit 12
4'b1101: anode = 7'b0100001; // digit 13
4'b1110: anode = 7'b0000110; // digit 14
4'b1111: anode = 7'b0001110; // digit 15
default: anode = 7'b1111111;
endcase
end
endmodule

TEST BENCH
module test2 ();
reg clk, data_in,control,reset;
wire [9:0] data_out;
shift_register c1(data_in,control,clk,reset,data_out);

initial begin
$dumpfile("waveform.vcd");
$dumpvars(0, test2);
clk = 0;
#5 reset=1;
#5 reset=0;
control=1;
for (integer i = 0; i < 40; i = i + 1) begin
#10 clk=~clk;
data_in=$random % 2;
end
#100 $finish;
end
endmodule
HARDWARE

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 SIMULATION

4. Clock Dividers

A clock divider is a digital circuit or component used to divide the frequency of an input clock
signal by a specific integer factor to generate a slower clock signal at its output. Clock
dividers are commonly used in digital systems to generate clock signals of different
frequencies that are synchronized with the main clock signal.

The output frequency of a clock divider is typically determined by the input frequency and a
programmable divisor value, which specifies the division ratio. For example, if the input clock
frequency is 100 MHz and the divisor value is set to 10, the output clock frequency will be 10
MHz (100 MHz divided by 10).

Clock dividers are commonly implemented using digital logic circuits such as flip-flops,
counters, or frequency dividers. These circuits divide the input clock signal by toggling their
output state at specific intervals determined by the division ratio, thereby producing the
desired output frequency

Task 3 (a): Design of Mod 10 Counter

● Design and implement a counter that counts from 0 to 9 and rolls over. Observe the
count value on a 7-segment display.
● Use a clock divider that generates a clock of 1Hz in your design.

DIAGRAM

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 CODE
module mux_1 (
input clk_1Hz,
input reset,
input enable,
output [3:0] out,
output [6:0] disp
);

reg [3:0] count_value;

reg [24:0] counter = 0;

assign out = count_value;

always @(posedge clk_1Hz or negedge reset) begin

if (~reset) begin

count_value <= 4'b0000;

end
else if (enable) begin

if (counter == 25000000) begin

counter <= 0;
if (count_value == 4'b1001) begin
count_value <= 4'b0000;
end
else begin
count_value <= count_value + 1;
end
end
else begin

counter <= counter + 1;

end
end
end

SREG s1(out, disp);

Endmodule

HARDWARE

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 SIMULATION

Task 3 (b): Design of Two-Digit BCD Counter

Design, simulate, and implement a Two-Digit BCD Counter that counts from 00 to 99 and
resets to 00 after reaching 99. Display the counter's data in Decimal Format on the two
rightmost Seven-Segment Displays."

DIAGRAM

CODE
module task1(input enable,input rst, input clk, output [6:0]disp1,disp2 );
wire [3:0]ones,tens;
mux_0 m1( enable, rst,clk,ones,tens );
SREG s1(ones,disp1);
SREG s2(tens,disp2);

endmodule

module SREG(I,HEX0);
input [3:0]I;
output reg [6:0]HEX0;

always@(*)
begin
case(I)
4'b0000: HEX0 = 7'b1000000; // digit 0
4'b0001: HEX0 = 7'b1111001; // digit 1
4'b0010: HEX0 = 7'b0100100; // digit 2
4'b0011: HEX0 = 7'b0110000; // digit 3

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 4'b0100: HEX0 = 7'b0011001; // digit 4
4'b0101: HEX0 = 7'b0010010; // digit 5
4'b0110: HEX0 = 7'b0000010; // digit 6
4'b0111: HEX0 = 7'b1111000; // digit 7
4'b1000: HEX0 = 7'b0000000; // digit 8
4'b1001: HEX0 = 7'b0010000; // digit 9
4'b1010: HEX0 = 7'b0001000; // digit 10
4'b1011: HEX0 = 7'b0000011; // digit 11
4'b1100: HEX0 = 7'b1000110; // digit 12
default: HEX0 = 7'b1111111;
endcase
end
endmodule

module mux_0(input enable,input rst, input clk, output reg [3:0]ones,output

reg [3:0]tens );
always @(posedge clk, negedge rst) begin
if(~rst) begin
ones <= 4'b0000;
tens <= 4'b0000;
end
else if(enable) begin

if(ones >= 4'b1001 ) begin

ones <= 4'b0000;
tens <= tens+1;
end
else if(tens >= 4'b1001) begin
if(ones>=4'b1001) begin
tens <= 4'b0000;
end
else ones <= ones+1;
end
else begin
ones <= ones + 1;
end
end
end

endmodulE

SIMULATION

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 HARDWARE

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5. Learning Outcomes Checklist

After this lab, you will be able to:

� Understand how to code counter by instantiating flip flops and by writing a
behavioural Verilog code.

� Design of shift registers.

� Concept of Clock Dividers in Counters and for slowing down clock frequency

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