Unit - 4

MEMORY
Memory Hierarchy
A memory unit is an essential component in any digital computer since it is needed for storing
programs and data.

Design of Memory Hierarchy

In computers, the memory hierarchy primarily includes the following:
Levels of memory:
Level 0 or Register – It is a type of memory in which data is stored and accepted that are
immediately stored in CPU. Most commonly used register is accumulator, Program
counter, address register etc.
Level 1 or Cache memory – It is the fastest memory which has faster access time where
data is temporarily stored for faster access.
Level 2 or Main Memory – It is memory on which computer works currently. It is small
in size and once power is off data no longer stays in this memory.
Level 3 or Secondary Memory – It is external memory which is not as fast as main
memory but data stays permanently in this memory.
A memory unit can be classified into two categories:
1. Main Memory
2. Auxiliary Memory
1. The memory unit that establishes direct communication with the CPU is called Main
Memory. The main memory is often referred to as RAM (Random Access Memory).
 2. The memory units that provide backup storage are called Auxiliary Memory. For
instance, magnetic disks and magnetic tapes are the most commonly used auxiliary
memories.
4. Magnetic Disks
▪ In a computer, the magnetic disks are circular plates that’s fabricated with plastic or
metal with a magnetised material.
▪ Two faces of a disk are frequently used, and many disks can be stacked on a single
spindle by read/write heads that are obtainable on every plane.
▪ The disks in a computer jointly turn at high speed.
5. Magnetic Tape
▪ Magnetic tape refers to a normal magnetic recording designed with a slender
magnetizable overlay that covers an extended, thin strip of plastic film.
▪ It is used mainly to back up huge chunks of data. When a computer needs to access a
strip, it will first mount it to access the information. Once the information is allowed, it
will then be unmounted.
▪ The actual access time of a computer memory would be slower within a magnetic strip,
and it will take a few minutes for us to access a strip.
Characteristics of Memory Hierarchy
1. Capacity
2. Access Time
3. Performance
4. Cost per bit
1. Capacity
It refers to the total volume of data that a system’s memory can store. The capacity increases
moving from the top to the bottom in the Memory Hierarchy.
2. Access Time
It refers to the time interval present between the request for read/write and the data
availability. The access time increases as we move from the top to the bottom in the Memory
Hierarchy.
3.Performance
When a computer system was designed earlier without the Memory Hierarchy Design,
the gap in speed increased between the given CPU registers and the Main Memory due
to a large difference in the system’s access time.
4. Cost per bit
The cost per bit increases as one moves from the bottom to the top in the Memory Hierarchy,
i.e. External Memory is cheaper than Internal Memory
Semiconductor Memories
▪ Semiconductor memories are the volatile memory storages that store the program and
data until the power supply to the system is ON.
▪ The cycle time of these semiconductor memories ranges from 100 ns to 10 ns.
▪ The cycle time is the time from the start of one access to the start of the next access to
the memory.

Difference RAM ROM

Data RAM is a volatile memory which ROM is a non-volatile memory which could
retention could store the data as long as the retain the data even when power is turned off.
power is supplied.

Working Data stored in RAM can be Data stored in ROM can only be read.
type retrieved and altered.

Use Used to store the data that has to It stores the instructions required during
be currently processed by CPU bootstrap of the computer.
temporarily.

Speed It is a high-speed memory. It is much slower than the RAM.

CPU The CPU can access the data stored The CPU can not access the data stored on it
Interaction on it. unless the data is stored in RAM.

Size and Large size with higher capacity, with Small size with less capacity, with respect to
Capacity respect to ROM RAM

Used as/in CPU Cache, Primary memory. Firmware, Micro-controllers

 Accessibility The data stored is easily accessible The data stored is not as easily accessible as in
RAM

Cost Costlier cheaper than RAM.

Storage A RAM chip can store only a few A ROM chip can store multiple megabytes (MB)
gigabytes (GB) of data. of data.

SRAM and DRAM :

1. SRAM :
Static RAM, or (SRAM) which stores a bit of data using the state of a six transistor memory cell.
SRAM memories are used to build Cache Memory.
2. DRAM :
Dynamic RAM, or (DRAM) which stores a bit data using a pair of transistor and capacitor which
constitute a DRAM memory cell.
The main memory is generally made up of DRAM chips
Difference between SRAM and DRAM :
Cache Memory:
▪ Cache Memory is a special very high-speed memory.
▪ It is used to speed up and synchronize with high-speed CPU. Cache memory is costlier
than main memory or disk memory but more economical than CPU registers.
▪ Cache memory is an extremely fast memory type that acts as a buffer between RAM
and the CPU.
▪ It holds frequently requested data and instructions so that they are immediately
available to the CPU when needed.

Cache Performance:
▪ Cache Performance: When the processor needs to read or write a location in main
memory, it first checks for a corresponding entry in the cache.
▪ If the processor finds that the memory location is in the cache, a cache hit has occurred
and data is read from the cache.
▪ If the processor does not find the memory location in the cache, a cache miss has
occurred. For a cache miss, the cache allocates a new entry and copies in data from
main memory, then the request is fulfilled from the contents of the cache.
▪ The performance of cache memory is frequently measured in terms of a quantity
called Hit ratio.
▪ Hit ratio = hit / (hit + miss) = no. of hits/total accesses
▪ We can improve Cache performance using higher cache block size, and higher
associativity, reduce miss rate, reduce miss penalty, and reduce the time to hit in the
cache.
Cache Mapping
There are three different types of mapping used for the purpose of cache memory which is as
follows:
1. Direct mapping
2. Associative mapping,
3. Set-Associativ mapping.

1. Direct mapping
▪ In Direct mapping, assign each memory block to a specific line in the cache. If a line is
previously taken up by a memory block when a new block needs to be loaded, the old
block is trashed. An address space is split into two parts index field and a tag field.
▪ The cache is used to store the tag field whereas the rest is stored in the main memory.
Direct mapping`s performance is directly proportional to the Hit ratio.
▪ For purposes of cache access, each main memory address can be viewed as consisting of
three fields.
▪ The least significant w bits identify a unique word or byte within a block of main
memory.
▪ In most contemporary machines, the address is at the byte level. The remaining s bits
specify one of the 2s blocks of main memory.
▪ The cache logic interprets these s bits as a tag of s-r bits (most significant portion) and a
line field of r bits.
▪ This latter field identifies one of the m=2r lines of the cache. Line offset is index bits in
the direct mapping.
2. Associative Mapping
▪ In this type of mapping, the associative memory is used to store content and addresses
of the memory word.
▪ Any block can go into any line of the cache. This means that the word id bits are used to
identify which word in the block is needed, but the tag becomes all of the remaining
bits.
▪ This enables the placement of any word at any place in the cache memory. It is
considered to be the fastest and the most flexible mapping form. In associative mapping
the index bits are zero.

3. Set-associative Mapping
▪ This form of mapping is an enhanced form of direct mapping where the drawbacks of
direct mapping are removed. Set associative addresses the problem of possible
thrashing in the direct mapping method.
▪ It does this by saying that instead of having exactly one line that a block can map to in
the cache, we will group a few lines together creating a set.
▪ Then a block in memory can map to any one of the lines of a specific set. Set-associative
mapping allows that each word that is present in the cache can have two or more words
in the main memory for the same index address.
▪ Set associative cache mapping combines the best of direct and associative cache
mapping techniques. In set associative mapping the index bits are given by the set offset
bits. In this case, the cache consists of a number of sets, each of which consists of a
number of lines. The relationships are
Design of 512×8 RAM using 128×8 RAM
▪ If we see RAM physically then we notice that RAM is made up of a few chips. We can
design the required RAM size using basic RAM chips. We can observe a basic RAM chip
as follows:

CS1: For chip select 1, the value should be 1

CS2: For chip select 2, the value should be 0.
Read and Write: Used for upcoming signals.
If we have n bit address and m bit words then our RAM size will be
2n x m.
 Example:
n=7 bit, m=8 bit RAM size= 128 x 8
Given:
Basic RAM size = 128 x 8
Required RAM size = 512 x 8
To design a RAM size of 512×8 from 128×8, here are some calculations we need to do first:
1. Number of chips required:
Number of chips required = Desired RAM Size/ Basic RAM Size =512x8/128x8 =4 chips
2. Address Bits:
Required Size is 512 x 8= 29 x 8 Therefore, 9 bit address is required
3. Decoder Size: If the number of words is increasing there will be a need for a decoder.
In this case number of words is increasing (from 128 to 512).
Size of decoder= number of times words increasing 128⇢512 words increased by 4
times Decoder Size= 2x4
Pictorial Description (Design of 512×8 RAM) is as follows:

2D and 2.5D Memory organization

➢ The internal structure of Memory either RAM or ROM is made up of memory cells that
contain a memory bit.
➢ A group of 8 bits makes a byte.
➢ The memory is in the form of a multidimensional array of rows and columns. In which,
each cell stores a bit and a complete row contains a word.
➢ A memory simply can be divided into this below form.

2n = N
where n is the no. of address lines and N is the total memory in bytes.

There will be 2n words.

2D Memory organization –

▪ In 2D organization, memory is divided in the form of rows and columns(Matrix).

▪ Each row contains a word, now in this memory organization, there is a decoder.
▪ A decoder is a combinational circuit that contains n input lines and 2 n output lines.
▪ One of the output lines selects the row by the address contained in the MAR and the
word which is represented by that row gets selected and is either read or written
through the data lines.
2.5D Memory organization-
▪ In 2.5D Organization the scenario is the same but we have two different decoders one is
a column decoder and another is a row decoder.
▪ Column decoder is used to select the column and a row decoder is used to select the
row.
▪ The address from the MAR goes as the decoders’ input.
▪ Decoders will select the respective cell through the bit outline, then the data from that
location will be read or through the bit, inline data will be written at that memory
location.

Read and Write Operations –

1. If the select line is in Reading mode then the Word/bit which is represented by the MAR
will be available to the data lines and will get read.
2. If the select line is in write mode then the data from the memory data register (MDR)
will be sent to the respective cell which is addressed by the memory address register
(MAR).
3. With the help of the select line, we can select the desired data and we can perform read
and write operations on it.
Comparison between 2D & 2.5D Organizations –
1. In 2D organization hardware is fixed but in 2.5D hardware changes.
2. 2D Organization requires more gates while 2.5D requires less.
3. 2D is more complex in comparison to the 2.5D organization.
4. Error correction is not possible in the 2D organization but in 2.5D it could be done easily.
5. 2D is more difficult to fabricate in comparison to the 2.5D organization.