Article

Variable Multiple Interleaved Bi‐Directional DC/DC Converter

with Current Ripple Optimization
Jiandong Duan 1, Shuai Wang 1, Yiming Xu 1, Shaogui Fan 2,*, Ke Zhao 1 and Li Sun 1

1 Department of Electrical Engineering, Harbin Institute of Technology, Harbin 150001, China

2 Yantai Research Institute, Harbin Engineering University, Yantai 265615, China
* Correspondence: [email protected]

Abstract: In order to reduce the current ripple and improve the power density of the system, the
multiple structure design is generally adopted by the traditional bidirectional DC/DC converter.
However, the fixed multiplicity design can’t make the DC/DC power converter always output the
smallest current ripple under different duty ratios. Through this research, it is found that the current
ripple is related to duty cycle and parallel multiplicity, and then a variable multiplicity bidirectional
DC/DC power converter is proposed. Firstly, the relationship between the current ripple and paral‐
lel multiplicity and duty cycle is deduced, and the basic topology of variable multiplicity bidirec‐
tional DC/DC power converter is determined; Secondly, the average value model and AC small
signal model of the system are established based on the topological structure, and then the state
equation is obtained. Thirdly, the current compensation control method is designed based on the
state equation. Finally, the experimental platform of variable multiplicity bidirectional DC/DC
power converter is built.

Keywords: bidirectional DC/DC converter; current ripple optimization; constant current control

1. Introduction
Energy storage systems have been widely used to improve the power distribution
between renewable power generation, large power grids, and user loads [1–3]. As the
Citation: Duan, J.; Wang, S.; Xu, Y.;
power transmission channel between the DC bus and the energy storage system, the bi‐
Fan, S.; Zhao, K.; Sun, L. Variable
directional DC/DC converter can realize bidirectional energy flow and improve energy
Multiple Interleaved Bi‐Directional
DC/DC Converter with Current
distribution efficiency [4–6]. However, the DC/DC converter may introduce a large cur‐
Ripple Optimization. Appl. Sci. 2023,
rent ripple to the DC bus, which affects the quality of the power supply [7,8].
13, 1744. https://doi.org/10.3390/ Many researchers have proposed different methods to reduce the current ripple, each
app13031744 of which has its advantages [9–11]. At present, the current ripple optimization methods
of DC/DC converter mainly include: input parallel output series (IPOS) DC/DC converter,
Academic Editor: Johannes Schwank
ripple current injection DC/DC converter, resonant ripple absorption DC/DC converter,
Received: 27 December 2022 DC/DC converter using coupled inductor technology, multiple DC/DC converter, etc. Ref‐
Revised: 20 January 2023 erence [12] studied an IPOS DC/DC converter, which could offset the current ripple to a
Accepted: 27 January 2023 certain extent, but has the problem of low voltage gain. The DC/DC converter with ripple
Published: 29 January 2023 current injection proposed in [13] artificially injects ripple current at both ends of the in‐
ductor to eliminate the ripple current. The ripple suppression effect is good, but the circuit
is more complicated. Reference [14] proposed a resonant ripple absorption DC/DC con‐
Copyright: © 2023 by the authors. Li‐ verter that uses the LC devices to generate resonance to optimize the current ripple, but
censee MDPI, Basel, Switzerland. the ripple suppression capability for dynamic loads is poor due to the fixed system pa‐
This article is an open access article rameters. The DC/DC converter with coupled inductor technology [15] replaces the in‐
distributed under the terms and con‐ ductor in the traditional DC/DC converter with a coupled inductor. When the coupling
ditions of the Creative Commons At‐
coefficient of the coupled inductor is selected reasonably, a better ripple suppression ef‐
tribution (CC BY) license (https://cre‐
fect can be achieved, however, the switching stress is larger due to the influence of leakage
ativecommons.org/licenses/by/4.0/).
inductance. The multiple DC/DC converter adopts multiple structure and has high power

Appl. Sci. 2023, 13, 1744. https://doi.org/10.3390/app13031744 www.mdpi.com/journal/applsci

Appl. Sci. 2023, 13, 1744 2 of 23

grade. The increase in converter multiplicity can reduce the current ripple, reduce the
switching stress, improve the equivalent switching speed, improve the dynamic perfor‐
mance, and then improve the power quality [16–23].
The above current ripple optimization methods of DC/DC converters mainly have
the problems of large switching stress and low voltage gain, so they are difficult to be
applied to high power energy storage systems, while the traditional multiple DC/DC con‐
verters can not only reduce switching stress, but also achieve better current ripple sup‐
pression through continuous improvement, so they are widely used in high power energy
storage systems [18,19]. Energy storage systems (especially battery energy storage sys‐
tems) are highly sensitive to current ripples, and excessive current ripples will affect the
service life of the system. Reducing the current ripple of the converter is of great signifi‐
cance for improving the quality of the power supply, prolonging the service life of the
system. However, the existing research mostly studies improving the circuit structure of
the multiplexed DC/DC converter to optimize the current ripple, such as using the cou‐
pled inductor instead of the traditional inductor [15] and using the new SiC device [24],
the working model of the multiplexed converter is also limited to the fixed multiplicity
model, and there are few studies on the influence of changing the parallel multiplicity on
the current ripple. In fact, related researches find the multiplicity of parallel circuits also
has an important influence on the magnitude of current ripple, and there is always a par‐
allel multiplicity corresponding to the minimum current ripple under different duty cycle
[20–23]. The main contribution of this paper is to propose a current ripple optimization
method for bidirectional DC/DC converters by changing the multiplicity of parallel cir‐
cuits. In reference [25], increasing the switching frequency can reduce the current ripple,
but this will inevitably increase the loss and reduce the efficiency. The biggest feature of
the method in this paper is that the actual operating multiplicity of the multiplexed
DC/DC converter will be dynamically changed according to the duty cycle, as a result, the
current ripple is optimized without changing the switching frequency. The improvements
are shown as follows: Firstly, the relationship between the current ripple and parallel mul‐
tiplicity and duty cycle is studied. Secondly, a control method that can change the parallel
multiplicity of the DC/DC converter to optimize the current ripple is proposed. Thirdly,
considering there are many similar circuits in the multiplex DC/DC converter, there will
be the problem of uneven current distribution due to the differences in devices. Although
automatic master control overcomes the vulnerability of the master‐slave method, where
the master is auto‐selected by the maximum, it can trigger larger fluctuations in the output
current [26]. In this paper, automatic master control and current compensation control are
combined, compared with the single automatic master control, this method can better re‐
alize the current balance distribution and optimize fluctuations on the output current
when the parallel multiple is switching.
This paper is organized as follows: In Section 2, the relationship between the current
ripple and parallel multiplicity and duty cycle is deduced, and the basic topology of var‐
iable multiplicity bidirectional DC/DC power converter is determined. In Section 3, the
average value model and AC small signal model of the system are established. In Section
4, the current compensation control is designed. In Section 5, the simulation model and
the experimental platform of variable multiplicity interleaving bidirectional DC/DC
power converter is built. The simulation and experiment results show that the optimiza‐
tion of the current ripple of the variable multiplicity bidirectional DC/DC converter is ob‐
vious.
Appl. Sci. 2023, 13, 1744 3 of 23

2. The Principle of Current Ripple Optimization

Assuming that the bidirectional DC/DC converter operates in Buck mode, the topol‐
ogy of the converter is shown in Figure 1.

S1
L
VDC
S2 VLoad

Figure 1. Bidirectional DC/DC converter in Buck mode.

The relationship among load‐side voltage ULoad, DC bus voltage, and duty cycle D is
shown as follows:

VLoad  DVDC (1)

For inductance L, the slope of the current rising phase is defined as kup, and the slope
of the current decreasing phase is defined as kdown.
 VDC  VLoad
kup  L
 (2)
k V
 Load
 down L
In same‐phase driving mode, iL1, iL2, iL3, iL4, and so on are exactly equal, then the peak‐
to‐peak value of the ripple of total current can be shown as:

iLs  iL1 iL2 ... iLn  nDkupT (3)

In the phase‐shift control, the relationship between the current and time is estab‐
lished by setting the current iL1 as the zero point at the initial time of a switching cycle
[0,T]. The current iL1, iL2, iL3, iL4, and so on are shown in Figure 2.

2T
DT DT 
n
T T T
DT  DT  ……
 D  1 T  iL
n n n

iL2 iL3 iLn-1

iL4……iLn-2
iL1 iLn

0
T 2T  n  1 T  n  1 T  2n  1 T
…… T …… 2T
n n n n n
t(s)
Figure 2. Multiple inductor current and total current waveform.

Assuming that the slope of ndown‐fold inductor current at the initial stage is kdown, and
satisfies ndown + nup =n. Then the following relationship can be obtained.
Appl. Sci. 2023, 13, 1744 4 of 23

 1  D  n  1  ndown

 (4)
 Dn  1  nup

Then, the duty cycle has the following relationship: 1  n dow n  1  D  1  n down . As‐
n n
n n 1
suming that D is 50%, and n dow n  or n dow n  can be obtained according to the
2 2
parity of n.
The expression of the first inductance current is shown as:

iL1  kupt t  0, DT 
 (5)
iL1  kdown  t  T  t  DT , T 
The expression of the second inductance current can be shown as:

  T  T
iL2  kdown  t  n  t   0, 
    n
  T  T T
iL2  k up  t   t   , DT   (6)
  n n n
  n 1   T 
iL2  kdown  t  T  t   DT  , T 
  n   n 

The expression of the third inductance current can be shown as:

  2T   2T 
iL3  kdown  t  n  t  0, 
    n
  2T   2T 2T 
iL3  kup  t   t   , DT   (7)
  n   n n
  n2   2T 
iL3  kdown  t  T  t   DT  , T 
  n   n 

The expression of the n‐th inductance current can be shown as:

  T  T
iLn  kup  t  n  t   0, DT  
n
   
  n 1   T n 1 
iLn  kdown  t  T  t   DT  , T (8)
  n   n n 
  n  1   n  1 
iL3  k up  t  T t T ,T 
  n   n 

According to Kirchhoff’s law, the expression of the iL in a switching cycle can be ob‐
tained and can be extended to the n‐th cycle, which is shown in (9).
Appl. Sci. 2023, 13, 1744 5 of 23

 nup k upT
iL   nup k up  ndown kdown  t  n
up  1
 2n
 ndown kdown T  nup  1 
   ndown  1 t   0, DT  T
 2n  n 

iL   n
up  1 kup   ndown  1 kdown t 

 k up  nup  1 nup  2  kdown  ndown  1 ndown  2   nup  1 T 
  T T t   DT  T, 
 2n 2n  n n
i
L   n
up  1 kup   ndown  1 kdown t 

 k up  nup  1  nup  4  kdown  ndown  1 ndown  4   nup  2 2T  (9)
  T T t   DT  T, 
 2n 2n  n n 
 

iL   nup k up  ndown kdown  t

 nup k upT ndown kdown T  n 1 n T
 
2n
nup  2n  1 
2n
 ndown  2n  1 t T , DT  down 
  n n 

iL   n
up  1 kup   ndown  1 kdown t 

 k up  nup  1 nup  2n  kdown  ndown  1  ndown  2n   n T 
  T T t   DT  down , T 
 2n 2n  n 

According to (5)–(9) and Figure 2, when phase shift control is applied to the n‐fold
DC/DC converter, the total ripple of the current flowing through the inductor L is shown
in (10):

 nup 1 
iLm   nup kup  ndown kdown  DT  T
 n 
(10)
 
TVDC 1  D   Dn  1   D 1  D n 1  Dn    Dn  1   1
 
L n
Define kLm as the ripple coefficient, which is shown in (11).

   
1  D    Dn  1   D 1  D  n 1  Dn    Dn  1   1

kLm   (11)
n
The expression of (11) can be rewritten to.

TVDC
iLm  kLm (12)
L
It can be seen from (11) that the ripple coefficient kLm is affected by the duty cycle D
and the number of parallel multiplicity n. When the bidirectional DC/DC converter oper‐
ates in Buck mode, the relationship between the ripple coefficient kLm, the duty cycle D,
and the number of parallel channel multiplicity n is shown in Figure 3. It can be seen from
Figure 3 that there is a point where the ripple coefficient kLm is 0 when different numbers
of parallel multiplicity n and different duty cycle D are taken.
Appl. Sci. 2023, 13, 1744 6 of 23

The ripple coefficient(kLm)

0.15

0.10

0.05

0
1.0
0.8 10
0.6 8
0.4 6
0.2 4
0 2

Figure 3. The relationship among kLm, D, and n of bidirectional DC/DC converter in Buck mode.

According to (11), the relationship between ripple coefficient kLm and duty cycle D
can be obtained, shown in Figure 4, when the number of multiplicities is different. It can
be seen from Figure 4 that there are n‐1 points where the ripple coefficient is zero for the
n‐multiplicity bidirectional DC/DC power converter.

0.14
n=2
n=3
0.12 n=4
n=5
The ripple coefficient(kLm)

n=6
0.10

0.08

0.06

0.04

0.02

0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Duty ratio(D)
Figure 4. Relationship between kLm and D with different parallel multiplicity.

As can be seen from Figure 4, under the condition of different duty cycles, it is not
that the more parallel multiplicity, the smaller the current ripple coefficient. Although the
ripple coefficient generally decreases with the increase of parallel multiplicity, consider‐
ing that too many parallel multiplicities will increase the complexity of the circuit; and
more when the number of parallel multiplicities is greater than six, the increase of parallel
multiplicity has no obvious effect on the reduction of current ripple. The principle of the
variable multiplicity bidirectional DC/DC power converter is to automatically select the
working number of parallel multiplicities according to the current duty cycles of the sys‐
tem. The number of parallel multiplicities that should be used for the minimum current
ripple when the duty cycle is in the range of 0.1–0.9 is shown in Table 1. For example,
when the duty cycle of the system is 0.25, the quadruple parallel structure should be
adopted, and the controller outputs four PWM signals with a 90‐degree phase shift in each
multiplicity.
Appl. Sci. 2023, 13, 1744 7 of 23

Table 1. The number of parallel multiplicities corresponding to different duty cycles.

Range of Duty Cycles Number of Parallel Multiplicities

0.1000~0.1835 6
0.1835~0.2254 5
0.2254~0.2887 4
0.2887~0.3675 6
0.3675~0.4772 5
0.4772~0.5528 6
0.5528~0.6324 5
0.6324~0.7113 6
0.7113~0.7746 4
0.7746~0.8165 5
0.8165~0.9000 6

Figure 5 shows the number of parallel multiplicities that should be taken to minimize
the current ripple. For example, when the duty cycle is 0.2, a five‐fold parallel structure
should be adopted, and the current ripple is the smallest; when the duty cycle is 0.25, a
four‐fold parallel structure should be adopted. Thus, a curve with the smallest current
ripple can be obtained in Figure 5. By calculating the intersection point of the minimum
current ripple carve in Figure 5, the corresponding relationship between the parallel mul‐
tiplicity and the duty range can be obtained, as shown in Table 1.

0.14
Minimum current ripple
N=2
0.12 N=3
The ripple coefficient(kLm)

N=4
N=5
0.10 N=6

0.08

0.06

0.04

0.02

0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Duty ratio(D)

Figure 5. Parallel multiplicity corresponding to the minimum current ripple coefficient under dif‐
ferent duty cycles.

3. The Model of Variable Multiplicity Interleaving Bidirectional DC/DC Power

Converter
3.1. The Mean Value Model
In Figure 6, VDC is DC side voltage, iDC is DC side current, iLk (1 ≤ k ≤ n) is inductor
current, Rk (1 ≤ k ≤ n) is the resistance of the inductor, VL is inductor voltage, VLoad is load‐
side voltage, iLoad is load‐side current, and D is duty cycle.
Appl. Sci. 2023, 13, 1744 8 of 23

S1 S3 S2n-1
iL1 L1 R1
iDC iL2 L2
R2

……
VDC
……
iLn Ln Rn

S2 S4 S2n VLoad

Figure 6. The topology of variable multiplicity bidirectional DC/DC power converter.

The DC side current is shown as:

n
iDC   Dk iLk (13)
k 1

When the lower arm is turned off and the upper arm is turned on, the voltages at
both ends of each inductance can be shown as:

 diL1
 VL1  L1 dt  VDC  VLoad  iL1 R1

V  L diL2  V  V  i R
 L2 2 DC Load L2 2
 dt (14)
 

 diLn
VLn  Ln dt  VDC  VLoad  iLn Rn

When the lower arm is turned on and the upper arm is turned off, the voltages at
both ends of each inductance can be shown as:

 diL1
 VL1  L1 dt  VLoad  iL1 R1

V  L diL2  VLoad  iL2 R2
 L2 2
 dt (15)
 

 diLn
VLn  Ln dt  VLoad  iLn Rn

Because the switching period Ts is very small, it can be considered that VDC and VLoad
are continuous and constant in a switching period. They can be expressed by their average
values in a period.

VDC  VDC T
s
 (16)
VLoad  VLoad Ts

According to the volt‐ampere characteristics and volt‐second balance principle of the

inductor, the average voltage of the inductor shown in (17) in a switching cycle can be
obtained by dealing with Equations (14)–(16).
Appl. Sci. 2023, 13, 1744 9 of 23

 1  D1Ts Ts

 vL1  t  Ts  T  0 vL1  t  dt  D1Ts vL1  t  dt   D1 VDC Ts  VLoad Ts
 iL1 Ts
R1
 s

 1  D2Ts Ts

 vL2  t  Ts   0 vL2  t  dt  D2Ts vL2  t  dt   D2 VDC Ts  VLoad Ts
 iL2 Ts
R2
 Ts (17)
 

 1 ns D T T

 vLn  t  Ts  T  0 vLn  t  dt  DnTs vLn  t  dt   Dn VDC Ts  VLoad  iLn
s

Ts Ts
Rn
 s

According to the volt‐ampere characteristics of the capacitor and Kirchhoff’s current

law, the average current flowing through the load capacitor in a switching cycle can be
obtained.

d vLoad  t 
iLoad  t 
Ts
C
Ts
dt (18)
 iL1  t  T  iL2  t  Ts
   iLn  t  Ts
s

The characteristic equation of inductance after averaging treatment is.

 d vL1  t 
 vL1  t   L1
Ts

 Ts
dt
 d vL2  t 

v t 
Ts
 L2
 L2 Ts
dt (19)

 
 d vLn  t 
 v t   Ln
Ts

 Ln Ts
dt
Substitute Equation (19) into Equation (17), and the following Equation (20) can be
obtained.

 d vL1  t 
 L1 Ts
 D1 VDC  VLoad  iL1 R1
 dt TS TS TS

 d v t
 L2   Ts
L2  D2 VDC  VLoad  iL2 R2
 dt Ts Ts Ts (20)

 
 d v t 
L Ln Ts
 Dn VDC  VLoad  iLn Rn
 n dt Ts Ts Ts

According to Equations (18) and (20), the average value model of the variable multi‐
plicity bidirectional DC/DC power converter in Buck mode can be obtained, as shown in
Figure 7.
Appl. Sci. 2023, 13, 1744 10 of 23

iDC iL1 L1 R1
1:D1

VDC VLoad

iL2 L2 R2
1:D2

… iLn Ln Rn
1:Dn

Figure 7. The average value model of the variable multiplicity bidirectional DC/DC power converter
in Buck mode.

3.2. The AC Small Signal Model

Equations (17) and (18) obtained in the mean value model are nonlinear equations,
so it is complex to solve them directly. However, there are DC components and low‐fre‐
quency small signal components in the variable, which can be solved in approximate
ways. The specific idea is to study the state of the DC/DC power converter near the steady‐
state working point, where the linearization is satisfied, and the equation can be linearized
to separate the DC components and small signal components [27]. Conditions are as fol‐
lows: the interleaved bidirectional DC/DC power converters should satisfy the low‐fre‐
quency assumption, small ripple assumption, and small signal assumption in the process
of modeling the AC small signal model [27,28].

x̂  t   X (21)

In Equation (21) [27], x̂  t  is the amplitude of the AC component, while X is the

amplitude of the DC component.
In a switching cycle, any variable can be divided into DC components and AC small
signal components, which is shown in (22).

 iLk  I Lk  iˆLk  t 
 Ts

 Dk  Dk  dˆk  t 
 Ts

 vLoad Ts
 VLoad  vˆLoad  t  1  k  6, k is integer  (22)

 vDC Ts
 VDC  vˆDC  t 

 iLoad Ts
 I Load  iˆLoad  t 

Equation (22) being brought into Equation (20) can get (23).
Appl. Sci. 2023, 13, 1744 11 of 23

 d  I L1  iˆL1  t  
 L1     D  dˆ t  V  vˆ t   V  vˆ
 1 1     DC DC     Load Load  t     I L1  iL1  t   R
 ˆ 
 dt

 L d  I L2  iL2  t     D  dˆ t  V  vˆ t   V  vˆ
 ˆ 
2     DC DC     Load Load  t     I L2  iL2  t   (23)
ˆ
 2
dt  2
 

 d  I  iˆ  t  
 L  Ln Ln    D  dˆ  t   V  vˆ  t    V  v̂  t     I  iˆ  t  
 n dt  n n   DC DC   Load Load   Ln Ln 

Ignoring the DC components and the second‐order AC small signal components in

Equation (23), the above equation can be transformed into the following form.

 diˆL1  t 
 L1  D1vˆDC  t   VDC dˆ1  t   vˆLoad  t   iˆL1  t  R1
 dt
 diˆL2  t 
 L2  D2 vˆDC  t   VDC dˆ2  t   vˆLoad  t   iˆL2  t  R2
 dt (24)
 

 diLn  t 
ˆ
 Ln  Dn vˆDC  t   VDC dˆn  t   vˆLoad  t   iˆLn  t  Rn
 dt
Solving Equations (22) and (18) simultaneously, the following equation can be ob‐
tained.

diˆLoad  t 
iˆLoad  t   C  iˆL1  t   iˆL2  t     iˆLn  t  (25)
dt
According to Equations (24) and (25), the AC small signal model of the variable mul‐
tiplicity bidirectional DC/DC power converter in Buck mode can be obtained, which is
shown in Figure 8.

iˆL1 L1 R1
1: dˆ1
v̂DC d̂1 I L1 d̂1VDC v̂Load

iˆL2 L2 R2
1: dˆ2

d̂ 2 I L2 d̂ 2VDC
…

iˆLn Ln Rn
1: dˆn

d̂ n I Ln d̂ nVDC

Figure 8. The AC small signal model of the variable multiplicity bidirectional DC/DC power con‐
verter in Buck mode.
Appl. Sci. 2023, 13, 1744 12 of 23

4. The Design of Control Strategy for the Variable Multiplicity Interleaving

Bidirectional DC/DC Power Converter
4.1. The Analysis of the Open‐Loop Characteristic of the Variable Multiplicity Interleaving
Bidirectional DC/DC Power Converter
In order to simplify the analysis, it is assumed that the parameters of each corre‐
sponding component in the variable multiplicity interleaving bidirectional DC/DC power
converter are entirely equal.

 L1  L2    Ln  L
L  L    L  L
 L1 L2 Ln L
 (26)
 1D  D 2    Dn  D
 R1  R2    Rn  R

The equation of the frequency domain is obtained by the Laplace transform of Equa‐
tions (24) and (25).

sLiˆL  s   DvˆDC  s   VDC dˆ  s   vˆLoad  s   iˆL  s  R

 (27)
iˆLoad  s   sCvˆLoad  s   niˆL  s 

In order to control the load voltage VLoad, the input can be assumed to be the ideal
voltage source, vˆDC  s   0 . Then, the transfer function Gid(s) between duty cycle d(s) and
inductance current iL(s) can be obtained by simplifying Equation (27).

iˆL  s  sCVDC
Gid  s    (28)
dˆ  s  s LC  sCR  n
2
vˆDC  s   0

The transfer function Gvd(s) between duty cycle d(s) and load voltage VLoad (s) can be
obtained.

vˆLoad  s  nVDC
Gvd  s    (29)
dˆ  s  vˆDC  s   0
s 2 LC  sCR  nVDC

The transfer function Gvi(s) between inductance current iL(s) and load voltage VLoad
(s) can be obtained according to Equations (28) and (29).

Gvd  s  n  s 2 LC  sCR  nVDC 

Gvi  s    (30)
Gid  s  s 3C 2 L  s 2 C 2 R  nsCVDC

Bring the data in Table 2 into Equation (28), and the transfer function Gid(s) can be
obtained.
sCVDC 6s
Gid  s    (31)
s LC  sCR  n 1.8 10 s  6 103 s  n
2 4 2
Appl. Sci. 2023, 13, 1744 13 of 23

Table 2. Parameters of variable multiplicity interleaving bidirectional DC/DC converter.

Parameter Value
DC voltage VDC 30 V
Switching period TS 0.0001s (10 kHz)
Inductance L 3 mH
Inductance resistance R 0.1 
Load capacitance C 0.06 F
Initial voltage of load capacitor VC0 5V
Load current ILoad 6A
Maximum number of parallel channels N 6

The Bode diagram corresponds to Gid(s) when the working multiples are 4, 5, and 6
respectively, as shown in Figure 9. It can be seen from the figure that the shapes of the
Bode diagrams under different multiplicities are the same, so the transfer function of the
five multiplicities is selected as the research object, and the current compensation network
is designed.

60
n=4
Magnitude(dB)

50 n=5
n=6
40
30
20
10
90 n=4
45 n=5
Phase(deg)

n=6
0
-45
-90
10 102 Frequency(rad/s) 103 104

Figure 9. The Bode diagrams when the working number of the parallel multiplicity is 4, 5, or 6.

As can be seen from Figure 9, the amplitude‐frequency characteristic curve is rising

in the low‐frequency band, there is a large steady‐state error in the system. In the middle‐
frequency band, the crossover frequency is very high, and the system may be affected by
switching frequency, harmonics, parasitic oscillation, and so on, unable to work stably.
The high‐frequency band declines slowly, and the system is vulnerable to high‐frequency
noise [29].

4.2. The Design of the Current Compensation Network

Due to the output current of variable multiplicity interleaving bidirectional DC/DC
power converter being constant, the single current closed‐loop control can be adopted,
and the control strategy diagram is shown in Figure 10.
Appl. Sci. 2023, 13, 1744 14 of 23

I ref
n
S1 PWM1 Current controller 1

S2 PWM2 Current controller 2

S3 PWM3 Current controller 3

S4 PWM4 Current controller 4

S5 PWM5 Current controller 5

S6 PWM6 Current controller 6

iL6 L6

S6 S12 L5
iL5

S5 S11
iL4 L4

S4 S10
iL3 L3

S3 S9
iL2 L2

S2 S8
iL1 L1

S7 C
S1

Figure 10. Control strategy diagram of variable multiplicity interleaving bidirectional DC/DC
power converter.

When the converter is operating in Buck mode, and the number of working multi‐
plicities is 5, then the transfer function of the current‐loop‐controlled object can be shown
as.

6s
Gid  s   (32)
1.8 10 s  6 103 s  5
4 2

Through the analysis of the above Bode diagram, it can be seen that there are at least
two integral links in the compensation link so that the amplitude‐frequency characteristic
curve can decrease at the slope of −20 dB/dec in the low‐frequency band. In order to make
the system have a strong ability to suppress high‐frequency noise, the high‐frequency
band of the amplitude‐frequency characteristic curve should decrease at the slope of 40
dB/dec [29].
The transfer function of the current compensation network is:
K  s  Z1  s  Z2 
Gidc  s  
s 2  s  p 
(33)

The aim of introducing two integral links into the above formula is to make the am‐
plitude‐frequency characteristic curve decrease at the slope of −20 dB/dec in the low‐fre‐
quency band. Z1 and Z2 are introduced to offset the two conjugate poles in the origi‐
nal transfer function. The ωp can ensure that the corrected system has enough phase angle
margin, at the same time, the amplitude‐frequency characteristic curve can decrease at the
slope of −40 dB/dec in the high‐frequency band to suppress the high‐frequency noise [29].
The transfer function of the current compensation link is:
Appl. Sci. 2023, 13, 1744 15 of 23

3  106  1.8  104 s 2  6  103 s  5 

Gidc  s   (34)
s 2   s  4500 

The Bode diagram of the current compensation link is shown in Figure 11.

Magnitude(dB) 40
20
0
-20
-40
-60
0
Phase(deg)

-45
-90
-135
-180
10 102 103 104 105
Frequency(rad/s)
Figure 11. The Bode diagram of the current compensation link.

The open‐loop transfer function of the corrected system is shown as.

1.8  10 7
GA  s   Gid  s  Gidc  s   (35)
s  s  4500 

The open‐loop amplitude‐frequency characteristic curve of the corrected system is

shown in Figure 12. It can be seen from the figure that, after correction, the amplitude‐
frequency characteristic curve of the corrected system decreases at the slope of 20 dB/dec
in the low‐frequency band, and the steady‐state error of the system is zero; The phase
angle margin in the middle‐frequency band is 54.2°, which meets the stability require‐
ment. The crossing frequency is 3.24  103 rad/s ( fc  515.7Hz ). The amplitude‐frequency
characteristic curve of the corrected system decreases at the slope of −40 dB/dec in the
high‐frequency band, and the system has a good ability to suppress the high‐frequency
noise. To sum up, the corrected system meets the design requirements.

40
20
Magnitude(dB)

0
-20
-40
-60
-90
Phase(deg)

-120 (3240,-125.8)

-150

-180 2
10 103 Frequency(rad/s) 104 105

Figure 12. The Bode diagram of the corrected system.

Appl. Sci. 2023, 13, 1744 16 of 23

4.3. The simulation of the Variable Multiplicity Interleaving Bidirectional DC/DC Power
Converter
Based on the analysis of the previous chapters, the simulation model is built, and
then the parameters in Table 2 are brought into the model. The simulation model is oper‐
ated to extract the current ripples of different parallel numbers when the duty cycle is
0.25, 0.33, 0.40, and 0.5, which are shown in Figures 13–16 (In each Figure, a is the current
ripples in four parallel multiplicities; b is the current ripples in five parallel multiplicities;
c is the current ripples in six parallel multiplicities.). Figure 13 shows the output current
ripples when the duty cycle is 0.25, and the current ripple is the smallest when the parallel
number is four; Figure 14 shows the output current ripples when the duty cycle is 0.33,
and the current ripple is the smallest when the parallel number is six; Figure 15 shows the
output current ripples when the duty cycle is 0.4, and the current ripple is the smallest
when the parallel number is five; Figure 16 shows the output current ripples when the
duty cycle is 0.50, and the current ripple is the smallest when the parallel number is six.
The above simulation results are consistent with the conclusion in Table 1, which is ob‐
tained from the previous analysis, this is when the duty cycle is different, the number of
parallel multiplicities with the smallest current ripples is different, and so the DC/DC con‐
verter needs to flexibly choose to turn on or turn off some parallel branches according to
the current ripple optimization law.

6.30
6.15
6.00
5.85
5.700.2490 0.2495 0.2500 0.2505 0.2510
(a)
Load current(A)

6.30
6.15
6.00
5.85
5.700.2490 0.2495 0.2500 0.2505 0.2510
(b)
6.30
6.15
6.00
5.85
5.700.2490 0.2495 0.2500 0.2505 0.2510
(c)

Figure 13. Output current ripples of DC‐DC converter with 0.25 duty cycle under the 6A output
current. (a) The current ripples in four parallel multiplicities; (b) The current ripples in five parallel
multiplicities; (c) The current ripples in six parallel multiplicities.
Appl. Sci. 2023, 13, 1744 17 of 23

6.30
6.15
6.00
5.85
5.700.3290 0.3295 0.3300 0.3305 0.3310
(a)
Load current(A)
6.30
6.15
6.00
5.85
5.70
0.3290 0.3295 0.3300 0.3305 0.3310
(b)
6.30
6.15
6.00
5.85
5.70
0.3290 0.3295 0.3300 0.3305 0.3310
(c)
t(s)
Figure 14. Output current ripples of DC‐DC converter with 0.33 duty cycle under the 6A output
current. (a) The current ripples in four parallel multiplicities; (b) The current ripples in five parallel
multiplicities; (c) The current ripples in six parallel multiplicities.

6.30
6.15
6.00
5.85
5.700.3990 0.3995 0.4000 0.4005 0.4010
(a)
Load current(A)

6.30
6.15
6.00
5.85
5.700.3990 0.3995 0.4000 0.4005 0.4010
(b)
6.30
6.15
6.00
5.85
5.700.3990 0.3995 0.4000 0.4005 0.4010
(c)
t(s)
Figure 15. Output current ripples of DC‐DC converter with 0.40 duty cycle under the 6A output
current. (a) The current ripples in four parallel multiplicities; (b) The current ripples in five parallel
multiplicities; (c) The current ripples in six parallel multiplicities.
Appl. Sci. 2023, 13, 1744 18 of 23

6.30
6.15
6.00
5.85
5.700.4990 0.4995 0.5000 0.5005 0.5010
(a)
Load current(A)
6.30
6.15
6.00
5.85
5.700.4990 0.4995 0.5000 0.5005 0.5010
(b)
6.30
6.15
6.00
5.85
5.700.4990 0.4995 0.5000 0.5005 0.5010
(c)
t(s)
Figure 16. Output current ripples of DC‐DC converter with 0.50 duty cycle under the 6A output
current. (a) The current ripples in four parallel multiplicities; (b) The current ripples in five parallel
multiplicities; (c) The current ripples in six parallel multiplicities.

5. The Experiment and Results

5.1. Experimental Platform
The experimental platform is shown in Figure 17, it can be divided into a control
module, power module, output module, power supply, and programmable load. The
TMS320F28377 microcontroller is used to control the whole system, and the XC3S500E‐
PQ208 is used to generate the PWM signal with the specific phase shift angle. The PWM
signal is transmitted to the power module through the optical fiber. In the experiment, the
30 V bus voltage is generated by the DC stabilized power supply, the load capacitance C
is replaced by a programmable load, the switching frequency is set to 10 KHz, the value
of filter inductance is 3 mH, the output current is 6 A.

Oscilloscope
Power
supply

Programmable
load

Output module Control

Power module module
Figure 17. Experimental platform.

5.2. The Experimental Results of the Current Ripple Optimization in Variable Channel
Interleaving Bidirectional DC/DC Power Converter
The current ripples of the 6 A output current of the DC‐DC converter are shown in
Figure 18. Figure 18a‐l represents the current ripples which are corresponding to different
Appl. Sci. 2023, 13, 1744 19 of 23

multiplicities in parallel when the duty cycles are 0.25, 0.33, 0.4, and 0.5, respectively. As
can be seen in Figure 18a‐c, when the duty cycle is 0.25, the maximum current ripples are
80 mA, 100 mA, and 120 mA when the number of parallel multiplicities is 4, 5, and 6,
respectively. As can be seen in Figure 18d‐f, when the duty cycle is 0.33, the maximum
current ripples are 160 mA, 145 mA, and 65 mA, when the number of parallel multiplici‐
ties is 4, 5, and 6, respectively. As can be seen in Figure 18g‐y, when the duty cycle is 0.4,
the maximum current ripples are 200 mA, 90 mA, and 100 mA, when the number of par‐
allel multiplicities is 4, 5, and 6, respectively. As can be seen in Figure 18j‐l, when the
duty cycle is 0.5, the maximum current ripples are 130 mA, 140 mA, and 120 mA when
the number of parallel multiplicities is 4, 5, and 6, respectively.
All optimization results of current ripples under different duty cycles and parallel
multiplicities in Figure 18 are identical to not only the simulation results above but also
the analytical results in Table 1, which demonstrate that the optimization method pro‐
posed in this paper is precise and practical.

iLoad(100mA/div) iLoad(100mA/div) iLoad(100mA/div)

PWM(20V/div) PWM(20V/div) PWM(20V/div)

N=4 Duty ratio=0.25 N=5 Duty ratio=0.25 N=

N=6 Duty ratio=0.25
Duty
6 ratio=0.2
(a) (b) (c)
iLoad(100mA/div) iLoad(100mA/div)
iLoad(100mA/div)

PWM(20V/div) PWM(20V/div) PWM(20V/div)

N=4 Duty ratio=0.33 N=5 Duty ratio=0.33 N=6 Duty ratio=0.33

(d) (e) (f)

iLoad(100mA/div) iLoad(100mA/div) iLoad(100mA/div)

PWM(20V/div) PWM(20V/div) PWM(20V/div)

N=4 Duty ratio=0.4 N=5 Duty ratio=0.4 N=6 Duty ratio=0.4

(g) (h) (y)

iLoad(100mA/div) iLoad(100mA/div) iLoad(100mA/div)

PWM(20V/div) PWM(20V/div) PWM(20V/div)

N=4 Duty ratio=0.5 N=5 Duty ratio=0.5 N=6 Duty ratio=0.5

(j) (k) (l)

Figure 18. Output current ripples of DC‐DC converter with different duty cycles under the same
output current. (a‐c) The current ripples of different parallel multiplicities when the duty cycle is
0.25; (d‐f) The current ripples of different parallel multiplicities when the duty cycle is 0.33; (g‐y)
Appl. Sci. 2023, 13, 1744 20 of 23

The current ripples of different parallel multiplicities when the duty cycle is 0.4; (j‐l) The current
ripples of different parallel multiplicities when the duty cycle is 0.5.

The three pictures of the same line in Figure 18 clearly show the size of the current
ripple under a different number of parallel channels with the same duty cycle. By extract‐
ing the data in Figure 18, Table 3 can be obtained. Compared with Figure 18, Table 3 is
more intuitive and convincing in numerical representation. Table 3 intuitively illustrates
the number of parallel branches that should be taken to minimize the current ripple under
experimental conditions.

Table 3. Output current ripples of DC‐DC converter with different duty cycles under the same out‐
put current.

The Maximum Current Ripple of the Number

The Number of Parallel
Duty Cycles of N Multiple Parallel Channels/mA
Channels to Be Used
N=4 N=5 N=6
0.25 80 100 120 4
0.33 160 145 65 6
0.40 200 90 100 5
0.50 130 140 120 6

In order to simplify the analysis process, only the current ripples corresponding to
duty cycles 0.25 and 0.5 are adopted. Figure 19a‐f shows the current ripples of the first
three channels when the parallel multiplicity is 4, 5, and 6. It can be seen that the larger
the duty cycle, the longer the rise time and the shorter the fall time, the peak value of the
ripple peak of a single brand is also increasing, and the total output current ripple is com‐
posed of multiple brand parallel outputs, so the total output current ripple cannot be
judged only by the size of a single brand current ripple. The current of each channel is not
completely coincident, mainly due to the measurement error of the sensor. Even if the
current sharing control method is taken, the current imbalance caused by the inconsistent
parameters of each channel cannot be fully compensated.
Appl. Sci. 2023, 13, 1744 21 of 23

iL1 iL3 iL1 iL3

iL2 iL2
PWM(20V/div) PWM(20V/div)

N=4 Duty ratio=0.25 N=4 Duty ratio=0.5

(a) (b)
iL1 iL3 iL1 iL3

iL2 iL2 PWM(20V/div)

PWM(20V/div)

N=5 Duty ratio=0.25 N=5 Duty ratio=0.5

(c) (d)
iL1 iL3 iL1 iL3

iL2
PWM(20V/div) iL2 PWM(20V/div)

N=6 Duty ratio=0.25 N=6 Duty ratio=0.5

(e) (f)

Figure 19. Current ripples of the first three channels under partial duty cycle when the parallel mul‐
tiplicity is 4, 5, and 6. (a,c,e) The current ripples of the first three channels with the duty cycle of 0.25
when the parallel multiplicity is 4, 5, and 6; (b,d,f) The current ripples of the first three channels
with the duty cycle of 0.5 when the parallel multiplicity is 4, 5, and 6.

6. Conclusions
The main contribution of this paper is to propose a variable multiplicity control
method of multiple interleaving bidirectional DC/DC power converters to optimize the
current ripple, that is, dynamically adjust the number of parallel multiplicities in the ac‐
tual operation of the circuit according to the duty cycles, so that the output current ripple
is as small as possible. First, the relationship between the current ripple and the number
of parallel multiplicities and the duty cycle is analyzed and deduced and the switching
logic that can generate the minimum current ripple is designed. Second, the average value
model and the AC small signal model of variable multiplicity interleaving bidirectional
DC/DC power converter are established, and the transfer function of the system is ob‐
tained. Third, according to the transfer function of the system, the control system of the
converter is designed. Simulation and experimental results show that the control method
proposed in this paper can effectively further reduce the current ripple of the traditional
multiple DC/DC converter, and to a certain, reduce the switching loss caused by a blind
increase of switching frequency to optimize current ripple, so it is of great significance.
All in all, the current ripple optimization algorithm proposed in this paper is suitable for
occasions that require low current ripple, such as battery energy storage systems, electric
vehicles, etc. However, due to multiple interleaving DC/DC converters using more paral‐
lel branches, the cost is relatively high. Further research on improving reliability and re‐
ducing costs is needed in the future.
Appl. Sci. 2023, 13, 1744 22 of 23

Author Contributions: Conceptualization, J.D. and S.W.; methodology, S.F.; validation, Y.X.; formal
analysis, K.Z. and L.S.; writing—original draft preparation, J.D., S.W. and Y.X.; writing—review and
editing, J.D., S.W. and Y.X. All authors have read and agreed to the published version of the manu‐
script.
Funding: This research was funded by the National Natural Science Foundation of China, grant
number 52177211, and by the Heilongjiang postdoctoral research starting fund, grant number LBH‐
Q20020.
Institutional Review Board Statement: Not applicable.
Informed Consent Statement: Not applicable.
Data Availability Statement: Not applicable.
Conflicts of Interest: The authors declare no conflict of interest.

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