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Full Introduction of QuickLogic EclipsePlus FPGA Family

The current technology enables the world to be more connected than ever before. Therefore, specialized
devices will become more critical as the world becomes more interconnected. In addition, we need tools that
are easier to use and cost-effective. QuickLogic specializes in developing advanced logic devices for
cutting-edge technology at an affordable price.

QuickLogic is proud to introduce the EclipsePlus family of products. It is a new range of logic device
families for cutting-edge FPGA-based designs. They offer significant performance improvements over
previous generations of technology. In addition, they have minimal increases in silicon area
and power requirements.

The EclipsePlus family of products includes the EclipsePlus H8. It is a low-power 8-bit processor core with
a 16-bit instruction word width and the 45nm EclipsePlus UV1. Additionally, it is a high-performance
1GHz+ ultra-low-power 45nm 8-bit processor core with a 16-bit instruction word width. The EclipsePlus
family also includes an extensive range of peripheral IP blocks. In addition, it contains peripherals
commonly found in ASICs such as ADCs, DACs, PLLs, and timers that we can mix and match to meet your
needs.

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Table of Contents

History of the EclipsePlus family

The EclipsePlus family of devices has roots in the original Eclipse family of products developed by
QuickLogic. The Eclipse family was initially a low-cost, low-power, high-performance 8-bit processor for
general applications. They developed it originally for use in QuickLogic’s flagship ULE cores. However, it
quickly became popular with other third-party manufacturers such as Rayming PCB & Assembly. As a result,
they also included it in their design platforms, making it one of the most widely used 8-bit cores available
today.

The next iteration of the Eclipse family emerged when QuickLogic began to look at
ultra-low-power electronic device applications. Specifically, applications that required approximately 1mW
and a 0.1V power supply. QuickLogic created a new generation of Eclipse devices based on the EclipsePlus
architecture to meet these requirements. However, it has a much more aggressive power reduction
methodology. Again, the goal was to fuse out the design rules for everything necessary for each specific
product and make it ultra-low power.

To achieve this, QuickLogic had to make several changes from the previous versions of the Eclipse family.
The most obvious modification was reducing the operating voltage from 2V down to 0.8V, reducing 33
percent in voltage. Also, to achieve the same performance as previous versions, QuickLogic had to increase
the logic gates and reduce the number of registers. The result of these changes is a new ultra-low power. It

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was also a low-cost processor core with a low-cost FPGA supporting an impressive performance/power ratio.
This is ideal for ultra-large area FPGAs. [Taken from QuickLogic product brochure]

The introduction of the EclipsePlus family represented a significant improvement over the prior generation.
It was ideally suited for high-performance applications that required high density (such as large-area FPGAs)
and ultra-low power applications that needed to consume less than 1mW.

The latest innovation of the EclipsePlus family

The introduction of the EclipsePlus family was an important stage in the evolution of QuickLogic products.
Still, recent technology advancements and increased demand for high-performance devices forced
QuickLogic to design a new generation of Eclipse products. The result is a new family called the EclipsePlus
H8, a low-power 8-bit processor core with a 16-bit instruction word width. Its artful design can keep pace
with Moore’s Law and take advantage of newer 45nm process technologies.

The EclipsePlus H8 implements some significant improvements over existing 8-bit cores that have been
around since the 80s. For example, the decreased gate count, register complement, and power consumption.
In addition, the EclipsePlus H8 features a 16-bit instruction word width, and the core can have from 32 to
128 registers. A special feature of the EclipsePlus H8 is that it supports register stacking. This allows access
to multiple registers with a single instruction. In addition, the EclipsePlus H8 provides up to 1K memory
locations for local variables stack and DSP math operations.

The EclipsePlus H8 has been suitable for use in both FPGAs and ASICs. However, both architectures
require different sets of standards and specifications. QuickLogic developed a special design methodology to
meet these requirements. It allows for implementing the EclipsePlus H8 in FPGAs and ASICs. In addition,
this new methodology will enable designers to modify their designs from one architecture to the other easily.
They will not need to rewrite the core logic or retest at a higher integration level.

The EclipsePlus H8 consists of an efficient logic design method called Logic Compaction. It came with the
first generation of Eclipse products. This provided designers with a high-density design method for
implementing 8-bit applications in the ULE FPGA2.

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Benefits of the EclipsePlus family

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QuickLogic EclipsePlus

1. High performance

The EclipsePlus H8 core offers device manufacturers the ability to create high-performance, high-density
FPGAs and ASICs that meet their customers increasing demand for larger quantities of more powerful
devices. In addition, the EclipsePlus H8 provides designers with a cost-effective solution that they can use to
implement not only high-level applications but also low-level embedded functions such as ultra low power
monitoring and control devices.

2. Low power operation

The EclipsePlus UV1 core offers similar benefits to device manufacturers as the EclipsePlus H8 core. Still,
instead of being used for high-performance applications, it has been designed for ultra-low power
applications. It requires a maximum operating voltage of 0.6V.

3. EclipsePlus Design Methodology

The EclipsePlus design methodology offers device manufacturers a cost-effective solution for implementing
high-performance, high-density FPGAs and ASICs at a fraction of the cost of other top-down methodologies.
The EclipsePlus design methodology depends on a combination of super structured programming, logic
compaction, and register stacking. It is programmable in VHDL, Verilog, and C, allowing designers to
quickly and easily implement their designs in FPGAs and ASICs.

The devices that comprise the latest Eclipse family devices are below.

 QL7180-7PS484C
 The QL7180-6PS484C
 QL7180-4PS484I
 The QL7120-T6PS484C
 QL7120-6PQ208C
 The QL7120-4PQ208C

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 QL7100-6PQ208
 The QL7100-4PQ208I

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Standard features for the EclipsePlus family

1. Embedded Computational Units

All members of the EclipsePlus family, except for the EclipsePlus UV1 core, offer embedded computational
units (ECU) that can help implement various embedded functions. For example, ECUs provide integrated
signal processing, DSP, and DMA functions. In addition, the ECUs include an on-chip memory that we can
configure as a programmable memory bank.

2. Embedded Instruction Decoders (ED)

All members of the EclipsePlus family support embedded instruction decoders (ED). It helps reduce the size
requirements of embedded applications. In addition, EDs accelerate high-speed execution in all significant
microprocessors by allowing instructions to be fetched efficiently from off-chip memories. Thereby, it
reduces the performance penalty caused by bringing instructions from on-integrated memories such as
SRAM.

3. Advanced Clock Network

All members of the EclipsePlus family support a flexible clock network that we can configure to meet
designers’ requirements. The clock network supports a FIFO-based counter, jitter, and input/output buffers.
The clock network can also be helpful for direct interface with off-chip memories or peripheral devices.

key features include:

a) Four phase-locked loops: We use these to control peripherals such as external memory interfaces, serial
ports, analog to digital converters, and counters. One is used to control the internal oscillator. The other three
can be helpful for 3 different clock frequencies.

b) 16 I/O controls: These control the internal multiplexers and registers. Additionally, they control the
interconnecting signals between the various units.

c) 20 quad-net networks: We use these to interconnect the various units. Generally, these contain either a
FIFO or a counter to control data transfer between the CPU and other components.

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d) Nine global clock networks: We use these to control the K, L, and M network, memory refresh, and
special features such as the serial interface. One of the clocks is dedicated, while the others are available for
higher-speed connections.

4. Programmable I/O

The members of the EclipsePlus family offer programmable input/output (I/O) units that provide designers
with a flexible and cost-effective method for implementing custom I/O peripheral functions. The I/O unit
consists of three outputs and two programmable FIFOs. The on-chip voltage regulator can control power
dissipation.

Key features include:

a) High-performance enhanced I/O: These offer designers the ability to implement a wide range of I/O
functions in low-power, high-performance packages. A single VDD line and two programmable
sub-registers are helpful for control. We can configure each one independently to select any I/O port.

b) Programmable slew rate control: We can configure the slew rate to support AC or DC I/O connections.

c) On-chip voltage regulator: The regulator allows designers to power the I/O multiplexer and registers
from 1.0 volt to 3.3 volts.

d) Three register configurations: These three programmable sub-registers can be configured to control the
operation of the I/O. The first two are programmable independently, while we can configure the third as an
output or input.

e) Eight independent I/O banks: Each programmable sub-register can control up to 8 I/O banks.

f) SSTL3, SSTL2, GTL+, PCI, LVCMOS, and LVTTL: The EclipsePlus family offers a wide selection of
I/O standards. The LVCMOS, GTL+, SSTL2, and SSTL3 are available on the EclipsePlus UV1 core.

5. Embedded Dual-Port SRAM

The members of the EclipsePlus family offer embedded dual-port SRAMs that we can use to implement a
wide range of memory applications. The dual-port SRAM consists of two banks, each of which has an
independent address bus, a data bus, and input/output pins. The memory operates at speeds up to 167Mhz
and has an on-chip voltage regulator that allows powering from 1.0 volt to 3.3 volts.

Key features include:

1) Configurable and cascadable: The memory configuration is programmable and cascadable. High-speed
RAMs are supported, allowing users to configure up to 8MB of DRAM.

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2) FIFO/ROM/ RAM wizard for automatic configuration: The EclipsePlus family of tools includes a
RAM/ROM/FIFO wizard that automatically allows users to perform complex configuration tasks.

3) 82,900 RAM bits: Each one of the RAM banks has access to up to 82,900 bits. This is sufficient for up to
eight banks of DRAM or up to 82,900 bits of ROM.

4) High-performance SRAM blocks: The number of SRAM bits available depends on the configuration. Bit
sizes from 32 to 2,304 bits are supported.

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6. Flexible Programmable Logic

The members of the EclipsePlus family offer programmable logic (PL) blocks we can use to implement a
wide range of digital-specific functions. The PL blocks are based on standard low-power SRAMs and
provide power dissipation from 1.0 volt to 3.3 volts.

EclipsePlus is used for programmable logic interfaces, enabling designers to implement custom electrical
interfaces in a low-cost and high-performance package. Programmable interconnections between the external
PL blocks represent a reduction in on-chip die area, and we can use it for custom timing cycles, control loops,
and peripheral logic. Programmable input/output (I/O) is also available.

The programmable interconnections between the two PL blocks can implement numerous clock-based
control loops, including clock recovery, filtering, equalization, and interconnecting signals. The
interconnections also allow for data transfer between the two blocks. In addition to internal programmable
logic, the EclipsePlus features lightning-fast response using on-chip FIFOs (and the lower power
requirements of FIFO designs) as well as on-chip input/output buffers.

Key features include:

a) 347 I/O pins: Each PL has more than 350 I/O pins, allowing designers to create a wide range of devices.
The number of I/O pins depends on the PL configuration and the RAM used for programmable logic.

b) 583,008 system gates: Each PL has a programmable gate configuration that we can use for standard logic
functions, custom circuits, or logic blocks. The number of gates depends on the PL configuration.

c) 4,032 logic cells: Each PL can be a programmable logic cell configuration. The number of cells depends
on the PL configuration.

d) 2.5 V VCC capable I/O: The I/O pins are capable of operating at either 2.5 volts or 3.3 volts, allowing
them to interface with a wide variety of devices.

e) 0.25 µm five-layer metal CMOS process: The EclipsePlus can take full advantage of the superior
performance of a five-layer metal CMOS process. As a result, the power dissipation is less than 45 mW at
167 MHz and can be reduced to 35 mW if needed.

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f) Multi-path programming support: Designers can program different blocks based on the application
requirements.

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EclipsePlus family software development platforms

The EclipsePlus family includes several different software development platforms that support the complete
range of member parts.

1. Third party

Third-party developers can customize any member of the EclipsePlus family. They can either develop their
device drivers or software packages with the EclipsePlus.

The EclipsePlus is licensed to third parties as a complete package, providing a wide range of programmable
logic functions, memory, and I/O interconnections. In addition, EclipsePlus’s features and a large number of
configurable I/O pins make it an ideal platform for developing custom logic blocks.

The EclipsePlus hardware is also available to third parties as a supply source for customization and assembly
of their own custom devices. This cost-effective solution allows loose coupling of the EclipsePlus design to
unique needs.

2. Embedded designers

Software developers can use EclipsePlus features to develop their custom software components. The
EclipsePlus provides a platform for developing custom digital-specific applications and reduces the cost of
developing custom digital-specific products compared to FPGA devices. In addition, developers can
translate their software into the appropriate PL configuration and create an EclipsePlus device using the
EclipsePlus hardware with minimal changes to the developer’s code.

This is possible with all members of the EclipsePlus family, providing an open platform that allows
third-party developers to customize programmable logic in a low-cost, high-performance package.

EclipsePlus programming environment

The EclipsePlus can develop custom logic elements rapidly using a familiar set of tools. After developers
have created their software, a full range of options is available to configure their customized EclipsePluss. In
addition to configuring internal programmable logic, external I/O level can be helpful, and the on-chip
FIFO/ROM/RAM wizard can configure the configuration easily.

3. Designers with existing code

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Developers can customize an existing design for use with an EclipsePluss. For example, they can create an
EclipsePlus configuration to match the device they are developing or program their new customized device
directly from their existing code.

The EclipsePlus is a family of products based on the same design. However, the devices differ in hardware
configuration and features. The table below summarizes the features of all three current members of the
family:

The EclipsePlus family has two significant sub-families: 1) a low-cost, high-performance PL solution
designed for custom logic applications, and 2) an advanced PL solution designed to help design
cost-effective FPGA digital specific components, supporting external memory and I/O interconnections, as
well as fast clock recovery.

The EclipsePlus family of products is available through a wide range of distributors and directly from
Quicklogic.

Quicklogic provides a fully digital design environment to support the EclipsePlus. In addition, the software
development tools make digital design easier, faster, and more cost-effective by providing a standard set of
tools. These tools include:

EclipsePlus designers can implement a wide range of devices with the same design flow for FPGAs,
including custom logic blocks or custom digital-specific components such as VCOs, PLLs, SerDes elements,
and complex components data converters.

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4. Free, open-source software

The EclipsePlus design is available as free, open-source software. The EclipsePlus design file is available on
the Quicklogic website. The source code files are also included in the distribution of the EclipsePlus design
and provide a complete description of its architecture.

Quicklogic also publishes an EclipsePlus project on Github, providing a full description of each member part
and its associated sources. FPGAs are widely used for complex digital applications such as
high-performance image processing and video processing because they provide a wide range of
programmable functions with low power consumption.

The EclipsePlus devices can meet the needs needed for design engineers, allowing them to implement very
large systems at a low cost with high-performance capabilities.

Quicklogic is the only company that can offer a complete solution using an open-source design, software,
and hardware.

The EclipsePlus Family is an open-source design that allows developers to customize a wide range of
programmable logic elements and use them in FPGA design. The EclipsePlus devices depend on the same
design used to manufacture the highly successful members of the Quicklogic family, providing advanced PL

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capabilities without the significant cost increase of development tools. In addition, the EclipsePlus can allow
rapid implementation of custom digital-specific components at low cost and low power consumption by
designers already familiar with FPGA designs for custom digital applications.

Installation

To install, first start the installation application:

1. Check the size of the EclipsePlus by clicking on the “Get File” button. This will download a file used to
create a configuration file.

2. Open the “Eclipse-Plus-Firmware-[version]-BINARY-EN” (e.g.,

Eclipse-Plus-Firmware-1.2.2-BINARY-EN). If this is a .vhd file, copy it to a directory on your computer,
then extract it using VC++ or some other C++ compiler generating tool.

3. Copy the “Eclipse-Plus-Firmware-1.2.2-BINARY-EN” file to the directory where you install your
EclipsePlus, and rename it to “eclipseplus.hex”.

4. Open Upc_LcdxDriver_Win32 (EclipsePlus Projects) and select “run” from the top menu. The driver
should then install automatically, displaying some messages about start-up and performing some initial
configuration in your computer’s operating system for you.

5. If the driver does not install automatically, click “install” on the first screen of the driver, it will then run,
and you must restart it whenever you want to open an EclipsePlus project.

6. Return to your EclipsePlus project directory and click on “open project” on the Upc_Lcd driver
application that you see running on your computer’s desktop (or from a shortcut icon), giving an appropriate
name in the open file dialogue box.

7. Your EclipsePlus should then start showing a blank screen for about two seconds before displaying
whatever program you have written using the EclipsePlus controller (a typical program would require
programming of various logic elements).

8. Close the Upc_Lcdx driver.

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Usage

Developers can quickly and easily implement all the features of EclipsePlus digital designs, including all
functions, inputs, and outputs of the design that are necessary for design engineers. The integration with an
existing design using their existing code is also easily accomplished. Furthermore, many of the device
settings are automatic, based on the model number of your device. The EclipsePlus uses a configuration file
to determine basic settings such as clock frequency or power consumption which can be adjusted later if

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needed. Once the device is ready, you can download the controller application (which generates a lot of
unnecessary code for no purpose) and use it with your system.

Suppose you have not already created a configuration file. In that case, you can create a copy of the generic
configuration provided with the EclipsePlus design by clicking “Save as” in the “Save…” menu or by
copying and pasting its contents into any file. This will set up all elements required to link your design using
Device Manager in Eclipse. The configuration file contains all necessary settings during integration,
including:

The programming model used is VHDL (a hardware description language). Using VHDL to program digital
designs is the standard method in the industry and greatly simplifies the design flow.

Users then create a concrete VHDL file that describes all of the inputs and outputs of their system. This
user-written VHDL part effectively replaces the “hardware description” part typically generated by FPGA
tools. Next, we compile the resulting Once compiled. Finally, we execute the bitstream is held in memory
and by the FPGA. Once the user has made some modifications to their design, they can then convert it back
into a standard VHDL file that can configure the device with any FPGA tool.

Cost

The EclipsePlus design had low cost in mind. The design can operate on various FPGA devices using the
same VHDL code. There are many different FPGA devices in widespread use, and the typical specifications
of each device may be easily determined by looking them up in three sources:

A common distinction between FPGAs is their architecture. The EclipsePlus devices use an “abstract”
architecture, allowing for much easier implementation on a wide variety of FPGAs that do not use the same
layout.

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Board Layout

The EclipsePlus can use a compact board layout and the fewest switches necessary. The framework
can reduce unnecessary routing by providing a common framework for all the included functions,
reinforcing the design philosophy. In addition, any unused components can be removed from their place on
the board, leaving room for other items in a custom design. We implement the second iteration of each
design on another bare circuit board (with the same basic dimensions) that uses the same wiring scheme as
the main substrate but includes no extra parts.

This is useful if you use an existing board and do not want to move any significant components.

Conclusion

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In conclusion, the EclipsePlus family can provide user-defined solutions for embedded applications. This
supports advanced features such as programmable I/O, memory, SCSI, and serial ports. It is robust hardware
that offers excellent performance. In addition, eclipsePlus family hardware is well-documented and free of
patents.

The EclipsePlus core is the starting point for the entire design flow and is easy to use.

It can also be a stand-alone starting point and provides high performance and flexibility. The EclipsePlus
core supports various peripherals such as I/O, memory, serial ports, and SCSI. In addition, a complete
EclipsePlus board is available that supports these peripherals.

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4. Where does the QuickLogic Eclipse FPGA Architecture Family play a role?

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