Fpga Wikipedia

An Altera Stratix IV GX FPGA
An example of a Xilinx Spartan 6 FPGA

programming/evaluation board
Field-programmable gate array
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A Field-programmable Gate Array
(FPGA) is an integrated circuit designed
to be congured by the customer or
designer after manufacturinghence
"eld-programmable". The FPGA
conguration is generally specied
using a hardware description language
(HDL), similar to that used for an
application-specic integrated circuit
(ASIC) (circuit diagrams were previously
used to specify the conguration, as
they were for ASICs, but this is
increasingly rare). FPGAs can be used to
implement any logical function that an
ASIC could perform. The ability to
update the functionality after shipping,
partial re-conguration of the portion of
the design
[1]
and the low non-recurring
engineering costs relative to an ASIC
design (notwithstanding the generally
higher unit cost), offer advantages for
many applications.
[2]
FPGAs contain programmable logic
components called "logic blocks", and a
hierarchy of recongurable
interconnects that allow the blocks to be
"wired together"somewhat like many (changeable) logic gates that can be
inter-wired in (many) dierent congurations. Logic blocks can be congured to
perform complex combinational functions, or merely simple logic gates like AND
and XOR. In most FPGAs, the logic blocks also include memory elements, which
may be simple ip-ops or more complete blocks of memory.
[2]
In addition to digital functions, some FPGAs have analog features. The most
common analog feature is programmable slew rate and drive strength on each
output pin, allowing the engineer to set slow rates on lightly loaded pins that
would otherwise ring unacceptably, and to set stronger, faster rates on heavily
loaded pins on high-speed channels that would otherwise run too slow.
[3][4]
Another relatively common analog feature is differential comparators on input
pins designed to be connected to differential signaling channels. A few "mixed
Field-programmable gate array - Wikipedia, the fre... http://en.wikipedia.org/wiki/Fpga
1 of 16 Tuesday 23 August 2011 02:56 PM
signal FPGAs" have integrated peripheral Analog-to-Digital Converters (ADCs)
and Digital-to-Analog Converters (DACs) with analog signal conditioning blocks
allowing them to operate as a system-on-a-chip.
[5]
Such devices blur the line
between an FPGA, which carries digital ones and zeros on its internal
programmable interconnect fabric, and field-programmable analog array (FPAA),
which carries analog values on its internal programmable interconnect fabric.
Contents
1 History
1.1 Modern developments
1.2 Gates
1.3 Market size
1.4 FPGA design starts
2 FPGA comparisons
2.1 Versus complex programmable logic devices
2.2 Security considerations
3 Applications
4 Architecture
5 FPGA design and programming
6 Basic process technology types
7 Major manufacturers
8 See also
9 References
10 Further reading
11 External links
History
The FPGA industry sprouted from programmable read-only memory (PROM) and
programmable logic devices (PLDs). PROMs and PLDs both had the option of
being programmed in batches in a factory or in the field (field programmable),
however programmable logic was hard-wired between logic gates.
[6]
In the late 1980s the Naval Surface Warfare Department funded an experiment
proposed by Steve Casselman to develop a computer that would implement
600,000 reprogrammable gates. Casselman was successful and a patent related
to the system was issued in 1992.
[6]
Some of the industrys foundational concepts and technologies for programmable
logic arrays, gates, and logic blocks are founded in patents awarded to David W.
Page and LuVerne R. Peterson in 1985.
[7][8]
Xilinx Co-Founders, Ross Freeman and Bernard Vonderschmitt, invented the rst
commercially viable eld programmable gate array in 1985 the XC2064.
[9]
The
XC2064 had programmable gates and programmable interconnects between
gates, the beginnings of a new technology and market.
[10]
The XC2064 boasted a
mere 64 configurable logic blocks (CLBs), with two 3-input lookup tables
(LUTs).
[11]
More than 20 years later, Freeman was entered into the National
Inventors Hall of Fame for his invention.
[12]
Xilinx continued unchallenged and quickly growing from 1985 to the mid-1990s,
when competitors sprouted up, eroding significant market-share. By 1993, Actel
was serving about 18 percent of the market.
[10]
The 1990s were an explosive period of time for FPGAs, both in sophistication and
the volume of production. In the early 1990s, FPGAs were primarily used in
telecommunications and networking. By the end of the decade, FPGAs found
their way into consumer, automotive, and industrial applications.
[13]
FPGAs got a glimpse of fame in 1997, when Adrian Thompson, a researcher
working at the University of Sussex, merged genetic algorithm technology and
FPGAs to create a sound recognition device. Thomsons algorithm congured an
array of 10 x 10 cells in a Xilinx FPGA chip to discriminate between two tones,
utilising analogue features of the digital chip. The application of genetic
algorithms to the conguration of devices like FPGAs is now referred to as
Evolvable hardware
[6][14]
Modern developments
A recent trend has been to take the coarse-grained architectural approach a step
further by combining the logic blocks and interconnects of traditional FPGAs
with embedded microprocessors and related peripherals to form a complete
"system on a programmable chip". This work mirrors the architecture by Ron
Perlof and Hana Potash of Burroughs Advanced Systems Group which combined
a reconfigurable CPU architecture on a single chip called the SB24. That work
was done in 1982. Examples of such hybrid technologies can be found in the
Xilinx Virtex-II PRO and Virtex-4 devices, which include one or more PowerPC
processors embedded within the FPGA's logic fabric. The Atmel FPSLIC is
another such device, which uses an AVR processor in combination with Atmel's
programmable logic architecture. The Actel SmartFusion devices incorporate an
ARM architecture Cortex-M3 hard processor core (with up to 512kB of flash and
64kB of RAM) and analog peripherals such as a multi-channel ADC and DACs to
their flash-based FPGA fabric.
In 2010, an extensible processing platform was introduced for FPGAs that fused
features of an ARM high-end microcontroller (hard-core implementations of a
32-bit processor, memory, and I/O) with an FPGA fabric to make FPGAs easier
for embedded designers to use. By incorporating the ARM processor-based
platform into a 28 nm FPGA family, the extensible processing platform enables
system architects and embedded software developers to apply a combination of
serial and parallel processing to address the challenges they face in designing
today's embedded systems, which must meet ever-growing demands to perform
highly complex functions. By allowing them to design in a familiar ARM
environment, embedded designers can benefit from the time-to-market
advantages of an FPGA platform compared to more traditional design cycles
associated with ASICs.
[15][16][17][18][19]
An alternate approach to using hard-macro processors is to make use of soft
processor cores that are implemented within the FPGA logic.
As previously mentioned, many modern FPGAs have the ability to be
reprogrammed at "run time," and this is leading to the idea of recongurable
computing or recongurable systems CPUs that recongure themselves to suit
the task at hand. The Mitrion Virtual Processor from Mitrionics is an example of
a recongurable soft processor, implemented on FPGAs. However, it does not
support dynamic reconguration at runtime, but instead adapts itself to a
specic program.
Additionally, new, non-FPGA architectures are beginning to emerge. Software-
configurable microprocessors such as the Stretch S5000 adopt a hybrid
approach by providing an array of processor cores and FPGA-like programmable
cores on the same chip.
Gates
1987: 9,000 gates, Xilinx
[10]
1992: 600,000, Naval Surface Warfare Department
[6]
Early 2000s: Millions
[13]
Market size
1985: First commercial FPGA technology invented by Xilinx
[10]
1987: $14 million
[10]
~1993: >$385 million
[10]
2005: $1.9 billion
[20]
2010 estimates: $2.75 billion
[20]
An Altera Cyclone II FPGA, on an Altera
teraSIC DE1 Prototyping board.
FPGA design starts
10,000
[21]
2005: 80,000
[22]
2008: 90,000
[23]
FPGA comparisons
Historically, FPGAs have been slower, less energy efficient and generally
achieved less functionality than their fixed ASIC counterparts. A study has
shown that designs implemented on FPGAs need on average 18 times as much
area, draw 7 times as much dynamic power, and are 3 times slower than the
corresponding ASIC implementations.
[24]
Advantages include the ability to
re-program in the field to fix bugs, and
may include a shorter time to market
and lower non-recurring engineering
costs.
[citation needed]
Vendors can also
take a middle road by developing their
hardware on ordinary FPGAs, but
manufacture their final version so it can
no longer be modified after the design
has been committed.
Xilinx claims that several market and
technology dynamics are changing the
ASIC/FPGA paradigm:
[25]
Integrated circuit costs are
rising aggressively
ASIC complexity has lengthened
development time
R&D resources and headcount
are decreasing
Revenue losses for slow time-to-market are increasing
Financial constraints in a poor economy are driving low-cost
technologies
These trends make FPGAs a better alternative than ASICs for a larger number of
higher-volume applications than they have been historically used for, to which
the company attributes the growing number of FPGA design starts (see
History).
[25]
Some FPGAs have the capability of partial re-configuration that lets one portion
of the device be re-programmed while other portions continue running.
Versus complex programmable logic devices
The primary differences between CPLDs (Complex Programmable Logic Devices)
and FPGAs are architectural. A CPLD has a somewhat restrictive structure
consisting of one or more programmable sum-of-products logic arrays feeding a
relatively small number of clocked registers. The result of this is less flexibility,
with the advantage of more predictable timing delays and a higher logic-
to-interconnect ratio. The FPGA architectures, on the other hand, are dominated
by interconnect. This makes them far more flexible (in terms of the range of
designs that are practical for implementation within them) but also far more
complex to design for.
Another notable difference between CPLDs and FPGAs is the presence in most
FPGAs of higher-level embedded functions (such as adders and multipliers) and
embedded memories, as well as to have logic blocks implement decoders or
mathematical functions.
Security considerations
With respect to security, FPGAs have both advantages and disadvantages as
compared to ASICs or secure microprocessors. FPGAs' flexibility makes malicious
modifications during fabrication a lower risk.
[26]
For many FPGAs, the loaded
design is exposed while it is loaded (typically on every power-on). To address
this issue, some FPGAs support bitstream encryption.,
[27][28]
although in July
2011, researchers published papers highlighting vulnerabilities in the bitstream
encryption of some devices related to the analysis of the device's power usage
fluctuations.
[29][30]
Applications
Applications of FPGAs include digital signal processing, software-defined radio,
aerospace and defense systems, ASIC prototyping, medical imaging, computer
vision, speech recognition, cryptography, bioinformatics, computer hardware
emulation, radio astronomy, metal detection and a growing range of other areas.
FPGAs originally began as competitors to CPLDs and competed in a similar
space, that of glue logic for PCBs. As their size, capabilities, and speed
increased, they began to take over larger and larger functions to the state where
some are now marketed as full systems on chips (SoC). Particularly with the
introduction of dedicated multipliers into FPGA architectures in the late 1990s,
applications which had traditionally been the sole reserve of DSPs began to
incorporate FPGAs instead.
[31][32]
FPGAs especially find applications in any area or algorithm that can make use of
the massive parallelism offered by their architecture. One such area is code
breaking, in particular brute-force attack, of cryptographic algorithms.
FPGAs are increasingly used in conventional high performance computing
applications where computational kernels such as Fast Fourier transform or
convolution are performed on the FPGA instead of a microprocessor.
The inherent parallelism of the logic resources on an FPGA allows for
considerable computational throughput even at a low MHz clock rates. The
flexibility of the FPGA allows for even higher performance by trading off
precision and range in the number format for an increased number of parallel
arithmetic units. This has driven a new type of processing called reconfigurable
computing, where time intensive tasks are offloaded from software to FPGAs.
The adoption of FPGAs in high performance computing is currently limited by
the complexity of FPGA design compared to conventional software and the
turn-around times of current design tools.
Traditionally, FPGAs have been reserved for specific vertical applications where
the volume of production is small. For these low-volume applications, the
premium that companies pay in hardware costs per unit for a programmable chip
is more affordable than the development resources spent on creating an ASIC for
a low-volume application. Today, new cost and performance dynamics have
broadened the range of viable applications.
Architecture
The most common FPGA architecture
[33]
consists of an array of logic blocks
(called Configurable Logic Block, CLB, or Logic Array Block, LAB, depending on
vendor), I/O pads, and routing channels. Generally, all the routing channels
have the same width (number of wires). Multiple I/O pads may fit into the height
of one row or the width of one column in the array.
An application circuit must be mapped into an FPGA with adequate resources.
While the number of CLBs/LABs and I/Os required is easily determined from the
design, the number of routing tracks needed may vary considerably even among
designs with the same amount of logic. For example, a crossbar switch requires
much more routing than a systolic array with the same gate count. Since unused
routing tracks increase the cost (and decrease the performance) of the part
without providing any benefit, FPGA manufacturers try to provide just enough
tracks so that most designs that will fit in terms of LUTs and IOs can be routed.
This is determined by estimates such as those derived from Rent's rule or by
experiments with existing designs.
In general, a logic block (CLB or LAB) consists of a few logical cells (called ALM,
LE, Slice etc.). A typical cell consists of a 4-input Lookup table (LUT), a Full
adder (FA) and a D-type flip-flop, as shown below. The LUTs are in this figure
split into two 3-input LUTs. In normal mode those are combined into a 4-input
LUT through the left mux. In arithmetic mode, their outputs are fed to the FA.
The selection of mode is programmed into the middle mux. The output can be
either synchronous or asynchronous, depending on the programming of the mux
to the right, in the figure example. In practice, entire or parts of the FA are put
as functions into the LUTs in order to save space.
[34][35][36]
Simplified example illustration of a logic cell
ALMs and Slices usually contains 2 or 4 structures similar to the example figure,
with some shared signals.
CLBs/LABs typically contains a few ALMs/LEs/Slices.
In recent years, manufacturers have started moving to 6-input LUTs in their
high performance parts, claiming increased performance.
[37]
Since clock signals (and often other high-fanout signals) are normally routed via
special-purpose dedicated routing networks in commercial FPGAs, they and
other signals are separately managed.
For this example architecture, the locations of the FPGA logic block pins are
shown below.
Logic Block Pin Locations
Each input is accessible from one side of the logic block, while the output pin
can connect to routing wires in both the channel to the right and the channel
below the logic block.
Each logic block output pin can connect to any of the wiring segments in the
channels adjacent to it.
Similarly, an I/O pad can connect to any one of the wiring segments in the
channel adjacent to it. For example, an I/O pad at the top of the chip can
connect to any of the W wires (where W is the channel width) in the horizontal
channel immediately below it.
Generally, the FPGA routing is unsegmented. That is, each wiring segment spans
only one logic block before it terminates in a switch box. By turning on some of
the programmable switches within a switch box, longer paths can be
constructed. For higher speed interconnect, some FPGA architectures use
longer routing lines that span multiple logic blocks.
Whenever a vertical and a horizontal channel intersect, there is a switch box. In
this architecture, when a wire enters a switch box, there are three
programmable switches that allow it to connect to three other wires in adjacent
channel segments. The pattern, or topology, of switches used in this architecture
is the planar or domain-based switch box topology. In this switch box topology, a
wire in track number one connects only to wires in track number one in adjacent
channel segments, wires in track number 2 connect only to other wires in track
number 2 and so on. The figure below illustrates the connections in a switch box.
Switch box topology
Modern FPGA families expand upon the above capabilities to include higher
level functionality fixed into the silicon. Having these common functions
embedded into the silicon reduces the area required and gives those functions
increased speed compared to building them from primitives. Examples of these
include multipliers, generic DSP blocks, embedded processors, high speed IO
logic and embedded memories.
FPGAs are also widely used for systems validation including pre-silicon
validation, post-silicon validation, and firmware development. This allows chip
companies to validate their design before the chip is produced in the factory,
reducing the time-to-market.
To shrink the size and power consumption of FPGAs, vendors such as Tabula and
Xilinx have introduced new 3D or stacked architectures.
[38][39]
Following the
introduction of its 28 nm 7-series FPGAs, Xilinx revealed that that several of the
highest-density parts in those FPGA product lines will be constructed using
multiple dice in one package, employing technology developed for 3D
construction and stacked-die assemblies. The technology stacks several (three or
four) active FPGA dice side-by-side on a silicon interposer a single piece of
silicon that carries passive interconnect.
[39][40]
FPGA design and programming
To define the behavior of the FPGA, the user provides a hardware description
language (HDL) or a schematic design. The HDL form is more suited to work
with large structures because it's possible to just specify them numerically
rather than having to draw every piece by hand. However, schematic entry can
allow for easier visualisation of a design.
Then, using an electronic design automation tool, a technology-mapped netlist is
generated. The netlist can then be fitted to the actual FPGA architecture using a
process called place-and-route, usually performed by the FPGA company's
proprietary place-and-route software. The user will validate the map, place and
route results via timing analysis, simulation, and other verification
methodologies. Once the design and validation process is complete, the binary
file generated (also using the FPGA company's proprietary software) is used to
(re)configure the FPGA. This file is transferred to the FPGA/CPLD via a serial
interface (JTAG) or to an external memory device like an EEPROM.
The most common HDLs are VHDL and Verilog, although in an attempt to reduce
the complexity of designing in HDLs, which have been compared to the
equivalent of assembly languages, there are moves to raise the abstraction level
through the introduction of alternative languages. National Instrument's
LabVIEW graphical programming language (sometimes referred to as "G") has
an FPGA add-in module available to target and program FPGA hardware.
To simplify the design of complex systems in FPGAs, there exist libraries of
predefined complex functions and circuits that have been tested and optimized
to speed up the design process. These predefined circuits are commonly called
IP cores, and are available from FPGA vendors and third-party IP suppliers
(rarely free, and typically released under proprietary licenses). Other predefined
circuits are available from developer communities such as OpenCores (typically
released under free and open source licenses such as the GPL, BSD or similar
license), and other sources.
In a typical design flow, an FPGA application developer will simulate the design
at multiple stages throughout the design process. Initially the RTL description in
VHDL or Verilog is simulated by creating test benches to simulate the system
and observe results. Then, after the synthesis engine has mapped the design to a
netlist, the netlist is translated to a gate level description where simulation is
repeated to confirm the synthesis proceeded without errors. Finally the design is
laid out in the FPGA at which point propagation delays can be added and the
simulation run again with these values back-annotated onto the netlist.
Basic process technology types
SRAM - based on static memory technology. In-system programmable
and re-programmable. Requires external boot devices. CMOS.
Antifuse - One-time programmable. CMOS.
PROM - Programmable Read-Only Memory technology. One-time
programmable because of plastic packaging.
EPROM - Erasable Programmable Read-Only Memory technology.
One-time programmable but with window, can be erased with ultraviolet
(UV) light. CMOS.
EEPROM - Electrically Erasable Programmable Read-Only Memory
technology. Can be erased, even in plastic packages. Some but not all
EEPROM devices can be in-system programmed. CMOS.
Flash - Flash-erase EPROM technology. Can be erased, even in plastic
packages. Some but not all flash devices can be in-system programmed.
Usually, a flash cell is smaller than an equivalent EEPROM cell and is
therefore less expensive to manufacture. CMOS.
Fuse - One-time programmable. Bipolar.
Major manufacturers
Xilinx and Altera are the current FPGA market leaders and long-time industry
rivals. Together, they control over 80 percent of the market,
[41]
with Xilinx alone
representing over 50 percent.
Both Xilinx and Altera provide free Windows and Linux design software.
[42][43]
Other competitors include Lattice Semiconductor (SRAM based with integrated
configuration Flash, instant-on, low power, live reconfiguration), Actel (antifuse,
flash-based, mixed-signal), SiliconBlue Technologies (extremely low power
SRAM-based FPGAs with option integrated nonvolatile configuration memory),
Achronix (http://www.achronix.com/) (RAM based, 1.5 GHz fabric speed) who
will be building their chips on Intels' state-of-the art 22 nm process,
[44]
and
QuickLogic (handheld focused CSSP, no general purpose FPGAs).
In March 2010, Tabula (http://www.tabula.com/) announced their new FPGA
technology that uses time-multiplexed logic and interconnect for greater
potential cost savings for high-density applications.
[45]
See also
Gate array
PSoC
Application-specific integrated circuit (ASIC)
Application-specific instruction-set processor (ASIP)
Impulse CoDeveloper (Impulse C)
Combinational logic
Complex programmable logic device (CPLD)
Erasable programmable logic device (EPLD)
Software Defined Silicon (SDS)
Soft processor
FPGA prototype
VHDL: VHSIC (Very High Speed Integrated Circuit) Hardware
Description Language
Verilog: Hardware Description Language
JHDL: Just-Another Hardware Description Language
Reconfigurable computing
Partial re-configuration
Hybrid-core computing
Configware
MyHDL Python based HDLgenerates Verilog or VHDL
SystemC System Description LanguageC like
Handel-C Extended C based description language designed for FPGAs
Minimig open source re-implementation of an Amiga 500 using an FPGA
Computing with Memory A time-multiplexed reconfigurable architecture
using 2-D memory array
Digital Clock Manager DCM - Digital Clock Management
Multi-gigabit transceiver or Serdes - Serial transceivers now becoming
very common in the FPGA fabric
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^ Huffmire Paper "Managing Security in FPGA-Based Embedded Systems
(http://www2.computer.org/portal/web/csdl/doi/10.1109/MDT.2008.166) ." Nov-Dec
2008. Retrieved Sept 22, 2009
26.
^ "Virtex-5 FPGA Conguration User Guide" (http://www.xilinx.com/support
/documentation/user_guides/ug191.pdf) . Xilinx Inc.. August 2010. pp. 3335.
http://www.xilinx.com/support/documentation/user_guides/ug191.pdf. Retrieved
2010-10-31.
27.
^ "Protecting Intellectual Property Through FPGA Design Security"
(http://www.altera.com/literature/ads/fpgadesignsecurity.pdf) . Altera Corporation.
http://www.altera.com/literature/ads/fpgadesignsecurity.pdf. Retrieved 2010-11-01.
28.
^ "On the Vulnerability of FPGA Bitstream Encryption against Power Analysis Attacks
Extracting Keys from Xilinx Virtex-II FPGAs" (http://eprint.iacr.org/2011/390) .
http://eprint.iacr.org/2011/390.
29.
^ "On the Portability of Side-Channel Attacks An Analysis of the Xilinx Virtex 4 and
Virtex 5 Bitstream Encryption Mechanism" (http://eprint.iacr.org/2011/391) .
http://eprint.iacr.org/2011/391.
30.
^ FPGA/DSP Blend Tackles Telecom Apps (http://www.bdti.com/articles
/info_eet0207fpga.htm)
31.
^ Xilinx aims 65-nm FPGAs at DSP applications (http://www.eetimes.com
/showArticle.jhtml?articleID=197001881)
32.
^ http://www.eecg.toronto.edu/~vaughn/challenge/fpga_arch.html 33.
^ http://www.altera.com/literature/hb/cyc2/cyc2_cii51002.pdf 34.
^ http://www.altera.com/literature/hb/stratix-iv/stx4_5v1_01.pdf 35.
^ http://www.xilinx.com/support/documentation/user_guides/ug070.pdf 36.
^ http://www.xilinx.com/bvdocs/whitepapers/wp245.pdf 37.
^ Dean Takahashi, VentureBeat. "Intel connection helped chip startup Tabula raise
$108M (http://venturebeat.com/2011/05/02/intel-connection-helped-chip-startup-
tabula-raise-108m) ." May 2, 2011. Retrieved May 13, 2011.
38.
^
a

b
Lawrence Latif, The Inquirer. "FPGA manufacturer claims to beat Moore's Law
(http://www.theinquirer.net/inquirer/news/1811460/fpga-manufacturer-claims-
beat-moores-law) ." October 27, 2010. Retrieved May 12, 2011.
39.
^ EDN Europe. "Xilinx adopts stacked-die 3D packaging (http://www.edn-europe.com
/xilinxadoptsstackeddie3dpackaging+article+4461+Europe.html) ." November 1, 2010.
Retrieved May 12, 2011.
40.
^ Seeking Alpha, "Altera and Xilinx Report: The Battle Continues
(http://seekingalpha.com/article/85478-altera-and-xilinx-report-the-battle-continues) ".
July 17, 2008. Retrieved February 5, 2009.
41.
^ "Xilinx ISE WebPACK" (http://www.xilinx.com/ise/logic_design_prod/webpack.htm) .
http://www.xilinx.com/ise/logic_design_prod/webpack.htm.
42.
^ "Quartus II Web edition software" (https://www.altera.com/support/software
/download/altera_design/quartus_we/dnl-quartus_we.jsp) . https://www.altera.com
/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp.
43.
^ "Achronix to use Intel's 22 nm manufacturing" (http://newsroom.intel.com
/community/intel_newsroom/blog/2010/11/01/chip-shot-achronix-to-use-intel-s-22nm-
44.
manufacturing) . http://newsroom.intel.com/community/intel_newsroom/blog/2010
/11/01/chip-shot-achronix-to-use-intel-s-22nm-manufacturing.
^ "Tabula's Time Machine - Micro Processor Report" (http://www.tabula.com
/news/M11_Tabula_Reprint.pdf) . http://www.tabula.com
/news/M11_Tabula_Reprint.pdf.
45.
Further reading
Hartmut F.-W. Sadrozinski; Jinyuan Wu (2010). Applications of Field-
Programmable Gate Arrays in Scientific Research. Taylor & Francis.
ISBN 978-143-984-133-4.
External links
Xilinx FPGA Related Training (http://www.xilinx.com/training)
University of North Carolina at Charlotte's Reconfigurable Computing
Laboratory (http://www.rcs.uncc.edu/wiki)
FPGA Database (http://so-logic.net/en/knowledgebase/fpga_universe)
Vaughn Betz's FPGA Architecture Page (http://www.eecg.toronto.edu
/~vaughn/challenge/fpga_arch.html)
Retrieved from "http://en.wikipedia.org/wiki/Field-programmable_gate_array"
Categories: Gate arrays
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