DAC

DAC7742
774
2

SBAS256A – DECEMBER 2002 – AUGUST 2007

16-Bit, Single Channel

DIGITAL-TO-ANALOG CONVERTER
With Internal Reference and Parallel Interface

FEATURES DESCRIPTION
● LOW POWER: 150mW Maximum The DAC7742 is a 16-bit Digital-to-Analog Converter (DAC)
● +10V INTERNAL REFERENCE that provides 16 bits of monotonic performance over the
specified operating temperature range and offers a +10V,
● UNIPOLAR OR BIPOLAR OPERATION
low-drift internal reference. Designed for automatic test equip-
● SETTLING TIME: 5µs to ±0.003% FSR
ment and industrial process control applications, the DAC7742
● 16-BIT MONOTINICITY, –40°C TO +85°C output swing can be configured in a ±10V, ±5V, or +10V
● ±10V, ±5V OR +10V CONFIGURABLE VOLTAGE range. The flexibility of the output configuration allows the
OUTPUT DAC7742 to provide both unipolar and bipolar operation by
● RESET TO MIN-SCALE OR MID-SCALE pin strapping. The DAC7742 includes a high-speed output
● DOUBLE-BUFFERED DATA INPUT amplifier with a maximum settling time of 5µs to ±0.003%
FSR for a 20V full-scale change and only consumes 100mW
● INPUT REGISTER DATA READBACK
(typical) of power.
● SMALL LQFP-48 PACKAGE
The DAC7742 features a standard 16-bit parallel interface with
● SUPPORTS TRANSPARENT DATA INPUT
double buffering to allow asynchronous updates of the analog
OPERATION
output, and data read-back to support data integrity verification
prior to an update. A user-programmable reset control allows
APPLICATIONS the DAC output to reset to min-scale (FFFFH) or mid-scale
(7FFFH) overriding the DAC register values. The DAC7742 is
● PROCESS CONTROL available in an LQFP-48 package and three performance
● ATE PIN ELECTRONICS grades specified to operate from –40°C to +85°C.
● CLOSED-LOOP SERVO CONTROL
● MOTOR CONTROL
● DATA ACQUISITION SYSTEMS
VDD VSS VCC REFADJ REFOUT REFIN VREF

ROFFSET

Buffer
REFEN RFB2
+10V
CS Reference
R/W
Control
RST Logic RFB1

RSTSEL

SJ
Input DAC
Data I/O I/O DAC
16 Register Register
Buffer VOUT

AGND DGND LDAC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 2002-2007, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
VCC to VSS ........................................................................... –0.3V to +32V
VCC to AGND ...................................................................... –0.3V to +16V DISCHARGE SENSITIVITY
VSS to AGND ...................................................................... –16V to +0.3V
AGND to DGND ................................................................. –0.3V to +0.3V This integrated circuit can be damaged by ESD. Texas Instru-
REFIN to AGND ............................................................. 0V to VCC – 1.4V ments recommends that all integrated circuits be handled with
VDD to DGND ........................................................................ –0.3V to +6V appropriate precautions. Failure to observe proper handling
Digital Input Voltage to DGND ................................. –0.3V to VDD + 0.3V
Digital Output Voltage to DGND .............................. –0.3V to VDD + 0.3V and installation procedures can cause damage.
Operating Temperature Range ........................................ –40°C to +85°C ESD damage can range from subtle performance degradation
Storage Temperature Range ......................................... –65°C to +150°C
Junction Temperature .................................................................... +150°C to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute maximum changes could cause the device not to meet its published
conditions for extended periods may affect device reliability. specifications.

PACKAGE/ORDERING INFORMATION
LINEARITY DIFFERENTIAL SPECIFIED
ERROR NONLINEARITY PACKAGE TEMPERATURE ORDERING PACKAGE TRANSPORT
PRODUCT (LSB) (LSB) PACKAGE-LEAD DESIGNATOR(1) RANGE NUMBER MARKING MEDIA, QUANTITY

DAC7742 ±6 ±4 LQFP-48 PT –40°C to +85°C DAC7742Y/250 DAC7742Y Tape and Reel, 250
" " " " " " DAC7742Y/2K " Tape and Reel, 2000
DAC7742 ±4 ±2 LQFP-48 PT –40°C to +85°C DAC7742YB/250 DAC7742YB Tape and Reel, 250
" " " " " " DAC7742YB/2K " Tape and Reel, 2000
DAC7742 ±3 ±1 LQFP-48 PT –40°C to +85°C DAC7742YC/250 DAC7742YC Tape and Reel, 250
" " " " " " DAC7742YC/2K " Tape and Reel, 2000

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.

ELECTRICAL CHARACTERISTICS
All specifications at TA = TMIN to TMAX, VCC = +15V, VSS = –15V, VDD = +5V, Internal reference enabled, unless otherwise noted.

DAC7742Y DAC7742YB DAC7742YC

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

ACCURACY
Linearity Error (INL) ±6 ±4 ±3 LSB
TA = 25°C ±5 ±3 ±2 LSB
Differential Linearity Error (DNL) ±4 ±2 ±1 LSB
Monotonicity 14 15 16 Bits
Offset Error ±0.1 ✻ ✻ % of FSR
Offset Error Drift ±2 ✻ ✻ ppm/°C
Gain Error With Internal REF ±0.4 ±0.25 ±0.2 % of FSR
With External REF ±0.25 ±0.1 ✻ % of FSR
Gain Error Drift With Internal REF ±15 ±10 ±7 ppm/°C
PSRR (VCC or VSS) At Full-Scale 50 200 ✻ ✻ ✻ ✻ ppm/V
ANALOG OUTPUT(1)
Voltage Output(2) +11.4/–4.75 0 to 10 ✻ ✻ V
+11.4/–11.4 ±10 ✻ ✻ V
+11.4/–6.4 ±5 ✻ ✻ V
Output Current ±5 ✻ ✻ mA
Output Impedance 0.1 ✻ ✻ Ω
Maximum Load Capacitance 200 ✻ ✻ pF
Short-Circuit Current ±15 ✻ ✻ mA
Short-Circuit Duration AGND Indefinite ✻ ✻
REFERENCE
Reference Output 9.96 10 10.04 9.975 ✻ 10.025 ✻ ✻ ✻ V
REFOUT Impedance 400 ✻ ✻ Ω
REFOUT Voltage Drift ±15 ±10 ±7 ppm/°C
REFOUT Voltage Adjustment(3) ±25 ✻ ✻ mV
REFIN Input Range(4) 4.75 VCC – 1.4 ✻ ✻ ✻ ✻ V
REFIN Input Current 10 ✻ ✻ nA
REFADJ Input Range Absolute Max Value that 0 10 ✻ ✻ ✻ ✻ V
can be applied is VCC
REFADJ Input Impedance 50 ✻ ✻ kΩ
VREF Output Current –2 +2 ✻ ✻ ✻ ✻ mA
VREF Impedance 1 ✻ ✻ Ω

2
DAC7742
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ELECTRICAL CHARACTERISTICS (Cont.)
All specifications at TA = TMIN to TMAX, VCC = +15V, VSS = –15V, VDD = +5V, Internal reference enabled, unless otherwise noted.

DAC7742Y DAC7742YB DAC7742YC

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

DYNAMIC PERFORMANCE
Settling Time to ±0.003% 20V Output Step 3 4 ✻ ✻ ✻ ✻ µs
RL = 5kΩ, CL = 200pF,
with external REFOUT
to REFIN filter(5)
Digital Feedthrough 2 ✻ ✻ nV-s
Output Noise Voltage at 10kHz 100 ✻ ✻ nV/√Hz
DIGITAL INPUT
VIH |IH| < 10µA 0.7 • VDD ✻ ✻ V
VIL |IL| < 10µA 0.3 • VDD ✻ ✻ V
Input Coding See Table III ✻ ✻
DIGITAL OUTPUT
VOH IOH = –0.8mA 3.6 ✻ ✻ V
VOL IOL = 1.6mA 0.4 ✻ ✻ V
POWER SUPPLY
VDD +4.75 +5.0 +5.25 ✻ ✻ ✻ ✻ ✻ ✻ V
VCC +11.4 +15.75 ✻ ✻ ✻ ✻ V
VSS Bipolar Operation –15.75 –11.4 ✻ ✻ ✻ ✻ V
Unipolar Operation –15.75 –4.75 ✻ ✻ ✻ ✻ V
IDD 100 ✻ ✻ µA
ICC Unloaded 4 6 ✻ ✻ ✻ ✻ mA
ISS Unloaded –4 –2.5 ✻ ✻ ✻ ✻ mA
Power No Load, Ext. Reference 85 ✻ ✻ mW
No Load, Int. Reference 100 150 ✻ ✻ ✻ ✻ mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻ ✻ ✻ ✻ °C

✻ Specifications same as DAC7742Y.

NOTES: (1) With minimum VCC/VSS requirements, internal reference enabled. (2) Please refer to the "Theory of Operation" section for more information with respect to output
voltage configurations. (3) See Figure 7 for gain and offset adjustment connection diagrams when using the internal reference. (4) The minimum value for REFIN must be equal
to the greater of VSS +14V and +4.75V, where +4.75V is the minimum voltage allowed. (5) Reference low-pass filter values: 100kΩ, 1.0µF (See Figure 10).

DAC7742 3
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PIN CONFIGURATION
Top View LQFP

REFADJ

RSTSEL
REFOUT

REFEN

DGND
REFIN

LDAC

RST
R/W

VDD
NC

CS
48 47 46 45 44 43 42 41 40 39 38 37

NC 1 36 NC

VSS 2 35 DB15

VCC 3 34 DB14

VREF 4 33 DB13

ROFFSET 5 32 DB12

AGND 6 31 DB11
DAC7742
AGND 7 30 DB10

RFB2 8 29 DB9

RFB1 9 28 DB8

SJ 10 27 DB7

VOUT 11 26 TEST

NC 12 25 NC

13 14 15 16 17 18 19 20 21 22 23 24
NC

NC

NC

DB0

DB1

DB2

DB3

DB4

DB5

DB6

NC

NC
PIN DESCRIPTIONS
PIN NAME DESCRIPTION PIN NAME DESCRIPTION

1 NC No Connection 28 DB8 Data Bit 8

2 VSS Negative Analog Power Supply 29 DB9 Data Bit 9

3 VCC Positive Analog Power Supply 30 DB10 Data Bit 10

4 VREF Buffered Output from REFIN; can be used to 31 DB11 Data Bit 11
drive external devices. Internally, this pin 32 DB12 Data Bit 12
directly drives the DAC's circuitry. 33 DB13 Data Bit 13
5 ROFFSET Offsetting Resistor 34 DB14 Data Bit 14
6 AGND Analog Ground (Must be tied to analog ground.) 35 DB15 Data Bit 15 (MSB)
7 AGND Analog Ground (Must be tied to analog ground.) 36 NC No Connection
8 RFB2 Feedback Resistor 2, used to configure DAC 37 DGND Digital Ground
output range. 38 VDD Digital Power Supply
9 RFB1 Feedback Resistor 1, used to configure DAC 39 RST VOUT reset; active LOW, depending on the state of
output range. RSTSEL, the DAC register is either reset to mid-
10 SJ Summing Junction of the Output Amplifier scale or min-scale.
11 VOUT DAC Voltage Output 40 LDAC DAC register load control, active LOW. Data is
12 NC No Connection loaded from the input register to the DAC register.
13 NC No Connection 41 CS Chip Select, Active LOW
14 NC No Connection 42 R/W Enabled by CS, controls data read (HIGH) and
15 NC No Connection write (LOW) from or to the input register.

16 DB0 Data Bit 0 (LSB) 43 RSTSEL Reset Select; determines the action of RST. If
HIGH, RST will reset the DAC register to mid-
17 DB1 Data Bit 1
scale. If LOW, RST will reset the DAC register to
18 DB2 Data Bit 2 min-scale.
19 DB3 Data Bit 3 44 REFEN Enables internal +10V reference (REFOUT), active
20 DB4 Data Bit 4 LOW.
21 DB5 Data Bit 5 45 REFOUT Internal Reference Output
22 DB6 Data Bit 6 46 REFADJ Internal Reference Trim. (Acts as a gain
23 NC No Connection adjustment input when the internal reference is
used.)
24 NC No Connection
47 REFIN Reference Input
25 NC No Connection
48 NC No Connection
26 TEST Reserved, Connect to DGND
27 DB7 Data Bit 7

4
DAC7742
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TIMING DIAGRAMS
DATA WRITE CYCLE

tWCS
CS
tLH
tWS tWH tLS

R/W

tDS tDH tDS tDH

Data In
DB15-DB0 Data Valid Data Valid

LDAC
tLWD
tS

VOUT

READ CYCLE RESET TIMING

tSS

RSTSEL
tSH
CS tRCS
tRDS tRSS
tRDH RST

R/W +FS tS

tDZ (RSTSEL = LOW)

VOUT Min-Scale
Data Valid
Data Out –FS
DB15-DB0 tCSD
+FS
Mid-Scale
VOUT (RSTSEL = HIGH)

–FS

TIMING CHARACTERISTICS
DAC7742Y

PARAMETER DESCRIPTION MIN TYP MAX UNITS

READ
tRCS CS LOW for Read 90 ns
tRDS R/W HIGH to CS LOW 10 ns
tRDH R/W HIGH After CS HIGH 10 ns
tDZ CS HIGH to Data Bus High Impedance 10 70 ns
tCSD CS LOW to Data Bus Valid 70 100 ns
WRITE
tWS R/W LOW to CS LOW 10 ns
tWH R/W LOW After CS HIGH 10 ns
tWCS CS LOW for Write 25 ns
tLWD LDAC LOW for Write 20 ns
tLS CS LOW to LDAC HIGH for Direct Update 30 ns
tLH CS LOW After LDAC HIGH 0 ns
tDS Data Valid to CS LOW 0 ns
tDH Data Valid After CS HIGH 20 ns
RESET
tRSS RST LOW 30 ns
tSS RSTSEL Valid Before RST LOW 0 ns
tSH RSTSEL Valid After RST HIGH 10 ns
ANALOG
tS Voltage Output Settling Time 5 µs

DAC7742 5
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 TYPICAL CHARACTERISTICS
TA = +25°C (unless otherwise noted).

LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE
6 6
4 4

INL (LSB)
INL (LSB)

2 2
0 0
–2 –2
Bipolar Configuration: VOUT = –10V to +10V Bipolar Configuration: VOUT = –10V to +10V
–4 –4
TA = 85°C, Internal Reference Enabled TA = 25°C, Internal Reference Enabled
–6 –6

2.0 2.0
1.5 1.5

DNL (LSB)
DNL (LSB)

1.0 1.0
0.5 0.5
0.0 0.0
–0.5 –0.5
–1.0 –1.0
–1.5 –1.5
–2.0 –2.0
FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H
Digital Input Code Digital Input Code

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE OFFSET ERROR vs TEMPERATURE
6 5
4 4
INL (LSB)

2
0 3
–2 2
Bipolar Configuration: VOUT = –10V to +10V
–4
TA = –40°C, Internal Reference Enabled 1
Error (mV)

–6 VOUT = –10V to +10V

0
2.0 VOUT = 0V to +10V
1.5 –1
DNL (LSB)

1.0
0.5 –2
0.0 –3
–0.5
–1.0 –4
–1.5
–2.0 –5
FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H –40 –15 10 35 60 85
Digital Input Code Temperature (°C)

GAIN ERROR vs TEMPERATURE VCC SUPPLY CURRENT vs DIGITAL INPUT CODE

0.15 4.4
Bipolar Configuration: VOUT = –10V to +10V
Ext. Ref, Bipolar Mode: Internal Reference Enabled, TA = 25°C
VOUT = –10V to +10V 4.3
0.10
4.2
Int. Ref, Bipolar Mode:
VOUT = –10V to +10V
Error (%)

ICC (mA)

4.1
0.05
4.0

3.9
0
Int. Ref, Unipolar Mode: Ext. Ref, Unipolar Mode:
3.8
VOUT = 0V to +10V VOUT = 0V to +10V
–0.05 3.7
–40 –15 10 35 60 85 FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H
Temperature (°C) Digital Input Code

6
DAC7742
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TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C (unless otherwise noted).

VCC SUPPLY CURRENT vs DIGITAL INPUT CODE VSS SUPPLY CURRENT vs DIGITAL INPUT CODE
3.4 –1.50
Bipolar Configuration: VOUT = –10V to +10V
External Reference, REFEN = 5V, TA = 25°C
3.3
–1.75
3.2
–2.00

ISS (mA)
ICC (mA)

3.1

3.0 –2.25

2.9
–2.50
2.8 Bipolar Configuration: VOUT = –10V to +10V
TA = 25°C
2.7 –2.75
FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H FFFFH DFFFH BFFFH 9FFFH 7FFFH 5FFFH 3FFFH 1FFFH 0000H

Digital Input Code Digital Input Code

SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs LOGIC INPUT VOLTAGE

6 1000
TA = 25°C, Transition
5 Shown for One Data
4 800 Input (CS = 5V, R/W = 0)

3
ICC
600
ICC, ISS (mA)

2
IDD (µA)

Load Current Excluded, VCC = +15V, VSS = –15V

1 Bipolar VOUT Configuration: –10V to +10V
0 400

–1
ISS
–2 200

–3
–4 0
–40 –15 10 35 60 85 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Temperature (°C) VLOGIC (V)

HISTOGRAM OF VCC CURRENT CONSUMPTION HISTOGRAM OF VSS CURRENT CONSUMPTION

100 100
Bipolar Output Configuration Bipolar Output Configuration
90 Internal Reference Enabled 90 Internal Reference Enabled
80 Code = AAAAH 80 Code = AAAAH
70 70
60 60
Frequency

Frequency

50 50
40 40
30 30
20 20
10 10
0 0
3.000 3.500 4.000 4.500 5.000 –3.50 –3.00 –2.50 –2.00 –1.50
ICC (mA) ISS (mA)

DAC7742 7
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TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C (unless otherwise noted).

POWER-SUPPY REJECTION RATIO vs FREQUENCY POWER-SUPPY REJECTION RATIO vs FREQUENCY

(Measured at VOUT) (Measured at VOUT)
10 10
Bipolar Configuration: ±10V VOUT Bipolar Configuration: ±10V VOUT, Code 0000H
0 Code 7FFFH 0 –VSS, VCC = 15V + 1Vp-p, VDD = 5V + 0.5Vp-p
–10 –VSS, VCC = 15V + 1Vp-p –10
VDD = 5V + 0.5Vp-p
–20 –20
VSS
PSRR (dB)

PSRR (dB)
–30 –30
VCC
–40 –40
VSS
–50 –50
VCC VDD
–60 –60
–70 –70
VDD
–80 –80
0.1k 1k 10k 100k 1M 10M 0.01k 0.1k 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

INTERNAL REFERENCE START-UP INTERNAL REFERENCE OUTPUT vs TEMPERATURE

10.015
VCC (5V/div)

15V
10.010

0V 10.005
REFOUT (V)

10.000
REFOUT (2V/div)

10V
9.995

9.990
0V
9.985
Time (2ms/div) –40 –15 10 35 60 85
Temperature (°C)

OUTPUT VOLTAGE vs RLOAD REFOUT VOLTAGE vs LOAD

12 11.0
Source
Loaded to VCC VCC = +15V
8
10.5

4
REFOUT (V)
VOUT (V)

10.0
0
9.5
–4
Sink
9.0
–8
Loaded to AGND
–12 8.5
0.0 0.1 1.0 10.0 100.0 1 10 100 1k
RLOAD (kΩ) REFOUT LOAD (kΩ)

8
DAC7742
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TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C (unless otherwise noted).

POWER-SUPPY REJECTION RATIO vs FREQUENCY

(Measured at REFOUT) OUTPUT NOISE vs FREQUENCY
10 900
Internal Reference Enabled Unipolar Configuration, Internal Reference Enabled
0 –VSS, VCC = 15V + 1Vp-p, 800
VDD = 5V + 0.5Vp-p 700
–10

Output Noise (nV/Hz)

–20 600
VCC Code 0000H
PSRR (dB)

–30 500

–40 400
VSS VDD
–50 300

–60 200
Code FFFFH
–70 100

–80 0
1 10 100 1k 10k 100k 1M 10M 0.01k 0.1k 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

OUTPUT NOISE vs FREQUENCY BROADBAND NOISE

800
Bipolar Configuration: ±10V, Internal Reference Enabled
700
Output Noise (nV/rtHz)

600

500 VOUT (V, 50µV/div)

400
Code FFFFH
300
Code 0000H
200 Internal Reference Enabled
Code 7FFFH Filtered with 1.6Hz Low-Pass
100 Code 0000H, Bipolar ±10V Configuration
10kHz Measurement BW
0
0.01k 0.1k 1k 10k 100k 1M 10M Time (100µs/div)
Frequency (Hz)

UNIPOLAR FULL-SCALE SETTLING TIME BIPOLAR FULL-SCALE SETTLING TIME

Small-Signal Error (150µV/div)

Small-Signal Error (300µV/div)

Large-Signal Output (5V/div)

Large-Signal Output (5V/div)

Unipolar Configurtaion: VOUT = 0V to +10V Bipolar Configurtaion: VOUT = –10V to +10V

+ Full-Scale to Zero-Scale +Full-Scale to –Full-Scale
5kΩ, 200pF Load 5kΩ, 200pF Load

Time (2µs/div) Time (2µs/div)

DAC7742 9
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TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C (unless otherwise noted).

UNIPOLAR FULL-SCALE SETTLING TIME BIPOLAR FULL-SCALE SETTLING TIME

Large-Signal Output (5V/div) Large-Signal Output (5V/div)

Small-Signal Error (150µV/div)

Small-Signal Error (300µV/div)

Unipolar Configuration: VOUT = 0V to +10V Bipolar Configuration: VOUT = –10 to +10V

Zero-Scale to +Full-Scale –Full-Scale to +Full-Scale
5kΩ, 200pF Load 5kΩ, 200pF Load

Time (2µs/div) Time (2µs/div)

MID-SCALE GLITCH MID-SCALE GLITCH

Code 7FFFH to 8000H Code 8000H to 7FFFH

Bipolar Configuration: ±10V VOUT Bipolar Configuration: ±10V VOUT
VOUT (V, 200mV/div)
VOUT (V, 200mV/div)

Time (1µs/div) Time (1µs/div)

DIGITAL FEEDTHROUGH

All Data Bits Toggling (5V/div)

VOUT = 7FFFH (100mV/div)

CS = 5V

Time (200ns/div)

10
DAC7742
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THEORY OF OPERATION The digital input is a parallel word made up of the 16-bit DAC
code and is loaded into the DAC register using the LDAC
The DAC7742 is a voltage output, 16-bit DAC with a +10V built- input pin. The converter can be powered from ±12V to ±15V
in internal reference. The architecture is an R-2R ladder con- dual analog supplies and a +5V logic supply. The device
figuration with the three MSBs segmented, followed by an offers a reset function, which immediately sets the DAC
operational amplifier that serves as a buffer, as shown in Figure output voltage and DAC register to min-scale (code FFFFH)
1. The output buffer is designed to allow user-configurable or mid-scale (code 7FFFH). The data I/O and reset functions
output adjustments giving the DAC7742 output voltage ranges are discussed in more detail in the following sections.
of 0V to +10V, –5V to +5V, or –10V to +10V. Please refer to
Figures 2, 3, and 4 for pin configuration information.

REFADJ REFOUT REFIN VREF ROFFSET

RFB2

Buffer R/4
RFB1
+10V Internal R/2 R/2 R/4
Reference
SJ
R

VOUT
2R 2R 2R 2R 2R 2R 2R 2R 2R
R/4

VREF
AGND

FIGURE 1. DAC7742 Architecture.

Data Bus

VDD
NC 36

DB15 35

DB14 34

DB13 33

DB12 32

DB11 31

DB10 30

DB9 29

DB8 28

DB7 27

TEST 26

NC 25

0.1µF 1µF
37

24

DGND NC
38

23

VDD NC
39

22

RST DB6
40

21

LDAC DB5
41

20

Control Bus CS DB4

42

19

R/W DB3 Data Bus

DAC7742
43

18

RSTSEL DB2
44

17

REFEN DB1
45

16

REFOUT DB0
46

15

REFADJ NC
47

14

REFIN NC
ROFFSET
48

13

NC NC
AGND

AGND

RFB2

RFB1

VOUT
VREF
VCC
VSS
NC

NC
SJ
10

11

12

VSS
1

(0V to +10V)
0.1µF 1µF

VCC

0.1µF 1µF

FIGURE 2. Basic Operation: VOUT = 0V to +10V.

DAC7742 11
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 Data Bus

VDD

NC 36

DB15 35

DB14 34

DB13 33

DB12 32

DB11 31

DB10 30

DB9 29

DB8 28

DB7 27

TEST 26

NC 25
0.1µF 1µF

37

24
DGND NC

38

23
VDD NC

39

22
RST DB6

40

21
LDAC DB5

41

20
Control Bus CS DB4

42

19
R/W DB3 Data Bus
DAC7742

43

18
RSTSEL DB2

44

17
REFEN DB1

45

16
46 REFOUT DB0

15
REFADJ NC
47

14
REFIN NC

ROFFSET
48

13
NC NC

AGND

AGND

RFB2

RFB1

VOUT
VREF
VCC
VSS
NC

NC
SJ
10

11

12
VSS
1

9
(–5V to +5V)
0.1µF 1µF

VCC

0.1µF 1µF

FIGURE 3. Basic Operation: VOUT = –5V to +5V.

Data Bus

VDD
NC 36

DB15 35

DB14 34

DB13 33

DB12 32

DB11 31

DB10 30

DB9 29

DB8 28

DB7 27

TEST 26

NC 25

0.1µF 1µF
37

24

DGND NC
38

23

VDD NC
39

22

RST DB6
40

21

LDAC DB5
41

20

Control Bus CS DB4

42

19

R/W DB3 Data Bus

DAC7742
43

18

RSTSEL DB2
44

17

REFEN DB1
45

16

REFOUT DB0
46

15

REFADJ NC
47

14

REFIN NC
ROFFSET
48

13

NC NC
AGND

AGND

RFB2

RFB1

VOUT
VREF
VCC
VSS
NC

NC
SJ
10

11

12

VSS
1

(–10V to +10V)
0.1µF 1µF

VCC

0.1µF 1µF

FIGURE 4. Basic Operation: VOUT = –10V to +10V.

12
DAC7742
www.ti.com SBAS256A
ANALOG OUTPUTS at the VREF pin. In this configuration, VREF is used to setup the
The output amplifier can swing to within 1.4V of the supply DAC7742 output amplifier into one of three voltage output
rails, specified over the –40°C to +85°C temperature range. modes as discussed earlier. VREF can also be used to drive
This allows for a ±10V DAC voltage output operation from other system components requiring an external reference.
±12V supplies with a typical 5% tolerance. The internal reference of the DAC7742 can be disabled when
When the DAC7742 is configured for a unipolar, 0V to 10V use of an external reference is desired. When using an
output, a negative voltage supply is required. This is due to external reference, the reference input, REFIN, can be any
internal biasing of the output stage. Please refer to the voltage between 4.75V (or VSS + 14V, whichever is greater)
“Electrical Characteristics” table for more information. and VCC – 1.4V.

The minimum and maximum voltage output values are de-

pendent upon the output configuration implemented and DIGITAL INTERFACE
reference voltage applied to the DAC7742. Please note that Table III shows the data format for the DAC7742 and
VSS (the negative power supply) must be in the range of Table II illustrates the basic control logic of the device. The
–4.75V to –15.75V for unipolar operation. The voltage on VSS interface consists of a chip select input (CS), read/write
sets several bias points within the converter and is required control input (R/W), data inputs (DB0-DB15), and a load DAC
in all modes of operation. If VSS is not in one of these two input (LDAC). An asynchronous reset input (RST) which is
configurations, the bias values may be in error and proper active LOW, is provided to simplify start-up conditions, peri-
operation of the device is not ensured. odic resets, or emergency resets to a known state, depend-
Supply sequence is important in establishing correct startup ing on the status of the reset select (RSTSEL) signal. The
of the DAC. DAC code is provided via a 16-bit parallel interface, as
shown in Table II. The input word makes up the DAC code
The digital supply (VDD) needs to establish correct bias
to be loaded into the data input register of the device. The
conditions before the analog supplies (VCC, VSS) are brought
data is latched into the input register on rising CS and is
up. If the digital supply cannot be brought up first, it must
loaded into the DAC register upon reception of a LOW level
come up before either analog supply (VCC or VSS), with the
on the LDAC input. This action updates the analog output,
preferred sequence of: VSS (device substrate), VDD, and then
VOUT, to the desired value. LDAC inputs of multiple DAC7742s
VCC.
can be connected when a synchronized update of numerous
DAC outputs is desired. Please refer to the timing section for
REFERENCE INPUTS more detailed data I/O information.
The DAC7742 provides a built-in +10V voltage reference and
on-chip buffer to allow external component reference drive. To ANALOG OUTPUT
use the internal reference, REFEN must be LOW, enabling the DIGITAL INPUT Unipolar Configuration Bipolar Configuration
reference circuitry of the DAC7742 (as shown in Table I) and Complementary Straight Binary Complementary Offset Binary
the REFOUT pin must be connected to REFIN. This is the input 0xFFFF Zero (0V) –Full-Scale (–VREF or –VREF/2)
to the on-chip reference buffer. The buffer’s output is provided 0xFFFE Zero + 1LSB –Full-Scale + 1LSB
: : :
REFEN ACTION 0x7FFF 1/2 Full-Scale Bipolar Zero
1 Internal Reference disabled; 0x7FFE 1/2 Full-Scale + 1LSB Bipolar Zero + 1LSB
REFOUT = High Impedance : : :
0 Internal Reference enabled; 0x0000 Full-Scale (VREF – 1LSB) +Full-Scale (+VREF – 1LSB
REFOUT = +10V or +VREF/2 – 1LSB)

TABLE I. REFEN Action. TABLE III. DAC7742 Data Format.

CONTROL STATUS COMMAND

R/W CS RST RSTSEL LDAC Input Register DAC Register Mode

L L H X H Write Hold Write Data to Input Register

X H H X L Hold Write Update DAC Register with Data from Input
Register
L L H X L Transparent Write Write DAC Register Directly from Data Bus
H L H X H, L Read Hold Read Data in Input Register
X H H X H Hold Hold No Change
X X L L X Reset to Min-Scale Reset to Min-Scale Reset to Input and DAC Register (FFFFH)
Min-Scale
X X L H X Reset to Mid-Scale Reset to Mid-Scale Reset to Input and DAC Register (7FFFH)
Mid-Scale

TABLE II. DAC7742 Logic Truth Table.

DAC7742 13
SBAS256A www.ti.com
DAC RESET
(+VREF)
The RST and RSTSEL inputs control the reset of the analog
output. The reset command is level triggered by a LOW signal + Full-Scale
Gain Adjust
on RST. Once RST is LOW, the DAC output will begin settling 1LSB
Rotates
the Line

Full Scale Range

to the mid-scale or min-scale code depending on the state of

Analog Output
the RSTSEL input. A HIGH value on RSTSEL will cause VOUT
to reset to the mid-scale code (7FFFH) and a LOW value will
reset VOUT to min-scale (FFFFH). A change in the state of the Input =
RSTSEL input while RST is LOW will cause a corresponding FFFFH Input =
0000 H
change in the reset command selected internally and conse-
quently change the output value of VOUT of the DAC. Note that Zero Scale
(AGND)
a valid reset signal also resets the input register of the DAC to Digital Input

the value specified by the state of RSTSEL. Offset Adjust Translates the Line

FIGURE 5. Relationship of Offset and Gain Adjustments for

GAIN AND OFFSET CALIBRATION
VOUT = 0V to +10V Output Configuration.
The architecture of the DAC7742 is designed in such a way
as to allow for easily configurable offset and gain calibration
using a minimum of external components. The DAC7742 (+VREF or +VREF/2)
has built-in feedback resistors and output amplifier summing
+ Full-
points brought out of the package in order to make the Scale
absolute calibration possible. Figures 5 and 6 illustrate the 1LSB
relationship of offset and gain adjustments for the DAC7742 Input =
Gain

Full-Scale
FFFFH

Range
in a unipolar configuration and in a bipolar configuration, Adjust
Rotates
respectively.
Analog Output
the Line Offset
When calibrating the DAC’s output, offset should be adjusted Adjust
Translates
first to avoid 1st-order interaction of adjustments. In unipolar the Line
Input =
mode, the DAC7742’s offset is adjusted from code FFFFH 0000 H
Input = 7FFFH
and for either bipolar mode, offset adjustments are made at
code 7FFFH. Gain adjustment can then be made at code
– Full-Scale
0000H for each configuration, where the output of the DAC (–VREF OR –VREF/2)
should be at +10V for the 0V to +10V – 1LSB or ±10V output Digital Input
range and +5V – 1LSB for the ±5V output range. Figure 7
shows the generalized external offset and gain adjustment FIGURE 6. Relationship of Offset and Gain Adjustments for
circuitry using potentiometers. VOUT = –10V to +10V Output Configuration. (Same
Theory Applies for VOUT = –5V to +5V.)

15 REFOUT

16 REFADJ
Optional Gain 17 REFIN
ROFFSET

Adjust
AGND

AGND

RFB2

RFB1

VOUT
VREF

18 NC
VCC
VSS
NC

SJ

RPOT1
10

11
1

ISJ

R1
(Other Connections Omitted
RS
for Clarity)
RPOT2
+
VOADJ
–

Optional Offset
Adjust

FIGURE 7. Generalized External Calibration Circuitry for Gain and Symmetrical Offset Adjustment.

14
DAC7742
www.ti.com SBAS256A
OFFSET ADJUSTMENT REFADJ can be driven by a low impedance voltage source
Offset adjustment is accomplished by introducing a small such as a unipolar, 0V to +10V DAC or a potentiometer (less
current into the summing junction (SJ) of the DAC7742. The than 100kΩ), see Figure 7. Since the input impedance of
voltage at SJ, or VSJ, is dependent on the output configura- REFADJ is typically 50kΩ, the smaller the resistance of the
tion of the DAC7742. Table IV shows the required pin potentiometer, the more linear the adjustment will be. A 10kΩ
strapping for a given configuration and the nominal values of potentiometer is suggested if linearity of the reference adjust-
VSJ for each output range. ment is of concern.

REFERENCE OUTPUT PIN STRAPPING VSJ(1) OFFSET ADJUST RANGE

CONFIGURATION CONFIGURATION ROFFSET RFB1 RFB2 50
typ –10V to +10V VOUT
Internal 0V to +10V to VREF to VOUT to VOUT +5V Configuration

Offset Adjustment at VOUT (mV)

Reference –10V to +10V NC NC to VOUT +3.333V
min (75% of typ)
–5V to +5V to AGND to VOUT to VOUT +2.5V 25
External 0V to VREF to VREF to VOUT to VOUT VREF/2
Reference –VREF to VREF NC NC to VOUT VREF/3 typ
–VREF/2 to VREF/2 to AGND to VOUT to VOUT VREF/4 0
NOTE: (1) Voltage measured at VSJ for a given configuration. min (75% of typ)
TABLE IV. Nominal VSJ vs VOUT and Reference Configuration. 0V to 10V and –5V to +5V
–25 VOUT Configuration

The current level required to adjust the DAC7742’s offset can

be created by using a potentiometer divider, see Figure 7. –50
Another alternative is to use a unipolar DAC in order to apply –2 –1 0 1 2
a voltage, VOADJ, to the resistor RS. A ±1.2µA current range ISJ (µA)
applied to SJ will ensure offset adjustment coverage of the
±0.1% maximum offset specification of the DAC7742. FIGURE 8. Offset Adjustment Transfer Characteristic.
When in a unipolar configuration (VSJ = 5V), only a single
resistor, RS, is needed for symmetrical offset adjustment with When the DAC7742’s internal reference is not used, gain
a 0V to 10V VOADJ range. When in one of the two bipolar adjustments can be made via trimming the external refer-
configurations, VSJ is either +3.333v (±10V range) or +2.5V ence applied to the DAC at REFIN. This can be accomplished
(±5V range), and circuit values chosen to match those given through using a potentiometer, unipolar DAC, or other means
in Table V will provide symmetrical offset adjust. Please refer of precision voltage adjustment to control the voltage pre-
to Figure 7 for component configuration. sented to the DAC7742 by the external reference. Figure 9
and Table VI summarize the range of adjustment of the
internal reference via REFADJ.
OUTPUT RPOT2 R1 RS ISJ NOMINAL
CONFIGURATION RANGE OFFSET
ADJUSTMENT
0V to +10V 10k 0 2.5M ±2µA ±25mV REFOUT ADJUST RANGE
40
–10V to +10V 10k 5k 1.5M ±2.2µA ±55mV
–5V to +5V 10k 10k 1.5M ±1.7µA ±21mV 30
Typical REFOUT
Adjustment Range
REFOUT Adjustment (mV)

TABLE V. Recommended External Component Values for 20

Symmetrical Offset Adjustment (VREF = 10V).
10

0 Minimum REFOUT
Figure 8 illustrates the typical and minimum offset adjustment Adjustment Range
–10
ranges provided by forcing a current at SJ for a given output
voltage configuration. –20

–30
GAIN ADJUSTMENT –40
When using the internal reference of the DAC7742, gain 0 2 4 6 8 10
adjustment is performed by adjusting the device’s internal REFADJ (V)
reference voltage via the reference adjust pin, REFADJ.
FIGURE 9. Internal Reference Adjustment Transfer Charac-
The effect of a reference voltage change on the gain of the
teristic.
DAC output can be seen in the generic equation (for
unipolar configuration):
VOLTAGE AT REFADJ REFOUT VOLTAGE
 (65535 – N) 
VOUT = VREFIN •  
REFADJ = 0V 10V + 25mV (min)
 65536  REFADJ = 5V or NC(1) 10V
REFADJ = 10V 10V – 25mV (max)
Where N is represented in decimal format and ranges from NOTE: "NC" is "Not Connected".
0 to 65535. TABLE VI. Minimum Internal Reference Adjustment Range.

DAC7742 15
SBAS256A www.ti.com
NOISE PERFORMANCE LAYOUT
Increased noise performance of the DAC output can be
achieved by filtering the voltage reference input to the A precision analog component requires careful layout, adequate
DAC7742. Figure 10 shows a typical internal reference filter bypassing, and clean, well-regulated power supplies. The
schematic. A low-pass filter applied between the REFOUT and DAC7742 offers separate digital and analog supplies, as it will
REFIN pins can increase noise immunity at the DAC and often be used in close proximity with digital logic, microcontrollers,
output amplifier. The REFOUT pin can source a maximum of microprocessors, and digital signal processors. The more digital
50µA so care should be taken in order to avoid overloading logic present in the design and the higher the switching speed,
the internal reference output. the more important it will become to separate the analog and
digital ground and supply planes at the device.
Since the DAC7742 has both analog and digital ground pins,
return currents can be better controlled and have less effect
on the DAC output error. Ideally, AGND would be connected
directly to an analog ground plane and DGND to the digital
ground plane. The analog ground plane would be separate
from the ground connection for the digital components until
43 RSTSEL
they were connected at the power entry point of the system.
44 REFEN
100kΩ The voltages applied to VCC and VSS should be well regulated
45 REFOUT and low noise. Switching power supplies and DC/DC con-
1µF 46 REFADJ
verters will often have high-frequency glitches or spikes
riding on the output voltage. In addition, digital components
47 REFIN
can create similar high-frequency spikes as their internal
48 NC logic switches states. This noise can easily couple into the
VCC
VSS
NC

(Other Connections
Omitted for Clarity) DAC output voltage through various paths between the
power connections and analog output.
1

In addition, a 1µF to 10µF bypass capacitor in parallel with a

0.1µF bypass capacitor is strongly recommended for each
supply input. In some situations, additional bypassing may
be required, such as a 100µF electrolytic capacitor or even
a "Pi" filter made up of inductors and capacitors–all designed
FIGURE 10. Internal Reference Filter. to essentially low-pass filter the analog supplies, removing
any high frequency noise components.

16
DAC7742
www.ti.com SBAS256A
 PACKAGE OPTION ADDENDUM

www.ti.com 7-Oct-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

DAC7742YB/250 ACTIVE LQFP PT 48 250 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 DAC7742Y
B
DAC7742YC/250 ACTIVE LQFP PT 48 250 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 DAC7742Y
C

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 7-Oct-2021

Addendum-Page 2
 PACKAGE OUTLINE
PT0048A SCALE 2.000
LQFP - 1.6 mm max height
LOW PROFILE QUAD FLATPACK

9.2
8.8
7.2
B
6.8

9.2 7.2
8.8 6.8

0.27
48X
0.17
0.08 C A B
44X 0.5

SEE DETAIL A 4X 5.5

1.6 MAX C

SEATING PLANE

0.1 C

1.45
0.25 1.35
GAGE PLANE

0.75 0.5 MIN

0 -7 0.45

DETAIL A
A15.000

4215159/A 12/2021
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026.
4. This may also be a thermally enhanced plastic package with leads conected to the die pads.

www.ti.com
 EXAMPLE BOARD LAYOUT
PT0048A LQFP - 1.6 mm max height
LOW PROFILE QUAD FLATPACK

PKG
SYMM
48 37
SEE SOLDER MASK
DETAILS

48X (1.6)

1
36

48X (0.3)

44X (0.5)

PKG SYMM (8.2)

(R0.05) TYP

12 25

13 24

(8.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE 10.000

0.05 MAX 0.05 MIN

ALLAROUND ALL AROUND

EXPOSED METAL EXPOSED METAL

METAL EDGE SOLDER MASK METAL UNDER

SOLDER MASK
OPENING OPENING SOLDER MASK
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
SOLDER MASK DETAILS 4215159/A 12/2021
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PT0048A LQFP - 1.6 mm max height
LOW PROFILE QUAD FLATPACK

PKG
SYMM
48 37

48X (1.6)

1
36

48X (0.3)

44X (0.5)

PKG SYMM (8.2)

(R0.05) TYP

12 25

13 24

(8.2)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE: 10X

4215159/A 12/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
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