HT48R06A-1/HT48C06

8-Bit Cost-Effective I/O Type OTP/Mask MCU

Features
· Operating voltage: · HALT function and wake-up feature reduce power
fSYS=4MHz: 2.2V~5.5V consumption
fSYS=8MHz: 3.3V~5.5V · Up to 0.5ms instruction cycle with 8MHz system clock
· 13 bidirectional I/O lines at VDD=5V
· An interrupt input shared with an I/O line · Allinstructionsinoneortwomachinecycles
· 8-bit programmable timer/event counter with over- · 14-bit table read instruction
flow interrupt and 8-stage prescaler · Two-level subroutine nesting
· On-chip crystal and RC oscillator · Bit manipulation instruction
· Watchdog Timer · 63 powerful instructions
· 1024´14 program memory ROM · Low voltage reset function
· 64´8 data memory RAM · 16-pin SSOP package
· Buzzer driving pair and PFD supported 18-pin DIP/SOP package

General Description
The HT48R06A-1/HT48C06 are 8-bit high perfor- The advantages of low power consumption, I/O flexibil-
mance, RISC architecture microcontroller devices spe- ity, timer functions, oscillator options, HALT and
cifically designed for cost-effective multiple I/O control wake-up functions, watchdog timer, buzzer driver, as
product applications. The mask version HT48C06 is well as low cost, enhance the versatility of these devices
fully pin and functionally compatible with the OTP ver- to suit a wide range of application possibilities such as
sion HT48R06A-1 device. industrial control, consumer products, subsystem con-
trollers, etc.

Block Diagram
IN T /P C 0

In te rru p t
C ir c u it
S T A C K 0 M P r e s c a le r fS Y S
T M R U
S T A C K 1 X T M R /P C 1
P ro g ra m P ro g ra m IN T C
R O M C o u n te r T M R C

P C 0 P C 1

In s tr u c tio n
R e g is te r M P M D A T A W D T S
U M fS /4
M e m o ry Y S
X W D T P r e s c a le r W D T U
X

R C O S C
P C C P O R T C
P C 0 ~ P C 1
In s tr u c tio n M U X P C
D e c o d e r
B Z /B Z
P B C P O R T B
A L U S T A T U S P B 0 ~ P B 2
P B
T im in g S h ifte r
G e n e ra to r

P A C P O R T A
P A 0 ~ P A 7
P A
O S C 2 O S C 1 A C C
R E S
V D D
V S S

Rev. 1.20 1 May 12, 2003

This datasheet has been downloaded from http://www.digchip.com at this page

 HT48R06A-1/HT48C06

Pin Assignment

P A 3 1 1 8 P A 4
P A 3 1 1 6 P A 4 P A 2 2 1 7 P A 5
P A 2 2 1 5 P A 5 P A 1 3 1 6 P A 6
P A 1 3 1 4 P A 6 P A 0 4 1 5 P A 7
P A 0 4 1 3 P A 7 P B 2 5 1 4 O S C 2
P B 0 /B Z 5 1 2 O S C 2 P B 1 /B Z 6 1 3 O S C 1
V S S 6 1 1 O S C 1 P B 0 /B Z 7 1 2 V D D
P C 0 /IN T 7 1 0 V D D V S S 8 1 1 R E S
P C 1 /T M R 8 9 R E S P C 0 /IN T 9 1 0 P C 1 /T M R

H T 4 8 R 0 6 A -1 /H T 4 8 C 0 6 H T 4 8 R 0 6 A -1 /H T 4 8 C 0 6
1 6 S S O P -A 1 8 D IP -A /S O P -A

Pad Assignment
HT48C06

P A 1

P A 2

P A 3

P A 4

P A 5

P A 6
1 8 1 7 1 6 1 5 1 4 1 3

(0 ,0 )
P A 0 1
1 2 P A 7

P B 2 2 1 1 O S C 2

P B 1 /B Z 3

4 5 6 7 8 9 1 0
P B 0 /B Z

V S S

P C 0 /IN T

P C 1 /T M R

R E S

V D D

O S C 1

* The IC substrate should be connected to VSS in the PCB layout artwork.

Rev. 1.20 2 May 12, 2003

 HT48R06A-1/HT48C06

Pad Description
Pad Name I/O Options Description
Bidirectional 8-bit input/output port. Each bit can be configured as wake-up
Pull-high* input by options. Software instructions determine the CMOS output or
PA0~PA7 I/O
Wake-up Schmitt trigger input with a pull-high resistor (determined by pull-high op-
tions).
Bidirectional 3-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with a pull-high resistor (determined by
PB0/BZ
Pull-high* pull-high options).
PB1/BZ I/O
I/O or BZ/BZ The PB0 and PB1 are pin-shared with the BZ and BZ, respectively. Once the
PB2
PB0 and PB1 are selected as buzzer driving outputs, the output signals come
from an internal PFD generator (shared with a timer/event counter).
VSS ¾ ¾ Negative power supply, ground
Bidirectional I/O lines. Software instructions determine the CMOS output or
Schmitt trigger input with a pull-high resistor (determined by pull-high op-
PC0/INT
I/O Pull-high* tions). The external interrupt and timer input are pin-shared with the PC0 and
PC1/TMR
PC1, respectively. The external interrupt input is activated on a high to low
transition.
RES I ¾ Schmitt trigger reset input. Active low

VDD ¾ ¾ Positive power supply

OSC1, OSC2 are connected to an RC network or Crystal (determined by op-
OSC1 I Crystal
tions) for the internal system clock. In the case of RC operation, OSC2 is the
OSC2 O or RC
output terminal for 1/4 system clock.

* All pull-high resistors are controlled by an option bit.

Absolute Maximum Ratings

Supply Voltage ...........................VSS-0.3V to VSS+6.0V Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-40°C to 85°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.

Rev. 1.20 3 May 12, 2003

 HT48R06A-1/HT48C06

D.C. Characteristics Ta=25°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions

¾ fSYS=4MHz 2.2 ¾ 5.5 V

VDD Operating Voltage
¾ fSYS=8MHz 3.3 ¾ 5.5 V

3V ¾ 0.6 1.5 mA
IDD1 Operating Current (Crystal OSC) No load, fSYS=4MHz
5V ¾ 2 4 mA

3V ¾ 0.8 1.5 mA
IDD2 Operating Current (RC OSC) No load, fSYS=4MHz
5V ¾ 2.5 4 mA
IDD3 Operating Current (Crystal OSC) 5V No load, fSYS=8MHz ¾ 3 5 mA

3V ¾ ¾ 5 mA
ISTB1 Standby Current (WDT Enabled) No load, system HALT
5V ¾ ¾ 10 mA
3V ¾ ¾ 1 mA
ISTB2 Standby Current (WDT Disabled) No load, system HALT
5V ¾ ¾ 2 mA
Input Low Voltage for I/O Ports,
VIL1 ¾ ¾ 0 ¾ 0.3VDD V
TMR and INT
Input High Voltage for I/O Ports,
VIH1 ¾ ¾ 0.7VDD ¾ VDD V
TMR and INT
VIL2 Input Low Voltage (RES) ¾ ¾ 0 ¾ 0.4VDD V
VIH2 Input High Voltage (RES) ¾ ¾ 0.9VDD ¾ VDD V
VLVR Low Voltage Reset ¾ LVR enabled 2.7 3.0 3.3 V

3V 4 8 ¾ mA
IOL I/O Port Sink Current VOL=0.1VDD
5V 10 20 ¾ mA

3V -2 -4 ¾ mA
IOH I/O Port Source Current VOH=0.9VDD
5V -5 -10 ¾ mA

3V ¾ 40 60 80 kW
RPH Pull-high Resistance
5V ¾ 10 30 50 kW

Rev. 1.20 4 May 12, 2003

 HT48R06A-1/HT48C06

A.C. Characteristics Ta=25°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions

¾ 2.2V~5.5V 400 ¾ 4000 kHz

fSYS1 System Clock (Crystal OSC)
¾ 3.3V~5.5V 400 ¾ 8000 kHz

¾ 2.2V~5.5V 400 ¾ 4000 kHz

fSYS2 System Clock (RC OSC)
¾ 3.3V~5.5V 400 ¾ 8000 kHz

¾ 2.2V~5.5V 0 ¾ 4000 kHz

fTIMER Timer I/P Frequency (TMR)
¾ 3.3V~5.5V 0 ¾ 8000 kHz

3V ¾ 45 90 180 ms
tWDTOSC Watchdog Oscillator Period
5V ¾ 32 65 130 ms
3V 11 23 46 ms
tWDT1 Watchdog Time-out Period (RC) Without WDT prescaler
5V 8 17 33 ms
Watchdog Time-out Period
tWDT2 ¾ Without WDT prescaler ¾ 1024 ¾ tSYS
(System Clock)
tRES External Reset Low Pulse Width ¾ ¾ 1 ¾ ¾ ms
tSST System Start-up Timer Period ¾ Wake-up from HALT ¾ 1024 ¾ tSYS

tINT Interrupt Pulse Width ¾ ¾ 1 ¾ ¾ ms

Rev. 1.20 5 May 12, 2003

 HT48R06A-1/HT48C06

Functional Description
Execution Flow When executing a jump instruction, conditional skip ex-
The system clock for the microcontroller is derived from ecution, loading PCL register, subroutine call, initial re-
either a crystal or an RC oscillator. The system clock is set, internal interrupt, external interrupt or return from
internally divided into four non-overlapping clocks. One subroutine, the PC manipulates the program transfer by
instruction cycle consists of four system clock cycles. loading the address corresponding to each instruction.

Instruction fetching and execution are pipelined in such The conditional skip is activated by instructions. Once
a way that a fetch takes an instruction cycle while de- the condition is met, the next instruction, fetched during
coding and execution takes the next instruction cycle. the current instruction execution, is discarded and a
However, the pipelining scheme causes each instruc- dummy cycle replaces it to get the proper instruction.
tion to effectively execute in a cycle. If an instruction Otherwise proceed with the next instruction.
changes the program counter, two cycles are required to The lower byte of the program counter (PCL) is a read-
complete the instruction. able and writable register (06H). Moving data into the
PCL performs a short jump. The destination will be
Program Counter - PC within 256 locations.
The program counter (PC) controls the sequence in When a control transfer takes place, an additional
which the instructions stored in program ROM are exe- dummy cycle is required.
cuted and its contents specify full range of program
memory.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.

T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4
S y s te m C lo c k

O S C 2 ( R C o n ly )

P C P C P C + 1 P C + 2

F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 ) F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )

Execution flow

Program Counter
Mode
*9 *8 *7 *6 *5 *4 *3 *2 *1 *0
Initial Reset 0 0 0 0 0 0 0 0 0 0
External Interrupt 0 0 0 0 0 0 0 1 0 0
Timer/Event Counter Overflow 0 0 0 0 0 0 1 0 0 0
Skip PC+2
Loading PCL *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from Subroutine S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program counter

Note: *9~*0: Program counter bits S9~S0: Stack register bits

#9~#0: Instruction code bits @7~@0: PCL bits

Rev. 1.20 6 May 12, 2003

 HT48R06A-1/HT48C06

Program Memory - ROM · Table location

The program memory is used to store the program in- Any location in the program memory can be used as
structions which are to be executed. It also contains look-up tables. The instructions ²TABRDC [m]² (the
data, table, and interrupt entries, and is organized into current page, 1 page=256 words) and ²TABRDL [m]²
1024´14 bits, addressed by the program counter and ta- (the last page) transfer the contents of the lower-order
ble pointer. byte to the specified data memory, and the
Certain locations in the program memory are reserved higher-order byte to TBLH (08H). Only the destination
for special usage: of the lower-order byte in the table is well-defined, the
other bits of the table word are transferred to the lower
· Location 000H
portion of TBLH, and the remaining 2 bits are read as
This area is reserved for program initialization. After ²0². The Table Higher-order byte register (TBLH) is
chip reset, the program always begins execution at lo- read only. The table pointer (TBLP) is a read/write reg-
cation 000H. ister (07H), which indicates the table location. Before
· Location 004H accessing the table, the location must be placed in
This area is reserved for the external interrupt service TBLP. The TBLH is read only and cannot be restored.
program. If the INT input pin is activated, the interrupt If the main routine and the ISR (Interrupt Service Rou-
is enabled and the stack is not full, the program begins tine) both employ the table read instruction, the con-
execution at location 004H. tents of the TBLH in the main routine are likely to be
changed by the table read instruction used in the ISR.
· Location 008H
Errors can occur. In other words, using the table read
This area is reserved for the timer/event counter inter-
instruction in the main routine and the ISR simulta-
rupt service program. If a timer interrupt results from a
neously should be avoided. However, if the table read
timer/event counter overflow, and if the interrupt is en-
instruction has to be applied in both the main routine
abled and the stack is not full, the program begins ex-
and the ISR, the interrupt is supposed to be disabled
ecution at location 008H.
prior to the table read instruction. It will not be enabled
until the TBLH has been backed up. All table related
0 0 0 H instructions require two cycles to complete the opera-
D e v ic e In itia liz a tio n P r o g r a m tion. These areas may function as normal program
0 0 4 H memory depending upon the requirements.
E x te r n a l In te r r u p t S u b r o u tin e
0 0 8 H Stack Register - STACK
T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e
This is a special part of the memory which is used to
P ro g ra m save the contents of the program counter (PC) only. The
n 0 0 H M e m o ry stack is organized into 2 levels and is neither part of the
L o o k - u p T a b le ( 2 5 6 w o r d s ) data nor part of the program space, and is neither read-
n F F H
able nor writable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
L o o k - u p T a b le ( 2 5 6 w o r d s )
3 F F H stack. At the end of a subroutine or an interrupt routine,
1 4 b its signaled by a return instruction (RET or RETI), the pro-
N o te : n ra n g e s fro m 0 to 3 gram counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
Program memory stack.

Table Location
Instruction
*9 *8 *7 *6 *5 *4 *3 *2 *1 *0
TABRDC [m] P9 P8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m] 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table location

Note: *9~*0: Table location bits P9, P8: Current program counter bits
@7~@0: Table pointer bits

Rev. 1.20 7 May 12, 2003

 HT48R06A-1/HT48C06

If the stack is full and a non-masked interrupt takes In d ir e c t A d d r e s s in g R e g is te r

0 0 H
place, the interrupt request flag will be recorded but the 0 1 H M P
acknowledgment will be inhibited. When the stack 0 2 H
pointer is decremented (by RET or RETI), the interrupt 0 3 H
will be serviced. This feature prevents stack overflow al- 0 4 H
lowing the programmer to use the structure more easily. 0 5 H A C C
In a similar case, if the stack is full and a ²CALL² is sub- 0 6 H P C L
sequently executed, stack overflow occurs and the first 0 7 H T B L P
entry will be lost (only the most recent 2 return ad- 0 8 H T B L H

dresses are stored). 0 9 H W D T S

0 A H S T A T U S
0 B H IN T C S p e c ia l P u r p o s e
Data Memory - RAM
0 C H D A T A M E M O R Y
The data memory is designed with 81´8 bits. The data 0 D H T M R
memory is divided into two functional groups: special 0 E H T M R C
function registers and general purpose data memory 0 F H
(64´8). Most are read/write, but some are read only. 1 0 H
1 1 H
The special function registers include the indirect ad-
1 2 H P A
d re s s in g r e g i s t e r ( 0 0 H ) , t i m e r / ev e n t co u n t e r
1 3 H P A C
(TMR;0DH), timer/event counter control register 1 4 H P B
(TMRC;0EH), program counter lower-order byte regis- 1 5 H P B C
ter (PCL;06H), memory pointer register (MP;01H), ac- 1 6 H P C
cumulator (ACC;05H), table pointer (TBLP;07H), table 1 7 H P C C
higher-order byte register (TBLH;08H), status register 1 8 H
(STATUS;0AH), interrupt control register (INTC;0BH), 1 9 H : U n u s e d
Watchdog Timer option setting register (WDTS;09H), 1 A H R e a d a s "0 0 "
I/O registers (PA;12H, PB;14H, PC;16H) and I/O control 1 B H
registers (PAC;13H, PBC;15H, PCC;17H). The remain- 1 C H

ing space before the 40H is reserved for future ex- 1 D H

1 E H
panded usage and reading these locations will get
1 F H
²00H². The general purpose data memory, addressed 2 0 H
from 40H to 7FH, is used for data and control informa-
3 F H
tion under instruction commands. 4 0 H
G e n e ra l P u rp o s e
All of the data memory areas can handle arithmetic,
D A T A M E M O R Y
logic, increment, decrement and rotate operations di- (6 4 B y te s )
rectly. Except for some dedicated bits, each bit in the
7 F H
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through RAM mapping
memory pointer register (MP;01H).
can carry out immediate data operations. The data
Indirect Addressing Register
movement between two data memory locations must
Location 00H is an indirect addressing register that is pass through the accumulator.
not physically implemented. Any read/write operation of
[00H] accesses data memory pointed to by MP (01H). Arithmetic and Logic Unit - ALU
Reading location 00H itself indirectly will return the re-
This circuit performs 8-bit arithmetic and logic opera-
sult 00H. Writing indirectly results in no operation.
tions. The ALU provides the following functions:
The memory pointer register MP (01H) is a 7-bit register. · Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
The bit 7 of MP is undefined and reading will return the
· Logic operations (AND, OR, XOR, CPL)
result ²1². Any writing operation to MP will only transfer
· Rotation (RL, RR, RLC, RRC)
the lower 7-bit data to MP.
· Increment and Decrement (INC, DEC)

Accumulator · Branch decision (SZ, SNZ, SIZ, SDZ ....)

The accumulator is closely related to ALU operations. It The ALU not only saves the results of a data operation
is also mapped to location 05H of the data memory and but also changes the status register.

Rev. 1.20 8 May 12, 2003

 HT48R06A-1/HT48C06

Status Register - STATUS terrupt requires servicing within the service routine, the
This 8-bit register (0AH) contains the zero flag (Z), carry EMI bit and the corresponding bit of INTC may be set to
flag (C), auxiliary carry flag (AC), overflow flag (OV), allow interrupt nesting. If the stack is full, the interrupt re-
power down flag (PD), and watchdog time-out flag (TO). quest will not be acknowledged, even if the related inter-
It also records the status information and controls the rupt is enabled, until the SP is decremented. If
operation sequence. immediate service is desired, the stack must be pre-
vented from becoming full.
With the exception of the TO and PD flags, bits in the
status register can be altered by instructions like most All these kinds of interrupts have a wake-up capability.
other registers. Any data written into the status register As an interrupt is serviced, a control transfer occurs by
will not change the TO or PD flag. In addition operations pushing the program counter onto the stack, followed by
related to the status register may give different results a branch to a subroutine at specified location in the pro-
from those intended. The TO flag can be affected only gram memory. Only the program counter is pushed onto
by system power-up, a WDT time-out or executing the the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
²CLR WDT² or ²HALT² instruction. The PD flag can be
which corrupts the desired control sequence, the con-
affected only by executing the ²HALT² or ²CLR WDT²
tents should be saved in advance.
instruction or a system power-up.
External interrupts are triggered by a high to low transi-
The Z, OV, AC and C flags generally reflect the status of
tion of INT and the related interrupt request flag (EIF; bit
the latest operations.
4 of INTC) will be set. When the interrupt is enabled, the
In addition, on entering the interrupt sequence or exe- stack is not full and the external interrupt is active, a sub-
cuting the subroutine call, the status register will not be routine call to location 04H will occur. The interrupt re-
pushed onto the stack automatically. If the contents of quest flag (EIF) and EMI bits will be cleared to disable
the status are important and if the subroutine can cor- other interrupts.
rupt the status register, precautions must be taken to
The internal timer/event counter interrupt is initialized by
save it properly.
setting the timer/event counter interrupt request flag
Interrupt (TF; bit 5 of INTC), caused by a timer overflow. When
the interrupt is enabled, the stack is not full and the TF
The device provides an external interrupt and internal
bit is set, a subroutine call to location 08H will occur. The
timer/event counter interrupts. The Interrupt Control
related interrupt request flag (TF) will be reset and the
Register (INTC;0BH) contains the interrupt control bits
EMI bit cleared to disable further interrupts.
to set the enable or disable and the interrupt request
flags. During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the ²RETI²
Once an interrupt subroutine is serviced, all the other in-
instruction is executed or the EMI bit and the related in-
terrupts will be blocked (by clearing the EMI bit). This
terrupt control bit are set to 1 (of course, if the stack is
scheme may prevent any further interrupt nesting. Other
not full). To return from the interrupt subroutine, ²RET²
interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If a certain in- or ²RETI² may be invoked. RETI will set the EMI bit to en-
able an interrupt service, but RET will not.

Labels Bits Function

C is set if the operation results in a carry during an addition operation or if a borrow does not take
C 0 place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the
AC 1
high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z 2 Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
OV 3
highest-order bit, or vice versa; otherwise OV is cleared.
PD is cleared by system power-up or executing the ²CLR WDT² instruction. PD is set by execut-
PD 4
ing the ²HALT² instruction.
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set
TO 5
by a WDT time-out.
¾ 6 Unused bit, read as ²0²
¾ 7 Unused bit, read as ²0²
Status register

Rev. 1.20 9 May 12, 2003

 HT48R06A-1/HT48C06

Register Bit No. Label Function

0 EMI Controls the master (global) interrupt (1= enabled; 0= disabled)
1 EEI Controls the external interrupt (1= enabled; 0= disabled)
2 ETI Controls the timer/event counter interrupt (1= enabled; 0= disabled)

INTC 3 ¾ Unused bit, read as ²0²

(0BH) 4 EIF External interrupt request flag (1= active; 0= inactive)
5 TF Internal timer/event counter request flag (1= active; 0= inactive)
6 ¾ Unused bit, read as ²0²
7 ¾ Unused bit, read as ²0²

INTC register

Interrupts, occurring in the interval between the rising Both are designed for system clocks, namely the RC os-
edges of two consecutive T2 pulses, will be serviced on cillator and the Crystal oscillator, which are determined
the latter of the two T2 pulses, if the corresponding inter- by the options. No matter what oscillator type is se-
rupts are enabled. In the case of simultaneous requests lected, the signal provides the system clock. The HALT
the following table shows the priority that is applied. mode stops the system oscillator and ignores an exter-
These can be masked by resetting the EMI bit. nal signal to conserve power.
No. Interrupt Source Priority Vector If an RC oscillator is used, an external resistor between
OSC1 and VDD is required and the resistance must
a External Interrupt 1 04H
range from 24kW to 1MW. The system clock, divided by
b Timer/Event Counter Overflow 2 08H 4, is available on OSC2, which can be used to synchro-
The timer/event counter interrupt request flag (TF), ex- nize external logic. The RC oscillator provides the most
ternal interrupt request flag (EIF), enable timer/event cost effective solution. However, the frequency of oscil-
counter bit (ETI), enable external interrupt bit (EEI) and lation may vary with VDD, temperatures and the chip it-
enable master interrupt bit (EMI) constitute an interrupt self due to process variations. It is, therefore, not
control register (INTC) which is located at 0BH in the suitable for timing sensitive operations where an accu-
data memory. EMI, EEI, ETI are used to control the en- rate oscillator frequency is desired.
abling/disabling of interrupts. These bits prevent the re- If the Crystal oscillator is used, a crystal across OSC1
quested interrupt from being serviced. Once the and OSC2 is needed to provide the feedback and phase
interrupt request flags (TF, EIF) are set, they will remain shift required for the oscillator, and no other external
in the INTC register until the interrupts are serviced or components are required. Instead of a crystal, a resona-
cleared by a software instruction. tor can also be connected between OSC1 and OSC2 to
It is recommended that a program does not use the get a frequency reference, but two external capacitors in
²CALL subroutine² within the interrupt subroutine. In- OSC1 and OSC2 are required (If the oscillating fre-
terrupts often occur in an unpredictable manner or need quency is less than 1MHz).
to be serviced immediately in some applications. If only The WDT oscillator is a free running on-chip RC oscilla-
one stack is left and enabling the interrupt is not well tor, and no external components are required. Even if
controlled, the original control sequence will be dam- the system enters the power down mode, the system
aged once the ²CALL² operates in the interrupt subrou- clock is stopped, but the WDT oscillator still works with a
tine. period of approximately 65ms/5V. The WDT oscillator
can be disabled by options to conserve power.
Oscillator Configuration
There are two oscillator circuits in the microcontroller.
V D D

O S C 1 O S C 1
4 7 0 p F

O S C 2 fS Y S /4 O S C 2
N M O S O p e n D r a in
C r y s ta l O s c illa to r R C O s c illa to r
System oscillator

Rev. 1.20 10 May 12, 2003

 HT48R06A-1/HT48C06

Watchdog Timer - WDT The WDT overflow under normal operation will initialize
The clock source of WDT is implemented by a dedicated ²chip reset² and set the status bit ²TO². But in the HALT
RC oscillator (WDT oscillator) or instruction clock (sys- mode, the overflow will initialize a ²warm reset², and
tem clock divided by 4), decided by options. This timer is only the PC and SP are reset to zero. To clear the con-
designed to prevent a software malfunction or sequence tents of WDT (including the WDT prescaler), three
from jumping to an unknown location with unpredictable methods are adopted; external reset (a low level to
results. The Watchdog Timer can be disabled by an op- RES), software instruction and a ²HALT² instruction.
tion. If the Watchdog Timer is disabled, all the execu- The software instruction include ²CLR WDT² and the
tions related to the WDT result in no operation. other set - ²CLR WDT1² and ²CLR WDT2². Of these
Once the internal WDT oscillator (RC oscillator with a two types of instruction, only one can be active depend-
period of 65ms/5V normally) is selected, it is first divided ing on the option - ²CLR WDT times selection option². If
by 256 (8-stage) to get the nominal time-out period of the ²CLR WDT² is selected (i.e. CLRWDT times equal
approximately 17ms/5V. This time-out period may vary one), any execution of the ²CLR WDT² instruction will
with temperatures, VDD and process variations. By in- clear the WDT. In the case that ²CLR WDT1² and ²CLR
voking the WDT prescaler, longer time-out periods can WDT2² are chosen (i.e. CLRWDT times equal two),
be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of these two instructions must be executed to clear the
the WDTS) can give different time-out periods. If WS2, WDT; otherwise, the WDT may reset the chip as a result
WS1, and WS0 are all equal to 1, the division ratio is up of time-out.
to 1:128, and the maximum time-out period is 2.1s/5V
seconds. If the WDT oscillator is disabled, the WDT Power Down Operation - HALT
clock may still come from the instruction clock and oper- The HALT mode is initialized by the ²HALT² instruction
ate in the same manner except that in the HALT state and results in the following...
the WDT may stop counting and lose its protecting pur- · The system oscillator will be turned off but the WDT
pose. In this situation the logic can only be restarted by oscillator keeps running (if the WDT oscillator is se-
external logic. The high nibble and bit 3 of the WDTS are lected).
reserved for user¢s defined flags, which can be used to · The contents of the on chip RAM and registers remain
indicate some specified status. unchanged.
If the device operates in a noisy environment, using the · WDT and WDT prescaler will be cleared and re-
on-chip RC oscillator (WDT OSC) is strongly recom- counted again (if the WDT clock is from the WDT os-
mended, since the HALT will stop the system clock. cillator).
· AlloftheI/Oportsmaintaintheiroriginalstatus.
WS2 WS1 WS0 Division Ratio
· The PD flag is set and the TO flag is cleared.
0 0 0 1:1
The system can leave the HALT mode by means of an
0 0 1 1:2 external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
0 1 0 1:4
causes a device initialization and the WDT overflow per-
0 1 1 1:8 forms a ²warm reset². After the TO and PD flags are ex-
1 0 0 1:16 amined, the reason for chip reset can be determined.
The PD flag is cleared by system power-up or executing
1 0 1 1:32
the ²CLR WDT² instruction and is set when executing
1 1 0 1:64 the ²HALT² instruction. The TO flag is set if the WDT
1 1 1 1:128 time-out occurs, and causes a wake-up that only resets
the PC and SP; the others keep their original status.
WDTS register

S y s te m C lo c k /4
W D T P r e s c a le r
O p tio n 8 - b it C o u n te r 7 - b it C o u n te r
S e le c t
W D T
O S C
8 -to -1 M U X W S 0 ~ W S 2

W D T T im e - o u t

Watchdog Timer

Rev. 1.20 11 May 12, 2003

 HT48R06A-1/HT48C06

The port A wake-up and interrupt methods can be con- V D D

sidered as a continuation of normal execution. Each bit R E S
tS S T
in port A can be independently selected to wake up the
device by the options. Awakening from an I/O port stim- S S T T im e - o u t
ulus, the program will resume execution of the next in-
C h ip R e s e t
struction. If it is awakening from an interrupt, two
sequences may happen. If the related interrupt is dis- Reset timing chart
abled or the interrupt is enabled but the stack is full, the
V D D
program will resume execution at the next instruction. If
the interrupt is enabled and the stack is not full, the regu-
lar interrupt response takes place. If an interrupt request
flag is set to ²1² before entering the HALT mode, the R E S
wake-up function of the related interrupt will be disabled.
Once a wake-up event occurs, it takes 1024 tSYS (sys-
tem clock period) to resume normal operation. In other
words, a dummy period will be inserted after wake-up. If
the wake-up results from an interrupt acknowledgment, Reset circuit
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next H A L T W a rm R e s e t
instruction execution, this will be executed immediately
after the dummy period is finished. W D T

To minimize power consumption, all the I/O pins should

R E S
be carefully managed before entering the HALT status.
C o ld
R e s e t
Reset S S T
O S C 1 1 0 - b it R ip p le
There are three ways in which a reset can occur: C o u n te r

· RES reset during normal operation

S y s te m R e s e t
· RES reset during HALT
· WDT time-out reset during normal operation
Reset configuration
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re - When a system reset occurs, the SST delay is added
set² that resets only the PC and SP, leaving the other cir- during the reset period. Any wake-up from HALT will en-
cuits in their original state. Some registers remain un- able the SST delay.
changed during other reset conditions. Most registers
An extra option load time delay is added during system
are reset to the ²initial condition² when the reset condi-
reset (power-up, WDT time-out at normal mode or RES
tions are met. By examining the PD and TO flags, the
reset).
program can distinguish between different ²chip resets².
The functional unit chip reset status are shown below.
TO PD RESET Conditions
PC 000H
0 0 RES reset during power-up
Interrupt Disable
u u RES reset during normal operation Prescaler Clear
0 1 RES wake-up HALT Clear. After master reset,
WDT
WDT begins counting
1 u WDT time-out during normal operation
Timer/Event Counter Off
1 1 WDT wake-up HALT
Input/Output Ports Input mode
Note: ²u² means ²unchanged² SP Points to the top of the stack
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.

Rev. 1.20 12 May 12, 2003

 HT48R06A-1/HT48C06

The states of the registers is summarized in the table.

Reset WDT time-out RES Reset RES Reset WDT Time-out
Register
(Power On) (Normal Operation) (Normal Operation) (HALT) (HALT)*
TMR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
TMRC 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu
Program
000H 000H 000H 000H 000H
Counter
MP -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu
ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu
STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu
INTC --00 -000 --00 -000 --00 -000 --00 -000 --uu -uuu
WDTS 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu
PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PB ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu
PBC ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu
PC ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu
PCC ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu

Note: ²*² means ²warm reset²

²u² means ²unchanged²
²x² means ²unknown²

Timer/Event Counter The timer/event counter can generate PFD signal by us-
A timer/event counter (TMR) is implemented in the ing external or internal clock and PFD frequency is de-
microcontroller. The timer/event counter contains an 8-bit termine by the equation fINT/[2´(256-N)].
programmable count-up counter and the clock may come There are 2 registers related to the timer/event counter;
from an external source or the system clock. TMR ([0DH]), TMRC ([0EH]). Two physical registers are
Using external clock input allows the user to count exter- mapped to TMR location; writing TMR makes the start-
nal events, measure time internals or pulse widths, or ing value be placed in the timer/event counter preload
generate an accurate time base. While using the inter- register and reading TMR retrieves the contents of the
nal clock allows the user to generate an accurate time timer/event counter. The TMRC is a timer/event counter
base. control register, which defines some options.

fS Y S 8 - s ta g e P r e s c a le r
f IN T D a ta B u s
8 -1 M U X
T M 1
T M 0 T im e r /E v e n t C o u n te r R e lo a d
P S C 2 ~ P S C 0 T M R P r e lo a d R e g is te r

T E

P u ls e W id th T im e r /E v e n t O v e r flo w
T M 1 M e a s u re m e n t C o u n te r
T M 0 to In te rru p t
M o d e C o n tro l
T O N
1 /2 B Z
B Z

Timer/Event Counter

Rev. 1.20 13 May 12, 2003

 HT48R06A-1/HT48C06

Label
Bits Function
(TMRC)
To define the prescaler stages, PSC2, PSC1, PSC0=
000: fINT=fSYS/2
001: fINT=fSYS/4
010: fINT=fSYS/8
PSC0~PSC2 0~2 011: fINT=fSYS/16
100: fINT=fSYS/32
101: fINT=fSYS/64
110: fINT=fSYS/128
111: fINT=fSYS/256
To define the TMR active edge of the timer/event counter
TE 3
(0=active on low to high; 1=active on high to low)
To enable or disable timer counting
TON 4
(0=disabled; 1=enabled)
¾ 5 Unused bit, read as ²0²
To define the operating mode
01=Event count mode (external clock)
TM0 6
10=Timer mode (internal clock)
TM1 7
11=Pulse width measurement mode
00=Unused

TMRC register

The TM0, TM1 bits define the operating mode. The tomatically after the measurement cycle is completed.
event count mode is used to count external events, But in the other two modes the TON can only be reset by
which means the clock source comes from an external instructions. The overflow of the timer/event counter is
(TMR) pin. The timer mode functions as a normal timer one of the wake-up sources. No matter what the opera-
with the clock source coming from the fINT clock. The tion mode is, writing a 0 to ETI can disable the interrupt
pulse width measurement mode can be used to count service.
the high or low level duration of the external signal In the case of timer/event counter OFF condition, writing
(TMR). The counting is based on the fINT clock. data to the timer/event counter preload register will also
In the event count or timer mode, once the timer/event reload that data to the timer/event counter. But if the
counter starts counting, it will count from the current timer/event counter is turned on, data written to it will
contents in the timer/event counter to FFH. Once over- only be kept in the timer/event counter preload register.
flow occurs, the counter is reloaded from the timer/event The timer/event counter will still operate until overflow
counter preload register and generates the interrupt re- occurs. When the timer/event counter (reading TMR) is
quest flag (TF; bit 5 of INTC) at the same time. read, the clock will be blocked to avoid errors. As clock
blocking may results in a counting error, this must be
In the pulse width measurement mode with the TON
taken into consideration by the programmer.
and TE bits equal to one, once the TMR has received a
transient from low to high (or high to low if the TE bits is The bit0~2 of the TMRC can be used to define the
²0²) it will start counting until the TMR returns to the orig- pre-scaling stages of the internal clock sources of the
inal level and resets the TON. The measured result will timer/event counter. The definitions are as shown. The
remain in the timer/event counter even if the activated overflow signal of the timer/event counter can be used
transient occurs again. In other words, only one cycle to generate PFD signals for buzzer driving.
measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it re- Input/Output Ports
ceives further transient pulse. Note that, in this operat- There are 13 bidirectional input/output lines in the
ing mode, the timer/event counter starts counting not microcontroller, labeled from PA to PC, which are
according to the logic level but according to the transient mapped to the data memory of [12H], [14H] and [16H]
edges. In the case of counter overflows, the counter is respectively. All of these I/O ports can be used for input
reloaded from the timer/event counter preload register and output operations. For input operation, these ports
and issues the interrupt request just like the other two are non-latching, that is, the inputs must be ready at the
modes. To enable the counting operation, the timer ON T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H
bit (TON; bit 4 of TMRC) should be set to 1. In the pulse or 16H). For output operation, all the data is latched and
width measurement mode, the TON will be cleared au- remains unchanged until the output latch is rewritten.

Rev. 1.20 14 May 12, 2003

 HT48R06A-1/HT48C06

V D D

C o n tr o l B it P U
D a ta B u s D Q

W r ite C o n tr o l R e g is te r C K Q B
C h ip R e s e t S
P A 0 ~ P A 7
P B 0 ~ P B 2
R e a d C o n tr o l R e g is te r P C 0 ~ P C 1
D a ta B it
D Q

W r ite D a ta R e g is te r C K Q B
S
M
P B 0 U
( P B 0 , P B 1 O n ly ) X
E X T
B Z E N
M ( P B 0 , P B 1 O n ly )
U
X
R e a d D a ta R e g is te r
S y s te m W a k e -u p
( P A o n ly ) O P 0 ~ O P 7
IN T fo r P C 0 O n ly
T M R fo r P C 1 O n ly

Input/output ports

Each I/O line has its own control register (PAC, PBC, There is a pull-high option available for all I/O lines.
PCC) to control the input/output configuration. With this Once the pull-high option is selected, all I/O lines have
control register, CMOS output or Schmitt trigger input pull-high resistors. Otherwise, the pull-high resistors are
with or without pull-high resistor structures can be re- absent. It should be noted that a non-pull-high I/O line
configured dynamically (i.e. on-the-fly) under software operating in input mode will cause a floating state.
control. To function as an input, the corresponding latch
The PB0 and PB1 are pin-shared with BZ and BZ signal,
of the control register must write ²1². The input source respectively. If the BZ/BZ option is selected, the output
also depends on the control register. If the control regis- signal in output mode of PB0/PB1 will be the PFD signal
ter bit is ²1², the input will read the pad state. If the con- generated by timer/event counter overflow signal. The
trol register bit is ²0², the contents of the latches will input mode always remaining its original functions.
move to the internal bus. The latter is possible in the Once the BZ/BZ option is selected, the buzzer output
²read-modify-write² instruction. signals are controlled by PB0 data register only. The I/O
For output function, CMOS is the only configuration. functions of PB0/PB1 are shown below.
These control registers are mapped to locations 13H, PB0 I/O I I I I O O O O O O
15H and 17H.
PB1 I/O I O O O I I I O O O
After a chip reset, these input/output lines remain at high
PB0/PB1 Mode x C B B C B B C B B
levels or floating state (dependent on pull-high options).
Each bit of these input/output latches can be set or PB0 Data x x 0 1 D 0 1 D0 0 1
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H or PB1 Data x D x x x x x D1 x x
16H) instructions.
PB0 Pad Status I I I I D 0 B D0 0 B
Some instructions first input data and then follow the
PB1 Pad Status I D 0 B I I I D1 0 B
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states Note: I: input; O: output; D, D0, D1: data;
into the CPU, execute the defined operations B: buzzer option, BZ or BZ; x: don't care
(bit-operation), and then write the results back to the C: CMOS output
latches or the accumulator.
The PC0 and PC1 are pin-shared with INT, TMR and
Each line of port A has the capability of waking-up the pins respectively.
device. The highest 6-bit of port C and 5 bits of port B
It is recommended that unused or not bonded out I/O
are not physically implemented; on reading them a ²0² is lines should be set as output pins by software instruction
returned whereas writing then results in a no-operation. to avoid consuming power under input floating state.
See Application note.

Rev. 1.20 15 May 12, 2003

 HT48R06A-1/HT48C06

Options
The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper
system functioning.
Items Options
1 WDT clock source: WDTOSC or fSYS/4
2 WDT function: enable or disable
3 LVR function: enable or disable
4 CLRWDT instruction(s): one or two clear WDT instruction(s)
5 System oscillator: RC or crystal
6 Pull-high resistors (PA~PC): none or pull-high
7 BZ function: enable or disable
8 PA0~PA7 wake-up: enable or disable

Application Circuits
RC Oscillator for Multiple I/O Applications Crystal Oscillator for Multiple I/O Applications
V D D

0 .1 m F 2 4 k W ~ C 1
1 M W O S C 1
O S C 1
P A 0 ~ P A 7 P A 0 ~ P A 7
4 7 0 p F C 2
O S C 2
P B 0 /B Z P B 0 /B Z
fS Y S /4 O S C 2
P B 1 /B Z P B 1 /B Z
P B 2 P B 2
V D D V D D

P C 0 /IN T P C 0 /IN T
1 0 0 k W P C 1 /T M R 1 0 0 k W P C 1 /T M R

R E S R E S

1 0 k W 1 0 k W

0 .1 m F 0 .1 m F

H T 4 8 R 0 6 A -1 /H T 4 8 C 0 6 H T 4 8 R 0 6 A -1 /H T 4 8 C 0 6
N o te : T h e r e s is ta n c e a n d c a p a c ita n c e N o te : C 1 = C 2 = 3 0 0 p F if fS Y S < 1 M H z
fo r r e s e t c ir c u it s h o u ld b e d e s ig n e d O th e r w is e , C 1 = C 2 = 0 .
to e n s u re th a t th e V D D is s ta b le a n d
r e m a in s in a v a lid r a n g e o f th e o p e r a tin g
v o lta g e b e fo r e b r in g in g R E S to h ig h .

Rev. 1.20 16 May 12, 2003

 HT48R06A-1/HT48C06

Instruction Set Summary

Instruction Flag
Mnemonic Description
Cycle Affected
Arithmetic
ADD A,[m] Add data memory to ACC 1 Z,C,AC,OV
ADDM A,[m] Add ACC to data memory 1(1) Z,C,AC,OV
ADD A,x Add immediate data to ACC 1 Z,C,AC,OV
ADC A,[m] Add data memory to ACC with carry 1 Z,C,AC,OV
ADCM A,[m] Add ACC to data memory with carry 1(1) Z,C,AC,OV
SUB A,x Subtract immediate data from ACC 1 Z,C,AC,OV
SUB A,[m] Subtract data memory from ACC 1 Z,C,AC,OV
SUBM A,[m] Subtract data memory from ACC with result in data memory 1(1) Z,C,AC,OV
SBC A,[m] Subtract data memory from ACC with carry 1 Z,C,AC,OV
SBCM A,[m] Subtract data memory from ACC with carry and result in data memory 1(1) Z,C,AC,OV
DAA [m] Decimal adjust ACC for addition with result in data memory 1(1) C
Logic Operation
AND A,[m] AND data memory to ACC 1 Z
OR A,[m] OR data memory to ACC 1 Z
XOR A,[m] Exclusive-OR data memory to ACC 1 Z
ANDM A,[m] AND ACC to data memory 1(1) Z
ORM A,[m] OR ACC to data memory 1(1) Z
XORM A,[m] Exclusive-OR ACC to data memory 1(1) Z
AND A,x AND immediate data to ACC 1 Z
OR A,x OR immediate data to ACC 1 Z
XOR A,x Exclusive-OR immediate data to ACC 1 Z
CPL [m] Complement data memory 1(1) Z
CPLA [m] Complement data memory with result in ACC 1 Z
Increment & Decrement
INCA [m] Increment data memory with result in ACC 1 Z
INC [m] Increment data memory 1(1) Z
DECA [m] Decrement data memory with result in ACC 1 Z
DEC [m] Decrement data memory 1(1) Z
Rotate
RRA [m] Rotate data memory right with result in ACC 1 None
RR [m] Rotate data memory right 1(1) None
RRCA [m] Rotate data memory right through carry with result in ACC 1 C
RRC [m] Rotate data memory right through carry 1(1) C
RLA [m] Rotate data memory left with result in ACC 1 None
RL [m] Rotate data memory left 1(1) None
RLCA [m] Rotate data memory left through carry with result in ACC 1 C
RLC [m] Rotate data memory left through carry 1(1) C
Data Move
MOV A,[m] Move data memory to ACC 1 None
MOV [m],A Move ACC to data memory 1(1) None
MOV A,x Move immediate data to ACC 1 None
Bit Operation
CLR [m].i Clear bit of data memory 1(1) None
SET [m].i Set bit of data memory 1(1) None

Rev. 1.20 17 May 12, 2003

 HT48R06A-1/HT48C06

Instruction Flag
Mnemonic Description
Cycle Affected
Branch
JMP addr Jump unconditionally 2 None
SZ [m] Skip if data memory is zero 1(2) None
SZA [m] Skip if data memory is zero with data movement to ACC 1(2) None
SZ [m].i Skip if bit i of data memory is zero 1(2) None
SNZ [m].i Skip if bit i of data memory is not zero 1(2) None
SIZ [m] Skip if increment data memory is zero 1(3) None
SDZ [m] Skip if decrement data memory is zero 1(3) None
SIZA [m] Skip if increment data memory is zero with result in ACC 1(2) None
SDZA [m] Skip if decrement data memory is zero with result in ACC 1(2) None
CALL addr Subroutine call 2 None
RET Return from subroutine 2 None
RET A,x Return from subroutine and load immediate data to ACC 2 None
RETI Return from interrupt 2 None
Table Read
TABRDC [m] Read ROM code (current page) to data memory and TBLH 2(1) None
TABRDL [m] Read ROM code (last page) to data memory and TBLH 2(1) None
Miscellaneous
NOP No operation 1 None
CLR [m] Clear data memory 1(1) None
SET [m] Set data memory 1(1) None
CLR WDT Clear Watchdog Timer 1 TO,PD
CLR WDT1 Pre-clear Watchdog Timer 1 TO(4),PD(4)
CLR WDT2 Pre-clear Watchdog Timer 1 TO(4),PD(4)
SWAP [m] Swap nibbles of data memory 1(1) None
SWAPA [m] Swap nibbles of data memory with result in ACC 1 None
HALT Enter power down mode 1 TO,PD

Note: x: Immediate data

m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
: and (2)
(4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO and PD are cleared.
Otherwise the TO and PD flags remain unchanged.

Rev. 1.20 18 May 12, 2003

 HT48R06A-1/HT48C06

Instruction Definition

ADC A,[m] Add data memory and carry to the accumulator

Description The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the accumulator.
Operation ACC ¬ ACC+[m]+C
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ Ö Ö Ö Ö

ADCM A,[m] Add the accumulator and carry to data memory

Description The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the specified data memory.
Operation [m] ¬ ACC+[m]+C
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ Ö Ö Ö Ö

ADD A,[m] Add data memory to the accumulator

Description The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation ACC ¬ ACC+[m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ Ö Ö Ö Ö

ADD A,x Add immediate data to the accumulator

Description The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation ACC ¬ ACC+x
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ Ö Ö Ö Ö

ADDM A,[m] Add the accumulator to the data memory

Description The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation [m] ¬ ACC+[m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ Ö Ö Ö Ö

Rev. 1.20 19 May 12, 2003

 HT48R06A-1/HT48C06

AND A,[m] Logical AND accumulator with data memory

Description Data in the accumulator and the specified data memory perform a bitwise logical_AND op-
eration. The result is stored in the accumulator.
Operation ACC ¬ ACC ²AND² [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

AND A,x Logical AND immediate data to the accumulator

Description Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation ACC ¬ ACC ²AND² x
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

ANDM A,[m] Logical AND data memory with the accumulator

Description Data in the specified data memory and the accumulator perform a bitwise logical_AND op-
eration. The result is stored in the data memory.
Operation [m] ¬ ACC ²AND² [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

CALL addr Subroutine call

Description The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation Stack ¬ PC+1
PC ¬ addr
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

CLR [m] Clear data memory

Description The contents of the specified data memory are cleared to 0.
Operation [m] ¬ 00H
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.20 20 May 12, 2003

 HT48R06A-1/HT48C06

CLR [m].i Clear bit of data memory

Description The bit i of the specified data memory is cleared to 0.
Operation [m].i ¬ 0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

CLR WDT Clear Watchdog Timer

Description The WDT is cleared (clears the WDT). The power down bit (PD) and time-out bit (TO) are
cleared.
Operation WDT ¬ 00H
PD and TO ¬ 0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ 0 0 ¾ ¾ ¾ ¾

CLR WDT1 Preclear Watchdog Timer

Description Together with CLR WDT2, clears the WDT. PD and TO are also cleared. Only execution of
this instruction without the other preclear instruction just sets the indicated flag which im-
plies this instruction has been executed and the TO and PD flags remain unchanged.
Operation WDT ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ 0* 0* ¾ ¾ ¾ ¾

CLR WDT2 Preclear Watchdog Timer

Description Together with CLR WDT1, clears the WDT. PD and TO are also cleared. Only execution of
this instruction without the other preclear instruction, sets the indicated flag which implies
this instruction has been executed and the TO and PD flags remain unchanged.
Operation WDT ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ 0* 0* ¾ ¾ ¾ ¾

CPL [m] Complement data memory

Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation [m] ¬ [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

Rev. 1.20 21 May 12, 2003

 HT48R06A-1/HT48C06

CPLA [m] Complement data memory and place result in the accumulator
Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation ACC ¬ [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

DAA [m] Decimal-Adjust accumulator for addition

Description The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumu-
lator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD ad-
justment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö

DEC [m] Decrement data memory

Description Data in the specified data memory is decremented by 1.
Operation [m] ¬ [m]-1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

DECA [m] Decrement data memory and place result in the accumulator
Description Data in the specified data memory is decremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation ACC ¬ [m]-1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

Rev. 1.20 22 May 12, 2003

 HT48R06A-1/HT48C06

HALT Enter power down mode

Description This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PD) is set and the WDT time-out bit (TO) is cleared.
Operation PC ¬ PC+1
PD ¬ 1
TO ¬ 0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ 0 1 ¾ ¾ ¾ ¾

INC [m] Increment data memory

Description Data in the specified data memory is incremented by 1
Operation [m] ¬ [m]+1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

INCA [m] Increment data memory and place result in the accumulator
Description Data in the specified data memory is incremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation ACC ¬ [m]+1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

JMP addr Directly jump

Description The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation PC ¬addr
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

MOV A,[m] Move data memory to the accumulator

Description The contents of the specified data memory are copied to the accumulator.
Operation ACC ¬ [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.20 23 May 12, 2003

 HT48R06A-1/HT48C06

MOV A,x Move immediate data to the accumulator

Description The 8-bit data specified by the code is loaded into the accumulator.
Operation ACC ¬ x
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

MOV [m],A Move the accumulator to data memory

Description The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation [m] ¬ACC
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

NOP No operation
Description No operation is performed. Execution continues with the next instruction.
Operation PC ¬ PC+1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

OR A,[m] Logical OR accumulator with data memory

Description Data in the accumulator and the specified data memory (one of the data memories) per-
form a bitwise logical_OR operation. The result is stored in the accumulator.
Operation ACC ¬ ACC ²OR² [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

OR A,x Logical OR immediate data to the accumulator

Description Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation ACC ¬ ACC ²OR² x
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

ORM A,[m] Logical OR data memory with the accumulator

Description Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation [m] ¬ACC ²OR² [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

Rev. 1.20 24 May 12, 2003

 HT48R06A-1/HT48C06

RET Return from subroutine

Description The program counter is restored from the stack. This is a 2-cycle instruction.
Operation PC ¬ Stack
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

RET A,x Return and place immediate data in the accumulator

Description The program counter is restored from the stack and the accumulator loaded with the speci-
fied 8-bit immediate data.
Operation PC ¬ Stack
ACC ¬ x
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

RETI Return from interrupt

Description The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation PC ¬ Stack
EMI ¬ 1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

RL [m] Rotate data memory left

Description The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

RLA [m] Rotate data memory left and place result in the accumulator
Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.20 25 May 12, 2003

 HT48R06A-1/HT48C06

RLC [m] Rotate data memory left through carry

Description The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re-
places the carry bit; the original carry flag is rotated into the bit 0 position.
Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö

RLCA [m] Rotate left through carry and place result in the accumulator
Description Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö

RR [m] Rotate data memory right

Description The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

RRA [m] Rotate right and place result in the accumulator

Description Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

RRC [m] Rotate data memory right through carry

Description The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö

Rev. 1.20 26 May 12, 2003

 HT48R06A-1/HT48C06

RRCA [m] Rotate right through carry and place result in the accumulator
Description Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö

SBC A,[m] Subtract data memory and carry from the accumulator
Description The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the accumulator.
Operation ACC ¬ ACC+[m]+C
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ Ö Ö Ö Ö

SBCM A,[m] Subtract data memory and carry from the accumulator
Description The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the data memory.
Operation [m] ¬ ACC+[m]+C
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ Ö Ö Ö Ö

SDZ [m] Skip if decrement data memory is 0

Description The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

SDZA [m] Decrement data memory and place result in ACC, skip if 0
Description The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy-
cles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.20 27 May 12, 2003

 HT48R06A-1/HT48C06

SET [m] Set data memory

Description Each bit of the specified data memory is set to 1.
Operation [m] ¬ FFH
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

SET [m]. i Set bit of data memory

Description Bit i of the specified data memory is set to 1.
Operation [m].i ¬ 1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

SIZ [m] Skip if increment data memory is 0

Description The contents of the specified data memory are incremented by 1. If the result is 0, the fol-
lowing instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

SIZA [m] Increment data memory and place result in ACC, skip if 0
Description The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory re-
mains unchanged. If the result is 0, the following instruction, fetched during the current in-
struction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

SNZ [m].i Skip if bit i of the data memory is not 0

Description If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other-
wise proceed with the next instruction (1 cycle).
Operation Skip if [m].i¹0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.20 28 May 12, 2003

 HT48R06A-1/HT48C06

SUB A,[m] Subtract data memory from the accumulator

Description The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation ACC ¬ ACC+[m]+1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ Ö Ö Ö Ö

SUBM A,[m] Subtract data memory from the accumulator

Description The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation [m] ¬ ACC+[m]+1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ Ö Ö Ö Ö

SUB A,x Subtract immediate data from the accumulator

Description The immediate data specified by the code is subtracted from the contents of the accumula-
tor, leaving the result in the accumulator.
Operation ACC ¬ ACC+x+1
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ Ö Ö Ö Ö

SWAP [m] Swap nibbles within the data memory

Description The low-order and high-order nibbles of the specified data memory (1 of the data memo-
ries) are interchanged.
Operation [m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

SWAPA [m] Swap data memory and place result in the accumulator
Description The low-order and high-order nibbles of the specified data memory are interchanged, writ-
ing the result to the accumulator. The contents of the data memory remain unchanged.
Operation ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.20 29 May 12, 2003

 HT48R06A-1/HT48C06

SZ [m] Skip if data memory is 0

Description If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if [m]=0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

SZA [m] Move data memory to ACC, skip if 0

Description The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation Skip if [m]=0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

SZ [m].i Skip if bit i of the data memory is 0

Description If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if [m].i=0
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

TABRDC [m] Move the ROM code (current page) to TBLH and data memory
Description The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation [m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

TABRDL [m] Move the ROM code (last page) to TBLH and data memory
Description The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation [m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.20 30 May 12, 2003

 HT48R06A-1/HT48C06

XOR A,[m] Logical XOR accumulator with data memory

Description Data in the accumulator and the indicated data memory perform a bitwise logical Exclu-
sive_OR operation and the result is stored in the accumulator.
Operation ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

XORM A,[m] Logical XOR data memory with the accumulator

Description Data in the indicated data memory and the accumulator perform a bitwise logical Exclu-
sive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation [m] ¬ ACC ²XOR² [m]
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

XOR A,x Logical XOR immediate data to the accumulator

Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op-
eration. The result is stored in the accumulator. The 0 flag is affected.
Operation ACC ¬ ACC ²XOR² x
Affected flag(s)
TC2 TC1 TO PD OV Z AC C

¾ ¾ ¾ ¾ ¾ Ö ¾ ¾

Rev. 1.20 31 May 12, 2003

 HT48R06A-1/HT48C06

Package Information
16-pin SSOP (150mil) Outline Dimensions

1 6 9

A B

1 8

C '
G
D H

E F a

Dimensions in mil
Symbol
Min. Nom. Max.
A 228 ¾ 244
B 150 ¾ 157
C 8 ¾ 12
C¢ 189 ¾ 197
D 54 ¾ 60
E ¾ 25 ¾
F 4 ¾ 10
G 22 ¾ 28
H 7 ¾ 10
a 0° ¾ 8°

Rev. 1.20 32 May 12, 2003

 HT48R06A-1/HT48C06

18-pin DIP (300mil) Outline Dimensions

1 8 1 0
B
1 9

D
a
E G I
F

Dimensions in mil
Symbol
Min. Nom. Max.
A 895 ¾ 915
B 240 ¾ 260
C 125 ¾ 135
D 125 ¾ 145
E 16 ¾ 20
F 50 ¾ 70
G ¾ 100 ¾
H 295 ¾ 315
I 335 ¾ 375
a 0° ¾ 15°

Rev. 1.20 33 May 12, 2003

 HT48R06A-1/HT48C06

18-pin SOP (300mil) Outline Dimensions

1 8 1 0

A B

1 9

C '
G
D H

E F a

Dimensions in mil
Symbol
Min. Nom. Max.
A 394 ¾ 419
B 290 ¾ 300
C 14 ¾ 20
C¢ 447 ¾ 460
D 92 ¾ 104
E ¾ 50 ¾
F 4 ¾ ¾
G 32 ¾ 38
H 4 ¾ 12
a 0° ¾ 10°

Rev. 1.20 34 May 12, 2003

 HT48R06A-1/HT48C06

Product Tape and Reel Specifications

Reel Dimensions

D
T 2

A B C

T 1

SSOP 16S
Symbol Description Dimensions in mm
A Reel Outer Diameter 330±1.0
B Reel Inner Diameter 62±1.5
13.0+0.5
C Spindle Hole Diameter
-0.2
D Key Slit Width 2.0±0.5
12.8+0.3
T1 Space Between Flange
-0.2
T2 Reel Thickness 18.2±0.2

SOP 18W
Symbol Description Dimensions in mm
A Reel Outer Diameter 330±1.0
B Reel Inner Diameter 62±1.5
13.0+0.5
C Spindle Hole Diameter
-0.2
D Key Slit Width 2.0±0.5
24.8+0.3
T1 Space Between Flange
-0.2
T2 Reel Thickness 30.2±0.2

Rev. 1.20 35 May 12, 2003

 HT48R06A-1/HT48C06

Carrier Tape Dimensions

P 0 P 1
D t

F
W
B 0
C

D 1 P
K 0

A 0

SSOP 16S
Symbol Description Dimensions in mm
12.0+0.3
W Carrier Tape Width
-0.1
P Cavity Pitch 8.0±0.1
E Perforation Position 1.75±0.1
F Cavity to Perforation (Width Direction) 5.5±0.1
D Perforation Diameter 1.55±0.1
D1 Cavity Hole Diameter 1.5+0.25
P0 Perforation Pitch 4.0±0.1
P1 Cavity to Perforation (Length Direction) 2.0±0.1
A0 Cavity Length 6.4±0.1
B0 Cavity Width 5.2±0.1
K0 Cavity Depth 2.1±0.1
t Carrier Tape Thickness 0.30±0.05
C Cover Tape Width 9.3

SOP 18W
Symbol Description Dimensions in mm
24.0+0.3
W Carrier Tape Width
-0.1
P Cavity Pitch 16.0±0.1
E Perforation Position 1.75±0.1
F Cavity to Perforation (Width Direction) 11.5±0.1
D Perforation Diameter 1.5±0.1
D1 Cavity Hole Diameter 1.5+0.25
P0 Perforation Pitch 4.0±0.1
P1 Cavity to Perforation (Length Direction) 2.0±0.1
A0 Cavity Length 10.9±0.1
B0 Cavity Width 12.0±0.1
K0 Cavity Depth 2.8±0.1
t Carrier Tape Thickness 0.3±0.05
C Cover Tape Width 21.3

Rev. 1.20 36 May 12, 2003

 HT48R06A-1/HT48C06

Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Sales Office)
11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Semiconductor (Shanghai) Inc.
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor (Hong Kong) Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Holmate Semiconductor, Inc.
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com

Copyright Ó 2003 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.

Rev. 1.20 37 May 12, 2003