Circulating Current Control and Reduction

in a Paralleled Converter Test-bed System

Yiwei Ma, Liu Yang, Jing Wang, Xiaojie Shi, Fred Wang, Leon M. Tolbert
Center for Ultra-Wide-Area Resilient Electric Energy Transmission Networks (CURENT)
The University of Tennessee
Knoxville, TN USA 37996-2250
[email protected]

Abstract—It is a flexible and effective approach to emulate the Therefore, it is important to investigate the cause and the
behaviors of electric power system components using reduction method of the circulating current problems caused
interconnected parallel power converters. The reduction of by the paralleling of converters. In [6] and [7], the authors
unnecessary circulating current is essential for the validity of derived the models for the paralleled converters, and
the test-bed system. The types of the circulating current in the proposed control methods to limit the zero sequence
test bed system are discussed in this paper. The causes and the circulating current. The harmonic currents caused by the
reduction strategies for the switching period circulating dead-time of the converters were modeled and analyzed in
current, zero sequence circulating current and lower order [8] and [9]. Physical methods could also be adopted to
harmonics are presented. Simulation and experimental results
reduce the circulating current by adding interphase inductor
are given to verify the feasibility.
or common-mode inductor [10, 11].
I. INTRODUCTION Different from other cases, the paralleled converters in
Using regenerative rectifiers and inverters to emulate the HTB do not have a common load, and the converters have
elements in a power system provides a flexible and easy way distinctively different output to emulate various components
to study and analyze the characteristics of the tested in a power system. Hence the circulating current pattern is
components [1-3]. It allows the converters to serve as the not totally the same. In this paper, the types of the circulating
virtual power sources or loads working in the test currents in the HTB are discussed first. The cause of each
environment without the need for the full scale transmission, type of circulating current and the reduction methods are
generation, and load equipment. analyzed respectively. Simulation and experimental results
are also presented.
Based on this idea, a Hardware Test-Bed (HTB) was
proposed to create a multi-converter emulation system with
each converter representing a single or a congregated
element of power system. It is conceptualized to demonstrate
a large scale power system transmission network, and helps
with the testing and integration of various technologies on
monitoring, modeling, control, and actuation [4, 5].
The HTB is proposed to have a paralleled converter
structure which is illustrated in Fig. 1. The DC link is
supported by an active rectifier which is connected to the
utility line, and the DC voltage could be considered as
constant. The AC terminals of the converters are connected
together through filtering inductors, establishing the
emulated power system. The paralleling structure of the
HTB enables the power to be recycled between the power
source emulators and the load emulators, thus the total power
consumption would be reduced [4, 5].
Paralleling of converters will induce undesirable Figure 1. HTB converter cluster configuration.
circulating current, and thus cause the operation difficulty
and undermine the credibility of the HTB emulation.

U.S. Government work not protected by U.S. copyright 5426

 II. CIRCULATING CURRENTS IN HTB during the switch cycle is determined by average parameters
Typically, the circulating current is defined as the current of the converters:
difference between the assigned share of the total load
current for a specific converter, and the actual converter ∆ (1)
2
output current [12, 13]. However, there is no actual load in
the HTB. The sum of total converter output current is zero, where Vdc is the DC voltage, L is the inductance of the output
and all the current in the emulating system could be filter, Ts is the period of the switching cycle, D1 and D2 are
considered as circulating current. the output duty ratios of the analyzed phase for both
converters.
Thus, the output current could be characterized into three
types of circulating currents: Current ripples would be introduced when there is phase
displacement between the carrier waves of the converters.
The first type is the emulating current. It is determined by The amplitude ∆I could be expressed as (2), assuming D2 is
the model of emulated object. Ideally, this part of the current larger than D1.
is exactly the same with the output current of the emulated
object, after the scaling of the emulation. This type of
circulating current includes the fundamental frequency 0 |∆ |
2
current, and some low order harmonic current generated by ∆ |∆ | |∆ | (2)
the model of the non-linear load. 2 2 2 2

The second type is the switching period circulating |∆ |

2 2
current. It is inevitable to have some switching ripple in the
converter based test bed system. Generally, the emulation Thus, if the carrier wave time difference between the two
would not take the switching period performance into converters ∆t is kept small, the current ripple could be kept
account. But if not considered, large switching ripple would to a minimal value.
have negative impact on the monitoring and demonstration Fig. 3 gives the simulation comparison of the phase
of the emulation system. Thus, this type of circulating current with synchronized carrier wave and intentionally 180°
current should be suppressed. interleaved carrier wave. The synchronization could decrease
The third type is the other undesired circulating currents the switching period circulation current. And the phase
in the test-bed. This includes the zero sequence current displacement of the carrier wave does not have any impact
which is not found in the actual power system unless faulted, on the averaged emulating current.
and lower order harmonics due to the imperfection of the With the increased number of converters in parallel, the
converter and the controller. If not considered, this type of principle of superposition would apply to each converter.
circulating current would pollute the emulating environment, The single phase current change of the i-th converter ∆ is
and may cause instability of the HTB system. determined by (3). The sum of the current changes of all the
converters is 0.
III. SWITCHING PERIOD CIRCULATING CURRENT
The switching ripple of the output current is a major
concern in the paralleled converter system. For HTB system, ∆ 1 (3)
2
,
the focus is the output currents for the individual converter
emulators, instead of a total current from the sum of the
converters for the other cases. The analysis and the
reduction method are presented in this section.
The single phase terminal voltage of a converter could
be either positive or negative DC-bus voltage. Thus in a
switching cycle, the voltage drop on the filtering inductors
could step several times from negative to positive, and back
to negative, resulting in large switching ripples. These
current ripples are not represented in the average model of
the converter system. Thus they would not have great
impact on the HTB emulation accuracy. But large current
ripples would impair the measurement and demonstration of
the emulation, and even deteriorate the performance of the
system control.
The current ripples in the switching period are largely
dependent on the time difference of the carrier waves and
Figure 2. Diagrammatic sketch of a single phase current in a two-
duty ratios of the converters. Fig. 2 illustrates a single phase converter system
current in a two-converter system. The current increase ∆

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 50
IV. UNDESIRED CIRCULATING CURRENTS
0 A. Zero Sequence Circulating Current
The zero sequence current paths are rarely presented in
the normal grid-connected applications due to the lack of the
-50
0.082 0.084 0.086 0.088 0.09 0.092 0.094 0.096 0.098

50 grounding wire. But this path is formed by sharing the

common DC and AC links of the converters. In addition, the
0 impedance of the path is dependent on the filter inductor,
which is relatively small, as shown in Fig. 4. If the zero
-50
0.082 0.084 0.086 0.088 0.09 0.092 0.094 0.096 0.098 sequence duty cycle of the converters in the HTB system is
20 not totally the same, the unwanted zero sequence current
would dominate in the emulated grid. Therefore, it is needed
0 to eliminate this circulating current.
-20
First, a common mode choke is connected in series with
0.082 0.084 0.086 0.088 0.09 0.092 0.094 0.096 0.098
the filtering inductor for each converter. It will not influence
the voltages and currents in the dq axis, but greatly increase
the loop inductance on the zero axis. This common mode
Figure 3. Phase current (a) with synchronized carrier wave; (b) without choke would also help to reduce switching period circulating
synchronized carrier wave; (c) ripple current.
current when the synchronization is not reached
The current ripple is represented as the additional Second, a zero sequence current loop is implemented into
variation between the beginning and the end of the switching the emulating converters in HTB. The basic idea of
cycle. Define the current trip ∆ as the total variation during maintaining the same zero sequence duty cycle for each one
the cycle, i.e. for Fig. 2, ∆ is∆ 2∆ . Thus, for any of the of the converters is to let one converter have no zero
two converters, the current trip is calculated by: sequence injection (outputting pure Sinusoidal PWM), and
∆
let the other converters follow this reference. If there are n
,
converters in the HTB system, n-1 converters should have
∆ the zero sequence current control given in Fig. 5 [7]. The
2 2
(4) open-loop bode plot of the control system is shown in Fig. 6.
∆ ∆ A resonant controller focused on reducing the third order
2 2
harmonics is added together with a PI controller. The
∆
2 2 bandwidth of the controller can be relatively low compared
where ∆ is the time difference between the i-th and the j-th to the fundamental frequency controller on the dq axis, since
converter, and and represent the single phase duty it is not required to have fast tracking capability.
ratios of the analyzed converters.
There is no way that the current variation could cancel
with each other while applying the super position principle,
because when the terminal voltage of the converter is a
negative DC voltage, the phase current can only rise, and
vice versa. Thus the overall current trip of the i-th converter
can be calculated by:

∆ , ∆ , 1 (5)
,

Hence, it is indicated that the current trip ∆ , will never

be less than the absolute value of the current increase ∆ .
And not all the converters are able to have zero switching
period current ripples when multiple converters are
paralleled. But it is optimal to have the carrier wave of the
converters synchronized.
In practice, this synchronization requires inter-
communication among the converters. A master converter
sends out trigger pulses using the CAN bus communication
at the beginning of every 8 switching cycles, and other slave
converters should slightly adjust their switching frequency
depending on the leading or lagging of the detection of the
trigger pulse until synchronized [14]. Figure 4. Averge model of two paralleled converter in dq0 axis.

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 crossing area of the dead-time compensation is relatively
small. Thus the converter output duty-ratio could be
compensated by the direction of the output current.
Fig. 7 shows the open-loop simulation of the dead-time
effect. The results verify that the dead-time effect is mainly
dependent on the direction of the phase current. Also, the
harmonic content in the current is much larger than the
harmonics in the voltage. It is due to the paralleled structure
of the converter system.

100

Averaged Phase
Voltage (V)
0

Figure 5. Zero sequence current control scheme. -100

0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1

Dead-time Effect (V)

10

Bode Diagram
100
0
Magnitude (dB)

50
-10
0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1

50
Phase Current (A)
0

0
-50
0

-50
-45 0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1
Phase (deg)

Time (s)
-90

-135 Figure 7. Open-loop simulation of the dead-time effect.

-180
10
0 1
10 10
2 3
10 10
4 V. EXPERIMENT
Frequency (Hz)
The hardware configuration of one of the HTB cabinets
is shown in Fig. 8, which includes one active rectifier and
Figure 6. Bode plot of the open-loop zero sequence current control system. three converters to emulate the power grid. Fig. 9 gives the
experiment connection diagram. The DC voltage rating of
B. Low Order Harmonic Circulating Current the converters is 600 V, and the power rating is 30 kW. The
The harmonic circulating current in the parallel output filter of the converter L is 0.5 mH. The common mode
converters is mainly caused by the imperfection of the choke LC is 12 mH, and LT is the inductors that emulate the
converters. These imperfections include the dead-time effect transmission line. Texas Instrument DSP TMS320F28335
of the converter control, rise time and fall time of the phase was used to control the converters.
current, and the voltage drops on the power electronic
devices [8]. In the experiments, Converter #1 and #2 are emulating
generators, feeding the power to the load emulated by
Undesired low order harmonic circulating current could Converter #3.
affect the input signal of the converter emulator. The
emulation result would not be accurate if the emulating A. Switching Period Circulating Current
model is misguided by the harmonic current, and generate Fig. 10 gives the experimental waveforms in the
the wrong output. However, this type of harmonic circulating switching cycles. The voltage and current waveforms are
current should not be suppressed intentionally by control from phase A of the Converter #1, #2 and #3. The carrier
strategies. Otherwise, when emulating the non-linear load or waves for the three converters are synchronized, so that the
the faulted cases, the desired emulating harmonic current output voltages are aligned. The phase current is kept the
produced by the emulator could be compromised by the same when the three voltages are either all positive or all
control. negative. Thus the switching period circulating currents are
reduced.
Thus, the dead-time compensation is adopted to
minimize the output of the low order harmonics. Since the B. Dead-time Compensation
ripples on the current could be largely reduced by Only Converter #2 and Converter #3 are involved in this
synchronizing the carrier wave of the PWM, the zero experiment. Fig. 11 gives the experimental results for the

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dead-time compensation. The current distortion is very large
when the converter is open-loop controlled. Using the
designed closed-loop control, most of the harmonics are
eliminated. But there is still some distortion at the zero-
crossing point. After the dead-time compensation, the total
harmonic distortion of the current decreases from 4.0% to
2.1%, thus the compensation strategy is verified.
C. Zero Sequence Circulating Current Control
Fig. 12 shows the experiment comparison between with
and without the zero sequence current controllers activated.
If the zero sequence currents are not controlled, the phase
currents of the converters would have a DC-bias shifting
Figure 10. Experimental wavefroms of switching cycle circulating current.
between the positive and negative in a long time scale. The
controllers for Converter #2 and #3 are activated in the Fig.
12 (b), the DC-bias is eliminated. The current spikes on the
edges are caused by the interference of the current probe.

(a)

(b)
Figure 8. HTB cabinet configuration.

(c)
Figure 9. Experiment connection diagram.
Figure 11. Experimental waveforms of dead-time compensation (a) open-
loop control without compensation; (b) closed-loop control without
compensation; (c) closed-loop control with compensation.

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 (a) (a)

(b) (b)
Figure 12. Experimental waveforms of zero sequence circulating current (a) Figure 13. Experimental waveforms of the negative sequence circulating
without control; (b) Converter #2 and Converter #3 are controlled. currents (a) without accurate current measurements; (b) with accurate
current measurements.
D. Negative Sequence Circulating Current
The structure of paralleled converters also introduces The causes for the circulating currents in the HTB were
negative sequence circulating currents [17, 18]. The negative analyzed, and the reduction methods for each type of the
sequence current would be represented by the second order circulating currents were presented respectively. The
harmonics on the dq axis. It can be reduced since it is within switching period circulating current was suppressed by the
the bandwidth of the controllers on the converter emulator. synchronization of the carrier waves between the converters.
However, when the current and voltage sensor on the The zero sequence circulating current was controlled by
converter emulator was not accurate enough, a small amount injecting zero sequence duty ratios to the modulation of the
of the unbalance would be enlarged by the emulation converter emulators, and the dead-time effect was
models, and result in a non-negligible unbalanced current compensated to reduce the low order harmonic circulating
output. Fig. 13 gives the experimental waveforms of currents. Simulations and experiments were performed to
Converter #1, in the three converters emulating environment. validate the analysis and corresponding mitigation methods.
When there is a 2% gain error on the Converter #1, phase B, ACKNOWLEDGMENT
the phase current would have around 15% unbalanced
current, shown in Fig 13 (a). After the sensors on the This work was supported primarily by the Engineering
converters are tuned, this unbalance disappears. Research Center Program of the National Science
Foundation and the Department of Energy under NSF Award
Since it is related with the negative sequence models of Number EEC-1041877 and the CURENT Industry
the emulated generators and the load, the specific controller Partnership Program
is not yet designed, and will be considered in the future
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