DATASHEET

HFA3101 FN3663
Gilbert Cell UHF Transistor Array Rev 5.00
September 2004

The HFA3101 is an all NPN transistor array configured as a Features

Multiplier Cell. Based on Intersil’s bonded wafer UHF-1 SOI
process, this array achieves very high fT (10GHz) while • Pb-free Available as an Option
maintaining excellent hFE and VBE matching characteristics • High Gain Bandwidth Product (fT) . . . . . . . . . . . . . 10GHz
that have been maximized through careful attention to circuit
• High Power Gain Bandwidth Product. . . . . . . . . . . . 5GHz
design and layout, making this product ideal for
communication circuits. For use in mixer applications, the • Current Gain (hFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
cell provides high gain and good cancellation of 2nd order • Low Noise Figure (Transistor) . . . . . . . . . . . . . . . . . 3.5dB
distortion terms.
• Excellent hFE and VBE Matching
Ordering Information • Low Collector Leakage Current . . . . . . . . . . . . . . <0.01nA
PART NUMBER TEMP. PKG. • Pin to Pin Compatible to UPA101
(BRAND) RANGE (°C) PACKAGE DWG. #

HFA3101B -40 to 85 8 Ld SOIC M8.15 Applications

(H3101B)
• Balanced Mixers
HFA3101BZ -40 to 85 8 Ld SOIC M8.15
(H3101B) (Note) (Pb-free) • Multipliers

HFA3101B96 -40 to 85 8 Ld SOIC Tape M8.15 • Demodulators/Modulators

(H3101B) and Reel
• Automatic Gain Control Circuits
HFA3101BZ96 -40 to 85 8 Ld SOIC Tape M8.15
(H3101B) (Note) and Reel (Pb-free) • Phase Detectors

NOTE: Intersil Pb-free products employ special Pb-free material • Fiber Optic Signal Processing
sets; molding compounds/die attach materials and 100% matte tin
• Wireless Communication Systems
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL • Wide Band Amplification Stages
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020C. • Radio and Satellite Communications
• High Performance Instrumentation
Pinout
HFA3101
(SOIC)
TOP VIEW
8

Q1 Q2 Q3 Q4

Q5 Q6
1

NOTE: Q5 and Q6 - 2 Paralleled 3m x 50m Transistors 

Q1, Q2, Q3, Q4 - Single 3m x 50m Transistors

FN3663 Rev 5.00 Page 1 of 12

September 2004
HFA3101

Absolute Maximum Ratings Thermal Information

VCEO, Collector to Emitter Voltage . . . . . . . . . . . . . . . . . . . . . . 8.0V Thermal Resistance (Typical, Note 1) JA (oC/W)
VCBO, Collector to Base Voltage . . . . . . . . . . . . . . . . . . . . . . . 12.0V SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
VEBO, Emitter to Base Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . .175oC
IC, Collector Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Operating Conditions Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications TA = 25oC

(NOTE 2)
TEST
PARAMETER TEST CONDITIONS LEVEL MIN TYP MAX UNITS
Collector to Base Breakdown Voltage, V(BR)CBO, Q1 thru IC = 100A, IE = 0 A 12 18 - V
Q6
Collector to Emitter Breakdown Voltage, V(BR)CEO, IC = 100A, IB = 0 A 8 12 - V
Q5 and Q6
Emitter to Base Breakdown Voltage, V(BR)EBO, Q1 thru Q6 IE = 10A, IC = 0 A 5.5 6 - V
Collector Cutoff Current, ICBO, Q1 thru Q4 VCB = 8V, IE = 0 A - 0.1 10 nA
Emitter Cutoff Current, IEBO, Q5 and Q6 VEB = 1V, IC = 0 A - - 200 nA
DC Current Gain, hFE, Q1 thru Q6 IC = 10mA, VCE = 3V A 40 70 -
Collector to Base Capacitance, CCB Q1 thru Q4 VCB = 5V, f = 1MHz C - 0.300 - pF
Q5 and Q6 - 0.600 - pF
Emitter to Base Capacitance, CEB Q1 thru Q4 VEB = 0, f = 1MHz B - 0.200 - pF
Q5 and Q6 - 0.400 - pF
Current Gain-Bandwidth Product, fT Q1 thru Q4 IC = 10mA, VCE = 5V C - 10 - GHz
Q5 and Q6 IC = 20mA, VCE = 5V C - 10 - GHz
Power Gain-Bandwidth Product, fMAX Q1 thru Q4 IC = 10mA, VCE = 5V C - 5 - GHz
Q5 and Q6 IC = 20mA, VCE = 5V C - 5 - GHz
Available Gain at Minimum Noise Figure, GNFMIN, IC = 5mA, f = 0.5GHz C - 17.5 - dB
Q5 and Q6 VCE = 3V
f = 1.0GHz C - 11.9 - dB
Minimum Noise Figure, NFMIN, Q5 and Q6 IC = 5mA, f = 0.5GHz C - 1.7 - dB
VCE = 3V
f = 1.0GHz C - 2.0 - dB
50 Noise Figure, NF50, Q5 and Q6 IC = 5mA, f = 0.5GHz C - 2.25 - dB
VCE = 3V
f = 1.0GHz C - 2.5 - dB
DC Current Gain Matching, hFE1/hFE2, Q1 and Q2, IC = 10mA, VCE = 3V A 0.9 1.0 1.1
Q3 and Q4, and Q5 and Q6
Input Offset Voltage, VOS, (Q1 and Q2), (Q3 and Q4), IC = 10mA, VCE = 3V A - 1.5 5 mV
(Q5 and Q6)
Input Offset Current, IC, (Q1 and Q2), (Q3 and Q4), IC = 10mA, VCE = 3V A - 5 25 A
(Q5 and Q6)
Input Offset Voltage TC, dVOS/dT, (Q1 and Q2, Q3 and Q4, IC = 10mA, VCE = 3V C - 0.5 - V/oC
Q5 and Q6)
Collector to Collector Leakage, ITRENCH-LEAKAGE VTEST = 5V B - 0.01 - nA

FN3663 Rev 5.00 Page 2 of 12

September 2004
HFA3101

Electrical Specifications TA = 25oC

(NOTE 2)
TEST
PARAMETER TEST CONDITIONS LEVEL MIN TYP MAX UNITS
NOTE:
2. Test Level: A. Production Tested, B. Typical or Guaranteed Limit Based on Characterization, C. Design Typical for Information Only.

PSPICE Model for a 3 m x 50 m Transistor

.Model NUHFARRY NPN
+ (IS = 1.840E-16 XTI = 3.000E+00 EG = 1.110E+00 VAF = 7.200E+01
+ VAR = 4.500E+00 BF = 1.036E+02 ISE = 1.686E-19 NE = 1.400E+00
+ IKF = 5.400E-02 XTB = 0.000E+00 BR = 1.000E+01 ISC = 1.605E-14
+ NC = 1.800E+00 IKR = 5.400E-02 RC = 1.140E+01 CJC = 3.980E-13
+ MJC = 2.400E-01 VJC = 9.700E-01 FC = 5.000E-01 CJE = 2.400E-13
+ MJE = 5.100E-01 VJE = 8.690E-01 TR = 4.000E-09 TF = 10.51E-12
+ ITF = 3.500E-02 XTF = 2.300E+00 VTF = 3.500E+00 PTF = 0.000E+00
+ XCJC = 9.000E-01 CJS = 1.689E-13 VJS = 9.982E-01 MJS = 0.000E+00
+ RE = 1.848E+00 RB = 5.007E+01 RBM = 1.974E+00 KF = 0.000E+00
+ AF = 1.000E+00)

Common Emitter S-Parameters of 3 m x 50 m Transistor

FREQ. (Hz) |S11| PHASE(S11) |S12| PHASE(S12) |S21| PHASE(S21) |S22| PHASE(S22)

VCE = 5V and IC = 5mA

1.0E+08 0.83 -11.78 1.41E-02 78.88 11.07 168.57 0.97 -11.05

2.0E+08 0.79 -22.82 2.69E-02 68.63 10.51 157.89 0.93 -21.35

3.0E+08 0.73 -32.64 3.75E-02 59.58 9.75 148.44 0.86 -30.44

4.0E+08 0.67 -41.08 4.57E-02 51.90 8.91 140.36 0.79 -38.16

5.0E+08 0.61 -48.23 5.19E-02 45.50 8.10 133.56 0.73 -44.59

6.0E+08 0.55 -54.27 5.65E-02 40.21 7.35 127.88 0.67 -49.93

7.0E+08 0.50 -59.41 6.00E-02 35.82 6.69 123.10 0.62 -54.37

8.0E+08 0.46 -63.81 6.27E-02 32.15 6.11 119.04 0.57 -58.10

9.0E+08 0.42 -67.63 6.47E-02 29.07 5.61 115.57 0.53 -61.25

1.0E+09 0.39 -70.98 6.63E-02 26.45 5.17 112.55 0.50 -63.96

1.1E+09 0.36 -73.95 6.75E-02 24.19 4.79 109.91 0.47 -66.31

1.2E+09 0.34 -76.62 6.85E-02 22.24 4.45 107.57 0.45 -68.37

1.3E+09 0.32 -79.04 6.93E-02 20.53 4.15 105.47 0.43 -70.19

1.4E+09 0.30 -81.25 7.00E-02 19.02 3.89 103.57 0.41 -71.83

1.5E+09 0.28 -83.28 7.05E-02 17.69 3.66 101.84 0.40 -73.31

1.6E+09 0.27 -85.17 7.10E-02 16.49 3.45 100.26 0.39 -74.66

1.7E+09 0.25 -86.92 7.13E-02 15.41 3.27 98.79 0.38 -75.90

1.8E+09 0.24 -88.57 7.17E-02 14.43 3.10 97.43 0.37 -77.05

1.9E+09 0.23 -90.12 7.19E-02 13.54 2.94 96.15 0.36 -78.12

2.0E+09 0.22 -91.59 7.21E-02 12.73 2.80 94.95 0.35 -79.13

2.1E+09 0.21 -92.98 7.23E-02 11.98 2.68 93.81 0.35 -80.09

FN3663 Rev 5.00 Page 3 of 12

September 2004
HFA3101

Common Emitter S-Parameters of 3 m x 50 m Transistor (Continued)

FREQ. (Hz) |S11| PHASE(S11) |S12| PHASE(S12) |S21| PHASE(S21) |S22| PHASE(S22)

2.2E+09 0.20 -94.30 7.25E-02 11.29 2.56 92.73 0.34 -80.99

2.3E+09 0.20 -95.57 7.27E-02 10.64 2.45 91.70 0.34 -81.85

2.4E+09 0.19 -96.78 7.28E-02 10.05 2.35 90.72 0.33 -82.68

2.5E+09 0.18 -97.93 7.29E-02 9.49 2.26 89.78 0.33 -83.47

2.6E+09 0.18 -99.05 7.30E-02 8.96 2.18 88.87 0.33 -84.23

2.7E+09 0.17 -100.12 7.31E-02 8.47 2.10 88.00 0.33 -84.97

2.8E+09 0.17 -101.15 7.31E-02 8.01 2.02 87.15 0.33 -85.68

2.9E+09 0.16 -102.15 7.32E-02 7.57 1.96 86.33 0.33 -86.37

3.0E+09 0.16 -103.11 7.32E-02 7.16 1.89 85.54 0.33 -87.05

VCE = 5V and IC = 10mA

1.0E+08 0.72 -16.43 1.27E-02 75.41 15.12 165.22 0.95 -14.26

2.0E+08 0.67 -31.26 2.34E-02 62.89 13.90 152.04 0.88 -26.95

3.0E+08 0.60 -43.76 3.13E-02 52.58 12.39 141.18 0.79 -37.31

4.0E+08 0.53 -54.00 3.68E-02 44.50 10.92 132.57 0.70 -45.45

5.0E+08 0.47 -62.38 4.05E-02 38.23 9.62 125.78 0.63 -51.77

6.0E+08 0.42 -69.35 4.31E-02 33.34 8.53 120.37 0.57 -56.72

7.0E+08 0.37 -75.26 4.49E-02 29.47 7.62 116.00 0.51 -60.65

8.0E+08 0.34 -80.36 4.63E-02 26.37 6.86 112.39 0.47 -63.85

9.0E+08 0.31 -84.84 4.72E-02 23.84 6.22 109.36 0.44 -66.49

1.0E+09 0.29 -88.83 4.80E-02 21.75 5.69 106.77 0.41 -68.71

1.1E+09 0.27 -92.44 4.86E-02 20.00 5.23 104.51 0.39 -70.62

1.2E+09 0.25 -95.73 4.90E-02 18.52 4.83 102.53 0.37 -72.28

1.3E+09 0.24 -98.75 4.94E-02 17.25 4.49 100.75 0.35 -73.76

1.4E+09 0.22 -101.55 4.97E-02 16.15 4.19 99.16 0.34 -75.08

1.5E+09 0.21 -104.15 4.99E-02 15.19 3.93 97.70 0.33 -76.28

1.6E+09 0.20 -106.57 5.01E-02 14.34 3.70 96.36 0.32 -77.38

1.7E+09 0.20 -108.85 5.03E-02 13.60 3.49 95.12 0.31 -78.41

1.8E+09 0.19 -110.98 5.05E-02 12.94 3.30 93.96 0.31 -79.37

1.9E+09 0.18 -113.00 5.06E-02 12.34 3.13 92.87 0.30 -80.27

2.0E+09 0.18 -114.90 5.07E-02 11.81 2.98 91.85 0.30 -81.13

2.1E+09 0.17 -116.69 5.08E-02 11.33 2.84 90.87 0.30 -81.95

2.2E+09 0.17 -118.39 5.09E-02 10.89 2.72 89.94 0.29 -82.74

2.3E+09 0.16 -120.01 5.10E-02 10.50 2.60 89.06 0.29 -83.50

2.4E+09 0.16 -121.54 5.11E-02 10.13 2.49 88.21 0.29 -84.24

2.5E+09 0.16 -122.99 5.12E-02 9.80 2.39 87.39 0.29 -84.95

2.6E+09 0.15 -124.37 5.12E-02 9.49 2.30 86.60 0.29 -85.64

2.7E+09 0.15 -125.69 5.13E-02 9.21 2.22 85.83 0.29 -86.32

2.8E+09 0.15 -126.94 5.13E-02 8.95 2.14 85.09 0.29 -86.98

2.9E+09 0.15 -128.14 5.14E-02 8.71 2.06 84.36 0.29 -87.62

3.0E+09 0.14 -129.27 5.15E-02 8.49 1.99 83.66 0.29 -88.25

FN3663 Rev 5.00 Page 4 of 12

September 2004
HFA3101

Application Information Figure 1 shows the typical input waveforms where the
frequency of the carrier is higher than the modulating signal.
The HFA3101 array is a very versatile RF Building block. It has
The output waveform shows a typical suppressed carrier
been carefully laid out to improve its matching properties,
output of an up converter or an AM signal generator.
bringing the distortion due to area mismatches, thermal
distribution, betas and ohmic resistances to a minimum. Carrier suppression capability is a property of the well known
Balanced modulator in which the output must be zero when
The cell is equivalent to two differential stages built as two
one or the other input (carrier or modulating signal) is equal to
“variable transconductance multipliers” in parallel, with their
zero. however, at very high frequencies, high frequency
outputs cross coupled. This configuration is well known in the
mismatches and AC offsets are always present and the
industry as a Gilbert Cell which enables a four quadrant
suppression capability is often degraded causing carrier and
multiplication operation.
modulating feedthrough to be present.
Due to the input dynamic range restrictions for the input levels
Being a frequency translation circuit, the balanced modulator
at the upper quad transistors and lower tail transistors, the
has the properties of translating the modulating frequency (M)
HFA3101 cell has restricted use as a linear four quadrant
to the carrier frequency (C), generating the two side bands
multiplier. However, its configuration is well suited for uses
U = C + M andLC - M. Figure 2 shows some
where its linear response is limited to one of the inputs only, as
translating schemes being used by balanced mixers.
in modulators or mixer circuit applications. Examples of these
circuits are up converters, down converters, frequency
doublers and frequency/phase detectors.
C - M C + M
Although linearization is still an issue for the lower pair input,
emitter degeneration can be used to improve the dynamic C
range and consequent linearity. The HFA3101 has the lower
pair emitters brought to external pins for this purpose.

In modulators applications, the upper quad transistors are

used in a switching mode where the pairs Q1/Q2 and Q3/Q4
act as non saturating high speed switches. These switches are
controlled by the signal often referred as the carrier input. The
signal driving the lower pair Q5/Q6 is commonly used as the FIGURE 2A. UP CONVERSION OR SUPPRESSED CARRIER AM
modulating input. This signal can be linearly transferred to the
output by either the use of low signal levels (Well below the
thermal voltage of 26mV) or by the use of emitter IF (C -  M)
degeneration. The chopped waveform appearing at the output FOLDED BACK
of the upper pair (Q1 to Q4) resembles a signal that is M
multiplied by +1 or -1 at every half cycle of the switching
waveform.
C
CARRIER SIGNAL
+1

-1

FIGURE 2B. DOWN CONVERSION

MODULATING SIGNAL

C
BASEBAND

DIFFERENTIAL OUTPUT
M

FIGURE 1. TYPICAL MODULATOR SIGNALS FIGURE 2C. ZERO IF OR DIRECT DOWN CONVERSION
FIGURE 2. MODULATOR FREQUENCY SPECTRUM

FN3663 Rev 5.00 Page 5 of 12

September 2004
HFA3101

The use of the HFA3101 as modulators has several The process of frequency doubling is also understood by
advantages when compared to its counterpart, the diode having the same signal being fed to both modulating and
doublebalanced mixer, in which it is required to receive enough carrier ports. The output frequency will be the sum of C and
energy to drive the diodes into a switching mode and has also M which is equivalent to the product of the input frequency by
some requirements depending on the frequency range 2 and a zero Hz or DC frequency equivalent to the difference of
desired, of different transformers to suit specific frequency C and M . Figure 2 also shows one technique in use today
responses. The HFA3101 requires very low driving capabilities where a process of down conversion named zero IF is made
for its carrier input and its frequency response is limited by the by using a local oscillator with a very pure signal frequency
fT of the devices, the design and the layout techniques being equal to the incoming RF frequency signal that contains a
utilized. baseband (audio or digital signal) modulation. Although
complex, the extraction or detection of the signal is
Up conversion uses, for UHF transmitters for example, can be
straightforward.
performed by injecting a modulating input in the range of 45MHz
to 130MHz that carries the information often called IF Another useful application of the HFA3101 is its use as a high
(Intermediate frequency) for up conversion (The IF signal has frequency phase detector where the two signals are fed to the
been previously modulated by some modulation scheme from a carrier and modulation ports and the DC information is extracted
baseband signal of audio or digital information) and by injecting from its output. In this case, both ports are utilized in a switching
the signal of a local oscillator of a much higher frequency range mode or overdrive, such that the process of multiplication takes
from 600MHz to 1.2GHz into the carrier input. Using the example place in a quasi digital form (2 square waves). One application of
of a 850MHz carrier input and a 70MHz IF, the output spectrum a phase detector is frequency or phase demodulation where the
will contain a upper side band of 920MHz, a lower side band of FM signal is split before the modulating and carrier ports. The
780MHz and some of the carrier (850MHz) and IF (70MHz) lower input port is always 90 degrees apart from the carrier input
feedthrough. A Band pass filter at the output can attenuate the signal through a high Q tuned phase shift network. The network,
undesirable signals and the 920MHz signal can be routed to a being tuned for a precise 90 degrees shift at a nominal frequency,
transmitter RF power amplifier. will set the two signals 90 degrees apart and a quiescent output
DC level will be present at the output. When the input signal is
Down conversion, as the name implies, is the process used to
frequency modulated, the phase shift of the signal coming from
translate a higher frequency signal to a lower frequency range
the network will deviate from 90 degrees proportional to the
conserving the modulation information contained in the higher
frequency deviation of the FM signal and a DC variation at the
frequency signal. One very common typical down conversion
output will take place, resembling the demodulated FM signal.
use for example, is for superheterodyne radio receivers where
a translated lower frequency often referred as intermediate The HFA3101 could also be used for quadrature detection,
frequency (IF) is used for detection or demodulation of the (I/Q demodulation), AGC control with limited range, low level
baseband signal. Other application uses include down multiplication to name a few other applications.
conversion for special filtering using frequency translation
Biasing
methods.
Various biasing schemes can be employed for use with the
An oscillator referred as the local oscillator (LO) drives the HFA3101. Figure 3 shows the most common schemes. The
upper quad transistors of the cell with a frequency calledC . biasing method is a choice of the designer when cost, thermal
The lower pair is driven by the RF signal of frequency M to be dependence, voltage overheads and DC balancing properties
translated to a lower frequency IF . The spectrum of the IF are taken into consideration.
output will contain the sum and difference of the frequencies
C and M. Notice that the difference can become negative Figure 3A shows the simplest form of biasing the HFA3101.
when the frequency of the local oscillator is lower than the The current source required for the lower pair is set by the
incoming frequency and the signal is folded back as in Figure voltage across the resistor RBIAS less a VBE drop of the lower
2. transistor. To increase the overhead, collector resistors are
substituted by an RF choke as the upper pair functions as a
NOTE: The acronyms R F , IF and LO are often interchanged in the current source for AC signals. The bases of the upper and
industry depending on the application of the cell as mixers or
modulators. The output of the cell also contains multiples of the
lower transistors are biased by RB1 and RB2 respectively. The
frequency of the signal being fed to the upper quad pair of transistors voltage drop across the resistor R2 must be higher than a VBE
because of the switching action equivalent to a square wave with an increase sufficient to assure that the collector to base
multiplication. In practice, however, not only the odd multiples in the junctions of the lower pair are always reverse biased. Notice
case of a symmetrical square wave but some of the even multiples will that this same voltage also sets the VCE of operation of the
also appear at the output spectrum due to the nature of the actual
switching waveform and high frequency performance. By-products of
lower pair which is important for the optimization of gain.
the form M*C + N*M with M and N being positive or negative Resistors REE are nominally zero for applications where the
integers are also expected to be present at the output and their levels input signals are well below 25mV peak. Resistors REE are
are carefully examined and minimized by the design. This distortion is used to increase the linearity of the circuit upon higher level
considered one of the figures of merit for a mixer application.

FN3663 Rev 5.00 Page 6 of 12

September 2004
HFA3101

signals. The drop across REE must be taken into consideration compensation as the lower pair VBE drop at the rate of
when setting the current source value. -2mV/oC.

Figure 3B depicts the use of a common resistor sharing the Figure 3C uses a split supply.
current through the cell which is used for temperature
VCC
VCC
RC
VCC

LCH LCH
RB1 LCH
RB1
R1 R1 RB1
R1

5
8

5
R2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q5 Q6 Q5 Q6
Q5 Q6
R2 R2
1

4
1

4
REE REE REE REE
REE REE

RBIAS RBIAS RBIAS

RB2 RB2
RB2
RE RE RE

VEE

FIGURE 3A. FIGURE 3B. FIGURE 3C.

FIGURE 3.

Design Example: Down Converter Mixer The design flexibility of the HFA3101 is demonstrated by a low
Figure 4 shows an example of a low cost mixer for cellular cost, and low voltage mixer application at the 900MHz range.
applications. The choice of good quality chip components with their self
VCC resonance outside the boundaries of the application are
3V important. The design has been optimized to accommodate
LO IN
0.1 the evaluation of the same layout for various quiescent current
0.01 LCH 2K
390nH values and lower supply voltages. The choice of RE became
IF OUT
important for the available overhead and also for maintaining
825MHz 51
an AC true impedance for high frequency signals. The value of
VCC 5p TO 12p
8

27 has been found to be the optimum minimum for the

75MHz application. The input impedances of the HFA3101 base input
0.01
ports are high enough to permit their termination with 50
110 Q1 Q2 Q3 Q4 resistors. Notice the AC termination by decoupling the bias
Q5 Q6 circuit through good quality capacitors.
RF IN
0.01 The choice of the bias has been related to the available power
330
1

0.01
supply voltage with the values of R1, R2 and RBIAS splitting the
51 voltages for optimum VCE values. For evaluation of the cell
900MHz quiescent currents, the voltage at the emitter resistor RE has
0.01 220 been recorded.
27
The gain of the circuit, being a function of the load and the
combined emitter resistances at high frequencies have been
FIGURE 4. 3V DOWN CONVERTER APPLICATION kept to a maximum by the use of an output match network. The
high output impedance of the HFA3101 permits broadband
match if so desired at 50 (RL = 50 to 2k) as well as with
tuned medium Q matching networks (L, T etc.).

FN3663 Rev 5.00 Page 7 of 12

September 2004
HFA3101

Stability setup as in Table 1. S22 characterization is enough to assure

The cell, by its nature, has very high gain and precautions the calculation of L, T or transmission line matching networks.
must be taken to account for the combination of signal TABLE 1. S22 PARAMETERS FOR DOWN CONVERSION,
reflections, gain, layout and package parasitics. The rule of LCH = 10H
thumb of avoiding reflected waves must be observed. It is
FREQUENCY RESISTANCE REACTANCE
important to assure good matching between the mixer stage
and its front end. Laboratory measurements have shown some 10MHz 265 615
susceptibility for oscillation at the upper quad transistors input. 45MHz 420 - 735
Any LO prefiltering has to be designed such the return loss is
75MHz 122 - 432
maintained within acceptable limits specially at high
frequencies. Typical off the shelf filters exhibits very poor 100MHz 67 - 320
return loss for signals outside the passband. It is suggested
that a “pad” or a broadband resistive network be used to TABLE 2. TYPICAL PARAMETERS FOR DOWN CONVERSION,
interface the LO port with a filter. The inclusion of a parallel 2K LCH = 10H
resistor in the load decreases the gain slightly which improves
VCC = 3V,
the stability factor and also improves the distortion products
PARAMETER LO LEVEL IBIAS = 8mA
(output intermodulation or 3rd order intercept). The
Power Gain -6dBm 8.5dB
employment of good RF techniques shall suffice the stability
requirements. TOI Output -6dBm 11.5dBm
NF SSB -6dBm 14.5dB
Evaluation
The evaluation of the HFA3101 in a mixer configuration is Power Gain 0dBm 8.6dB
presented in Figures 6 to 11, Table 1 and Table 2. The layout TOI Output 0dBm 11dBm
is depicted in Figure 5. NF SSB 0dBm 15dB

VCC = 4V,
PARAMETER LO LEVEL IBIAS = 19mA
Power Gain -6dBm 10dB
TOI Output -6dBm 13dBm
NF SSB -6dBm 20dB
Power Gain 0dBm 11dB
TOI Output 0dBm 12.5dBm
NF SSB 0dBm 24dB

TABLE 3. TYPICAL VALUES OF S22 FOR THE OUTPUT PORT.

LCH = 390nH IBIAS = 8mA (SET UP OF FIGURE 11)

FREQUENCY RESISTANCE REACTANCE

300MHz 22 -115
600MHz 7.5 -43
900MHz 5.2 -14
1.1GHz 3.9 0

TABLE 4. TYPICAL VALUES OF S22. LCH = 390nH, IBIAS = 18mA

FREQUENCY RESISTANCE REACTANCE

FIGURE 5. UP/DOWN CONVERTER LAYOUT, 400%;
300MHz 23.5 -110
MATERIAL G10, 0.031
600MHz 10.3 -39
The output matching network has been designed from data 900MHz 8.7 -14
taken at the output port at various test frequencies with the
1.1GHz 8 0

FN3663 Rev 5.00 Page 8 of 12

September 2004
HFA3101

Up Converter Example can permit the evaluation of a frequency doubler to 2.4GHz if

An application for a up converter as well as a frequency so desired.
multiplier can be demonstrated using the same layout, with an The addition of the resistors REE can increase considerably
addition of matching components. The output port S22 must be the dynamic range of the up converter as demonstrated at
characterized for proper matching procedures and depending Figure 13. The evaluation results depicted in Table 5 have
on the frequency desired for the output, transmission line been obtained by a triple stub tuner as a matching network for
transformations can be designed. The return loss of the input the output due to the layout constraints. Based on the
ports maintain acceptable values in excess of 1.2GHz which evaluation results it is clear that the cell requires a higher Bias
current for overall performance.

VCC 3V
S11 LOG MAG
LCH 0dB
0.1 5dB/DIV
2K

4V
8

3V

Q1 Q2 Q3 Q4

Q5 Q6
1

100MHz 1.1GHz
FIGURE 6. OUTPUT PORT S22 TEST SET UP FIGURE 7. LO PORT RETURN LOSS

S11 LOG MAG S22 LOG MAG

0dB 0dB
10dB/DIV 5dB/DIV

100MHz 1.1GHz 10MHz 110MHz

FIGURE 8. RF PORT RETURN LOSS FIGURE 9. IF PORT RETURN LOSS, WITH MATCHING
NETWORK

RF = 901MHz - 25dBm RF = 900MHz -25dBm

LO = 825MHz -6dBm LO = 825MHz -6dBm
10dB/ 10dB/
DIV -17dBm DIV
-26dBm

-36dBm

-53dBm

-58dBm
SPAN SPAN
40MHz 500MHz
64M 76MHz 88M 675 750 825 900 975
11*LO - 10RF IF 12RF - 13LO LO - 2RF LO + 2RF

FIGURE 10. TYPICAL IN BAND OUTPUT SPECTRUM, VCC = 3V FIGURE 11. TYPICAL OUT OF BAND OUTPUT SPECTRUM

FN3663 Rev 5.00 Page 9 of 12

September 2004
HFA3101

Design Example: Up Converter Mixer TABLE 5. TYPICAL PARAMETERS FOR THE UP CONVERTER
EXAMPLE
Figure 12 shows an example of an up converter for cellular
applications. VCC = 3V, VCC = 4V,
PARAMETER IBIAS = 8mA IBIAS = 18mA
Conclusion Power Gain, LO = -6dBm 3dB 5.5dBm
The HFA3101 offers the designer a number of choices and
Power Gain, LO = 0dBm 4dB 7.2dB
different applications as a powerful RF building block. Although
isolation is degraded from the theoretical results for the cell RF Isolation, LO = 0dBm 15dBc 22dBc
due to the unbalanced, nondifferential input schemes being LO Isolation, LO = 0dBm 28dBc 28dBc
used, a number of advantages can be taken into consideration
like cost, flexibility, low power and small outline when deciding
for a design.

VCC 3V

47-100pF 0.1
LO IN
0.01 390nH
825MHz
0.01 5.2nH
51 900MHz
11p
8

5
VCC 3V

0.01
110
Q1 Q2 Q3 Q4

Q5 Q6
0.01 RF IN
0.01
330 75MHz
1

REE REE 51

0.01
220

27

FIGURE 12. UP CONVERTER

OUTPUT WITHOUT EMITTER DEGENERATION OUTPUT WITH EMITTER DEGENERATION REE = 4.7 EXPANDED SPECTRUM REE = 4.7

890 901 912 SPAN 825 900 976

2LO - 10RF 12RF 50MHz

RF = 76MHz
LO = 825MHz
FIGURE 13. TYPICAL SPECTRUM PERFORMANCE OF UP CONVERTER

FN3663 Rev 5.00 Page 10 of 12

September 2004
HFA3101

Typical Performance Curves for Transistors

140
70
VCE = 5V
IB = 1mA
120
60
IB = 800A
100
50
IB = 600A
80
IC (mA)

40

hFE
IB = 400A 60
30
40
20 IB = 200A
20
10
0
0 10-10 10-8 10-6 10-4 10-2 100
0 2.0 4.0 6.0 IC (A)
VCE (V)

FIGURE 14. IC vs VCE FIGURE 15. HFE vs IC

100
12
VCE = 3V
10-2
10

10-4
IC AND IB (A)

8
fT (GHz)

10-6 6

10-8 4

10-10 2

10-12 0
0.20 0.40 0.60 0.80 1.0 10-4 10-3 10-2 10-1
VBE (V) IC (A)

FIGURE 16. GUMMEL PLOT FIGURE 17. fT vs IC

4.8 20

4.6 18

4.4 16
NOISE FIGURE (dB)

4.2 14
|S21| (dB)

4.0 12

3.8 10

3.6 8

3.4 6

3.2 4
0 0.5 1.0 1.5 2.0 2.5 3.0
FREQUENCY (GHz)

FIGURE 18. GAIN AND NOISE FIGURE vs FREQUENCY

NOTE: Figures 14 through 18 are only for Q5 and Q6.

FN3663 Rev 5.00 Page 11 of 12

September 2004
HFA3101

Die Characteristics
PROCESS PASSIVATION:
UHF-1 Type: Nitride
Thickness: 4kÅ 0.5kÅ
DIE DIMENSIONS:
53 mils x 52 mils x 14 mils SUBSTRATE POTENTIAL (Powered Up):
1340m x 1320m x 355.6m Floating

METALLIZATION:
Type: Metal 1: AlCu(2%)/TiW
Thickness: Metal 1: 8kÅ 0.5kÅ

Type: Metal 2: AlCu(2%)

Thickness: Metal 2: 16kÅ 0.8kÅ

Metallization Mask Layout

HFA3101

7 7 6 6

8 5

8 5

1 4

1 4

2 2 3 3

© Copyright Intersil Americas LLC 1998-2004. All Rights Reserved.

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com

FN3663 Rev 5.00 Page 12 of 12

September 2004