16F87X Datasheet - Version Resumida

PIC16F87X
Data Sheet
28/40-Pin 8-Bit CMOS FLASH
Microcontrollers
 2001 Microchip Technology Inc. DS30292C

PIC16F87X
28/40-Pin 8-Bit CMOS FLASH Microcontrollers
Devices Included in this Data Sheet: Pin Diagram

• PIC16F873 • PIC16F876 PDIP
• PIC16F874 • PIC16F877
MCLR/VPP 1 40 RB7/PGD
RA0/AN0 2 39 RB6/PGC
Microcontroller Core Features: RA1/AN1 3 38 RB5
RA2/AN2/VREF- 4 37 RB4
• High performance RISC CPU RA3/AN3/VREF+ 5 36 RB3/PGM
• Only 35 single word instructions to learn RA4/T0CKI 6 35 RB2
RA5/AN4/SS 7 34 RB1
• All single cycle instructions except for program
PIC16F877/874
RE0/RD/AN5 8 33 RB0/INT
branches which are two cycle RE1/WR/AN6 9 32 VDD
• Operating speed: DC - 20 MHz clock input RE2/CS/AN7 10 31 VSS
VDD 11 30 RD7/PSP7
DC - 200 ns instruction cycle
VSS 12 29 RD6/PSP6
• Up to 8K x 14 words of FLASH Program Memory, OSC1/CLKIN 13 28 RD5/PSP5
Up to 368 x 8 bytes of Data Memory (RAM) OSC2/CLKOUT 14 27 RD4/PSP4
Up to 256 x 8 bytes of EEPROM Data Memory RC0/T1OSO/T1CKI 15 26 RC7/RX/DT

RC1/T1OSI/CCP2 16 25 RC6/TX/CK
• Pinout compatible to the PIC16C73B/74B/76/77 RC2/CCP1 17 24 RC5/SDO
• Interrupt capability (up to 14 sources) RC3/SCK/SCL 18 23 RC4/SDI/SDA
RD0/PSP0 19 22 RD3/PSP3
• Eight level deep hardware stack RD1/PSP1 20 21 RD2/PSP2
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST) Peripheral Features:
• Watchdog Timer (WDT) with its own on-chip RC • Timer0: 8-bit timer/counter with 8-bit prescaler
oscillator for reliable operation • Timer1: 16-bit timer/counter with prescaler,
• Programmable code protection can be incremented during SLEEP via external
• Power saving SLEEP mode crystal/clock
• Selectable oscillator options • Timer2: 8-bit timer/counter with 8-bit period
• Low power, high speed CMOS FLASH/EEPROM register, prescaler and postscaler
technology • Two Capture, Compare, PWM modules
• Fully static design - Capture is 16-bit, max. resolution is 12.5 ns
• In-Circuit Serial Programming (ICSP) via two - Compare is 16-bit, max. resolution is 200 ns
pins - PWM max. resolution is 10-bit
• Single 5V In-Circuit Serial Programming capability • 10-bit multi-channel Analog-to-Digital converter
• In-Circuit Debugging via two pins • Synchronous Serial Port (SSP) with SPI (Master
• Processor read/write access to program memory mode) and I2C (Master/Slave)
• Wide operating voltage range: 2.0V to 5.5V • Universal Synchronous Asynchronous Receiver
• High Sink/Source Current: 25 mA Transmitter (USART/SCI) with 9-bit address
• Commercial, Industrial and Extended temperature detection
ranges • Parallel Slave Port (PSP) 8-bits wide, with
• Low-power consumption: external RD, WR and CS controls (40/44-pin only)
- < 0.6 mA typical @ 3V, 4 MHz • Brown-out detection circuitry for
Brown-out Reset (BOR)
- 20 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
 2001 Microchip Technology Inc. DS30292C-page 1

PIC16F87X
Pin Diagrams
PDIP, SOIC
MCLR/VPP 1 28 RB7/PGD
RA0/AN0 2 27 RB6/PGC
RA1/AN1 3 26 RB5
PIC16F876/873
RA2/AN2/VREF- 4 25 RB4
RA3/AN3/VREF+ 5 24 RB3/PGM
RA4/T0CKI 6 23 RB2
RA5/AN4/SS 7 22 RB1
VSS 8 21 RB0/INT
OSC1/CLKIN 9 20 VDD
OSC2/CLKOUT 10 19 VSS
RC0/T1OSO/T1CKI 11 18 RC7/RX/DT
RC1/T1OSI/CCP2 12 17 RC6/TX/CK
RC2/CCP1 13 16 RC5/SDO
RC3/SCK/SCL 14 15 RC4/SDI/SDA
RA3/AN3/VREF+
RA2/AN2/VREF-
MCLR/VPP
RB7/PGD
RB6/PGC
RA1/AN1
RA0/AN0
PLCC
RB5
RB4
NC
NC
6
5
4
3
2
1
44
43
42
41
40
RA4/T0CKI 7 39 RB3/PGM
RA5/AN4/SS 8 38 RB2
RE0/RD/AN5 9 37 RB1
RE1/WR/AN6 10 36 RB0/INT
RE2/CS/AN7 11 PIC16F877 35 VDD
VDD 12 34 VSS
VSS 13
PIC16F874 33 RD7/PSP7
OSC1/CLKIN 14 32 RD6/PSP6
OSC2/CLKOUT 15 31 RD5/PSP5
RC0/T1OSO/T1CK1 16 30 RD4/PSP4
NC 17 9 RC7/RX/DT
18
19
20
21
22
23
24
25
26
27
282
RC1/T1OSI/CCP2
RC3/SCK/SCL
RC4/SDI/SDA
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RC1/T1OSI/CCP2
RC5/SDO
NC
RC4/SDI/SDA
RC6/TX/CK
RC6/TX/CK
RC2/CCP1
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC5/SDO
NC
QFP
44
43
42
41
40
39
38
37
36
35
34
RC7/RX/DT 1 33 NC
RD4/PSP4 2 32 RC0/T1OSO/T1CKI
RD5/PSP5 3 31 OSC2/CLKOUT
RD6/PSP6 4 30 OSC1/CLKIN
RD7/PSP7 5 PIC16F877 29 VSS
VSS 6 28 VDD
VDD 7
PIC16F874 27 RE2/AN7/CS
RB0/INT 8 26 RE1/AN6/WR
RB1 9 25 RE0/AN5/RD
RB2 10 24 RA5/AN4/SS
RB3/PGM 11 23 RA4/T0CKI
12
13
14
15
16
17
18
19
20
21
22
RA3/AN3/VREF+
RB4
RB5
RA0/AN0
RA1/AN1
NC
NC
RB6/PGC
RB7/PGD
MCLR/VPP
RA2/AN2/VREF-
DS30292C-page 2  2001 Microchip Technology Inc.

PIC16F87X
Key Features
PICmicro™ Mid-Range Reference PIC16F873 PIC16F874 PIC16F876 PIC16F877
Manual (DS33023)
Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz DC - 20 MHz

RESETS (and Delays) POR, BOR POR, BOR POR, BOR POR, BOR
(PWRT, OST) (PWRT, OST) (PWRT, OST) (PWRT, OST)
FLASH Program Memory
4K 4K 8K 8K
(14-bit words)
Data Memory (bytes) 192 192 368 368
EEPROM Data Memory 128 128 256 256
Interrupts 13 14 13 14
I/O Ports Ports A,B,C Ports A,B,C,D,E Ports A,B,C Ports A,B,C,D,E
Timers 3 3 3 3
Capture/Compare/PWM Modules 2 2 2 2
Serial Communications MSSP, USART MSSP, USART MSSP, USART MSSP, USART
Parallel Communications — PSP — PSP
10-bit Analog-to-Digital Module 5 input channels 8 input channels 5 input channels 8 input channels
Instruction Set 35 instructions 35 instructions 35 instructions 35 instructions

PIC16F87X
Table of Contents
1.0 Device Overview ................................................................................................................................................... 5
2.0 Memory Organization.......................................................................................................................................... 11
3.0 I/O Ports .............................................................................................................................................................. 29
4.0 Data EEPROM and FLASH Program Memory.................................................................................................... 41
5.0 Timer0 Module .................................................................................................................................................... 47
6.0 Timer1 Module .................................................................................................................................................... 51
7.0 Timer2 Module .................................................................................................................................................... 55
8.0 Capture/Compare/PWM Modules ....................................................................................................................... 57
9.0 Master Synchronous Serial Port (MSSP) Module ............................................................................................... 65
10.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ........................................ 95
11.0 Analog-to-Digital Converter (A/D) Module......................................................................................................... 111
12.0 Special Features of the CPU............................................................................................................................. 119
13.0 Instruction Set Summary................................................................................................................................... 135
14.0 Development Support ....................................................................................................................................... 143
15.0 Electrical Characteristics................................................................................................................................... 149
16.0 DC and AC Characteristics Graphs and Tables................................................................................................ 177
17.0 Packaging Information ...................................................................................................................................... 189
Appendix A: Revision History .................................................................................................................................... 197
Appendix B: Device Differences ................................................................................................................................ 197
Appendix C: Conversion Considerations ................................................................................................................... 198
Index .......................................................................................................................................................................... 199
On-Line Support ......................................................................................................................................................... 207
Reader Response ...................................................................................................................................................... 208
PIC16F87X Product Identification System ................................................................................................................. 209
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PIC16F87X
1.0 DEVICE OVERVIEW There are four devices (PIC16F873, PIC16F874,
PIC16F876 and PIC16F877) covered by this data
This document contains device specific information. sheet. The PIC16F876/873 devices come in 28-pin
Additional information may be found in the PICmicro™ packages and the PIC16F877/874 devices come in
Mid-Range Reference Manual (DS33023), which may 40-pin packages. The Parallel Slave Port is not
be obtained from your local Microchip Sales Represen- implemented on the 28-pin devices.
tative or downloaded from the Microchip website. The
The following device block diagrams are sorted by pin
Reference Manual should be considered a complemen-
number; 28-pin for Figure 1-1 and 40-pin for Figure 1-2.
tary document to this data sheet, and is highly recom-
The 28-pin and 40-pin pinouts are listed in Table 1-1
mended reading for a better understanding of the device
and Table 1-2, respectively.
architecture and operation of the peripheral modules.
FIGURE 1-1: PIC16F873 AND PIC16F876 BLOCK DIAGRAM
Program Data
Device Data Memory
FLASH EEPROM
PIC16F873 4K 192 Bytes 128 Bytes
PIC16F876 8K 368 Bytes 256 Bytes
13 Data Bus 8 PORTA

Program Counter
RA0/AN0
FLASH RA1/AN1
Program RA2/AN2/VREF-
Memory RAM RA3/AN3/VREF+
8 Level Stack File RA4/T0CKI
(13-bit) Registers RA5/AN4/SS
Program 14 PORTB
Bus RAM Addr(1) 9
RB0/INT
Addr MUX RB1
Instruction reg
RB2
Direct Addr 7 Indirect
8 Addr RB3/PGM
RB4
FSR reg RB5
RB6/PGC
STATUS reg RB7/PGD
8
PORTC
RC0/T1OSO/T1CKI
3 MUX
Power-up RC1/T1OSI/CCP2
Timer RC2/CCP1
Instruction Oscillator RC3/SCK/SCL
Decode & Start-up Timer RC4/SDI/SDA
ALU
Control Power-on RC5/SDO
Reset 8 RC6/TX/CK
RC7/RX/DT
Timing Watchdog
Generation Timer W reg
OSC1/CLKIN Brown-out
OSC2/CLKOUT Reset
In-Circuit
Debugger
Low Voltage
Programming
MCLR VDD, VSS
Timer0 Timer1 Timer2 10-bit A/D
Synchronous
Data EEPROM CCP1,2 USART
Serial Port
Note 1: Higher order bits are from the STATUS register.

PIC16F87X
TABLE 1-1: PIC16F873 AND PIC16F876 PINOUT DESCRIPTION
DIP SOIC I/O/P Buffer
Pin Name Description
Pin# Pin# Type Type
OSC1/CLKIN 9 9 I ST/CMOS(3) Oscillator crystal input/external clock source input.

OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
MCLR/VPP 1 1 I/P ST Master Clear (Reset) input or programming voltage input. This
pin is an active low RESET to the device.
PORTA is a bi-directional I/O port.
RA0/AN0 2 2 I/O TTL RA0 can also be analog input0.
RA1/AN1 3 3 I/O TTL RA1 can also be analog input1.
RA2/AN2/VREF- 4 4 I/O TTL RA2 can also be analog input2 or negative analog
reference voltage.
RA3/AN3/VREF+ 5 5 I/O TTL RA3 can also be analog input3 or positive analog
reference voltage.
RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0
module. Output is open drain type.
RA5/SS/AN4 7 7 I/O TTL RA5 can also be analog input4 or the slave select
for the synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT 21 21 I/O TTL/ST(1) RB0 can also be the external interrupt pin.
RB1 22 22 I/O TTL
RB2 23 23 I/O TTL
RB3/PGM 24 24 I/O TTL RB3 can also be the low voltage programming input.
RB4 25 25 I/O TTL Interrupt-on-change pin.
RB5 26 26 I/O TTL Interrupt-on-change pin.
RB6/PGC 27 27 I/O TTL/ST(2) Interrupt-on-change pin or In-Circuit Debugger pin. Serial
programming clock.
RB7/PGD 28 28 I/O TTL/ST(2) Interrupt-on-change pin or In-Circuit Debugger pin. Serial
programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1/T1OSI/CCP2 12 12 I/O ST RC1 can also be the Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output
for both SPI and I2C modes.
RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 20 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

PIC16F87X
2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization
There are three memory blocks in each of the The PIC16F87X devices have a 13-bit program counter
PIC16F87X MCUs. The Program Memory and Data capable of addressing an 8K x 14 program memory
Memory have separate buses so that concurrent space. The PIC16F877/876 devices have 8K x 14
access can occur and is detailed in this section. The words of FLASH program memory, and the
EEPROM data memory block is detailed in Section 4.0. PIC16F873/874 devices have 4K x 14. Accessing a
location above the physically implemented address will
Additional information on device memory may be found
cause a wraparound.
in the PICmicro Mid-Range Reference Manual,
(DS33023). The RESET vector is at 0000h and the interrupt vector
is at 0004h.
FIGURE 2-1: PIC16F877/876 PROGRAM

MEMORY MAP AND FIGURE 2-2: PIC16F874/873 PROGRAM
STACK MEMORY MAP AND
STACK
PC<12:0>
PC<12:0>
CALL, RETURN 13
CALL, RETURN 13
RETFIE, RETLW RETFIE, RETLW
Stack Level 1 Stack Level 1

Stack Level 2
Stack Level 2
Stack Level 8 Stack Level 8
RESET Vector 0000h RESET Vector 0000h
Interrupt Vector 0004h Interrupt Vector 0004h

0005h
0005h
Page 0
Page 0
07FFh On-Chip
07FFh
Program
0800h
Memory 0800h
Page 1
On-Chip Page 1
0FFFh
Program 0FFFh
Memory 1000h
1000h
Page 2
17FFh
1800h
Page 3
1FFFh
1FFFh

PIC16F87X
2.2 Data Memory Organization Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
The data memory is partitioned into multiple banks Function Registers. Above the Special Function Regis-
which contain the General Purpose Registers and the ters are General Purpose Registers, implemented as
Special Function Registers. Bits RP1 (STATUS<6>) static RAM. All implemented banks contain Special
and RP0 (STATUS<5>) are the bank select bits. Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
RP1:RP0 Bank Note: EEPROM Data Memory description can be
00 0 found in Section 4.0 of this data sheet.
01 1 2.2.1 GENERAL PURPOSE REGISTER
10 2 FILE
11 3
The register file can be accessed either directly, or indi-
rectly through the File Select Register (FSR).

PIC16F87X
FIGURE 2-3: PIC16F877/876 REGISTER FILE MAP
File File File File

Address Address Address Address
Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h 105h 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h 107h 187h
PORTD(1) 08h TRISD(1) 88h 108h 188h
PORTE(1) 09h TRISE(1) 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDATA 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2 18Dh
TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved(2) 18Eh
TMR1H 0Fh 8Fh EEADRH 10Fh Reserved(2) 18Fh
T1CON 10h 90h 110h 190h
TMR2 11h SSPCON2 91h 111h 191h
T2CON 12h PR2 92h 112h 192h
SSPBUF 13h SSPADD 93h 113h 193h
SSPCON 14h SSPSTAT 94h 114h 194h
CCPR1L 15h 95h 115h 195h
CCPR1H 16h 96h 116h 196h
CCP1CON 17h 97h General 117h General 197h
Purpose Purpose
RCSTA 18h TXSTA 98h Register 118h Register 198h
TXREG 19h SPBRG 99h 16 Bytes 119h 16 Bytes 199h
RCREG 1Ah 9Ah 11Ah 19Ah
CCPR2L 1Bh 9Bh 11Bh 19Bh
CCPR2H 1Ch 9Ch 11Ch 19Ch
CCP2CON 1Dh 9Dh 11Dh 19Dh
ADRESH 1Eh ADRESL 9Eh 11Eh 19Eh
ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh
20h A0h 120h 1A0h
General General General General

Purpose Purpose Purpose Purpose
Register Register Register Register
80 Bytes 80 Bytes 80 Bytes
96 Bytes EFh 16Fh 1EFh
F0h 170h accesses 1F0h
accesses accesses
70h-7Fh 70h-7Fh 70h - 7Fh
7Fh FFh 17Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
Unimplemented data memory locations, read as ’0’.

* Not a physical register.
Note 1: These registers are not implemented on the PIC16F876.
2: These registers are reserved, maintain these registers clear.

PIC16F87X
2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
The Special Function Registers are registers used by associated with the core functions are described in
the CPU and peripheral modules for controlling the detail in this section. Those related to the operation of
desired operation of the device. These registers are the peripheral features are described in detail in the
implemented as static RAM. A list of these registers is peripheral features section.
given in Table 2-1.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY

Value on: Details
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, on
BOR page:
Bank 0
00h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27
01h TMR0 Timer0 Module Register xxxx xxxx 47
02h(3) PCL Program Counter (PC) Least Significant Byte 0000 0000 26
03h(3) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 18
04h(3) FSR Indirect Data Memory Address Pointer xxxx xxxx 27
05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 29
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 31
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx 33
08h(4) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx 35
09h(4) PORTE — — — — — RE2 RE1 RE0 ---- -xxx 36
0Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 26
0Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 20
0Ch PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 22
0Dh PIR2 — (5) — EEIF BCLIF — — CCP2IF -r-0 0--0 24
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 52
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 52
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 51
11h TMR2 Timer2 Module Register 0000 0000 55
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 55
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 70, 73
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 67
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx 57
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx 57
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 58
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 96
19h TXREG USART Transmit Data Register 0000 0000 99
1Ah RCREG USART Receive Data Register 0000 0000 101
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx 57
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx 57
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 58
1Eh ADRESH A/D Result Register High Byte xxxx xxxx 116
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 111
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’.
5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.

PIC16F87X
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on: Details
BOR page:
Bank 1
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19
85h TRISA — — PORTA Data Direction Register --11 1111 29
86h TRISB PORTB Data Direction Register 1111 1111 31
87h TRISC PORTC Data Direction Register 1111 1111 33
88h(4) TRISD PORTD Data Direction Register 1111 1111 35
89h(4) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 37
8Ch PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 21
8Dh PIE2 — (5) — EEIE BCLIE — — CCP2IE -r-0 0--0 23
8Eh PCON — — — — — — POR BOR ---- --qq 25
8Fh — Unimplemented — —
90h — Unimplemented — —
91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 68
92h PR2 Timer2 Period Register 1111 1111 55
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 73, 74
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 66
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 95
99h SPBRG Baud Rate Generator Register 0000 0000 97
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx 116
9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 0--- 0000 112

PIC16F87X
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on: Details
BOR page:
Bank 2
101h TMR0 Timer0 Module Register xxxx xxxx 47
102h(3) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 26
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 31
10Ch EEDATA EEPROM Data Register Low Byte xxxx xxxx 41
10Dh EEADR EEPROM Address Register Low Byte xxxx xxxx 41
10Eh EEDATH — — EEPROM Data Register High Byte xxxx xxxx 41
10Fh EEADRH — — — EEPROM Address Register High Byte xxxx xxxx 41
Bank 3
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19
186h TRISB PORTB Data Direction Register 1111 1111 31
18Ch EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 41, 42
18Dh EECON2 EEPROM Control Register2 (not a physical register) ---- ---- 41
18Eh — Reserved maintain clear 0000 0000 —
18Fh — Reserved maintain clear 0000 0000 —

PIC16F87X
2.2.2.1 STATUS Register For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
The STATUS register contains the arithmetic status of
as 000u u1uu (where u = unchanged).
the ALU, the RESET status and the bank select bits for
data memory. It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
The STATUS register can be the destination for any
STATUS register, because these instructions do not
instruction, as with any other register. If the STATUS
affect the Z, C or DC bits from the STATUS register. For
register is the destination for an instruction that affects
other instructions not affecting any status bits, see the
the Z, DC or C bits, then the write to these three bits is
“Instruction Set Summary."
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not Note: The C and DC bits operate as a borrow
writable, therefore, the result of an instruction with the and digit borrow bit, respectively, in sub-
STATUS register as destination may be different than traction. See the SUBLW and SUBWF
intended. instructions for examples.
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C
bit 7 bit 0
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
(for borrow, the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high, or low order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F87X
2.2.2.2 OPTION_REG Register
Note: To achieve a 1:1 prescaler assignment for
The OPTION_REG Register is a readable and writable
the TMR0 register, assign the prescaler to
register, which contains various control bits to configure
the Watchdog Timer.
the TMR0 prescaler/WDT postscaler (single assign-
able register known also as the prescaler), the External
INT Interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128
Legend:
Note: When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are enabled, bit 3
in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper oper-
ation of the device

PIC16F87X
2.2.2.3 INTCON Register
Note: Interrupt flag bits are set when an interrupt
The INTCON Register is a readable and writable regis-
condition occurs, regardless of the state of
ter, which contains various enable and flag bits for the
its corresponding enable bit or the global
TMR0 register overflow, RB Port change and External
enable bit, GIE (INTCON<7>). User soft-
RB0/INT pin interrupts.
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set
the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared
(must be cleared in software).
0 = None of the RB7:RB4 pins have changed state
Legend:

PIC16F87X
2.2.2.4 PIE1 Register
The PIE1 register contains the individual enable bits for Note: Bit PEIE (INTCON<6>) must be set to
the peripheral interrupts. enable any peripheral interrupt.
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)

PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
bit 7 PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit

1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1: PSPIE is reserved on PIC16F873/876 devices; always maintain this bit clear.
Legend:

PIC16F87X
2.2.2.5 PIR1 Register Note: Interrupt flag bits are set when an interrupt
The PIR1 register contains the individual flag bits for condition occurs, regardless of the state of
the peripheral interrupts. its corresponding enable bit or the global
ware should ensure the appropriate interrupt
bits are clear prior to enabling an interrupt.
REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit

1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1 = The SSP interrupt condition has occurred, and must be cleared in software before returning
from the Interrupt Service Routine. The conditions that will set this bit are:
• SPI
- A transmission/reception has taken place.
• I2C Slave
• I2C Master
- The initiated START condition was completed by the SSP module.
- The initiated STOP condition was completed by the SSP module.
- The initiated Restart condition was completed by the SSP module.
- The initiated Acknowledge condition was completed by the SSP module.
- A START condition occurred while the SSP module was idle (Multi-Master system).
- A STOP condition occurred while the SSP module was idle (Multi-Master system).
0 = No SSP interrupt condition has occurred.
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: PSPIF is reserved on PIC16F873/876 devices; always maintain this bit clear.
Legend:

PIC16F87X
2.2.2.6 PIE2 Register
The PIE2 register contains the individual enable bits for
the CCP2 peripheral interrupt, the SSP bus collision
interrupt, and the EEPROM write operation interrupt.
REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh)

U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0
— Reserved — EEIE BCLIE — — CCP2IE
bit 7 bit 0
bit 7 Unimplemented: Read as '0'

bit 6 Reserved: Always maintain this bit clear
bit 4 EEIE: EEPROM Write Operation Interrupt Enable
1 = Enable EE Write Interrupt
0 = Disable EE Write Interrupt
bit 3 BCLIE: Bus Collision Interrupt Enable
1 = Enable Bus Collision Interrupt
0 = Disable Bus Collision Interrupt
bit 2-1 Unimplemented: Read as '0'
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:

PIC16F87X
2.2.2.7 PIR2 Register .
Note: Interrupt flag bits are set when an interrupt
The PIR2 register contains the flag bits for the CCP2
condition occurs, regardless of the state of
interrupt, the SSP bus collision interrupt and the
its corresponding enable bit or the global
EEPROM write operation interrupt.
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)

U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0
— Reserved — EEIF BCLIF — — CCP2IF
bit 7 bit 0

bit 6 Reserved: Always maintain this bit clear
bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the SSP, when configured for I2C Master mode
0 = No bus collision has occurred
bit 0 CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused
Legend:

PIC16F87X
2.2.2.8 PCON Register Note: BOR is unknown on POR. It must be set by
The Power Control (PCON) Register contains flag bits the user and checked on subsequent
to allow differentiation between a Power-on Reset RESETS to see if BOR is clear, indicating
(POR), a Brown-out Reset (BOR), a Watchdog Reset a brown-out has occurred. The BOR status
(WDT), and an external MCLR Reset. bit is a “don’t care” and is not predictable if
the brown-out circuit is disabled (by clear-
ing the BODEN bit in the configuration
word).
REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1
— — — — — — POR BOR
bit 7 bit 0

bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:

PIC16F87X
2.3 PCL and PCLATH Note 1: There are no status bits to indicate stack
The program counter (PC) is 13-bits wide. The low byte overflow or stack underflow conditions.
comes from the PCL register, which is a readable and 2: There are no instructions/mnemonics
writable register. The upper bits (PC<12:8>) are not called PUSH or POP. These are actions
readable, but are indirectly writable through the that occur from the execution of the
PCLATH register. On any RESET, the upper bits of the CALL, RETURN, RETLW and RETFIE
PC will be cleared. Figure 2-5 shows the two situations instructions, or the vectoring to an inter-
for the loading of the PC. The upper example in the fig- rupt address.
ure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the fig- 2.4 Program Memory Paging
ure shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PCH). All PIC16F87X devices are capable of addressing a
continuous 8K word block of program memory. The
CALL and GOTO instructions provide only 11 bits of
FIGURE 2-5: LOADING OF PC IN
address to allow branching within any 2K program
DIFFERENT SITUATIONS memory page. When doing a CALL or GOTO instruction,
the upper 2 bits of the address are provided by
PCH PCL PCLATH<4:3>. When doing a CALL or GOTO instruc-
12 8 7 0 Instruction with
tion, the user must ensure that the page select bits are
PC PCL as programmed so that the desired program memory
Destination page is addressed. If a return from a CALL instruction
PCLATH<4:0> 8
5 ALU (or interrupt) is executed, the entire 13-bit PC is popped
off the stack. Therefore, manipulation of the
PCLATH
PCLATH<4:3> bits is not required for the return instruc-
tions (which POPs the address from the stack).
PCH PCL
Note: The contents of the PCLATH register are
12 11 10 8 7 0
unchanged after a RETURN or RETFIE
PC GOTO,CALL instruction is executed. The user must
PCLATH<4:3> 11 rewrite the contents of the PCLATH regis-
2 Opcode <10:0> ter for any subsequent subroutine calls or
GOTO instructions.
PCLATH
Example 2-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the Interrupt
2.3.1 COMPUTED GOTO Service Routine (if interrupts are used).
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a EXAMPLE 2-1: CALL OF A SUBROUTINE
table read using a computed GOTO method, care IN PAGE 1 FROM PAGE 0
should be exercised if the table location crosses a PCL ORG 0x500
memory boundary (each 256 byte block). Refer to the BCF PCLATH,4
application note, “Implementing a Table Read" BSF PCLATH,3 ;Select page 1
(AN556). ;(800h-FFFh)
CALL SUB1_P1 ;Call subroutine in
2.3.2 STACK : ;page 1 (800h-FFFh)
:
The PIC16F87X family has an 8-level deep x 13-bit wide ORG 0x900 ;page 1 (800h-FFFh)
hardware stack. The stack space is not part of either pro- SUB1_P1
gram or data space and the stack pointer is not readable : ;called subroutine
or writable. The PC is PUSHed onto the stack when a ;page 1 (800h-FFFh)
CALL instruction is executed, or an interrupt causes a :
RETURN ;return to
branch. The stack is POPed in the event of a
;Call subroutine
RETURN,RETLW or a RETFIE instruction execution. ;in page 0
PCLATH is not affected by a PUSH or POP operation. ;(000h-7FFh)
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).

PIC16F87X
2.5 Indirect Addressing, INDF and A simple program to clear RAM locations 20h-2Fh
FSR Registers using indirect addressing is shown in Example 2-2.
The INDF register is not a physical register. Addressing EXAMPLE 2-2: INDIRECT ADDRESSING
the INDF register will cause indirect addressing. MOVLW 0x20 ;initialize pointer
Indirect addressing is possible by using the INDF reg- MOVWF FSR ;to RAM
ister. Any instruction using the INDF register actually NEXT CLRF INDF ;clear INDF register
accesses the register pointed to by the File Select Reg- INCF FSR,F ;inc pointer
ister, FSR. Reading the INDF register itself, indirectly BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next
(FSR = ’0’) will read 00h. Writing to the INDF register
CONTINUE
indirectly results in a no operation (although status bits : ;yes continue
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 2-6.
FIGURE 2-6: DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing
RP1:RP0 6 From Opcode 0 IRP 7 FSR register 0
Bank Select Location Select Bank Select Location Select

00 01 10 11
00h 80h 100h 180h
Data
Memory(1)
7Fh FFh 17Fh 1FFh

Bank 0 Bank 1 Bank 2 Bank 3
Note 1: For register file map detail, see Figure 2-3.

PIC16F87X
3.0 I/O PORTS FIGURE 3-1: BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the Data Data Latch
Bus
device. In general, when a peripheral is enabled, that D Q
pin may not be used as a general purpose I/O pin.
VDD
WR
Additional information on I/O ports may be found in the Port
PICmicro™ Mid-Range Reference Manual, (DS33023). CK Q
P I/O pin(1)
3.1 PORTA and the TRISA Register TRIS Latch

N
D Q
PORTA is a 6-bit wide, bi-directional port. The corre-
sponding data direction register is TRISA. Setting a WR
TRISA bit (= 1) will make the corresponding PORTA pin TRIS VSS
CK Q
an input (i.e., put the corresponding output driver in a Analog
Hi-Impedance mode). Clearing a TRISA bit (= 0) will Input
Mode
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
RD
Reading the PORTA register reads the status of the TRIS TTL
pins, whereas writing to it will write to the port latch. All Input
Buffer
write operations are read-modify-write operations. Q D
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch. EN
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI RD Port
pin is a Schmitt Trigger input and an open drain output.
All other PORTA pins have TTL input levels and full
To A/D Converter
CMOS output drivers.
Other PORTA pins are multiplexed with analog inputs Note 1: I/O pins have protection diodes to VDD and VSS.
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1). FIGURE 3-2: BLOCK DIAGRAM OF
RA4/T0CKI PIN
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as '0'. Data Data Latch
Bus D Q
The TRISA register controls the direction of the RA WR
pins, even when they are being used as analog inputs. Port
CK Q
The user must ensure the bits in the TRISA register are N I/O pin(1)
maintained set when using them as analog inputs. TRIS Latch
D Q VSS
EXAMPLE 3-1: INITIALIZING PORTA WR
TRIS Schmitt
BCF STATUS, RP0 ; CK Q
Trigger
BCF STATUS, RP1 ; Bank0 Input
CLRF PORTA ; Initialize PORTA by Buffer
; clearing output RD
; data latches TRIS
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0x06 ; Configure all pins
MOVWF ADCON1 ; as digital inputs Q D
MOVLW 0xCF ; Value used to
; initialize data ENEN
; direction
RD Port
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6>are always TMR0 Clock Input
; read as ’0’.
Note 1: I/O pin has protection diodes to VSS only.

PIC16F87X
TABLE 3-1: PORTA FUNCTIONS
Name Bit# Buffer Function

RA0/AN0 bit0 TTL Input/output or analog input.
RA3/AN3/VREF bit3 TTL Input/output or analog input or VREF.
RA4/T0CKI bit4 ST Input/output or external clock input for Timer0. Output is open drain type.
RA5/SS/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on: Value on all

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other
BOR RESETS
05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
Shaded cells are not used by PORTA.
Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of
the following modes, where PCFG3:PCFG0 = 0100,0101, 011x, 1101, 1110, 1111.

PIC16F87X
3.2 PORTB and the TRISB Register This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
PORTB is an 8-bit wide, bi-directional port. The corre- interrupt in the following manner:
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB pin a) Any read or write of PORTB. This will end the
an input (i.e., put the corresponding output driver in a mismatch condition.
Hi-Impedance mode). Clearing a TRISB bit (= 0) will b) Clear flag bit RBIF.
make the corresponding PORTB pin an output (i.e., put A mismatch condition will continue to set flag bit RBIF.
the contents of the output latch on the selected pin). Reading PORTB will end the mismatch condition and
Three pins of PORTB are multiplexed with the Low allow flag bit RBIF to be cleared.
Voltage Programming function: RB3/PGM, RB6/PGC The interrupt-on-change feature is recommended for
and RB7/PGD. The alternate functions of these pins wake-up on key depression operation and operations
are described in the Special Features Section. where PORTB is only used for the interrupt-on-change
Each of the PORTB pins has a weak internal pull-up. A feature. Polling of PORTB is not recommended while
single control bit can turn on all the pull-ups. This is per- using the interrupt-on-change feature.
formed by clearing bit RBPU (OPTION_REG<7>). The This interrupt-on-mismatch feature, together with soft-
weak pull-up is automatically turned off when the port ware configureable pull-ups on these four pins, allow
pin is configured as an output. The pull-ups are dis- easy interface to a keypad and make it possible for
abled on a Power-on Reset. wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-up on Key
FIGURE 3-3: BLOCK DIAGRAM OF Strokes” (AN552).
RB3:RB0 PINS RB0/INT is an external interrupt input pin and is config-
VDD ured using the INTEDG bit (OPTION_REG<6>).
RBPU(2)
Weak RB0/INT is discussed in detail in Section 12.10.1.
P Pull-up
Data Latch
Data Bus
D Q FIGURE 3-4: BLOCK DIAGRAM OF
WR Port
I/O RB7:RB4 PINS
CK pin(1)
VDD
TRIS Latch
RBPU(2)
D Q Weak
P Pull-up
TTL
WR TRIS Input Data Latch
CK Buffer Data Bus
D Q
I/O
WR Port CK pin(1)
RD TRIS
TRIS Latch
D Q
Q D
RD Port WR TRIS TTL
CK Input
EN
Buffer ST
Buffer
RB0/INT
RB3/PGM
RD TRIS
Latch
Schmitt Trigger RD Port
Buffer Q D
RD Port
Note 1: I/O pins have diode protection to VDD and VSS. EN Q1
2: To enable weak pull-ups, set the appropriate TRIS Set RBIF
bit(s) and clear the RBPU bit (OPTION_REG<7>).
Q D
Four of the PORTB pins, RB7:RB4, have an interrupt- RD Port
From other
on-change feature. Only pins configured as inputs can RB7:RB4 pins EN
cause this interrupt to occur (i.e., any RB7:RB4 pin Q3
configured as an output is excluded from the interrupt- RB7:RB6
on-change comparison). The input pins (of RB7:RB4) In Serial Programming Mode
are compared with the old value latched on the last Note 1: I/O pins have diode protection to VDD and VSS.
read of PORTB. The “mismatch” outputs of RB7:RB4 2: To enable weak pull-ups, set the appropriate TRIS
are OR’ed together to generate the RB Port Change bit(s) and clear the RBPU bit (OPTION_REG<7>).
Interrupt with flag bit RBIF (INTCON<0>).

PIC16F87X
TABLE 3-3: PORTB FUNCTIONS
Name Bit# Buffer Function
RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
(3)
RB3/PGM bit3 TTL Input/output pin or programming pin in LVP mode. Internal software
programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB5 bit5 TTL Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB6/PGC bit6 TTL/ST(2) Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming clock.
RB7/PGD bit7 TTL/ST(2) Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: Low Voltage ICSP Programming (LVP) is enabled by default, which disables the RB3 I/O function. LVP
must be disabled to enable RB3 as an I/O pin and allow maximum compatibility to the other 28-pin and
40-pin mid-range devices.
TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on: Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other
BOR RESETS
06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.

PIC16F87X
3.3 PORTC and the TRISC Register FIGURE 3-6: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
PORTC is an 8-bit wide, bi-directional port. The corre-
OVERRIDE) RC<4:3>
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC Port/Peripheral Select(2)
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISC bit (= 0) will Peripheral Data Out
0
make the corresponding PORTC pin an output (i.e., put VDD
Data Bus
the contents of the output latch on the selected pin). WR
D Q P I/O
Port 1 pin(1)
PORTC is multiplexed with several peripheral functions CK Q
(Table 3-5). PORTC pins have Schmitt Trigger input Data Latch
buffers.
D Q
When the I2C module is enabled, the PORTC<4:3> WR
TRIS
pins can be configured with normal I2C levels, or with CK Q N
SMBus levels by using the CKE bit (SSPSTAT<6>). TRIS Latch
Vss
When enabling peripheral functions, care should be RD
taken in defining TRIS bits for each PORTC pin. Some TRIS
Schmitt
peripherals override the TRIS bit to make a pin an out- Trigger
put, while other peripherals override the TRIS bit to Peripheral
OE(3) Q D
make a pin an input. Since the TRIS bit override is in Schmitt
Trigger
effect while the peripheral is enabled, read-modify- EN with
write instructions (BSF, BCF, XORWF) with TRISC as RD SMBus
Port 0 levels
destination, should be avoided. The user should refer SSPl Input
to the corresponding peripheral section for the correct
TRIS bit settings. 1
CKE
FIGURE 3-5: PORTC BLOCK DIAGRAM SSPSTAT<6>
(PERIPHERAL OUTPUT
Note 1: I/O pins have diode protection to VDD and VSS.
OVERRIDE) RC<2:0>, 2: Port/Peripheral select signal selects between port data
RC<7:5> and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
Port/Peripheral Select(2)
Peripheral Data Out

0 VDD
Data Bus
D Q
WR P I/O
Port CK Q 1 pin(1)
Data Latch
D Q
WR
TRIS CK Q
N
TRIS Latch
VSS
RD
TRIS
Schmitt
Trigger
Peripheral
OE(3) Q D
RD EN
Port
Peripheral Input
Note 1: I/O pins have diode protection to VDD and VSS.

2: Port/Peripheral select signal selects between port
data and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.

PIC16F87X
TABLE 3-5: PORTC FUNCTIONS
Name Bit# Buffer Type Function

RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input.
RC1/T1OSI/CCP2 bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/
Compare2 output/PWM2 output.
RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI
and I2C modes.
RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).
RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output.
RC6/TX/CK bit6 ST Input/output port pin or USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT bit7 ST Input/output port pin or USART Asynchronous Receive or
Synchronous Data.
Legend: ST = Schmitt Trigger input
TABLE 3-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on: Value on all

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other
BOR RESETS
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged

PIC16F87X
5.0 TIMER0 MODULE Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
The Timer0 module timer/counter has the following fea- increment either on every rising, or falling edge of pin
tures: RA4/T0CKI. The incrementing edge is determined by
• 8-bit timer/counter the Timer0 Source Edge Select bit, T0SE
• Readable and writable (OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
• 8-bit software programmable prescaler
discussed in detail in Section 5.2.
• Internal or external clock select
The prescaler is mutually exclusively shared between
• Interrupt on overflow from FFh to 00h
the Timer0 module and the Watchdog Timer. The pres-
• Edge select for external clock caler is not readable or writable. Section 5.3 details the
Figure 5-1 is a block diagram of the Timer0 module and operation of the prescaler.
the prescaler shared with the WDT.
5.1 Timer0 Interrupt
Additional information on the Timer0 module is avail-
able in the PICmicro™ Mid-Range MCU Family Refer- The TMR0 interrupt is generated when the TMR0 reg-
ence Manual (DS33023). ister overflows from FFh to 00h. This overflow sets bit
Timer mode is selected by clearing bit T0CS T0IF (INTCON<2>). The interrupt can be masked by
(OPTION_REG<5>). In Timer mode, the Timer0 mod- clearing bit T0IE (INTCON<5>). Bit T0IF must be
ule will increment every instruction cycle (without pres- cleared in software by the Timer0 module Interrupt Ser-
caler). If the TMR0 register is written, the increment is vice Routine before re-enabling this interrupt. The
inhibited for the following two instruction cycles. The TMR0 interrupt cannot awaken the processor from
user can work around this by writing an adjusted value SLEEP, since the timer is shut-off during SLEEP.
to the TMR0 register.
FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
CLKOUT (= FOSC/4) Data Bus
8
M 1
0
RA4/T0CKI U M
X SYNC
pin U 2 TMR0 Reg
1 0
X Cycles
T0SE
T0CS
PSA Set Flag Bit T0IF
on Overflow
PRESCALER
0
M 8-bit Prescaler
U
Watchdog 1 X 8
Timer
8 - to - 1MUX PS2:PS0
PSA
0 1
WDT Enable bit
MUX PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).

PIC16F87X
5.2 Using Timer0 with an External Timer0 module means that there is no prescaler for the
Clock Watchdog Timer, and vice-versa. This prescaler is not
readable or writable (see Figure 5-1).
When no prescaler is used, the external clock input is
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
the same as the prescaler output. The synchronization
determine the prescaler assignment and prescale ratio.
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and When assigned to the Timer0 module, all instructions
Q4 cycles of the internal phase clocks. Therefore, it is writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
necessary for T0CKI to be high for at least 2Tosc (and BSF 1,x....etc.) will clear the prescaler. When assigned
a small RC delay of 20 ns) and low for at least 2Tosc to WDT, a CLRWDT instruction will clear the prescaler
(and a small RC delay of 20 ns). Refer to the electrical along with the Watchdog Timer. The prescaler is not
specification of the desired device. readable or writable.
Note: Writing to TMR0, when the prescaler is
5.3 Prescaler assigned to Timer0, will clear the prescaler
There is only one prescaler available, which is mutually count, but will not change the prescaler
exclusively shared between the Timer0 module and the assignment.
Watchdog Timer. A prescaler assignment for the
REGISTER 5-1: OPTION_REG REGISTER

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU
bit 6 INTEDG
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128
Legend:
Note: To avoid an unintended device RESET, the instruction sequence shown in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023) must be executed when changing the prescaler assignment from
Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.

PIC16F87X
TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0
Value on: Value on

BOR RESETS
01h,101h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu

0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
Shaded cells are not used by Timer0.

PIC16F87X
10.0 ADDRESSABLE UNIVERSAL The USART can be configured in the following modes:
SYNCHRONOUS • Asynchronous (full duplex)
ASYNCHRONOUS RECEIVER • Synchronous - Master (half duplex)
TRANSMITTER (USART) • Synchronous - Slave (half duplex)
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to
The Universal Synchronous Asynchronous Receiver
be set in order to configure pins RC6/TX/CK and
Transmitter (USART) module is one of the two serial
RC7/RX/DT as the Universal Synchronous Asynchro-
I/O modules. (USART is also known as a Serial Com-
nous Receiver Transmitter.
munications Interface or SCI.) The USART can be con-
figured as a full duplex asynchronous system that can The USART module also has a multi-processor com-
communicate with peripheral devices such as CRT ter- munication capability using 9-bit address detection.
minals and personal computers, or it can be configured
as a half duplex synchronous system that can commu-
nicate with peripheral devices such as A/D or D/A inte-
grated circuits, serial EEPROMs etc.
REGISTER 10-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC — BRGH TRMT TX9D
bit 7 bit 0
bit 7 CSRC: Clock Source Select bit

Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.

bit 4 SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of Transmit Data, can be parity bit
Legend:

PIC16F87X
REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave:
Don’t care
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and load of the receive buffer when
RSR<8> is set
0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of Received Data (can be parity bit, but must be calculated by user firmware)
Legend:

PIC16F87X
10.1 USART Baud Rate Generator It may be advantageous to use the high baud rate
(BRG) (BRGH = 1), even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
The BRG supports both the Asynchronous and Syn- baud rate error in some cases.
chronous modes of the USART. It is a dedicated 8-bit
Writing a new value to the SPBRG register causes the
baud rate generator. The SPBRG register controls the
BRG timer to be reset (or cleared). This ensures the
period of a free running 8-bit timer. In Asynchronous
BRG does not wait for a timer overflow before output-
mode, bit BRGH (TXSTA<2>) also controls the baud
ting the new baud rate.
rate. In Synchronous mode, bit BRGH is ignored.
Table 10-1 shows the formula for computation of the 10.1.1 SAMPLING
baud rate for different USART modes which only apply
in Master mode (internal clock). The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
Given the desired baud rate and FOSC, the nearest
low level is present at the RX pin.
integer value for the SPBRG register can be calculated
using the formula in Table 10-1. From this, the error in
baud rate can be determined.
TABLE 10-1: BAUD RATE FORMULA
SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)

0 (Asynchronous) Baud Rate = FOSC/(64(X+1)) Baud Rate = FOSC/(16(X+1))
1 (Synchronous) Baud Rate = FOSC/(4(X+1)) N/A
X = value in SPBRG (0 to 255)
TABLE 10-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on: Value on

BOR RESETS
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.

PIC16F87X
TABLE 10-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz
BAUD
RATE SPBRG SPBRG SPBRG
% % %
(K) value value value
KBAUD ERROR KBAUD ERROR KBAUD ERROR
(decimal) (decimal) (decimal)
0.3 - - - - - - - - -
1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129
2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64
9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15
19.2 19.531 1.72 15 19.231 0.16 12 19.531 1.72 7
28.8 31.250 8.51 9 27.778 3.55 8 31.250 8.51 4
33.6 34.722 3.34 8 35.714 6.29 6 31.250 6.99 4
57.6 62.500 8.51 4 62.500 8.51 3 52.083 9.58 2
HIGH 1.221 - 255 0.977 - 255 0.610 - 255
LOW 312.500 - 0 250.000 - 0 156.250 - 0
FOSC = 4 MHz FOSC = 3.6864 MHz

BAUD
RATE SPBRG SPBRG
% %
(K) value value
ERROR ERROR
KBAUD (decimal) KBAUD (decimal)
0.3 0.300 0 207 0.3 0 191
1.2 1.202 0.17 51 1.2 0 47
2.4 2.404 0.17 25 2.4 0 23
9.6 8.929 6.99 6 9.6 0 5
19.2 20.833 8.51 2 19.2 0 2
28.8 31.250 8.51 1 28.8 0 1
33.6 - - - - - -
57.6 62.500 8.51 0 57.6 0 0
HIGH 0.244 - 255 0.225 - 255
LOW 62.500 - 0 57.6 - 0
TABLE 10-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)

FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz
BAUD
RATE SPBRG SPBRG SPBRG
% % %
(K) value value value
KBAUD ERROR KBAUD ERROR KBAUD ERROR
(decimal) (decimal) (decimal)
0.3 - - - - - - - - -
1.2 - - - - - - - - -
2.4 - - - - - - 2.441 1.71 255
9.6 9.615 0.16 129 9.615 0.16 103 9.615 0.16 64
19.2 19.231 0.16 64 19.231 0.16 51 19.531 1.72 31
28.8 29.070 0.94 42 29.412 2.13 33 28.409 1.36 21
33.6 33.784 0.55 36 33.333 0.79 29 32.895 2.10 18
57.6 59.524 3.34 20 58.824 2.13 16 56.818 1.36 10
HIGH 4.883 - 255 3.906 - 255 2.441 - 255
LOW 1250.000 - 0 1000.000 0 625.000 - 0
FOSC = 4 MHz FOSC = 3.6864 MHz

BAUD
RATE SPBRG SPBRG
% %
(K) value value
ERROR ERROR
KBAUD (decimal) KBAUD (decimal)
0.3 - - - - - -
1.2 1.202 0.17 207 1.2 0 191
2.4 2.404 0.17 103 2.4 0 95
9.6 9.615 0.16 25 9.6 0 23
19.2 19.231 0.16 12 19.2 0 11
28.8 27.798 3.55 8 28.8 0 7
33.6 35.714 6.29 6 32.9 2.04 6
57.6 62.500 8.51 3 57.6 0 3
HIGH 0.977 - 255 0.9 - 255
LOW 250.000 - 0 230.4 - 0

PIC16F87X
10.2 USART Asynchronous Mode enabled/disabled by setting/clearing enable bit TXIE
( PIE1<4>). Flag bit TXIF will be set, regardless of the
In this mode, the USART uses standard non-return-to- state of enable bit TXIE and cannot be cleared in soft-
zero (NRZ) format (one START bit, eight or nine data ware. It will reset only when new data is loaded into the
bits, and one STOP bit). The most common data format TXREG register. While flag bit TXIF indicates the status
is 8-bits. An on-chip, dedicated, 8-bit baud rate gener- of the TXREG register, another bit TRMT (TXSTA<1>)
ator can be used to derive standard baud rate frequen- shows the status of the TSR register. Status bit TRMT
cies from the oscillator. The USART transmits and is a read only bit, which is set when the TSR register is
receives the LSb first. The transmitter and receiver are empty. No interrupt logic is tied to this bit, so the user
functionally independent, but use the same data format has to poll this bit in order to determine if the TSR reg-
and baud rate. The baud rate generator produces a ister is empty.
clock, either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by Note 1: The TSR register is not mapped in data
the hardware, but can be implemented in software (and memory, so it is not available to the user.
stored as the ninth data bit). Asynchronous mode is 2: Flag bit TXIF is set when enable bit TXEN
stopped during SLEEP. is set. TXIF is cleared by loading TXREG.
Asynchronous mode is selected by clearing bit SYNC Transmission is enabled by setting enable bit TXEN
(TXSTA<4>). (TXSTA<5>). The actual transmission will not occur
The USART Asynchronous module consists of the fol- until the TXREG register has been loaded with data
lowing important elements: and the baud rate generator (BRG) has produced a
shift clock (Figure 10-2). The transmission can also be
• Baud Rate Generator
started by first loading the TXREG register and then
• Sampling Circuit setting enable bit TXEN. Normally, when transmission
• Asynchronous Transmitter is first started, the TSR register is empty. At that point,
• Asynchronous Receiver transfer to the TXREG register will result in an immedi-
ate transfer to TSR, resulting in an empty TXREG. A
10.2.1 USART ASYNCHRONOUS back-to-back transfer is thus possible (Figure 10-3).
TRANSMITTER Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
The USART transmitter block diagram is shown in transmitter. As a result, the RC6/TX/CK pin will revert
Figure 10-1. The heart of the transmitter is the transmit to hi-impedance.
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The In order to select 9-bit transmission, transmit bit TX9
TXREG register is loaded with data in software. The (TXSTA<6>) should be set and the ninth bit should be
TSR register is not loaded until the STOP bit has been written to TX9D (TXSTA<0>). The ninth bit must be
transmitted from the previous load. As soon as the written before writing the 8-bit data to the TXREG reg-
STOP bit is transmitted, the TSR is loaded with new ister. This is because a data write to the TXREG regis-
data from the TXREG register (if available). Once the ter can result in an immediate transfer of the data to the
TXREG register transfers the data to the TSR register TSR register (if the TSR is empty). In such a case, an
(occurs in one TCY), the TXREG register is empty and incorrect ninth data bit may be loaded in the TSR
flag bit TXIF (PIR1<4>) is set. This interrupt can be register.
FIGURE 10-1: USART TRANSMIT BLOCK DIAGRAM

Data Bus
TXIF TXREG Register
TXIE
8
MSb LSb
(8) • • • 0 Pin Buffer
and Control
TSR Register RC6/TX/CK pin
Interrupt
TXEN Baud Rate CLK

TRMT SPEN
SPBRG
Baud Rate Generator TX9

TX9D

PIC16F87X
When setting up an Asynchronous Transmission, 5. Enable the transmission by setting bit TXEN,
follow these steps: which will also set bit TXIF.
1. Initialize the SPBRG register for the appropriate 6. If 9-bit transmission is selected, the ninth bit
baud rate. If a high speed baud rate is desired, should be loaded in bit TX9D.
set bit BRGH (Section 10.1). 7. Load data to the TXREG register (starts trans-
2. Enable the asynchronous serial port by clearing mission).
bit SYNC and setting bit SPEN. 8. If using interrupts, ensure that GIE and PEIE
3. If interrupts are desired, then set enable bit (bits 7 and 6) of the INTCON register are set.
TXIE.
4. If 9-bit transmission is desired, then set transmit
bit TX9.
FIGURE 10-2: ASYNCHRONOUS MASTER TRANSMISSION

Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
START Bit Bit 0 Bit 1 Bit 7/8 STOP Bit
Word 1
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit Word 1

(Transmit Shift Transmit Shift Reg
Reg. Empty Flag)
FIGURE 10-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)

Write to TXREG
Word 1 Word 2
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
START Bit Bit 0 Bit 1 Bit 7/8 STOP Bit START Bit Bit 0
TXIF bit Word 1 Word 2
(Interrupt Reg. Flag)
TRMT bit Word 1

(Transmit Shift Word 2
Transmit Shift Reg. Transmit Shift Reg.
Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.
TABLE 10-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on: Value on

BOR RESETS
0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear.

PIC16F87X
10.2.2 USART ASYNCHRONOUS is possible for two bytes of data to be received and
RECEIVER transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
The receiver block diagram is shown in Figure 10-4. the STOP bit of the third byte, if the RCREG register is
The data is received on the RC7/RX/DT pin and drives still full, the overrun error bit OERR (RCSTA<1>) will be
the data recovery block. The data recovery block is set. The word in the RSR will be lost. The RCREG reg-
actually a high speed shifter, operating at x16 times the ister can be read twice to retrieve the two bytes in the
baud rate; whereas, the main receive serial shifter FIFO. Overrun bit OERR has to be cleared in software.
operates at the bit rate or at FOSC. This is done by resetting the receive logic (CREN is
Once Asynchronous mode is selected, reception is cleared and then set). If bit OERR is set, transfers from
enabled by setting bit CREN (RCSTA<4>). the RSR register to the RCREG register are inhibited,
and no further data will be received. It is therefore,
The heart of the receiver is the receive (serial) shift reg-
essential to clear error bit OERR if it is set. Framing
ister (RSR). After sampling the STOP bit, the received
error bit FERR (RCSTA<2>) is set if a STOP bit is
data in the RSR is transferred to the RCREG register (if
detected as clear. Bit FERR and the 9th receive bit are
it is empty). If the transfer is complete, flag bit RCIF
buffered the same way as the receive data. Reading
(PIR1<5>) is set. The actual interrupt can be enabled/
the RCREG will load bits RX9D and FERR with new
disabled by setting/clearing enable bit RCIE
values, therefore, it is essential for the user to read the
(PIE1<5>). Flag bit RCIF is a read only bit, which is
RCSTA register before reading the RCREG register in
cleared by the hardware. It is cleared when the RCREG
order not to lose the old FERR and RX9D information.
register has been read and is empty. The RCREG is a
double buffered register (i.e., it is a two deep FIFO). It
FIGURE 10-4: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK FERR

OERR
CREN
FOSC
SPBRG
÷64 MSb RSR Register LSb
or
Baud Rate Generator ÷16 STOP (8) 7 • • • 1 0 START
RC7/RX/DT
Pin Buffer Data
and Control Recovery RX9
SPEN RX9D RCREG Register

FIFO
Interrupt RCIF
Data Bus
RCIE

PIC16F87X
FIGURE 10-5: ASYNCHRONOUS RECEPTION
RX (pin) START START START

bit bit0 bit1 bit7/8 STOP bit bit0 bit7/8 STOP bit bit7/8 STOP
bit bit bit
Rcv Shift
Reg
Rcv Buffer Reg
Word 1 Word 2
RCREG RCREG
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
When setting up an Asynchronous Reception, follow 6. Flag bit RCIF will be set when reception is com-
these steps: plete and an interrupt will be generated if enable
1. Initialize the SPBRG register for the appropriate bit RCIE is set.
baud rate. If a high speed baud rate is desired, 7. Read the RCSTA register to get the ninth bit (if
set bit BRGH (Section 10.1). enabled) and determine if any error occurred
2. Enable the asynchronous serial port by clearing during reception.
bit SYNC and setting bit SPEN. 8. Read the 8-bit received data by reading the
3. If interrupts are desired, then set enable bit RCREG register.
RCIE. 9. If any error occurred, clear the error by clearing
4. If 9-bit reception is desired, then set bit RX9. enable bit CREN.
5. Enable the reception by setting bit CREN. 10. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 10-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on: Value on

BOR RESETS
0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u
10Bh,18Bh
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.

PIC16F87X
11.0 ANALOG-TO-DIGITAL The A/D module has four registers. These registers
are:
CONVERTER (A/D) MODULE
• A/D Result High Register (ADRESH)
The Analog-to-Digital (A/D) Converter module has five
• A/D Result Low Register (ADRESL)
inputs for the 28-pin devices and eight for the other
devices. • A/D Control Register0 (ADCON0)
• A/D Control Register1 (ADCON1)
The analog input charges a sample and hold capacitor.
The output of the sample and hold capacitor is the input The ADCON0 register, shown in Register 11-1, con-
into the converter. The converter then generates a dig- trols the operation of the A/D module. The ADCON1
ital result of this analog level via successive approxima- register, shown in Register 11-2, configures the func-
tion. The A/D conversion of the analog input signal tions of the port pins. The port pins can be configured
results in a corresponding 10-bit digital number. The as analog inputs (RA3 can also be the voltage refer-
A/D module has high and low voltage reference input ence), or as digital I/O.
that is software selectable to some combination of VDD, Additional information on using the A/D module can be
VSS, RA2, or RA3. found in the PICmicro™ Mid-Range MCU Family Ref-
The A/D converter has a unique feature of being able erence Manual (DS33023).
to operate while the device is in SLEEP mode. To oper-
ate in SLEEP, the A/D clock must be derived from the
A/D’s internal RC oscillator.
REGISTER 11-1: ADCON0 REGISTER (ADDRESS: 1Fh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON
bit 7 bit 0
bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits

00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from the internal A/D module RC oscillator)
bit 5-3 CHS2:CHS0: Analog Channel Select bits
000 = channel 0, (RA0/AN0)
101 = channel 5, (RE0/AN5)(1)
110 = channel 6, (RE1/AN6)(1)
111 = channel 7, (RE2/AN7)(1)
bit 2 GO/DONE: A/D Conversion Status bit
If ADON = 1:
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D
conversion is complete)
bit 0 ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shut-off and consumes no operating current
Note 1: These channels are not available on PIC16F873/876 devices.
Legend:

PIC16F87X
REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
bit 7 ADFM: A/D Result Format Select bit

1 = Right justified. 6 Most Significant bits of ADRESH are read as ‘0’.
0 = Left justified. 6 Least Significant bits of ADRESL are read as ‘0’.
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits:
PCFG3: AN7(1) AN6(1) AN5(1) AN4 AN3 AN2 AN1 AN0 CHAN/
VREF+ VREF-
PCFG0 RE2 RE1 RE0 RA5 RA3 RA2 RA1 RA0 Refs(2)
0000 A A A A A A A A VDD VSS 8/0
0001 A A A A VREF+ A A A RA3 VSS 7/1
0010 D D D A A A A A VDD VSS 5/0
0011 D D D A VREF+ A A A RA3 VSS 4/1
0100 D D D D A D A A VDD VSS 3/0
0101 D D D D VREF+ D A A RA3 VSS 2/1
011x D D D D D D D D VDD VSS 0/0
1000 A A A A VREF+ VREF- A A RA3 RA2 6/2
1001 D D A A A A A A VDD VSS 6/0
1010 D D A A VREF+ A A A RA3 VSS 5/1
1011 D D A A VREF+ VREF- A A RA3 RA2 4/2
1100 D D D A VREF+ VREF- A A RA3 RA2 3/2
1101 D D D D VREF+ VREF- A A RA3 RA2 2/2
1110 D D D D D D D A VDD VSS 1/0
1111 D D D D VREF+ VREF- D A RA3 RA2 1/2
A = Analog input D = Digital I/O
Note 1: These channels are not available on PIC16F873/876 devices.

2: This column indicates the number of analog channels available as A/D inputs and
the number of analog channels used as voltage reference inputs.
Legend:
The ADRESH:ADRESL registers contain the 10-bit To determine sample time, see Section 11.1. After this
result of the A/D conversion. When the A/D conversion acquisition time has elapsed, the A/D conversion can
is complete, the result is loaded into this A/D result reg- be started.
ister pair, the GO/DONE bit (ADCON0<2>) is cleared
and the A/D interrupt flag bit ADIF is set. The block dia-
gram of the A/D module is shown in Figure 11-1.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.

PIC16F87X
These steps should be followed for doing an A/D 3. Wait the required acquisition time.
Conversion: 4. Start conversion:
1. Configure the A/D module: • Set GO/DONE bit (ADCON0)
• Configure analog pins/voltage reference and 5. Wait for A/D conversion to complete, by either:
digital I/O (ADCON1) • Polling for the GO/DONE bit to be cleared
• Select A/D input channel (ADCON0) (with interrupts enabled); OR
• Select A/D conversion clock (ADCON0) • Waiting for the A/D interrupt
• Turn on A/D module (ADCON0) 6. Read A/D result register pair
2. Configure A/D interrupt (if desired): (ADRESH:ADRESL), clear bit ADIF if required.
• Clear ADIF bit 7. For the next conversion, go to step 1 or step 2,
• Set ADIE bit as required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
• Set PEIE bit
required before the next acquisition starts.
• Set GIE bit
FIGURE 11-1: A/D BLOCK DIAGRAM

CHS2:CHS0
111
RE2/AN7(1)
110
RE1/AN6(1)
101
RE0/AN5(1)
100
RA5/AN4
VAIN
(Input Voltage) 011
RA3/AN3/VREF+
010
A/D RA2/AN2/VREF-
Converter
001
RA1/AN1
VDD 000
RA0/AN0
VREF+
(Reference
Voltage)
PCFG3:PCFG0
VREF-
(Reference
Voltage)
VSS
PCFG3:PCFG0
Note 1: Not available on PIC16F873/876 devices.

PIC16F87X
11.1 A/D Acquisition Requirements After the analog input channel is selected (changed),
this acquisition must be done before the conversion
For the A/D converter to meet its specified accuracy, can be started.
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The To calculate the minimum acquisition time,
analog input model is shown in Figure 11-2. The source Equation 11-1 may be used. This equation assumes
impedance (RS) and the internal sampling switch (RSS) that 1/2 LSb error is used (1024 steps for the A/D). The
impedance directly affect the time required to charge 1/2 LSb error is the maximum error allowed for the A/D
the capacitor CHOLD. The sampling switch (RSS) to meet its specified resolution.
impedance varies over the device voltage (VDD), see To calculate the minimum acquisition time, TACQ, see
Figure 11-2. The maximum recommended imped- the PICmicro™ Mid-Range Reference Manual
ance for analog sources is 10 kΩ. As the impedance (DS33023).
is decreased, the acquisition time may be decreased.
EQUATION 11-1: ACQUISITION TIME
TACQ = Amplifier Settling Time +

Hold Capacitor Charging Time +
Temperature Coefficient
= TAMP + TC + TCOFF
= 2µs + TC + [(Temperature -25°C)(0.05µs/°C)]
TC = CHOLD (RIC + RSS + RS) In(1/2047)
= - 120pF (1kΩ + 7kΩ + 10kΩ) In(0.0004885)
= 16.47µs
TACQ = 2µs + 16.47µs + [(50°C -25°C)(0.05µs/°C)
= 19.72µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leak-
age specification.
4: After a conversion has completed, a 2.0TAD delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
FIGURE 11-2: ANALOG INPUT MODEL

VDD
Sampling
Switch
VT = 0.6V
RS ANx RIC ≤ 1k SS RSS
CHOLD
VA CPIN I LEAKAGE = DAC capacitance
5 pF VT = 0.6V ± 500 nA = 120 pF
VSS
Legend CPIN = input capacitance

VT = threshold voltage 6V
5V
I LEAKAGE = leakage current at the pin due to VDD 4V
various junctions 3V
RIC = interconnect resistance 2V
SS = sampling switch
CHOLD = sample/hold capacitance (from DAC) 5 6 7 8 9 10 11
Sampling Switch
(kΩ)

PIC16F87X
11.2 Selecting the A/D Conversion For correct A/D conversions, the A/D conversion clock
Clock (TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
The A/D conversion time per bit is defined as TAD. The
Table 11-1 shows the resultant TAD times derived from
A/D conversion requires a minimum 12TAD per 10-bit
the device operating frequencies and the A/D clock
conversion. The source of the A/D conversion clock is
source selected.
software selected. The four possible options for TAD
are:
• 2TOSC
• 8TOSC
• 32TOSC
• Internal A/D module RC oscillator (2-6 µs)
TABLE 11-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD) Maximum Device Frequency
Operation ADCS1:ADCS0 Max.

2TOSC 00 1.25 MHz
8TOSC 01 5 MHz
32TOSC 10 20 MHz
RC(1, 2, 3) 11 (Note 1)
Note 1: The RC source has a typical TAD time of 4 µs, but can vary between 2-6 µs.
2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recom-
mended for SLEEP operation.
3: For extended voltage devices (LC), please refer to the Electrical Characteristics (Sections 15.1 and 15.2).
11.3 Configuring Analog Port Pins

The ADCON1 and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
Note 1: When reading the port register, any pin
configured as an analog input channel will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
2: Analog levels on any pin that is defined as
a digital input (including the AN7:AN0
pins), may cause the input buffer to con-
sume current that is out of the device
specifications.

PIC16F87X
11.4 A/D Conversions acquisition is started. After this 2TAD wait, acquisition
on the selected channel is automatically started. The
Clearing the GO/DONE bit during a conversion will GO/DONE bit can then be set to start the conversion.
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed In Figure 11-3, after the GO bit is set, the first time seg-
A/D conversion sample. That is, the ADRESH:ADRESL ment has a minimum of TCY and a maximum of TAD.
registers will continue to contain the value of the last Note: The GO/DONE bit should NOT be set in
completed conversion (or the last value written to the the same instruction that turns on the A/D.
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2TAD wait is required before the next
FIGURE 11-3: A/D CONVERSION TAD CYCLES
TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
ADRES is loaded
GO bit is cleared
ADIF bit is set
Holding capacitor is connected to analog input
11.4.1 A/D RESULT REGISTERS Format Select bit (ADFM) controls this justification.
Figure 11-4 shows the operation of the A/D result justi-
The ADRESH:ADRESL register pair is the location fication. The extra bits are loaded with ’0’s’. When an
where the 10-bit A/D result is loaded at the completion A/D result will not overwrite these locations (A/D dis-
of the A/D conversion. This register pair is 16-bits wide. able), these registers may be used as two general
The A/D module gives the flexibility to left or right justify purpose 8-bit registers.
the 10-bit result in the 16-bit result register. The A/D
FIGURE 11-4: A/D RESULT JUSTIFICATION
10-bit Result
ADFM = 1 ADFM = 0
7 2107 0 7 0765 0
0000 00 0000 00
ADRESH ADRESL ADRESH ADRESL
10-bit Result 10-bit Result
Right Justified Left Justified

PIC16F87X
11.5 A/D Operation During SLEEP Turning off the A/D places the A/D module in its lowest
current consumption state.
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC Note: For the A/D module to operate in SLEEP,
(ADCS1:ADCS0 = 11). When the RC clock source is the A/D clock source must be set to RC
selected, the A/D module waits one instruction cycle (ADCS1:ADCS0 = 11). To allow the con-
before starting the conversion. This allows the SLEEP version to occur during SLEEP, ensure the
instruction to be executed, which eliminates all digital SLEEP instruction immediately follows the
switching noise from the conversion. When the conver- instruction that sets the GO/DONE bit.
sion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D 11.6 Effects of a RESET
interrupt is enabled, the device will wake-up from A device RESET forces all registers to their RESET
SLEEP. If the A/D interrupt is not enabled, the A/D state. This forces the A/D module to be turned off, and
module will then be turned off, although the ADON bit any conversion is aborted. All A/D input pins are con-
will remain set. figured as analog inputs.
When the A/D clock source is another clock option (not The value that is in the ADRESH:ADRESL registers is
RC), a SLEEP instruction will cause the present conver- not modified for a Power-on Reset. The
sion to be aborted and the A/D module to be turned off, ADRESH:ADRESL registers will contain unknown data
though the ADON bit will remain set. after a Power-on Reset.
TABLE 11-2: REGISTERS/BITS ASSOCIATED WITH A/D
Value on Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, MCLR,
BOR WDT
0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
89h(1) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111
09h(1) PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: These registers/bits are not available on the 28-pin devices.

PIC16F87X
FIGURE 15-21: A/D CONVERSION TIMING
BSF ADCON0, GO 1 TCY

(TOSC/2)(1)
131
Q4
130
A/D CLK 132
A/D DATA 9 8 7 ... ... 2 1 0
ADRES OLD_DATA NEW_DATA
ADIF
GO DONE
SAMPLING STOPPED
SAMPLE
Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
TABLE 15-13: A/D CONVERSION REQUIREMENTS

Param
Sym Characteristic Min Typ† Max Units Conditions
No.
130 TAD A/D clock period Standard(F) 1.6 — — µs TOSC based, VREF ≥ 3.0V
Extended(LF) 3.0 — — µs TOSC based, VREF ≥ 2.0V
Standard(F) 2.0 4.0 6.0 µs A/D RC mode
Extended(LF) 3.0 6.0 9.0 µs A/D RC mode
131 TCNV Conversion time (not including S/H time) — 12 TAD
(Note 1)
132 TACQ Acquisition time (Note 2) 40 — µs
10* — — µs The minimum time is the

amplifier settling time. This may
be used if the "new" input volt-
age has not changed by more
than 1 LSb (i.e., 20.0 mV @
5.12V) from the last sampled
voltage (as stated on CHOLD).
134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
§ This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.1 for minimum conditions.

PIC16F87X
12.0 SPECIAL FEATURES OF THE SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
CPU
SLEEP through external RESET, Watchdog Timer
All PIC16F87X devices have a host of features Wake-up, or through an interrupt.
intended to maximize system reliability, minimize cost Several oscillator options are also made available to
through elimination of external components, provide allow the part to fit the application. The RC oscillator
power saving operating modes and offer code protec- option saves system cost while the LP crystal option
tion. These are: saves power. A set of configuration bits is used to
• Oscillator Selection select various options.
• RESET Additional information on special features is available
- Power-on Reset (POR) in the PICmicro™ Mid-Range Reference Manual,
- Power-up Timer (PWRT) (DS33023).
- Oscillator Start-up Timer (OST)
12.1 Configuration Bits
- Brown-out Reset (BOR)
• Interrupts The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
• Watchdog Timer (WDT)
device configurations. The erased, or unprogrammed
• SLEEP value of the configuration word is 3FFFh. These bits
• Code Protection are mapped in program memory location 2007h.
• ID Locations It is important to note that address 2007h is beyond the
• In-Circuit Serial Programming user program memory space, which can be accessed
• Low Voltage In-Circuit Serial Programming only during programming.
• In-Circuit Debugger
PIC16F87X devices have a Watchdog Timer, which
can be shut-off only through configuration bits. It runs
off its own RC oscillator for added reliability.
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in RESET until the crystal
oscillator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 72 ms (nomi-
nal) on power-up only. It is designed to keep the part in
RESET while the power supply stabilizes. With these
two timers on-chip, most applications need no external
RESET circuitry.

PIC16F87X
REGISTER 12-1: CONFIGURATION WORD (ADDRESS 2007h)(1)
CP1 CP0 DEBUG — WRT CPD LVP BODEN CP1 CP0 PWRTE WDTE F0SC1 F0SC0
bit13 bit0
bit 13-12, CP1:CP0: FLASH Program Memory Code Protection bits(2)

bit 5-4 11 = Code protection off
10 = 1F00h to 1FFFh code protected (PIC16F877, 876)
10 = 0F00h to 0FFFh code protected (PIC16F874, 873)
01 = 1000h to 1FFFh code protected (PIC16F877, 876)
bit 11 DEBUG: In-Circuit Debugger Mode

1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger.
bit 10 Unimplemented: Read as ‘1’
bit 9 WRT: FLASH Program Memory Write Enable

1 = Unprotected program memory may be written to by EECON control
0 = Unprotected program memory may not be written to by EECON control
bit 8 CPD: Data EE Memory Code Protection

1 = Code protection off
0 = Data EEPROM memory code protected
bit 7 LVP: Low Voltage In-Circuit Serial Programming Enable bit

1 = RB3/PGM pin has PGM function, low voltage programming enabled
0 = RB3 is digital I/O, HV on MCLR must be used for programming
bit 6 BODEN: Brown-out Reset Enable bit(3)

1 = BOR enabled
0 = BOR disabled
bit 3 PWRTE: Power-up Timer Enable bit(3)

1 = PWRT disabled
0 = PWRT enabled
bit 2 WDTE: Watchdog Timer Enable bit

1 = WDT enabled
0 = WDT disabled
bit 1-0 FOSC1:FOSC0: Oscillator Selection bits

11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: The erased (unprogrammed) value of the configuration word is 3FFFh.

2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
3: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled.

PIC16F87X
12.2 Oscillator Configurations FIGURE 12-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
12.2.1 OSCILLATOR TYPES LP OSC
The PIC16F87X can be operated in four different oscil- CONFIGURATION)
lator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes: OSC1
Clock from
• LP Low Power Crystal Ext. System PIC16F87X
• XT Crystal/Resonator Open OSC2
• HS High Speed Crystal/Resonator
• RC Resistor/Capacitor
12.2.2 CRYSTAL OSCILLATOR/CERAMIC

RESONATORS
In XT, LP or HS modes, a crystal or ceramic resonator TABLE 12-1: CERAMIC RESONATORS
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 12-1). The Ranges Tested:
PIC16F87X oscillator design requires the use of a par-
allel cut crystal. Use of a series cut crystal may give a Mode Freq. OSC1 OSC2
frequency out of the crystal manufacturers specifica- XT 455 kHz 68 - 100 pF 68 - 100 pF
tions. When in XT, LP or HS modes, the device can 2.0 MHz 15 - 68 pF 15 - 68 pF
have an external clock source to drive the OSC1/ 4.0 MHz 15 - 68 pF 15 - 68 pF
CLKIN pin (Figure 12-2). HS 8.0 MHz 10 - 68 pF 10 - 68 pF
16.0 MHz 10 - 22 pF 10 - 22 pF
FIGURE 12-1: CRYSTAL/CERAMIC
These values are for design guidance only.
RESONATOR OPERATION See notes following Table 12-2.
(HS, XT OR LP
OSC CONFIGURATION) Resonators Used:
455 kHz Panasonic EFO-A455K04B ± 0.3%
C1(1) OSC1
2.0 MHz Murata Erie CSA2.00MG ± 0.5%
To
Internal 4.0 MHz Murata Erie CSA4.00MG ± 0.5%
XTAL
RF(3)
Logic 8.0 MHz Murata Erie CSA8.00MT ± 0.5%
OSC2 16.0 MHz Murata Erie CSA16.00MX ± 0.5%
SLEEP
(2)
Rs All resonators used did not have built-in capacitors.
C2(1) PIC16F87X
Note 1: See Table 12-1 and Table 12-2 for recom-

mended values of C1 and C2.
2: A series resistor (Rs) may be required for AT
strip cut crystals.
3: RF varies with the crystal chosen.

PIC16F87X
TABLE 12-2: CAPACITOR SELECTION FOR 12.2.3 RC OSCILLATOR
CRYSTAL OSCILLATOR
For timing insensitive applications, the “RC” device
Crystal Cap. Range Cap. Range option offers additional cost savings. The RC oscillator
Osc Type frequency is a function of the supply voltage, the resis-
Freq. C1 C2
tor (REXT) and capacitor (CEXT) values, and the operat-
LP 32 kHz 33 pF 33 pF ing temperature. In addition to this, the oscillator
200 kHz 15 pF 15 pF frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
XT 200 kHz 47-68 pF 47-68 pF
in lead frame capacitance between package types will
1 MHz 15 pF 15 pF also affect the oscillation frequency, especially for low
4 MHz 15 pF 15 pF CEXT values. The user also needs to take into account
HS 4 MHz 15 pF 15 pF variation due to tolerance of external R and C compo-
nents used. Figure 12-3 shows how the R/C combina-
8 MHz 15-33 pF 15-33 pF tion is connected to the PIC16F87X.
20 MHz 15-33 pF 15-33 pF
These values are for design guidance only. FIGURE 12-3: RC OSCILLATOR MODE
See notes following this table.
VDD
Crystals Used
32 kHz Epson C-001R32.768K-A ± 20 PPM REXT
Internal
200 kHz STD XTL 200.000KHz ± 20 PPM OSC1
Clock
1 MHz ECS ECS-10-13-1 ± 50 PPM
CEXT PIC16F87X
4 MHz ECS ECS-40-20-1 ± 50 PPM
VSS
8 MHz EPSON CA-301 8.000M-C ± 30 PPM OSC2/CLKOUT
20 MHz EPSON CA-301 20.000M- ± 30 PPM FOSC/4
C Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20pF
Note 1: Higher capacitance increases the stability

of oscillator, but also increases the start-
up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components.
3: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
4: When migrating from other PICmicro
devices, oscillator performance should be
verified.

PIC16F87X
12.3 RESET SLEEP, and Brown-out Reset (BOR). They are not
affected by a WDT Wake-up, which is viewed as the
The PIC16F87X differentiates between various kinds of resumption of normal operation. The TO and PD bits
RESET: are set or cleared differently in different RESET situa-
• Power-on Reset (POR) tions as indicated in Table 12-4. These bits are used in
• MCLR Reset during normal operation software to determine the nature of the RESET. See
Table 12-6 for a full description of RESET states of all
• MCLR Reset during SLEEP
registers.
• WDT Reset (during normal operation)
A simplified block diagram of the On-Chip Reset Circuit
• WDT Wake-up (during SLEEP)
is shown in Figure 12-4.
• Brown-out Reset (BOR)
These devices have a MCLR noise filter in the MCLR
Some registers are not affected in any RESET condi- Reset path. The filter will detect and ignore small
tion. Their status is unknown on POR and unchanged pulses.
in any other RESET. Most other registers are reset to a
“RESET state” on Power-on Reset (POR), on the It should be noted that a WDT Reset does not drive
MCLR and WDT Reset, on MCLR Reset during MCLR pin low.
FIGURE 12-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External
Reset
MCLR
SLEEP
WDT WDT
Module Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset S
BODEN
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter R Q
OSC1
(1) PWRT
On-chip
RC OSC 10-bit Ripple Counter
Enable PWRT
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

PIC16F87X
12.4 Power-On Reset (POR) 12.7 Brown-out Reset (BOR)
A Power-on Reset pulse is generated on-chip when The configuration bit, BODEN, can enable or disable
VDD rise is detected (in the range of 1.2V - 1.7V). To the Brown-out Reset circuit. If VDD falls below VBOR
take advantage of the POR, tie the MCLR pin directly (parameter D005, about 4V) for longer than TBOR
(or through a resistor) to VDD. This will eliminate (parameter #35, about 100µS), the brown-out situation
external RC components usually needed to create a will reset the device. If VDD falls below VBOR for less
Power-on Reset. A maximum rise time for VDD is spec- than TBOR, a RESET may not occur.
ified. See Electrical Specifications for details. Once the brown-out occurs, the device will remain in
When the device starts normal operation (exits the Brown-out Reset until VDD rises above VBOR. The
RESET condition), device operating parameters (volt- Power-up Timer then keeps the device in RESET for
age, frequency, temperature,...) must be met to ensure TPWRT (parameter #33, about 72mS). If VDD should fall
operation. If these conditions are not met, the device below VBOR during TPWRT, the Brown-out Reset pro-
must be held in RESET until the operating conditions cess will restart when VDD rises above VBOR with the
are met. Brown-out Reset may be used to meet the Power-up Timer Reset. The Power-up Timer is always
start-up conditions. For additional information, refer to enabled when the Brown-out Reset circuit is enabled,
Application Note, AN007, “Power-up Trouble Shoot- regardless of the state of the PWRT configuration bit.
ing”, (DS00007).
12.8 Time-out Sequence
12.5 Power-up Timer (PWRT)
On power-up, the time-out sequence is as follows: The
The Power-up Timer provides a fixed 72 ms nominal PWRT delay starts (if enabled) when a POR Reset
time-out on power-up only from the POR. The Power- occurs. Then OST starts counting 1024 oscillator
up Timer operates on an internal RC oscillator. The cycles when PWRT ends (LP, XT, HS). When the OST
chip is kept in RESET as long as the PWRT is active. ends, the device comes out of RESET.
The PWRT’s time delay allows VDD to rise to an accept- If MCLR is kept low long enough, the time-outs will
able level. A configuration bit is provided to enable/dis- expire. Bringing MCLR high will begin execution imme-
able the PWRT. diately. This is useful for testing purposes or to synchro-
The power-up time delay will vary from chip to chip due nize more than one PIC16F87X device operating in
to VDD, temperature and process variation. See DC parallel.
parameters for details (TPWRT, parameter #33). Table 12-5 shows the RESET conditions for the STA-
TUS, PCON and PC registers, while Table 12-6 shows
12.6 Oscillator Start-up Timer (OST) the RESET conditions for all the registers.
The Oscillator Start-up Timer (OST) provides a delay of
1024 oscillator cycles (from OSC1 input) after the 12.9 Power Control/Status Register
PWRT delay is over (if PWRT is enabled). This helps to (PCON)
ensure that the crystal oscillator or resonator has
The Power Control/Status Register, PCON, has up to
started and stabilized.
two bits depending upon the device.
The OST time-out is invoked only for XT, LP and HS
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
modes and only on Power-on Reset or Wake-up from
unknown on a Power-on Reset. It must then be set by
SLEEP.
the user and checked on subsequent RESETS to see if
bit BOR cleared, indicating a BOR occurred. When the
Brown-out Reset is disabled, the state of the BOR bit is
unpredictable and is, therefore, not valid at any time.
Bit1 is POR (Power-on Reset Status bit). It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
TABLE 12-3: TIME-OUT IN VARIOUS SITUATIONS
Power-up Wake-up from

Oscillator Configuration Brown-out
PWRTE = 0 PWRTE = 1 SLEEP
XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC

RC 72 ms — 72 ms —

PIC16F87X
TABLE 12-4: STATUS BITS AND THEIR SIGNIFICANCE
POR BOR TO PD
0 x 1 1 Power-on Reset
0 x 0 x Illegal, TO is set on POR
0 x x 0 Illegal, PD is set on POR
1 0 1 1 Brown-out Reset
1 1 0 1 WDT Reset
1 1 0 0 WDT Wake-up
1 1 u u MCLR Reset during normal operation
1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Legend: x = don’t care, u = unchanged
TABLE 12-5: RESET CONDITION FOR SPECIAL REGISTERS
Program STATUS PCON

Condition
Counter Register Register
Power-on Reset 000h 0001 1xxx ---- --0x
MCLR Reset during normal operation 000h 000u uuuu ---- --uu
MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu
WDT Reset 000h 0000 1uuu ---- --uu
WDT Wake-up PC + 1 uuu0 0uuu ---- --uu
Brown-out Reset 000h 0001 1uuu ---- --u0
(1)
Interrupt wake-up from SLEEP PC + 1 uuu1 0uuu ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).

PIC16F87X
TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Power-on Reset, MCLR Resets, Wake-up via WDT or
Register Devices
Brown-out Reset WDT Reset Interrupt
W 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu
INDF 873 874 876 877 N/A N/A N/A
TMR0 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu
PCL 873 874 876 877 0000h 0000h PC + 1(2)
STATUS 873 874 876 877 0001 1xxx 000q quuu (3) uuuq quuu(3)
FSR 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 873 874 876 877 --0x 0000 --0u 0000 --uu uuuu
PORTB 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu
PORTD 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu
PORTE 873 874 876 877 ---- -xxx ---- -uuu ---- -uuu
PCLATH 873 874 876 877 ---0 0000 ---0 0000 ---u uuuu
INTCON 873 874 876 877 0000 000x 0000 000u uuuu uuuu(1)
PIR1 873 874 876 877 r000 0000 r000 0000 ruuu uuuu(1)
873 874 876 877 0000 0000 0000 0000 uuuu uuuu(1)
PIR2 873 874 876 877 -r-0 0--0 -r-0 0--0 -r-u u--u(1)
TMR1L 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 873 874 876 877 --00 0000 --uu uuuu --uu uuuu
TMR2 873 874 876 877 0000 0000 0000 0000 uuuu uuuu
T2CON 873 874 876 877 -000 0000 -000 0000 -uuu uuuu
SSPBUF 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu
SSPCON 873 874 876 877 0000 0000 0000 0000 uuuu uuuu
CCPR1L 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 873 874 876 877 --00 0000 --00 0000 --uu uuuu
RCSTA 873 874 876 877 0000 000x 0000 000x uuuu uuuu
TXREG 873 874 876 877 0000 0000 0000 0000 uuuu uuuu
RCREG 873 874 876 877 0000 0000 0000 0000 uuuu uuuu
CCPR2L 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2H 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 873 874 876 877 0000 0000 0000 0000 uuuu uuuu
ADRESH 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 873 874 876 877 0000 00-0 0000 00-0 uuuu uu-u
OPTION_REG 873 874 876 877 1111 1111 1111 1111 uuuu uuuu
TRISA 873 874 876 877 --11 1111 --11 1111 --uu uuuu
TRISB 873 874 876 877 1111 1111 1111 1111 uuuu uuuu
TRISC 873 874 876 877 1111 1111 1111 1111 uuuu uuuu
TRISD 873 874 876 877 1111 1111 1111 1111 uuuu uuuu
TRISE 873 874 876 877 0000 -111 0000 -111 uuuu -uuu
PIE1 873 874 876 877 r000 0000 r000 0000 ruuu uuuu
873 874 876 877 0000 0000 0000 0000 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition,
r = reserved, maintain clear
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 12-5 for RESET value for specific condition.

PIC16F87X
TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on Reset, MCLR Resets, Wake-up via WDT or
Register Devices
Brown-out Reset WDT Reset Interrupt
PIE2 873 874 876 877 -r-0 0--0 -r-0 0--0 -r-u u--u
PCON 873 874 876 877 ---- --qq ---- --uu ---- --uu
PR2 873 874 876 877 1111 1111 1111 1111 1111 1111
SSPADD 873 874 876 877 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 873 874 876 877 --00 0000 --00 0000 --uu uuuu
TXSTA 873 874 876 877 0000 -010 0000 -010 uuuu -uuu
SPBRG 873 874 876 877 0000 0000 0000 0000 uuuu uuuu
ADRESL 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON1 873 874 876 877 0--- 0000 0--- 0000 u--- uuuu
EEDATA 873 874 876 877 0--- 0000 0--- 0000 u--- uuuu
EEADR 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu
EEDATH 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu
EEADRH 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu
EECON1 873 874 876 877 x--- x000 u--- u000 u--- uuuu
EECON2 873 874 876 877 ---- ---- ---- ---- ---- ----
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition,
r = reserved, maintain clear
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 12-5 for RESET value for specific condition.
FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT TOST
OST TIME-OUT
INTERNAL RESET

PIC16F87X
12.10 Interrupts The RB0/INT pin interrupt, the RB port change inter-
rupt, and the TMR0 overflow interrupt flags are con-
The PIC16F87X family has up to 14 sources of inter- tained in the INTCON register.
rupt. The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has indi- The peripheral interrupt flags are contained in the spe-
vidual and global interrupt enable bits. cial function registers, PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
Note: Individual interrupt flag bits are set, regard- function registers, PIE1 and PIE2, and the peripheral
less of the status of their corresponding interrupt enable bit is contained in special function reg-
mask bit, or the GIE bit. ister INTCON.
A global interrupt enable bit, GIE (INTCON<7>) When an interrupt is responded to, the GIE bit is
enables (if set) all unmasked interrupts, or disables (if cleared to disable any further interrupt, the return
cleared) all interrupts. When bit GIE is enabled, and an address is pushed onto the stack and the PC is loaded
interrupt’s flag bit and mask bit are set, the interrupt will with 0004h. Once in the Interrupt Service Routine, the
vector immediately. Individual interrupts can be dis- source(s) of the interrupt can be determined by polling
abled through their corresponding enable bits in vari- the interrupt flag bits. The interrupt flag bit(s) must be
ous registers. Individual interrupt bits are set, cleared in software before re-enabling interrupts to
regardless of the status of the GIE bit. The GIE bit is avoid recursive interrupts.
cleared on RESET.
For external interrupt events, such as the INT pin or
The “return from interrupt” instruction, RETFIE, exits PORTB change interrupt, the interrupt latency will be
the interrupt routine, as well as sets the GIE bit, which three or four instruction cycles. The exact latency
re-enables interrupts. depends when the interrupt event occurs. The latency
is the same for one or two-cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit, PEIE bit, or GIE bit.
FIGURE 12-9: INTERRUPT LOGIC
EEIF
EEIE
PSPIF
PSPIE
ADIF Wake-up (If in SLEEP mode)
T0IF
ADIE T0IE
RCIF INTF
RCIE INTE
Interrupt to CPU
TXIF RBIF
TXIE RBIE
SSPIF
SSPIE
PEIE
CCP1IF
CCP1IE GIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
BCLIF
BCLIE
The following table shows which devices have which interrupts.

Device T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF EEIF BCLIF CCP2IF
PIC16F876/873 Yes Yes Yes — Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
PIC16F877/874 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

PIC16F87X
12.10.1 INT INTERRUPT 12.11 Context Saving During Interrupts
External interrupt on the RB0/INT pin is edge triggered, During an interrupt, only the return PC value is saved
either rising, if bit INTEDG (OPTION_REG<6>) is set, on the stack. Typically, users may wish to save key reg-
or falling, if the INTEDG bit is clear. When a valid edge isters during an interrupt, (i.e., W register and STATUS
appears on the RB0/INT pin, flag bit INTF register). This will have to be implemented in software.
(INTCON<1>) is set. This interrupt can be disabled by
For the PIC16F873/874 devices, the register W_TEMP
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be defined in both banks 0 and 1 and must be
must be cleared in software in the Interrupt Service
defined at the same offset from the bank base address
Routine before re-enabling this interrupt. The INT inter-
(i.e., If W_TEMP is defined at 0x20 in bank 0, it must
rupt can wake-up the processor from SLEEP, if bit INTE
also be defined at 0xA0 in bank 1). The registers,
was set prior to going into SLEEP. The status of global
PCLATH_TEMP and STATUS_TEMP, are only defined
interrupt enable bit, GIE, decides whether or not the
in bank 0.
processor branches to the interrupt vector following
wake-up. See Section 12.13 for details on SLEEP Since the upper 16 bytes of each bank are common in
mode. the PIC16F876/877 devices, temporary holding regis-
ters W_TEMP, STATUS_TEMP, and PCLATH_TEMP
12.10.2 TMR0 INTERRUPT should be placed in here. These 16 locations don’t
require banking and therefore, make it easier for con-
An overflow (FFh → 00h) in the TMR0 register will set text save and restore. The same code shown in
flag bit T0IF (INTCON<2>). The interrupt can be Example 12-1 can be used.
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>) (Section 5.0).
12.10.3 PORTB INTCON CHANGE

An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>)
(Section 3.2).
EXAMPLE 12-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM

MOVWF W_TEMP ;Copy W to TEMP register
SWAPF STATUS,W ;Swap status to be saved into W
CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3
MOVWF PCLATH_TEMP ;Save PCLATH into W
CLRF PCLATH ;Page zero, regardless of current page
:
:(ISR) ;(Insert user code here)
:
MOVF PCLATH_TEMP, W ;Restore PCLATH
MOVWF PCLATH ;Move W into PCLATH
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W

PIC16F87X
12.12 Watchdog Timer (WDT) WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
The Watchdog Timer is a free running on-chip RC oscil- ues for the WDT prescaler (actually a postscaler, but
lator which does not require any external components. shared with the Timer0 prescaler) may be assigned
This RC oscillator is separate from the RC oscillator of using the OPTION_REG register.
the OSC1/CLKIN pin. That means that the WDT will
run, even if the clock on the OSC1/CLKIN and OSC2/ Note 1: The CLRWDT and SLEEP instructions
CLKOUT pins of the device has been stopped, for clear the WDT and the postscaler, if
example, by execution of a SLEEP instruction. assigned to the WDT, and prevent it from
timing out and generating a device
During normal operation, a WDT time-out generates a
RESET condition.
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to 2: When a CLRWDT instruction is executed
wake-up and continue with normal operation (Watch- and the prescaler is assigned to the WDT,
dog Timer Wake-up). The TO bit in the STATUS regis- the prescaler count will be cleared, but
ter will be cleared upon a Watchdog Timer time-out. the prescaler assignment is not changed.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 12.1).
FIGURE 12-10: WATCHDOG TIMER BLOCK DIAGRAM

From TMR0 Clock Source
(Figure 5-1)
0
M Postscaler
1 U
WDT Timer
X 8
8 - to - 1 MUX PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 5-1)
0 1
MUX PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 12-7: SUMMARY OF WATCHDOG TIMER REGISTERS
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2007h Config. bits (1) BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for operation of these bits.

PIC16F87X
12.17 In-Circuit Serial Programming
Note 1: The High Voltage Programming mode is
PIC16F87X microcontrollers can be serially pro-
always available, regardless of the state
grammed while in the end application circuit. This is
of the LVP bit, by applying VIHH to the
simply done with two lines for clock and data and three
MCLR pin.
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards 2: While in Low Voltage ICSP mode, the
with unprogrammed devices, and then program the RB3 pin can no longer be used as a gen-
microcontroller just before shipping the product. This eral purpose I/O pin.
also allows the most recent firmware, or a custom firm- 3: When using low voltage ICSP program-
ware to be programmed. ming (LVP) and the pull-ups on PORTB
When using ICSP, the part must be supplied at 4.5V to are enabled, bit 3 in the TRISB register
5.5V, if a bulk erase will be executed. This includes must be cleared to disable the pull-up on
reprogramming of the code protect, both from an on- RB3 and ensure the proper operation of
state to off-state. For all other cases of ICSP, the part the device.
may be programmed at the normal operating voltages. 4: RB3 should not be allowed to float if LVP
This means calibration values, unique user IDs, or user is enabled. An external pull-down device
code can be reprogrammed or added. should be used to default the device to
For complete details of serial programming, please normal operating mode. If RB3 floats
refer to the EEPROM Memory Programming Specifica- high, the PIC16F87X device will enter
tion for the PIC16F87X (DS39025). Programming mode.
5: LVP mode is enabled by default on all
12.18 Low Voltage ICSP Programming devices shipped from Microchip. It can be
The LVP bit of the configuration word enables low volt- disabled by clearing the LVP bit in the
age ICSP programming. This mode allows the micro- CONFIG register.
controller to be programmed via ICSP using a VDD 6: Disabling LVP will provide maximum com-
source in the operating voltage range. This only means patibility to other PIC16CXXX devices.
that VPP does not have to be brought to VIHH, but can If Low Voltage Programming mode is not used, the LVP
instead be left at the normal operating voltage. In this bit can be programmed to a '0' and RB3/PGM becomes
mode, the RB3/PGM pin is dedicated to the program- a digital I/O pin. However, the LVP bit may only be pro-
ming function and ceases to be a general purpose I/O grammed when programming is entered with VIHH on
pin. During programming, VDD is applied to the MCLR MCLR. The LVP bit can only be charged when using
pin. To enter Programming mode, VDD must be applied high voltage on MCLR.
to the RB3/PGM, provided the LVP bit is set. The LVP
bit defaults to on (‘1’) from the factory. It should be noted, that once the LVP bit is programmed
to 0, only the High Voltage Programming mode is avail-
able and only High Voltage Programming mode can be
used to program the device.
When using low voltage ICSP, the part must be supplied
at 4.5V to 5.5V, if a bulk erase will be executed. This
includes reprogramming of the code protect bits from an
on-state to off-state. For all other cases of low voltage
ICSP, the part may be programmed at the normal oper-
ating voltage. This means calibration values, unique
user IDs, or user code can be reprogrammed or added.

PIC16F87X
13.0 INSTRUCTION SET SUMMARY All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
Each PIC16F87X instruction is a 14-bit word, divided gram counter is changed as a result of an instruction.
into an OPCODE which specifies the instruction type In this case, the execution takes two instruction cycles
and one or more operands which further specify the with the second cycle executed as a NOP. One instruc-
operation of the instruction. The PIC16F87X instruction tion cycle consists of four oscillator periods. Thus, for
set summary in Table 13-2 lists byte-oriented, bit-ori- an oscillator frequency of 4 MHz, the normal instruction
ented, and literal and control operations. Table 13-1 execution time is 1 µs. If a conditional test is true, or the
shows the opcode field descriptions. program counter is changed as a result of an instruc-
For byte-oriented instructions, ’f’ represents a file reg- tion, the instruction execution time is 2 µs.
ister designator and ’d’ represents a destination desig- Table 13-2 lists the instructions recognized by the
nator. The file register designator specifies which file MPASMTM assembler.
register is to be used by the instruction.
Figure 13-1 shows the general formats that the instruc-
The destination designator specifies where the result of tions can have.
the operation is to be placed. If ’d’ is zero, the result is
placed in the W register. If ’d’ is one, the result is placed Note: To maintain upward compatibility with
in the file register specified in the instruction. future PIC16F87X products, do not use the
OPTION and TRIS instructions.
For bit-oriented instructions, ’b’ represents a bit field
designator which selects the number of the bit affected All examples use the following format to represent a
by the operation, while ’f’ represents the address of the hexadecimal number:
file in which the bit is located. 0xhh
For literal and control operations, ’k’ represents an where h signifies a hexadecimal digit.
eight or eleven bit constant or literal value.
FIGURE 13-1: GENERAL FORMAT FOR
TABLE 13-1: OPCODE FIELD INSTRUCTIONS
DESCRIPTIONS Byte-oriented file register operations
13 8 7 6 0
Field Description OPCODE d f (FILE #)
f Register file address (0x00 to 0x7F) d = 0 for destination W
W Working register (accumulator) d = 1 for destination f
f = 7-bit file register address
b Bit address within an 8-bit file register
k Literal field, constant data or label Bit-oriented file register operations
x Don't care location (= 0 or 1). 13 10 9 7 6 0
The assembler will generate code with x = 0. OPCODE b (BIT #) f (FILE #)
It is the recommended form of use for
compatibility with all Microchip software tools. b = 3-bit bit address
f = 7-bit file register address
d Destination select; d = 0: store result in W,
d = 1: store result in file register f. Literal and control operations
Default is d = 1.
PC Program Counter General
TO Time-out bit 13 8 7 0
OPCODE k (literal)
PD Power-down bit
k = 8-bit immediate value
The instruction set is highly orthogonal and is grouped
into three basic categories:
CALL and GOTO instructions only
• Byte-oriented operations
13 11 10 0
• Bit-oriented operations
OPCODE k (literal)
• Literal and control operations
k = 11-bit immediate value
A description of each instruction is available in the

PICmicro™ Mid-Range Reference Manual, (DS33023).

PIC16F87X
TABLE 13-2: PIC16F87X INSTRUCTION SET
Mnemonic, 14-Bit Opcode Status

Description Cycles Notes
Operands MSb LSb Affected
BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW - Clear W 1 00 0001 0xxx xxxx Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2
DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3
INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2
INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2
MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2
MOVWF f Move W to f 1 00 0000 lfff ffff
NOP - No Operation 1 00 0000 0xx0 0000
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2
BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2
BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3
LITERAL AND CONTROL OPERATIONS
ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
CALL k Call subroutine 2 10 0kkk kkkk kkkk
CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD
GOTO k Go to address 2 10 1kkk kkkk kkkk
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLW k Move literal to W 1 11 00xx kkkk kkkk
RETFIE - Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 01xx kkkk kkkk
RETURN - Return from Subroutine 2 00 0000 0000 1000
SLEEP - Go into standby mode 1 00 0000 0110 0011 TO,PD
SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023).

PIC16F87X
13.1 Instruction Descriptions
ADDLW Add Literal and W BCF Bit Clear f
Syntax: [label] ADDLW k Syntax: [label] BCF f,b
Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127
Operation: (W) + k → (W) 0≤b≤7
Status Affected: C, DC, Z Operation: 0 → (f<b>)
Description: The contents of the W register Status Affected: None

are added to the eight bit literal ’k’ Description: Bit 'b' in register 'f' is cleared.
and the result is placed in the W
register.
ADDWF Add W and f BSF Bit Set f
Syntax: [label] ADDWF f,d Syntax: [label] BSF f,b

Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127
d ∈ [0,1] 0≤b≤7
Operation: (W) + (f) → (destination) Operation: 1 → (f<b>)
Status Affected: C, DC, Z Status Affected: None
Description: Add the contents of the W register Description: Bit 'b' in register 'f' is set.
with register ’f’. If ’d’ is 0, the result
is stored in the W register. If ’d’ is
1, the result is stored back in
register ’f’.
ANDLW AND Literal with W BTFSS Bit Test f, Skip if Set
Syntax: [label] ANDLW k Syntax: [label] BTFSS f,b

Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127
0≤b<7
Operation: (W) .AND. (k) → (W)
Operation: skip if (f<b>) = 1
Status Affected: Z
Status Affected: None
Description: The contents of W register are
AND’ed with the eight bit literal Description: If bit 'b' in register 'f' is '0', the next
'k'. The result is placed in the W instruction is executed.
register. If bit 'b' is '1', then the next instruc-
tion is discarded and a NOP is
executed instead, making this a
2TCY instruction.
ANDWF AND W with f BTFSC Bit Test, Skip if Clear
Syntax: [label] ANDWF f,d Syntax: [label] BTFSC f,b

d ∈ [0,1] 0≤b≤7
Operation: (W) .AND. (f) → (destination) Operation: skip if (f<b>) = 0
Status Affected: Z Status Affected: None
Description: AND the W register with register Description: If bit 'b' in register 'f' is '1', the next
'f'. If 'd' is 0, the result is stored in instruction is executed.
the W register. If 'd' is 1, the result If bit 'b', in register 'f', is '0', the
is stored back in register 'f'. next instruction is discarded, and
a NOP is executed instead, making
this a 2TCY instruction.

PIC16F87X
CALL Call Subroutine CLRWDT Clear Watchdog Timer

Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT
Operands: 0 ≤ k ≤ 2047 Operands: None
Operation: (PC)+ 1→ TOS, Operation: 00h → WDT
k → PC<10:0>, 0 → WDT prescaler,
(PCLATH<4:3>) → PC<12:11> 1 → TO
Status Affected: None 1 → PD
Description: Call Subroutine. First, return Status Affected: TO, PD

address (PC+1) is pushed onto Description: CLRWDT instruction resets the
the stack. The eleven-bit immedi- Watchdog Timer. It also resets
ate address is loaded into PC bits the prescaler of the WDT. Status
<10:0>. The upper bits of the PC bits TO and PD are set.
are loaded from PCLATH. CALL is
a two-cycle instruction.
CLRF Clear f COMF Complement f

Syntax: [label] CLRF f Syntax: [ label ] COMF f,d
Operation: 00h → (f) d ∈ [0,1]
1→Z Operation: (f) → (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ’f’ are Description: The contents of register ’f’ are
cleared and the Z bit is set. complemented. If ’d’ is 0, the
result is stored in W. If ’d’ is 1, the
result is stored back in register ’f’.
CLRW Clear W DECF Decrement f

Syntax: [ label ] CLRW Syntax: [label] DECF f,d
Operands: None Operands: 0 ≤ f ≤ 127
Operation: 00h → (W) d ∈ [0,1]
1→Z Operation: (f) - 1 → (destination)
Description: W register is cleared. Zero bit (Z) Description: Decrement register ’f’. If ’d’ is 0,
is set. the result is stored in the W
register. If ’d’ is 1, the result is
stored back in register ’f’.

PIC16F87X
DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0

Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d
d ∈ [0,1] d ∈ [0,1]
Operation: (f) - 1 → (destination); Operation: (f) + 1 → (destination),
skip if result = 0 skip if result = 0
Status Affected: None Status Affected: None
Description: The contents of register ’f’ are Description: The contents of register ’f’ are
decremented. If ’d’ is 0, the result incremented. If ’d’ is 0, the result is
is placed in the W register. If ’d’ is placed in the W register. If ’d’ is 1,
1, the result is placed back in the result is placed back in
register ’f’. register ’f’.
If the result is 1, the next instruc- If the result is 1, the next instruc-
tion is executed. If the result is 0, tion is executed. If the result is 0,
then a NOP is executed instead a NOP is executed instead, making
making it a 2TCY instruction. it a 2TCY instruction.
GOTO Unconditional Branch IORLW Inclusive OR Literal with W

Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k
Operands: 0 ≤ k ≤ 2047 Operands: 0 ≤ k ≤ 255
Operation: k → PC<10:0> Operation: (W) .OR. k → (W)
PCLATH<4:3> → PC<12:11> Status Affected: Z
Status Affected: None Description: The contents of the W register are
Description: GOTO is an unconditional branch. OR’ed with the eight bit literal 'k'.
The eleven-bit immediate value is The result is placed in the W
loaded into PC bits <10:0>. The register.
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a two-
cycle instruction.
INCF Increment f IORWF Inclusive OR W with f
Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d

d ∈ [0,1] d ∈ [0,1]
Operation: (f) + 1 → (destination) Operation: (W) .OR. (f) → (destination)
Description: The contents of register ’f’ are Description: Inclusive OR the W register with
incremented. If ’d’ is 0, the result register 'f'. If 'd' is 0 the result is
is placed in the W register. If ’d’ is placed in the W register. If 'd' is 1
1, the result is placed back in the result is placed back in
register ’f’. register 'f'.

PIC16F87X
MOVF Move f NOP No Operation

Syntax: [ label ] MOVF f,d Syntax: [ label ] NOP
Operands: 0 ≤ f ≤ 127 Operands: None
d ∈ [0,1] Operation: No operation
Operation: (f) → (destination) Status Affected: None
Status Affected: Z Description: No operation.
Description: The contents of register f are
moved to a destination dependant
upon the status of d. If d = 0,
destination is W register. If d = 1,
the destination is file register f itself.
d = 1 is useful to test a file register,
since status flag Z is affected.
MOVLW Move Literal to W RETFIE Return from Interrupt

Syntax: [ label ] MOVLW k Syntax: [ label ] RETFIE
Operands: 0 ≤ k ≤ 255 Operands: None
Operation: k → (W) Operation: TOS → PC,
Status Affected: None 1 → GIE
Description: The eight bit literal ’k’ is loaded Status Affected: None
into W register. The don’t cares
will assemble as 0’s.
MOVWF Move W to f RETLW Return with Literal in W

Syntax: [ label ] MOVWF f Syntax: [ label ] RETLW k
Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ k ≤ 255
Operation: (W) → (f) Operation: k → (W);
Status Affected: None TOS → PC
Description: Move data from W register to Status Affected: None

register 'f'. Description: The W register is loaded with the
eight bit literal 'k'. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.

PIC16F87X
RLF Rotate Left f through Carry SLEEP

Syntax: [ label ] RLF f,d Syntax: [ label ] SLEEP
Operands: 0 ≤ f ≤ 127 Operands: None
d ∈ [0,1] Operation: 00h → WDT,
Operation: See description below 0 → WDT prescaler,
Status Affected: C 1 → TO,
0 → PD
Description: The contents of register ’f’ are rotated
one bit to the left through the Carry Status Affected: TO, PD
Flag. If ’d’ is 0, the result is placed in Description: The power-down status bit, PD is
the W register. If ’d’ is 1, the result is cleared. Time-out status bit, TO
stored back in register ’f’. is set. Watchdog Timer and its
C Register f prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
RETURN Return from Subroutine SUBLW Subtract W from Literal

Syntax: [ label ] RETURN Syntax: [ label ] SUBLW k
Operands: None Operands: 0 ≤ k ≤ 255
Operation: TOS → PC Operation: k - (W) → (W)
Status Affected: None Status Affected: C, DC, Z
Description: Return from subroutine. The stack Description: The W register is subtracted (2’s
is POPed and the top of the stack complement method) from the
(TOS) is loaded into the program eight-bit literal 'k'. The result is
counter. This is a two-cycle placed in the W register.
instruction.
RRF Rotate Right f through Carry SUBWF Subtract W from f

Syntax: [ label ] RRF f,d Syntax: [ label ] SUBWF f,d
d ∈ [0,1] d ∈ [0,1]
Operation: See description below Operation: (f) - (W) → (destination)
Status Affected: C Status C, DC, Z
Description: The contents of register ’f’ are Affected:
rotated one bit to the right through Description: Subtract (2’s complement method)
the Carry Flag. If ’d’ is 0, the result W register from register 'f'. If 'd' is 0,
is placed in the W register. If ’d’ is the result is stored in the W
1, the result is placed back in register. If 'd' is 1, the result is
register ’f’. stored back in register 'f'.
C Register f

PIC16F87X
SWAPF Swap Nibbles in f XORWF Exclusive OR W with f

Syntax: [ label ] SWAPF f,d Syntax: [label] XORWF f,d
d ∈ [0,1] d ∈ [0,1]
Operation: (f<3:0>) → (destination<7:4>), Operation: (W) .XOR. (f) → (destination)
(f<7:4>) → (destination<3:0>) Status Affected: Z
Status Affected: None Description: Exclusive OR the contents of the
Description: The upper and lower nibbles of W register with register 'f'. If 'd' is
register ’f’ are exchanged. If ’d’ is 0, the result is stored in the W
0, the result is placed in the W register. If 'd' is 1, the result is
register. If ’d’ is 1, the result is stored back in register 'f'.
placed in register ’f’.
XORLW Exclusive OR Literal with W

Syntax: [label] XORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .XOR. k → (W)
Status Affected: Z
Description: The contents of the W register
are XOR’ed with the eight-bit lit-
eral 'k'. The result is placed in
the W register.

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PIC16F87X

 2001 Microchip Technology Inc. DS30292C

Devices Included in this Data Sheet: Pin Diagram

Up to 256 x 8 bytes of EEPROM Data Memory RC0/T1OSO/T1CKI 15 26 RC7/RX/DT

 2001 Microchip Technology Inc. DS30292C-page 1

DS30292C-page 2  2001 Microchip Technology Inc.

Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz DC - 20 MHz

 2001 Microchip Technology Inc. DS30292C-page 3

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

DS30292C-page 4  2001 Microchip Technology Inc.

FIGURE 1-1: PIC16F873 AND PIC16F876 BLOCK DIAGRAM

13 Data Bus 8 PORTA

MCLR VDD, VSS

Timer0 Timer1 Timer2 10-bit A/D

Note 1: Higher order bits are from the STATUS register.

 2001 Microchip Technology Inc. DS30292C-page 5

OSC1/CLKIN 9 9 I ST/CMOS(3) Oscillator crystal input/external clock source input.

 2001 Microchip Technology Inc. DS30292C-page 7

FIGURE 2-1: PIC16F877/876 PROGRAM

Stack Level 1 Stack Level 1

Stack Level 8 Stack Level 8

RESET Vector 0000h RESET Vector 0000h

Interrupt Vector 0004h Interrupt Vector 0004h

 2001 Microchip Technology Inc. DS30292C-page 11

DS30292C-page 12  2001 Microchip Technology Inc.

File File File File

General General General General

Unimplemented data memory locations, read as ’0’.

 2001 Microchip Technology Inc. DS30292C-page 13

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY

 2001 Microchip Technology Inc. DS30292C-page 15

DS30292C-page 16  2001 Microchip Technology Inc.

 2001 Microchip Technology Inc. DS30292C-page 17

REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)

DS30292C-page 18  2001 Microchip Technology Inc.

REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)

bit 7 RBPU: PORTB Pull-up Enable bit

 2001 Microchip Technology Inc. DS30292C-page 19

REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)

bit 7 GIE: Global Interrupt Enable bit

DS30292C-page 20  2001 Microchip Technology Inc.

REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)

bit 7 PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit

 2001 Microchip Technology Inc. DS30292C-page 21

REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)

bit 7 PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit

DS30292C-page 22  2001 Microchip Technology Inc.

REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh)

bit 7 Unimplemented: Read as '0'

 2001 Microchip Technology Inc. DS30292C-page 23

REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)

bit 7 Unimplemented: Read as '0'

DS30292C-page 24  2001 Microchip Technology Inc.

REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh)

bit 7-2 Unimplemented: Read as '0'

 2001 Microchip Technology Inc. DS30292C-page 25

DS30292C-page 26  2001 Microchip Technology Inc.