CH 4 MARIE
CH 4 MARIE
CH 4 MARIE
MARIE: An
Introduction to a
Simple Computer
4.2 CPU Basics
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4.2 CPU Basics
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4.3 The Bus
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4.3 The Bus
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4.3 The Bus
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4.4 Clocks
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4.4 Clocks
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4.6 Memory Organization
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4.6 Memory Organization
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4.6 Memory Organization
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4.6 Memory Organization
High-Order Interleaving
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4.7 Interrupts
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4.8 MARIE
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4.8 MARIE
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4.8 MARIE
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4.8 MARIE
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4.8 MARIE
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4.8 MARIE
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4.8 MARIE
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4.8 MARIE
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4.8 MARIE
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RTN
• Add X
The data value stored at address X is added to
the AC. This can be accomplished as follows:
MAR ← X
MBR ← M[MAR]
AC ← AC + MBR
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RTN
Subt X
Similar to Add, this instruction subtracts the
value stored at address X from the
accumulator and places the result back in the
AC:
• MAR ← X
• MBR ← M[MAR]
• AC ← AC – MBR
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RTN
Input
Any input is put into the InREG. Then the data is
transferred into the AC.
AC ← InREG
Output
Data in AC to be placed into the OutREG, where it is
eventually sent to the output device.
OutREG ← AC
Halt
No operations are performed on registers; the machine
simply ceases execution of the program. 31
4.8 MARIE
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RTN
Jump X
This instruction causes an unconditional branch to
the given address, X. Therefore, to execute this
instruction, X must be loaded into the PC.
• PC ← X
In reality, the lower or least significant 12 bits of the
instruction register (or IR[11–0]) reflect the value of
X. So this transfer is more accurately depicted as:
• PC ← IR[11-0]
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4.9 Instruction Processing
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4.9 Instruction Processing
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4.9 Instruction Processing
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4.9 Instruction Processing
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4.9 Instruction Processing
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4.9 Instruction Processing
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4.10 A Simple Program
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4.10 A Simple Program
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4.10 A Simple Program
• Store 106
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4.11 A Discussion on Assemblers
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4.11 A Discussion on Assemblers
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4.11 A Discussion on Assemblers
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4.11 A Discussion on Assemblers
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4.12 Extending Our Instruction Set
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4.12 Extending Our Instruction Set
• CLEAR instruction.
• All it does is set the contents of the accumulator to
all zeroes.
• This is the RTL for CLEAR:
AC 0
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4.12 Extending Our Instruction Set
sum data in array
100 | LOAD Addr 10E | SKIPCOND 000
101 | STORE Next 10F | JUMP Loop
102 | LOAD Num 110 | HALT
103 | SUBT One 111 |Addr HEX 118
104 | STORE Ctr 112 |Next HEX 0
105 |Loop LOAD Sum 113 |Num DEC 5
106 | ADDI Next 114 |Sum DEC 0
107 | STORE Sum 115 |Ctr HEX 0
108 | LOAD Next 116 |One DEC 1
109 | ADD One 117 | DEC 10
10A | STORE Next 118 | DEC 15
10B | LOAD Ctr 119 | DEC 2
10C | SUBT One 11A | DEC 25
10D | STORE Ctr 11B | DEC 30
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4.12 Extending Our Instruction Set
if/else construct
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4.12 Extending Our Instruction Set
a simple subroutine
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4.13 A Discussion on Decoding
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4.13 A Discussion on Decoding
MAR X
MBR M[MAR]
AC AC + MBR
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4.13 A Discussion on Decoding
• Each of MARIE’s
registers and main
memory have a unique
address along the
datapath.
• The addresses take the
form of signals issued by
the control unit.
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4.13 A Discussion on Decoding
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4.13 A Discussion on Decoding
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4.13 Decoding
P0 P1 P2 P3 T0: MAR X
P0 P2 T1: MBR M[MAR]
A 0 P0 P1 P2 P5 T2: AC AC + MBR
Cr T3: [Reset counter]
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4.13 A Discussion on Decoding
Hardwired control
(1)
• The signal pattern just
described is the same
whether our machine used
(2) cycle counter
hardwired or
microprogrammed control.
(3) control matrix
• Hardwired control
uses the bits in the IR
to generate control
signals by feeding
these bits into basic
logic gates.
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1.6 The Computer Level Hierarchy
(Abstract virtual machines)
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Partial Instruction Decoder for
MARIE’s Instruction Set
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Ring Counter Using D Flip-Flops
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4.13 A Discussion on Decoding
Hardwired control
(1)
• Signals from the counter
and instruction decoder
are combined within,
• the control matrix to (2) cycle counter
• execution of
microoperations
involving,
• the ALU, registers, and
datapath.
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4.13 A Discussion on Decoding
This is the
hardwired
logic for
MARIE’s
Add = 0011
instruction.
P0 P1 P2 P 3 T0: MAR X
P0 P 2 T1: MBR M[MAR]
A0 P0 P1 P2 P 5 T2: AC AC + MBR
Cr T3: [Reset counter] 70
4.13 A Discussion on Decoding
4.13.3 Microprogrammed Control
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4.13 A Discussion on Decoding
This is how a generic
microprogrammed
control unit might look.
ROM, PROM,
or EPROM
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4.13 A Discussion on Decoding
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RTN for the fetch–decode–
execute cycle
• There are only 22 unique microoperations
to implement MARIE’s entire instruction
set.
• Two additional microoperations:
– NOP, “no operation” is useful when the system
must wait for a set of signals to stabilize, when
waiting for fetching from memory.
– Compares the bit (IR[15–12]) to a literal value
that is in the first 4 bits of the MicroOp2 field.
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4.13 A Discussion on Decoding
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4.13 A Discussion on Decoding
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4.13 A Discussion on Decoding
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4.13 A Discussion on Decoding
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Intel 4004 architectural block diagram
https://en.wikipedia.org/wiki/Intel_4004 81
https://upload.wikimedia.org/wikipedia/commons/0/00/Transistor_Count_and_Moore%27s_Law_-_2011.svg 82
4.14 Real World Architectures
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4.14 Real World Architectures
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4.14 Real World Architectures
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4.14 Real World Architectures
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4.14 Real World Architectures
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4.14 Real World Architectures
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Chapter 4 Conclusion
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Chapter 4 Conclusion
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End of Chapter 4
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