數位IC設計

RTL Coding – Part I

 Optimization issues for VLSI Design

Five optimization issues:

1. Area (less silicon, less cost, high yield)
2. Speed (design constraint, better
Done by timing performance)
designers
3. Power dissipation (cooling, battery)
+ tools
4. Testability (minimize the time spent to
test a single chip)
5. Design time (CAD tools)
 Top-Down Design Flow
Full-Adder

Design

Sub Sub Sub Sub

block block block block

Basic Basic Basic Basic Basic Basic Basic Basic

Element Element Element Element Element Element Element Element
 Bottom-Up Design Flow

Design

Sub Sub Sub Sub

block block block block

Basic Basic Basic Basic Basic Basic Basic Basic

Element Element Element Element Element Element Element Element
 Design Entry for VLSI System
Choose the design entry method:
IN[0]
Schematic IN[1]
IN[2]
OUT
IN[3]
Gate level design
Intuitive & easy to debug
HDL (Hardware Description Language)
Descriptive & portable always @(IN)
Easy to modify begin
OUT = (IN[0] | IN[1]) &
(IN[2] | IN[3]);
Mixed HDL & Schematic end

…
 Hardware Description Language (HDL)

• Hardware description language allows you to

describe circuit at different levels of abstractions,
and allows you to mix any level of abstraction in
the design
• Two of the most popular HDLs
-- Verilog -- VHDL
• HDLs can be used for both the cell-based
synthesis and FPGA/CPLD implementation
• Only Verilog is introduced here
 Why Verilog?
Verilog History
1. Verilog was written by gateway design automation in
the early 1980
2. Cadence acquired gateway in 1990
3. Cadence released Verilog to the public domain in 1991
4. In 1995, the language was ratified as IEEE standard 1364

Why Verilog ?
1. Choice of many design teams
2. Most of us are familiar with C- like syntax/semantics
 Verilog Features
Features:
◼ Procedural constructs for conditional, if-else, case and
looping operations
◼ Arithmetic, logical, bit-wise, and reduction operations
for expression
◼ Timing control

Basics of Verilog Language:

- Verilog Module - Identifier - Keyword
- Four Value Logic - Data Types - Numbers
- Port Mapping - Operator - Comments
 Verilog Module (1/3)

Stimulus Response
Verilog
and Generation
Module
Control

Waveform, Waveform,
Verification
test patterns text reports

Test Bench
 Verilog Module (2/3)
module module_name (port_name);
(1) port declaration

(2) data type declaration

(3)
module functionality or structure
endmodule module Add_half(sum, c_out, a, b);
input a, b;
(1) output sum, c_out;

(2) wire c_out_bar;

xor (sum, a, b);

(3) nand (c_out_bar, a, b);
c_out_bar c_out not (c_out, c_out_bar);

endmodule
 Verilog Module (3/3)
Verilog Module: basic building block

module DFF module ALU module MUX

-------------------- -------------------- --------------------
-------------------- -------------------- --------------------
------------------- ------------------- -------------------
- - -
- - -
- - -
------------------ ------------------ ------------------
------------------ ------------------ ------------------
endmodule endmodule endmodule
 Structural Description
Verilog allows three kinds of descriptions for circuits:
(1) Structural description (2) Data flow description
(3) Behavioral description

Structural description:
1. module OR_AND_STRUCTURAL(IN,OUT);

2. input [3:0] IN;

IN[0] TEMP[0]
3. output OUT; u1
IN[1]
4. wire [1:0] TEMP; OUT
IN[2] u2
IN[3] TEMP[1]
5. or u1(TEMP[0], IN[0], IN[1]);
6. or u2(TEMP[1], IN[2], IN[3]);
7. and (OUT, TEMP[0], TEMP[1]); Synthesized (synthesis) +
8. endmodule optimized by tools
 Data Flow Description
Data flow description
1. module OR_AND_DATA_FLOW(IN, OUT);
2. input [3:0] IN;
3. output OUT;
Synthesized and
optimized by tools 4. assign OUT = (IN[0] | IN[1]) & (IN[2] | IN[3]);

IN[0] 5. endmodule
IN[1]
OUT
IN[2]
IN[3]
NOTE:
What is the difference between C and Verilog ?

C : only one iteration (once) is implemented for assignment

Verilog : hard-wired circuit for assignment
 Behavioral (RTL) Description (1/2)
Behavioral description #1

1. module OR_AND_BEHAVIORAL(IN, OUT);

2. input [3:0] IN; IN[0]

3. output OUT; IN[1]
4. reg OUT; OUT
IN[2]
5. always @(IN)
IN[3]
6. begin
7. OUT = (IN[0] | IN[1]) & (IN[2] | IN[3]);
8. end
9. endmodule
Activate OUT while any voltage transition
(0 1 or 1 0) happens at signal IN
 Behavioral (RTL) Description (2/2)
IN[0] Behavioral description #2
IN[1]
OUT module or_and(IN, OUT);
IN[2]
IN[3] input [3:0] IN; output OUT; reg OUT; (Note)
Truth Table always @(IN)
IN[0] IN[1] IN[2] IN[3] OUT
0 0 0 0 0
begin
0 0 0 1 0 case(IN)
0 0 1 0 0 4'b0000: OUT = 0; 4'b0001: OUT = 0;
0 0 1 1 0
0 1 0 0 0 4'b0010: OUT = 0; 4'b0011: OUT = 0;
0 1 0 1 1 4'b0100: OUT = 0; 4'b0101: OUT = 1;
0 1 1 0 1 4'b0110: OUT = 1; 4'b0111: OUT = 1;
0 1 1 1 1
1 0 0 0 0 4'b1000: OUT = 0; 4'b1001: OUT = 1;
1 0 0 1 1 4'b1010: OUT = 1; 4'b1011: OUT = 1;
1 0 1 0 1
1 0 1 1 1
4'b1100: OUT = 0; 4'b1101: OUT = 1;
1 1 0 0 0 4'b1110: OUT = 1; default: OUT = 1;
1 1 0 1 1 endcase
1 1 1 0 1 Synthesized and
end
1 1 1 1 1 optimized by tools
endmodule
 Verilog Primitives

Note: all primitives are simulatable (可模擬)

but not all synthesizable (可合成)
 Instance Name
◼ A module instance must have a name.
ex: OR_AND_STRUCTURAL
Note: naming skill is very important in Verilog

◼ The use of an instance name with a primitive is

optional.
ex: u1, u2
or u1(TEMP[0], IN[0], IN[1]);
or u2(TEMP[1], IN[2], IN[3]);
and (OUT, TEMP[0], TEMP[1]);
 Structural Description
for Cell-Based Implementation
Structural description (cell-based):
module OR_AND_STRUCTURAL(IN,OUT);

input [3:0] IN;

output OUT;
wire [1:0] TEMP;
Cell library from:
IBM, TSMC, UMC,..
orf203 u1(TEMP[0], IN[0], IN[1]);
orf203 u2(TEMP[1], IN[2], IN[3]);
andf201 (OUT, TEMP[0], TEMP[1]);
endmodule

This kind of design is not portable. Why ?

Bad design method !
Gate Delay (1/3)
1. Cost (# of trans.)
2. Delay

Gate delay is dependent

on the VLSI technology
and the cell library.

Technology Mapping:
Convert the expression
a’b’+c(a+b) into a logic
schematic using gates
defined in the cell library
Translation +
Optimization
 Gate Delay (2/3)
Full-adder

nand gate: 4 trans.

or gate: 6 trans.

and gate: 6 trans. xor gate: 14 trans.

Totally, 46 transistors
Totally, 36 transistors

Delay (critical path)

=7.6 ns

7.6
Delay (critical path)= 9.0 ns
Critical Path: the longest path (delay) in a circuit
 Gate Delay (3/3)
Technology Mapping (logic synthesis):
convert the expression into a logic
schematic using gates defined in the
cell library
Translation + Optimization
 Difference Between C and Verilog (1/2)

C language: Verilog language:

k=a+b; a
k=a+b; d=k+e; + k
d=k+e; or b + d
a e b e adder

sel Two adders

sel k
(higher cost, higher speed)
multiplexer
reg
sel=0 + One adder
execute a+b (lower cost, lower speed)
sel=1
execute e+k d clock rate might be faster

C 語法中 變數k和d只被計算一次，欲多次計算需加上迴圈指令。
Verilog 語法中變數k和d需使用硬體元件來計算，感覺上該硬體永遠存在,
只要輸入值有任何改變， 相關聯的輸出會跟著改變 (軟體指令為sequential
process, 硬體則為一個彷彿永遠存在的實體) 。
 Difference Between C and Verilog (2/2)
1. 8-bit input wire, ?-bit adder, 2’s complement
(The number of bits (pins) required in a hardware design)
2. How about the critical path ?

a e b

a
sel
8 sel k
+ multiplexer
critical path reg
k ?
+ d +
b 8 ?
adder
e
d critical path
Critical path is longer, so the period Critical path is shorter, so the period
is longer and the clock rate is slower is shorter and the clock rate is faster

Clock rate=1/period (If period is 15 ns, the clock rate is about 67 MHz)
An Example
 Identifier

• Identifiers are names given to Verilog objects

• Names of modules, ports and instances are all
identifiers
• First character must use a letter, and other
character can use letter, number or “_”
• Upper case and lower case letters are different
• How to determine a suitable name ???
 Keywords
• Predefined identifiers to define the language
constructs
• All keywords are defined in lower case
• Cannot be used as identifiers
Examples: module, initial, assign, always,
endmodule, …
 Four Value Logic
◼ 0: logic 0 / false

◼ 1: logic 1 / true

◼ X: unknown logic value

◼ Z: high-impedance
 Four Value Logic: Example

• 6'hCA 001010 truncated, not 11001010

• 6'hA 001010 filled with two '0' on left
• 16'bZZ
ZZZZZZZZZZZZZZZ
filled with 16 Z's
 Timescale in Verilog

• The ‘timescale declares the time unit and its

precision.
‘timescale <time_unit> / <time_precision>
ex: ‘timescale 10 ns / 1 ns delay= 20 ns
c cbar

not #2 u1(cbar, c); Delay=20 ns

or #2.54 u2(TEMP[1], IN[2], IN[3]); Delay=25 ns

and # 3.55 (OUT, TEMP[0], TEMP[1]); Delay=36 ns

 Delay
Simulation Delay Physical Delay: NOTE
‘timescale 10 ns / 1 ns 1. Physical delay can be acquired
or #2.54 u1(TEMP[0], IN[0], IN[1]); after synthesis process.

or # 2.54 u2(TEMP[1], IN[2], IN[3]); 2. Physical delay is dependent on

and #3.55 (OUT, TEMP[0], TEMP[1]); the VLSI technology and cell lib.
(eg., 0.25, 0.18, 0.13, ….)
D=25 ns
3. After synthesis, the instruction
IN[0]
D=36 ns
IN[1] such as # 3.55 becomes useless.
OUT
4. Timescale is used for simulation
IN[2]
IN[3] Total_D=61 ns not for physical circuit.

If new IN[3] is activated at 10th ns, the simulated output OUT will be generated at 71th ns.
If new IN[1] is activated at 2th ns, the simulated output OUT will be generated at 63th ns.
 Data Types
• Nets
- physical connection between devices
• Registers
- abstract storage devices
• Parameters
- run-time constants
• The positions of three data types define whether they are
global to a module or local to a particular always statement
• By default, net and register are one-bit wide (a scalar)
not multi-bit wide (a vector)
 NETs
• Connects between structural elements
• Must be continuously driven by
- Continuous assignment
- Module or gate instantiation
• Default initial value for a wire is “Z”
 Types of Nets
◼ Net declaration
<nettype> <range>? <delay_spec>? <<net_name> <,net_name>*>

Note: Some of those net types are un-synthesizable (不能電路合成的)

 Nets (1/2)
wire, wand, wor, tri, supply0, supply1

wire k; // single-bit wire

wire [0:31] w1, w2; // Two 32-bit wires

wire w1;
assign w1=a; a
assign w1=b; (error) w1 (error)
b

Method 1:
wand x; i
x (ok)
assign x=j; assign x=i; j

Method 2:
wor y; o
assign y=o; assign y=p; p y (ok)
 Nets (2/2)
tri: all variables that drive the tri must have a value of Z
except one (ensured by the designer).
module tri-test(out, condition)
input [1:0] condition; output out;
reg a, b, c;
tri out;
always@(condition)
begin
a=1’bz; b=1’bz; c=1’bz;
case (condition) supply0 wires tied to logic 0 (ground)
2’b00: a=1’b1; supply1 wires tied to logic 1 (power)
2’b01: b=1’b0;
2’b10: c=1’b1;
endcase
end
assign out=a; assign out=b; assign out=c;
endmodule
 Registers
◼ Represent abstract data storage elements
◼ Hold its value until a new value is assigned to it
◼ Registers are used extensively in behavioral modeling
◼ Default initial value for a register is “X”
 Types Of Registers
◼ Register declaration
<register_type> <range>? <<register_name> <,register_name>*>

memory-block is an array of 256 registers,

reg a; // a scalar register
each of which is 8 bits width. You can
reg [3:0] b,c;// two 4-bit vector registers access individual register, but you cannot
reg [7:0] byte_reg; // a 8-bit registers access individual bits of register directly.
byte_reg=memory_block [120];
reg [7:0] memory_block [255:0];
bit=byte_reg [7]; // wire bit;
 Numbers (1/2)

◼ Numbers are integer or real constants.

Integer constants are written as
<size>’<base format><number>

◼ Real number can be represented in decimal or

scientific format.
◼ A number may be sized or unsized
 Numbers (2/2)

◼ The base format indicates the type of number

◼ Decimal (d or D)
◼ Hex (h or H)
◼ Octal (o or O)
◼ Binary (b or B)

ex: unsize

size
 Half Adder (1/5)

a\b 0 1 a sum
0 0 1 Add_half
b c_out
1 1 0

sum=a  b

a\b 0 1 a
sum
0 0 0 b
1 0 1
c_out
c_out =ab
c_out_bar
 Half Adder (2/5)
a
sum
b

c_out
Structural description
c_out_bar
module Add_half(sum, c_out, a, b);
input a, b;
output sum, c_out;
wire c_out_bar;
and (e, a, b,c,d);
xor (sum, a, b); a
nand (c_out_bar, a, b); b
e
c
not (c_out, c_out_bar); d
endmodule
 Half Adder (3/5)
Data flow description

module Add_half(sum, c_out, a, b);

input a, b;
output sum, c_out; a sum
half
adder c_out
assign {c_out, sum} = a + b; b
endmodule
Synthesized and
optimized by tools
assign: continuous assignment a
sum
b

c_out
c_out_bar
 Half Adder (4/5)
Behavioral description #1

module Add_half(sum, c_out, a, b);

input a, b;
output sum, c_out;
reg sum, c_out;

always @ (a or b)
begin
sum = a ^ b; a
c_out = a & b; b
sum

end
endmodule c_out
c_out_bar
 Half Adder (5/5)
Behavioral description #2
module Add_half(sum, c_out, a, b);
input a, b; 2'b10:begin
output sum, c_out; sum = 1; c_out = 0;
reg sum, c_out; end
always @(a or b) default:begin
begin sum = 0; c_out = 1;
case({a,b}) end
2'b00:begin endcase a\b 0 1
sum = 0;c_out = 0; end 0 0 1 sum
end endmodule 1 1 0
2'b01:begin
a\b 0 1
sum = 1; c_out = 0;
end 0 0 0 c_out
1 0 1
 Parameter
◼ Parameter declaration
parameter<range>?<list_of_assignments>
◼ You can use a parameter anywhere that you can
use a literal.
ex: module mod(ina, inb,out);
……..
parameter m1=8;
…. w1 can be set as a (n+1)-bit wire if
wire [m1:0] w1; we change m1 to n
…….. (i.e., m1=10 w1 becomes a 11-bit wire
endmodule m1=4 w1 becomes a 5-bit wire)
 Parameterized Design (1/2)
module PARAM(A , B , C); module test (a , b , c);
input [7 : 0] A , B; parameter width = 8;
output [7 : 0] C; input [width - 1 : 0] a, b;
wire f; output [width - 1 : 0] c;
or o1(f,A,B);
test #(4) u1(A , f , C);
assign c = a & b;
endmodule
endmodule
Override the value of width when the test module is instantiated
Save the file as PARAM.v and compile (synthesis) it
the width value become 4
 Parameterized Design (2/2)
module test_2(A , B , C , D);
module PARAM_1(A , B , C , D); parameter width = 8;
input [4 : 0] A; parameter height = 8;
input [3 : 0] B; parameter length = 8;
input [3 : 0] C;
output [5 : 0] D; input [width - 1 : 0] A;
input [height - 1 : 0] B;
test_2 #(5 , 4 , 4) u1(A , B , C , D); input [length- 1 : 0] C;
output [width : 0] D;
endmodule
assign D = A + B + C;

endmodule

Override those values of many parameters when the test_2 module

is instantiated (width = 5; height = 4; length = 4)
 Port Mapping
◼ In Order
Mux Mux_1(Sel,x,y,Mux_Out);
Register8 Register8_1(Clock,Reset,Mux_Out,Reg_Out);

◼ By Name
Mux Mux_1(.Sel(Sel),.x(x),.y(y),.out(Mux_Out));
Register8 Register8_1(.Clock(Clock), .Reset(Reset) ,.data(Mux_Out)
,.q(Reg_Out));
 Port Mapping by Position Association

module parent_mod;
wire [3:0] g;

child_mod G1(g[3], g[1], g[0], g[2]);

endmodule

module child_mod(sig_a, sig_b, sig_c, sig_d);

input sig_c, sig_d;
output sig_a, sig_b; g[3] g[1] g[0] g[2]

module description sig_a sig_b sig_c sig_d

endmodule
child_mod

in-order port mapping

 Port Mapping by Name Association
Name mapping is better, why ?
module parent_mod;
wire [3:0] g;

child_mod G1(.sig_c(g[3]), .sig_d(g[2]), .sig_b(g[0]),

.sig_a(g[1]));
endmodule

module child_mod(sig_a, sig_b, sig_c, sig_d);

input sig_c, sig_d;
output sig_a, sig_b; g[1] g[0] g[3] g[2]

module description sig_a sig_b sig_c sig_d

endmodule
child_mod
naming port mapping
 Expressions
◼ An expression comprises of operators
and operands, see Example, and are
covered separately in the following two
sections.
◼ Example
expression

W<= X - Y + Z

operators operands
 Verilog Operands
◼ Four data objects form the operands of an expression

Verilog Operands
Identifiers
Literals
string (bit & character) 4’b 1101
numeric (integer, real+) 34
Function Call
Index & Slice Names

Identifiers
◼ Verilog identifiers consists of letters, digits, underscores (_) and dollar sign ($)
◼ Verilog is case sensitive, so upper and lower case identifier names are treated
as different identifiers
 Identifier and Literal Operands (1/2)
1. module LITERALS(A1, A2, B1, B2, Y1, Y2);
2. input A1, A2, B1, B2;
3. output [7:0] Y1; output [5:0] Y2;
4. parameter CST = 4’b 1010, TF=25;
5. reg [7:0] Y1; reg [5:0] Y2;

6. always @(A1 or A2 or B1 or B2)

7. begin
8. if (A1 == 1) Identifier
9. Y1 = {CST, 4’b 0000};
10. else if (A2 == 1)
11. Y1 = {CST, 4’b 0101};
12. else Bit string literals
13. Y1 = {CST, 4’b 1111};
14. if (B1 == 0) Y2 = 10;
15. else if (B2 == 1) Y2 = 15;
16. else Y2 = TF +10 +15;
17. end Numeric (integer) literal
18. endmodule Identifier
 Identifier and Literal Operands (2/2)
parameter CST = 4’b 1010, TF=25;
if (A1 == 1)
Y1 = {CST, 4’b 0000};
else if (A2 == 1)
Y1 = {CST, 4’b 0101};
else
Y1 = {CST, 4’b 1111};
if (B1 == 0) Y2 = 10;
else if (B2 == 1) Y2 = 15;
else Y2 = TF +10 +15;

A1 0 1 0 1
A2 0 0 1 1
B1 0 1 0 1
B2 0 0 1 1
Y1 10101111 10100000 10100101 10100000
Y2 0010102 (10) 1100102 (50) 0010102 (10) 0011112 (15)
 Function Call Operands (1/4)
◼ Function calls, which must reside in an expression, are
operands. The single value returned from a function is the
operand value used in the expression.
1. module FUNCTION_CALLS (A1, A2, A3, A4, B1, B2, B3, B4, Y1, Y2);
2. input A1, A2, A3, A4, B1, B2, B3,B4; output [2:0] Y1, Y2;
3. reg [2:0] Y1, Y2;

4. function [2:0] Fn1;

5. input F1, F2, F3;
6. begin
7. Fn1 = F1+F2+F3;
8. end
9. endfunction

10. always @(A1 or A2 or A3 or A4 or B1 or B2 or B3 or B4)

11. begin
12. Y1 = Fn1(A1, A2, A3)+A4;
13. Y2 = Fn1(B1, B2, B3)-B4;
14. end
15. endmodule Function call operand
 Function Call Operands (2/4)
function [2:0] Fn1; always @(A1 or A2 or A3 or A4 or B1 or
input F1, F2, F3; B2 or B3 or B4)
begin begin
Fn1 = F1+F2+F3; Y1 = Fn1(A1, A2, A3)+A4;
end Y2 = Fn1(B1, B2, B3)-B4;
endfunction end

A1 0 0 1 1 2‘s complement is implemented: A-B

A2 0 0 1 1 (1) A加上B的2補數
(2) a.若有進位(carry),代表結果為正, 去
A3 0 0 0 0
掉進位,剩下即為結果
A4 0 1 0 1
b.若無進位(carry),代表結果為負, 取
B1 0 1 0 1
結果的2補數,在前面加上負號
B2 0 0 0 0
B3 0 0 1 1 1-1 2-1
B4 0 0 1 1
001 010
Y1[2:0] 000 001 010 011 +111 +111
Y2[2:0] 000 001 000 001 1000 1001
 Function Call Operands (3/4)
1. module FUNCTION_CALLS (A1, A2, A3, A4, Y1, Y2);
2. input A1, A2, A3, A4; output [4:0] Y1, Y2;
3. reg [4:0] Y1, Y2; always @(A1 or A2 or A3 or A4)
begin
4. function [4:0] Fn1; Y1 = Fn1(A1, A2, A3, A4)+10;
5. input F1, F2, F3, F4; Y2 = Fn2(A1, A2, A3, A4)-5;
6. begin end
7. Fn1 = F1+F2+F3+F4; endmodule
8. end
9. endfunction A1 0 0 0 1
A2 0 0 0 1
10. function [4:0] Fn2; A3 0 0 1 0
11. input F1, F2, F3, F4;
A4 0 1 0 0
12. begin
13. Fn2 = (F1+F2)+(F3+F4); Y1[4:0] 01010 01011 01011 01100
14. end Y2[4:0] 11011 11100 11100 11101
15. endfunction 00000+11011 (-5)=11011 - 00100+1= -00101(-5)
00001+11011 (-5)=11100 - 00011+1= -00100(-4)
 Function Call Operands (4/4)
F1

＋
F2 ＋
Fn1 = F1+F2+F3+F4;
F3 ＋ Fn1
F4

What is the different ?

Longer delay (3 stages) Why ?
F1
＋
F2
F3 ＋ Fn2
Fn2 = (F1+F2)+(F3+F4);
＋
F4

Shorter delay
Index and Slice Name Operands (1/2)
◼ Index operand specifies a single element of an
array and slice operand specifies a sequence of
elements within an array
1. module INDEX_SLICE_NAME (A, B, Y);
2. input [5:0] A, B;
3. output [11:0]Y;
4. parameter C = 3’b111;
5. reg [11:0] Y;

6. always @(A or B)
7. begin
8. Y[2:0] = A[2:0];
9. Y[3] = A[3] | B[3];
10. Y[5:4] = {A[5] | B[5], A[4] & B[4]};
11. Y[8:6] = B[2:0];
12. Y[11:9] = C;
13. end
14. endmodule
 Index and Slice Name Operands (2/2)
parameter C = 3’b111;
Y[2:0] = A[2:0]; Y[3]= A[3] | B[3];
Y[5:4] = {A[5] | B[5], A[4] & B[4]};
Y[8:6] = B[2:0]; Y[11:9]= C;

A[2:0] 000 010 100 101 110

A[3] 0 1 0 1 0
A[4] 0 1 0 1 0
A[5] 0 1 0 1 0
B[2:0] 110 111 101 001 000
B[3] 0 0 1 1 0
B[4] 0 0 1 1 0
B[5] 0 0 1 1 0
Y[0:2] 000 010 100 101 110
Y[3] 0 1 1 1 0
Y[5:4] 00 10 10 11 00
Y[8:6] 110 111 101 001 000
Y[11:9] 111 111 111 111 111
 Operators (1/3)
◼ Operators perform an operation on one or more
operands within an expression. An expression
combines operands with appropriate operators to
produce the desired function expression.

Name Operator
bit-select or part-select []
parenthesis ()
Arithmetic Operators
multiplication *
division /
addition +
subtraction -
modulus %
Sign Operators
identity +
negation -
 Operators (2/3)
Name Operator
Relational Operators
less than <
less than or equal to <=
greater than >
greater than or equal to >=
Equality Operators
logic equality ==
logic inequality !=
case equality ===
case inequality !==
Logical Comparison Operators
NOT !
AND &&
OR ||
Logical Bit-Wise Operators
unary negation NOT ~
binary AND &
binary OR |
binary XOR ^
binary XNOR ^~ or ~^
 Operators (3/3)

Name Operator
Shift Operators
logical shift left <<
logical shift right >>
Concatenation & Replication
Operators
concatenation {}
replication {{ }}
Reduction Operators
AND &
OR |
NAND ~&
NOR ~|
XOR ^
XNOR ^~ or ~^
Conditional Operator
conditional ?:
 Arithmetic Operators

1. module ARITHMETIC(A, B, Y1, Y2, Y3);

2. input [2:0] A, B;
3. output [3:0] Y1; Arithmetic operators:
4. output [4:0] Y3; (1) +
5. output [3:0] Y2; (2) -
6. reg [3:0] Y1; (3) *
7. reg [4:0] Y3; (4) / (++)non-syn.
8. reg [3:0] Y2; (5) % (++)non-syn.
9.
10. always @(A or B)
11. begin
12. Y1 = A + B;
A[2:0] 000 001 101 110
13. Y2 = A - B;
14. Y3 = A * B; B[2:0] 101 111 100 001
15. Y4 = A / B; (不建議) Y1[3:0] 0101 1000 1001 0111
16. Y5 = A % B;
17. end Y2[3:0] 1011 (-5) 1010(-6) 0001(+1) 0101(+5)
18. endmodule Y3[4:0] 00000 00111 10100 00110
 Sign Operators
1. module SIGN(A, B, Y1, Y2);
2. input [2:0] A;
Sign operators:
3. input [2:0] B;
(1) +
4. output [3:0] Y1;
(2) -
5. output [3:0] Y2;
6. reg [3:0] Y1;
7. reg [3:0] Y2;

8. always @(A or B)
9. begin
10. Y1 = A + -B; A[2:0] 000 001 100 101 110 111 000
11. Y2 = -A + B;
12. end B[2:0] 110 101 100 010 000 001 101
13. endmodule Y1[3:0] 1010 1100 0000 0011 0110 0110 1011
(-6) (-4) (0) (3) (6) (6) (-5)
Y2[3:0] 0110 0100 0000 1101 1010 1010 0101
(6) (4) (0) (-3) (-6) (-6) (5)
 Relational Operators
1. module RELATIONAL_OPERATORS(A, B, Y);
2. input [2:0] A;
3. input [2:0] B; Relational operators:
4. output [3:0] Y;
(1) <
5. reg [3:0] Y;
(2) <=
6. always @(A or B) (3) >=
7. begin (4) >
8. Y[0] = A > B;
9. Y[1] = A >= B;
10. Y[2] = A < B; A[2:0] 1 2 3 4 5 6 7 3 0
11. if ( A <= B)
12. Y[3] = 1; B[2:0] 3 5 6 7 2 1 0 3 6
13. else Y[3] 1 1 1 1 0 0 0 1 1
14. Y[3] = 0; Y[2] 1 1 1 1 0 0 0 0 1
15. end
16. endmodule Y[1] 0 0 0 0 1 1 1 1 0
Y[0] 0 0 0 0 1 1 1 0 0
 Equality & Inequality Operators
1. module EQUALITY_OPERATORS(A, B, Y);
2. input [2:0] A;
3. input [2:0] B; Equality operators:
4. output [4:0] Y; (1) == (等於)
5. reg [4:0] Y; (2) != (不等於)
(3) === (++) non-syn.
6. always @(A or B) (4) !== (++) non-syn.
7. begin
8. Y[0] = A != B; When comparison is true, the result is 1
9. Y[1] = A == B; When comparison is false, the result is 0
10. if ( A == B)
11. Y[4:2] = A;
12. else A[2:0] 0 7 4 1 0
13. Y[4:2] = B;
B[2:0] 3 7 3 4 5
14. end
Y[0] 1 0 1 1 1
15. endmodule Y[1] 0 1 0 0 0
Y[4:2] 3 7 3 4 5
 Logical Comparison Operators (1/2)
1. module COMPARISON(A, B, C1,C2,C3);
2. input [2:0] A,B;
3. output [2:0] C1, C2, C3;
4. reg [2:0] C1, C2, C3;
Logic comparison operators:
(1) ! (NOT)
5. always @(A or B)
6. begin (2) && (AND)
7. if (( A == 1) && ( B>2 ) ) (3) || (OR)
8. C1= 2’b 00; else C1= 2’b 11;
9. if (( A>3) || ( B>1 ) )
10. C2= 2’b 00; else C2= 2’b 11;
11. if (!A)
12. C3= 2’b 00; else C3= 2’b 11;
13. end
14. endmodule
 Logical Comparison Operators (2/2)
always @(A or B)
begin
if (( A == 1) && ( B>2))
C1= 2’b 00;
else C1= 2’b 11;
if (( A>3) || ( B>1 ) )
C2= 2’b 00;
else C2= 2’b 11;
if (!A)
C3= 2’b 00;
else C3= 2’b 11;
end

A[2:0] 000 001 010 101

B[2:0] 000 010 001 010
C1[2:0] 011 011 011 011
C2[2:0] 011 000 011 000
C3[2:0] 000 011 011 011
 Logical Bit-Wise Operators
module BITWISE(A, B, Y1, Y2, Y3, Y4, Y5);
input [3:0] A;
input [3:0] B; Logic bit-wise operators:
output [3:0] Y1, Y2, Y3, Y4, Y5; (1) ~ (unary NOT)
(2) & (binary AND)
(3) | (binary OR)
reg [3:0] Y1, Y2, Y3, Y4, Y5;
(4) ^ (binary XOR)
(5) ^~ or ~^ (binary XNOR)
always @(A or B)
begin
A[3:0] 0000 0001 0010 0110
Y1 = ~A; 0110
Y2 = A & B; & 0011 B[3:0] 0000 0000 0001 0011
Y3 = A | B ; 0010 Y1[3:0] 1111 1110 1101 1001
Y4 = A ^ B; Y2[3:0] 0000 0000 0000 0010
Y5 = A ^ ~ B; 0110 Y3[3:0] 0000 0001 0011 0111
end | 0011 Y4[3:0] 0000 0001 0011 0101
endmodule 0111 Y5[3:0] 1111 1110 1100 1010
 Shift Operators
1. module SHIFT(A, Y1, Y2);
2. input [7:0] A;
3. output [7:0] Y1;
4. output [7:0] Y2; Shift operators:
(1) << (left shift)
5. reg [7:0] Y1; (2) >> (right shift)
6. reg [7:0] Y2;

7. parameter B=3;

8. always @(A)
9. begin
10. Y1 = A << B; A[7:0] 00000000 00000001 00000011 00000100
11. Y2 = A >> 2; Y1[7:0] 00000000 00001000 00011000 00100000

12. end Y2[7:0] 00000000 00000000 00000000 00000001

13. endmodule
 Concatenation & Replication Operators
1. module CONCATENATION (A, B, Y);
2. input [2:0] A; Concatenation {}
3. input [2:0] B; Replication {{}}
4. output [14:0] Y;

5. reg [14:0] Y;
A[2:0] 000 001 010 011
6. parameter C=3’b011; B[2:0] 000 010 100 110
Y[14:0] 000 010 100 110
7. always @(A) 000 001 010 011
8. begin 011 011 011 011
9. Y = { B, A, { 2 { C } }, 3’b 001}; 011 011 011 011
10. end 001 001 001 001
11. endmodule 3+3+2*3+3=15
 Reduction Operators
module REDUCTION (A, Y);
Reduction operators:
input [3:0] A;
(1) & (2) |
output [5:0] Y;
(3)~& (4) ~|
(5) ^ (6) ~^
reg [5:0] Y;

always @(A) &A A[0] & A[1] & A[2] & A[3]
begin |A A[0] | A[1] | A[2] | A[3]
Y[0] = & A;
Y[1] = | A; ^A A[0] ^ A[1] ^ A[2] ^ A[3]
Y[2] = ~& A;
Y[3] = ~| A; A[3] 0 0 0 0
Y[4] = ^ A; // XOR,奇同位 A[2] 0 0 0 0
Y[5] = ~^ A; //XNOR,偶同位
A[1] 0 0 1 1
end
endmodule A[0] 0 1 0 1
Y[5:0] 101100 010110 010110 100110
 Conditional Operators
1. module ADD_SUB (A, B, SEL, Y);
2. input [7:0] A; input [7:0] B;
Conditional operators:
3. input SEL;
? :
4. output [8:0] Y1,Y2;
5. reg [8:0] Y2,Y1;
6. always @( A or B)
7. begin
8. Y1 = ( SEL == 1 ) ? A + B : A – B ;
9. Y2 = (!SEL) ? A : B;
10. end
endmodule SEL 0 0 1 1
A[7:0] 00000100 00000001 00000100 00000001
B[7:0] 00000001 00000010 00000001 00000010
Y1[8:0] 00000011 11111111 00000101 00000011
Y2[8:0] 00000100 00000001 00000001 00000010
 Full Adder (1/6)
Reduction with K-map or Boolean Algebra.
ab\c_in 0 1 ab\c_in 0 1
00 0 1 00 0 0
01 1 0 01 0 1
11 0 1 11 1 1
10 1 0 10 0 1
sum c_out
= abc_in+ abc_in+ abc_in+ abc_in = ab + abc_in+ abc_in
=(ab + ab)c_in+(ab + ab)c_in = ab +(ab + ab)c_in
=(a  b)c_in+(a b)c_in = ab +(a  b)c_in
=(a  b)  c_in
Reduction is done by user or tool.
 Full Adder (2/6)
module Add_full(c_in, sum, c_out, a, b);

input a, b, c_in; sum = (a  b)  c_in

output sum, c_out; c_out = ab + (a  b)c_in

reg sum, c_out;

always @(a or b or c_in)
begin
sum = (a ^ b) ^ c_in;
c_out = (a&b) | ((a ^ b) &c_in);
end or
endmodule structural description

assign {c_out, sum} = a + b + c_in;

data flow description
Save file as Add_full.v and Synthesize it
 Full Adder (3/6)
sum = (a  b)  c_in
c_out = ab + (a  b)c_in (a⊕b) ⊕ c_in
c_in a sum sum
Add_half (a⊕b) c_in
w1 w3
a a sum b c_out c_out
(a⊕b)
Add_half M2
b b c_out (a⊕b) c_in + ab
M1 ab w2

structural description Hierarchical Description

module Add_full(sum, c_out, a, b, c_in);
input a, b, c_in; data flow description
output sum, c_out; module Add_half(sum, c_out, a, b);
wire w1, w2, w3; input a, b;
output sum, c_out;
Add_half M1(w1, w2, a, b);
Add_half M2(sum, w3, c_in, w1); assign {c_out, sum} = a + b;
or (c_out, w2, w3); endmodule
endmodule
in-order port mapping
 Full Adder (4/6)
Implementation Issue:
module Add_full(sum, c_out, a, b, c_in);
input a, b, c_in; If both modules (Add_full
output sum, c_out;
wire w1, w2, w3; and Add_half) are saved
in the same file, then name
Add_half M1(w1, w2, a, b);
Add_half M2(sum, w3, c_in, w1); and save the file as
or (c_out, w2, w3); Add_full.v (top module)
endmodule

module Add_half(sum, c_out, a, b); Compile Add_full.v and

input a, b; synthesize it
output sum, c_out;

assign {c_out, sum} = a + b;

endmodule
Add_full.v
 Full Adder (5/6)
`include “Add_half.v”
module Add_full(sum, c_out, a, b, c_in);
input a, b, c_in; If modules Add_full and
output sum, c_out;
wire w1, w2, w3; Add_half are saved
in the distinguish files
Add_half M1(w1, w2, a, b);
Add_half M2(sum, w3, c_in, w1); (Add_full.v and Add_half
or (c_out, w2, w3); respectively), then the
endmodule Add_full.v include command is
necessary (otherwise ?..)
module Add_half(sum, c_out, a, b);
input a, b;
output sum, c_out; Compile Add_full.v and
synthesize it
assign {c_out, sum} = a + b;
endmodule
Add_half.v
 Full Adder (6/6)
4-bit Adder
module Adder_4_RTL(sum, c_out, a, b, c_in);

input [3:0] a, b;
input c_in;
output [3:0] sum;
output c_out;

assign {c_out, sum} = a + b+ c_in;

endmodule a b
1
c_in 4 4
The synthesized circuit is dependent on
the tool you use (might be ripple-carry 4-bit Adder

Adder or other Adders). 1 4

c_out sum
 3 to 8 Decoder (1/4)
Out[0]
In[0]
In[0] .
3-8 .
In[2] decoder
E Out[7]

E In[2] In[1] In[0] Out[7] Out[6] Out[5] Out[4] Out[3] Out[2] Out[1] Out[0]
0 X X X 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
 3 to 8 Decoder (2/4)
Structural description
1. module decoder (E , In , Out);
Out[0] 2. input E; input [2:0] In;
3. output [7:0] Out;
Out[1] wire [7:0] Out;
In[0] 4.

5. wire tmp0 , tmp1 , tmp2;

Out[2]
In[1]
6. not not1(tmp0,In[0]); not not2(tmp1,In[1]);
Out[3]
7. not not3(tmp2,In[2]);
In[2]
8. and and0(Out[0] , E , tmp0 , tmp1 , tmp2);
Out[4]
9. and and1(Out[1] , E , In[0] , tmp1 , tmp2);
E
10. and and2(Out[2] , E , tmp0 , In[1] , tmp2);
Out[5]
11. and and3(Out[3] , E , In[0] , In[1] , tmp2);
12. and and4(Out[4] , E , tmp0 , tmp1 , In[2]);
Out[6]
13. and and5(Out[5] , E , In[0] , tmp1 , In[2]);
14. and and6(Out[6] , E , tmp0 , In[1] , In[2]);
Out[7]
15. and and7(Out[7] , E , In[0] , In[1] , In[2]);
16. endmodule
 3 to 8 Decoder (3/4)
Data flow description Out[0]
1. module decoder(E , In , Out);
Out[1]
2. input E; In[0]
3. input [2:0]In; Out[2]
In[1]
4. output [7:0]Out;
Out[3]
5. wire [7:0]Out; In[2]

6. assign Out = E ? 1'b1 << In : 8'h0; Out[4]

E
7. endmodule true false Out[5]

E In Out Out[6]
0 X X X 00000000
1 0 0 0 00000001 Out[7]
1 0 0 1 00000010 Synthesized and
1 0 1 0 00000100 optimized by tools
….
 3 to 8 Decoder (4/4)
Behavioral description 3'b100: Out = 8'h10;
module Decoder_Behavioral(E, In, Out); 3'b101: Out = 8'h20;
Input E; 3'b110: Out = 8'h40;
input [2:0] In; default: Out = 8'h80;
output [7:0] Out; endcase
reg [7:0] Out; end
always @(E or In) end
begin endmodule
if(!E) E In Out
Out = 8'h00; 0 X X X 0000000 0
else 1 0 0 0 0000000 1
begin 1 0 0 1 0000001 0
case(In) 1 0 1 0 0000010 0
3'b000: Out = 8'h01; 1 0 1 1 0000100 0
3'b001: Out = 8'h02; 1 1 0 0 0001000 0
3'b010: Out = 8'h04; 1 1 0 1 0010000 0
3'b011: Out = 8'h08; 1 1 1 0 0100000 0
1 1 1 1 1000000 0
 Hierarchical Design of 3-8 decoder
Data flow description
module decoder_2_4(E , In , Out); E In[2] In[1] In[0]

input E; input [1:0] In;

output [3:0]Out; wire [3:0] Out;

assign Out = E ? 1'b1 << In : 4'h0; E1

2 to 4 decoder
endmodule

module decode_3_8(E , In , Out); In[1] In[0] In[1] In[0]

input E; input [2:0] In; Decoder1 Decoder 0
output [7:0] Out; wire E1 , G1 , G2 2- 4 decoder G1 2- 4 decoder
G2;
not u1(E1 , In[2]); and a1(G1 , E , In[2]);
and a2(G2 , E , E1); Out[7:4] Out[3:0]
decoder_2_4 M(G1 , In[1 : 0] , Out[7 : 4]);
decoder_2_4 L(G2 , In[1 : 0] , Out[3 : 0]);
endmodule
structural description
 Hierarchical Description of Circuit
module Add_rca_4(sum, c_out, a, b, c_in);
input [3:0] a, b;
input c_in;
Ripple-Carry output [3:0] sum;
Adder output c_out;
wire c_in2, c_in3, c_in4;

Add_full G1(sum[0], c_in2, a[0], b[0], c_in);

Add_full G2(sum[1], c_in3, a[1], b[1], c_in2);
Add_full G3(sum[2], c_in4, a[2], b[2], c_in3);
Add_full G4(sum[3], c_out, a[3], b[3], c_in4);
endmodule

a[3] b[3] a[2] b[2] a[1] b[1] a[0] b[0]

c_in
Add_full Add_full Add_full Add_full
c_out G4 G3 G2 G1
c_in4 c_in3 c_in2
sum[3] sum[2] sum[1] sum[0]
 Array of Instances
module array_of_nor(y, a, b); module array_of_nor(y, a, b);
input [0:7] a, b; input [0:7] a, b;
output [0:7] y; output [0:7] y;

nor (y[0], a[0], b[0]); nor [0:7] (y, a, b);

nor (y[1], a[1], b[1]); endmodule
nor (y[2], a[2], b[2]);
nor (y[3], a[3], b[3]);
8 nor (y[4], a[4], b[4]);
nor (y[5], a[5], b[5]);
nor (y[6], a[6], b[6]);
nor (y[7], a[7], b[7]);
endmodule
 Two alternatives for Continuous Assignment

module bit_or8_gate1(y, a, b);

module bit_or8_gate2(y, a, b);
input [7:0] a, b; input [7:0] a, b;
output [7:0] y; output [7:0] y;
wire [7:0] y = a | b;
assign y = a | b; endmodule
endmodule
 Multiple Instantiations and Assignments

module Multiple_Gates(y1, y2, y3, a1, a2, a3, a4);

input a1, a2, a3, a4;
output y1, y2, y3;

nand #1 G1(y1, a1, a2, a3), (y2, a2, a3, a4), (y3, a1, a4);
endmodule

module Multiple_Assigns(y1, y2, y3, a1, a2, a3, a4);

input a1, a2, a3, a4;
output y1, y2, y3;

assign #1 y1 = a1 ^ a2, y2 = a2 | a3, y3 = a1 + a2;

endmodule
 Simulation for a circuit

circuit

Stimulus Response
Verilog
and Generation
Module
Control

Verification Waveform
Waveform

input output
 Waveform Simulation (1/3)
Most EDA tools support waveform simulation
module OR_AND_DATA_FLOW(in, out);
IN[0]
IN[1] input [3:0] in;
OUT output out;
IN[2]
IN[3] assign out = (in[0] | in[1]) & (in[2] | in[3]);
endmodule
The results by using Altera functional simulation

No delay is introduced if only functional simulation is used

 Waveform Simulation (2/3)
The results by using Altera functional simulation + timing simulation

delay (based on Altera Cell)

No delay is introduced if only functional simulation is used

IN[0]
IN[1]
OUT
IN[2]
IN[3]
Waveform Simulation (3/3)
functional simulation for 3 to 8 decoder

functional simulation + timing simulation

delay delay
 Simulation for a circuit
non-synthesizable
non-synthesizable synthesizable

circuit
Stimulus Response
Verilog
and Generation
Module
Control

Verification Waveform,
Waveform,
text reports
test patterns

Test Bench
 ModelSim Test_Bench Simulation (1/4)
non-synthesizable
Test_bench #10 in1 = 1; in2 = 0; in3 = 0; in4 = 0;
#10 in1 = 1; in2 = 0; in3 = 0; in4 = 1;
module or_and_tb; #10 in1 = 1; in2 = 0; in3 = 1; in4 = 0;
reg in1, in2, in3, in4; ..
wire out; end
or_and ok(.in1(in1), .in2(in2), endmodule
.in3(In3), .in4(in4), .out(out)); synthesizable
initial module or_and (in, out);
begin input[3:0] in;
#0 in1=0; in2=0; in3=0; in4=0; output out;
#10 in1=0; in2=0; in3=0; in4=1; assign out = (in[0] | in[1]) & (in[2] | in[3]);
#10 in1=0; in2=0; in3=1; in4=0; endmodule
#10 in1=0; in2=0; in3=1; in4=1;
#10 in1=0; in2=1; in3=0; in4=0; Altera does not support this kind of
#10 in1=0; in2=1; in3=0; in4=1;
simulation (inputs is activated by
#10 in1=0; in2=1; in3=1; in4=0;
#10 in1=0; in2=1; in3=1; in4=1; commands in the test bench file).
ModelSim is a PC-based tool.
(workstation-like)
 ModelSim Test_Bench Simulation (2/4)
Functional simulation only (no delay is introduced)

In ModelSim, Input: test patterns (using comds.) Output: waveform

In Altera, Input: waveform Output: waveform
 ModelSim Test_Bench Simulation (3/4)

Test_bench #0 E = 0; in = 3'b000;
#10 E = 1; in = 3'b000;
module decoder_3_8_tb; #10 E = 1; in = 3'b001;
#10 E = 1; in = 3'b010;
reg E; #10 E = 1; in = 3'b011;
reg [2:0] in;
#10 E = 1; in = 3'b100;
wire [7:0] out; #10 E = 1; in = 3'b101;
#10 E = 1; in = 3'b110;
decoder #10 E = 1; in = 3'b111;
ok(.E(E), .in(in), .out(out));
end
initial endmodule
begin
Exhaustive test or partial test for functional simulation in
test_bench ? How about chip test ? Exhaustive or partial testing?
ModelSim Test_Bench Simulation (4/4)
 Signalscan Simulation in WS (1/4)
Test_bench #10 E = 1; in = 3'b101;
module decoder_3_8_tb;
#10 E = 1; in = 3'b110;
reg E; #10 E = 1; in = 3'b111;
reg [2:0] in;
End
wire [7:0] out; Initial
begin
decoder ok(.E(E), .in(in), .out(out)); $dumpfile(“decoder.fsdb”);
$dumpvars(0 , decoder_tb);
initial $shm_open(“ok”);
begin $shm_probe(“AS”);
#0 E = 0; in = 3'b000; end
#10 E = 1; in = 3'b000;
#10 E = 1; in = 3'b001;
#10 E = 1; in = 3'b010; endmodule
#10 E = 1; in = 3'b011;
#10 E = 1; in = 3'b100;
Signalscan Simulation in WS (2/4)
 Signalscan Simulation in WS (3/4)
module decoder_tb; initial
begin
reg E; for(i=0; i<8; i = i + 1)
reg [2:0] in; begin
reg [3:0] i; #10 E = 1 ; in[2:0] = i[3:0];
wire [7:0] out; #1 $fdisplay(decoder_1," E = %d
integer decoder_1; in[2] =%d in[1] = %d in[0] = %d
out = %b",E,in[2],in[1],in[0],out[7:0]);
decoder ok(.E(E), .in(in), .out(out)); $monitor($time , " E = %d in[2] = %d
in[1] = %d in[0] = %d out = %b", E,
initial //Open file_decoder in[2], in[1], in[0], out[7:0]);
begin end
decoder_1 = $fopen("decoder_out.txt");
end $dumpfile("sim_decoder.dump");
$dumpvars(1,decoder_tb);
$shm_open("sim_decoder");
$shm_probe("AC");
end
endmodule
 Signalscan Simulation in WS (4/4)
decoder_out.txt
E = 1 in[2] = 0 in[1] = 0 in[0] = 0 out = 00000001
E = 1 in[2] = 0 in[1] = 0 in[0] = 1 out = 00000010
E = 1 in[2] = 0 in[1] = 1 in[0] = 0 out = 00000100
E = 1 in[2] = 0 in[1] = 1 in[0] = 1 out = 00001000
E = 1 in[2] = 1 in[1] = 0 in[0] = 0 out = 00010000
E = 1 in[2] = 1 in[1] = 0 in[0] = 1 out = 00100000
E = 1 in[2] = 1 in[1] = 1 in[0] = 0 out = 01000000
E = 1 in[2] = 1 in[1] = 1 in[0] = 1 out = 10000000

What should we do after HDL simulation ?

FPGA synthesis or ASIC synthesis
 Synthesis Flow of VLSI design (1/3)
Behavioral requirement

Synthesis Verification and analysis

Functional design
High level synthesis Behavioral or functional simulation
Behavioral representation
Boolean equations and RTL
Verification and analysis
Synthesis Logic design
Logic synthesis Logic verification, Logic simulation
Structural representation Testing
Logic gates, connections
Synthesis Circuit design
Cell generators
Verification and analysis
Structural representation Circuit simulation, Circuit analysis
Transistors and connections
Synthesis
Floorplanning, Physical design Verification and analysis
Placement, Routing
Physical representation Design-rule checking
Mask layout rectangles Circuit extraction
 Synthesis Flow of VLSI design (2/3)
Synthesis:
1. A transition from a single domain to another
2. Add detail to the current state of the design
3. Perform fully automatically by some synthesis
tool or manually by the designer
Verification tool:
Check whether a synthesis step has left the
specification intact
Analysis tool:
Provide data on the quality of the design (speed,area,..)
 Synthesis Flow of VLSI design (3/3)

Behavioral
description
High level synthesis
logic synthesis RTL
Code

gates
circuits synthesis

Physical synthesis:
a. Floorplanning & Placement transistors
Fix the relative positions of physical synthesis
the subblocks

b. Routing
Generate the interconnection
wires between blocks