Report for E-design 344

by

Phora Ramotale
20927371

E-Design final report (Assignment # 3)

October 2019
Declaration

By submitting this report electronically, I declare that the entirety of the work contained
therein is my own, original work, that I am the sole author thereof (save to the extent
explicitly otherwise stated), that reproduction and publication thereof by Stellenbosch
University will not infringe any third party rights and that I have not previously in its
entirety or in part submitted it for obtaining any qualification.

Signature: ...............................
P. Ramotale

Date: ....................................

i
Contents

Declaration i

Contents ii

List of Figures iv

List of Tables vi

Nomenclature vii

1 System design 1
1.1 System overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Power conversion 3
2.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.1 Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.2 Switchmode regulation . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.3 Linear regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.4 Charge pump regulation . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 Summary and implementation . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Signal conditioning 8
3.1 Voltage transducer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.2 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.3 Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Current transducer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.2 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.3 Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Phase-shift transducer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.2 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.3 Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Summary and implementation . . . . . . . . . . . . . . . . . . . . . . . . . 16

ii
CONTENTS iii

4 Over-current protection 17
4.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 Reporting 21
5.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.1 Arduino Code Flow diagram . . . . . . . . . . . . . . . . . . . . . . 21
5.1.2 Python Code psuedocode . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.3 Arduino Beetle Over-voltage protection . . . . . . . . . . . . . . . . 22
5.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6 Extra functionality 23

7 System and conclusion 24

7.1 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2 Lessons learned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

References 25

Appendix A: GitHub Activity Heatmap 26

List of Figures

1.1 System diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1 Complete Power conditioning circuit diagram . . . . . . . . . . . . . . . . . 3

2.2 Power Conditioning Simulation results . . . . . . . . . . . . . . . . . . . . . 6
2.3 Power Conditioning Simulation results . . . . . . . . . . . . . . . . . . . . . 7
2.4 Implementation of the power conversion circuitry. . . . . . . . . . . . . . . . 7

3.1 Voltage transducer circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . 9

3.2 Voltage transducer simulation results. (a) No load simulated. (b) Mid-sized
load simulated. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Voltage transducer measurement results. (a) Mid-sized load input voltage
and analogue DC voltage. (b) No load input voltage and analogue DC . (c)
AC measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4 Current transducer circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . 11
3.5 Current transducer simulated results. (a) No load simulated. (b) Mid-load
simulated. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.6 Current transducer measured results. (a) Mid-load measured. (b) No-load
measured. (c) AC measured. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.7 Phase transducer circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . 13
3.8 Phase-shift transducer results. (a) Resistive load simulated. (b) Mid-sized
capacitive load simulated. Inputs and outputs of an XOR gate shown. . . . . 14
3.9 Phase-shift transducer results. (a) Resistive load measured. (b) 1k + 3.3µF
load measured. (c) Analogue signal noise measured. . . . . . . . . . . . . . 15
3.10 Implementation of the transducers circuitry. (a) Voltage load and current
transducers implementation. (b) Phase shift transducer implementation. . . 16

4.1 Over-Current Protection circuit diagram . . . . . . . . . . . . . . . . . . . . 17

4.2 Comparator circuit diagram for over-current protection . . . . . . . . . . . . 18
4.3 Over-current protection simulation results. (a) Simulation of SET and RE-
SET single pulses. (b) Input voltage at terminal 6 of the optoisolator. (c)
Voltage across the load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4 Reaction time of the trip circuit. (a) Set pulse measurement. (b) Measure
time for trip to occur. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1 Arduino Code Flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.2 Over-voltage protection circuit diagram . . . . . . . . . . . . . . . . . . . . . 22
5.3 Graphical User Interface results. (a) GUI display in debug mode with load
at normal operation. (b) GUI display showing normal load operation before
tripping and after tripping. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

iv
LIST OF FIGURES v

7.1 Complete PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

List of Tables

3.1 Voltage Transducer Unit Test Results. . . . . . . . . . . . . . . . . . . . . . 9

3.2 Voltage Transducer measurement results. . . . . . . . . . . . . . . . . . . . . 10
3.3 Current Transducer Unit Test Results. . . . . . . . . . . . . . . . . . . . . . 12
3.4 Current Transducer measurement results. . . . . . . . . . . . . . . . . . . . . 13
3.5 Phase Shift Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

vi
Nomenclature

Constants
VT = 26mV

Variables
P Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [W]
V Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [V]
I Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [A]
T Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [ ◦C ]
β BJT Current gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [1]
Vpp Peak to peak Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [ Vpp ]
η Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [%]

Abbreviations
AC Alternating Current
DC Direct Current
PC Personal Computer
PWM Pulse Width Modulation
BJT Bipolar Junction Transistor
RMS Root Mean Square
GUI Graphical User Interface

vii
Chapter 1

System design

1.1 System overview

The system diagram is shown in Fig. 1.1. From the diagram it can be noted that the 240
VAC voltage from the socket is stepped down to 18 VAC voltage by the 240/18 VAC 750
mA rated transformer. The low voltage power is essentially used to power the load as
well as the circuitry of the device. The load is connected after the 500mA over-current
protection fuse to provide extra caution regarding short circuit currents or high currents
resulting from faults. The 18 VAC voltage is also fed into the regulator and rectifiers
to convert the AC signal to +5 VDC and -5 VDC. These voltage levels are subsequently
used as power supplies for both positive and negative rails of the operational amplifiers.
The +5 VDC is also designed to supply power to the trip circuit.

The switch and over-current protection circuitry are connected at the high side of the
load whilst the current sense circuitry is connected at the low side of the load. Since the
signal from the current sense is significantly low, it is amplified prior to being fed to phase
angle to analogue conversion. The peak of current through the load is detected by the
current transducer which is represented by current peak level to analogue conversion block
from the diagram. The Voltage transducer is represented by voltage peak to analogue
conversion block. The voltage signal as well as preamplified current signal are fed into the
phase transducer and the analogue outputs of all these transducers are read by Arduino
Beetle. The Arduino beetle then converts the analogue signal to a digital signal which is
eventually send to the PC for display.

1
CHAPTER 1. SYSTEM DESIGN 2

Figure 1.1: System diagram

Chapter 2

Power conversion

Figure 2.1: Complete Power conditioning circuit diagram

2.1 Design
2.1.1 Rectifier
The idea is to get both +5VDC and -5VDC from 18VAC power supply. The first step is
to convert the AC signal to either half-wave of full-wave. Since the design of a fullwave
rectifier circuit is a bit involved than halfwave rectifier circuit but halfwave rectifier would
work just fine the halfwave wave rectifier is preferred over fullwave rectifier. Since the
standard 1N4007 rectifier diode is readily available and rated at 700V reverse voltage and
1A forward current [1] it is incorporated in this design to perform the rectification process.
A sufficiently large filtering capacitor is used to filter high frequency components of the
halfwave signal and thus obtain a rippled DC signal.
Design requirements of filtering capacitor:

• It must supply the maximum current of 250mA.

• Since the minimum input voltage to the switchmode regulator is 15VDC it must
have the minimum voltage of 15VDC.

3
CHAPTER 2. POWER CONVERSION 4

For 50Hz frequency: Period T = 20ms and assuming Vdiode = 0.7V

 
15
arccos 20 2
√
∆t = 20ms − = 16.76ms
(2π) (50)
Imax ∆t 250e − 3 × 16.76e − 3
∴C= = √ = 332.95µF
∆V 20 2 − 0.7 − 15
The parallel combination of a standard 220 µF and 120µF would give 340µF which will
work just fine.

2.1.2 Switchmode regulation

As the name implies switching regulators employ rapid switching using high frequency
pulse train. Filtering capacitors and feedback circuits ensure that the rippled input voltage
is converted to high noise (due to switching) DC output voltage with decent DC level.
The LM2595 switchmode regulator is used for this project since it has current rating of
up to 1A and high input voltages of up to 45 V [2]. The datasheet provides recommended
switchmode regulator circuit and values for certain circuit elements. Since the switching
regulator is used as an intermediate regulation stage its output is fed to the 100 mA 5VDC
LM7805 linear regulator. The regulator is designed to output 14 VDC and maximum
current of 250 mA. From the datasheet [2] the other feedback resistor can be determined
from equation 2.1 .
Recommended circuit’s elements and their values:

• CIN = 120 µF, 50 V electrolytic capacitor

• COU T 120 µF, 25 V electrolytic capacitor

• D1 - 3A, 40 V Schottky barrier diode, 1N582

• L1 - 100 µH (standard 68 µH inductor is used)

• R1 – 1kΩ
 
VOU T
∴ R2 = R1 − 1 = 10.38kΩ (2.1)
VREF
A standard 10 kΩ standard resistor is used. The feedforward capacitor is determined
from the following equation as suggested by manufacturer’s datasheet.
1
Cf f = = 3.226nF
31 × 103 × R2
A 3.3nF standard capacitor is used.

2.1.3 Linear regulation

It is imperative that the output voltage of the Linear regulator stays relatively constant
while supplying current within the design limits. The LM7805 linear regulator is supplied
by the 14VDC switchmode regulator and therefore the input voltage is within the allow-
able limit (30V maximum input voltage). As previously mentioned, the +5VDC supplies
CHAPTER 2. POWER CONVERSION 5

the operational amplifiers, Arduino Beetle and the trip circuit. Since the Arduino Bee-
tle can draw up to 40mA [3] while the trip circuit can draw the maximum of 30mA for
smooth operation. Assuming the operational amplifiers can draw 30mA combined it is
safe to design for 85% full load (Imax = 100m [4]). Assuming ambient temperature Tamb
= 35°C.
TJ − Tamb 150 − 35
Iload = = = 85.2mA
RθJA (Vin − Vout ) 150(14 − 5)
At 85% full load (85mA current and assuming 6mA quiescent current) the power
delivered to the load (58.8Ω) Pout = Iout 2 R = 425mW and the input power is Pin =
Vin (Iout − IQ ) = 14(85 − 6) = 1106mW and therefore the worst efficiency is calculated as
follows.
Pout 425
η= = = 38.4%
Pin 1106
The efficiency is quite low as expected. Another important factor is the allowable noise
levels of the output voltage. Since analogue outputs from the operational amplifiers will
be converted to digital signals noise level must be considered from accurate readings. The
most sensitive measurement is current measurement because it must be 1 mA accurate
on measuring up to 285 mA with a 5V ADC. Therefore, the allowable noise levels must
be less than 285
5
= 17.5 mV (20 mV seems reasonable enough).

2.1.4 Charge pump regulation

Since the charge pump deploys the PWM signal to generate the -5VDC required for this
project. It is necessary to amplify the 5V PWM from the Arduino Beetle to higher peak
to peak voltage level so that it can supply enough current and at the same time avoiding
drawing large current from the pins of Arduino Beetle. A simple BJT amplifier with DC
supply (14VDC) from the switchmode regulator output. For R4 = 1kΩ and R3 = 100Ω
the input voltage to the charge pump is 9V PWM.
The inverting capacitor C2 is selected such that it is large enough that it slowly
discharges and charges rapidly during the charging phase. Designing for 10KHz 50%
duty. The capacitor C2 has to supply the charge ∆Q2 = DTs Io where D is duty (50%),
Ts (100µs) is the switching period and Io (25mA) is the output current. The capacitor C3
= ∆Q2 ∆VO = DTS I0 ∆Vo = 62.5µF where ∆V = 20V ripple. Choosing a 100 µF ensures
constant voltage in case more than 25mA design current is drawn from the negative rails.
The voltage VC3 = Vcollector + 2Vdiode = -7 VDC (assuming Vdiode = 1 V) and putting 100
Ω in series with parallel combination of 5V clamping Zener diode and 100 µF capacitor
ensures that the output is clamped at -5VDC.

2.2 Simulation
The simulation results for power conditioning sub-circuits are shown bin Figure 2.2. For
all simulations depicted below the 18VAC input is used but safety considerations in the
design ensure smooth operation for higher input voltages such as 20 VAC.
CHAPTER 2. POWER CONVERSION 6

(a) (b)

(c) (d)

Figure 2.2: Power conditioning: (a) Simulation of the rectification showing the input
AC (Red), rectified signal at no load (Blue) and rectified signal at full load (Black). (b)
Simulation of the switching regulation showing the 50Hz input AC (Cyan) and 14VDC
output voltage. (c) Simulation of the Linear regulation showing the 14VDC input from the
output of switchmode regulator (Black) and 5VDC output voltage (Red). (d) Simulation
of the Charge pump regulation showing the -5VDC output (Blue) and 14VDC input
voltage (Black).

2.3 Measurements
Measurement results are shown in Figure 2.3.

2.4 Summary and implementation

The design performance exceeded my expectations in many ways. The measurement
results of the rectifier and all regulators a extremely close to the simulation results. Of
course minor discrepancies are inevitable because practical components have practical
imperfections as opposed to simulation’s. e.g the output of the linear regulator has 5%
tolerance. This is apparent as the measured positive rail voltage in Figure2.3c is 5.20VDC
The noise levels (less than 2.5mV peak to peak) of both positive rail (Figure 2.3e) and
negative rail (Figure 2.3f) are way below expected values. In general the performance of
the power system is excellent. The power conditioning circuitry is shown in Figure 2.4.
CHAPTER 2. POWER CONVERSION 7

(a) (b)

(c) (d)

(e) (f)

Figure 2.3: Power conditioning: (a) Input and output of the rectifier. (b) Input and
output of the switchmode regulator. (c) Practical measurements of the Linear regulation
showing the 14VDC input from the output of switchmode regulator and 5VDC output
voltage. (d) Measurements results of the Charge pump regulation showing the -5VDC
output and 14VDC input voltage.(e) Positive rail noise. (f) Negative rail noise.

Figure 2.4: Implementation of the power conversion circuitry.

Chapter 3

Signal conditioning

3.1 Voltage transducer

3.1.1 Design
The idea is to measure the voltage across a purely resistive load or resistive and capacitive
load. Since operational amplifiers (TLC2272 op amps) are incorporated in this design and
measured AC voltages levels range from 12 to 20 VAC as per requirement it is necessary
to scale down the voltage level down to acceptable levels. A simple series resistor voltage
divider circuit is used to accomplish that. The voltage divider circuit must utilise or most
preferably absorb no power from the source. Therefore, the resistor values must be large
enough to limit current thereby consuming less power. Also, the common mode input
voltages must be in the range −0.3 V to 4 V and preferably 3.5 V [5] as specified in the
datasheet reference. The voltage follower configuration ensures that the non-inverting
and inverting terminal voltages are the same and therefore differential voltage is always
less than the maximum allowable (±16 V) [5]. Selecting R1 = 100kΩ and making the low
voltage to be 4Vpeak for 20 VAC.
R2 × Vin
4=
R2 + R1
4R1
∴ R2 = √ = 16.47kΩ
20 2 − 4
A 22KΩ Potentiometer will be used instead of a fixed resistor. This is to accommodate
for tolerances in other fixed resistors. An active peak detector is used since it has low
output resistance and ability to get rid of rectifying diode. Since the complete design of
a peak detector incorporates a filtering capacitor and discharging resistor. The charging
time constant τcharging is extremely small since the diode resistance is very small and the
capacitor is connected directly to the inverting terminal. Designing for discharging time
τ
constant τdischarging = 1.5s and selecting R3 = 150 kΩ. C1 = discharging
R3
= 10µF.
The relationship between input peak voltage and analogue DC voltage is straight
forward. V peak = R2 R+R2
1
× Vanalogue = 7.67 × Vanalogue

∴ δVpeak = 7.67δVanalogue

Since the resolution of a 10-bit ADC is 2510 = 4.883mV ≈ 5mV the output has noise levels
lower than 5mV and therefore no impact on analogue readings.

8
CHAPTER 3. SIGNAL CONDITIONING 9

Figure 3.1: Voltage transducer circuit diagram.

3.1.2 Simulation
Figure 3.2a shows the no load simulation results while Figure 3.2b shows the mid-sized
load (1kΩ) load results. The simulation is made for different amplitude AC voltages.

(a) (b)

Figure 3.2: Voltage transducer simulation results. (a) No load simulated. (b) Mid-sized
load simulated.

3.1.3 Measurement
Figure 3.3a and 3.3c show the input voltage and DC analogue levels at no load and
mid-load conditions. The AC measurement is shown in figure 3.3c. Note that the ripple
amplitude is way less than the limiting condition for accurate analogue to digital readings
discussed in section 3.1.1. Voltage transducer unit test results are shown in Table 3.1.
The open, mid range and full load measurement results are shown in Table 3.2.

Table 3.1: Voltage Transducer Unit Test Results.

Emulated Level–Signal Generator Signal generator Analogue Output Deduced input Difference
Vpeak Vpeak Vpeak V DC Vpeak mV
16 3.963 3.92 -0.00127 15.82 -0.18
21 5.202 5.20 1.08 20.82 -0.815
21.15 5.239 5.24 1.12 20.35 -0.803
21.3 5.276 5.28 1.16 20.51 -0.792
26 6.440 6.44 2.29 25.07 -0.93
CHAPTER 3. SIGNAL CONDITIONING 10

(a) (b)

(c)

Figure 3.3: Voltage transducer measurement results. (a) Mid-sized load input voltage and
analogue DC voltage. (b) No load input voltage and analogue DC . (c) AC measurement.

Table 3.2: Voltage Transducer measurement results.

Measurement–Load R Measured input Analogue Output Deduced input Difference

Ω Vpeak V DC Vpeak mV
No Load Open 31.2 4.41 33.62 2420
Full Load 100 29.6 4.41 33.62 4020
Mid Range 1000 31.2 4.41 33.62 2420

3.2 Current transducer

3.2.1 Design
The idea is to measure current though the load by measuring the current through the
30mΩ current sense resistor. This is achieved by measuring the voltage across the current
sense resistor and then amplify this signal to prepare for conversion to analogue voltage
ranging from 0 V to 5 V. Since the detected signal is very small two amplification stages
are necessary. The first stage deploys the differential operational amplifier configuration
with the sense resistor on the low side. The output of this stage is basically in the order
ofmV but no greater than 1V. The second amplification stage ensures that the maximum
analogue output (which occurs when Imeasured is 285mA and VCurrentSense = 8.55mV) is
around 4V. This means that the required gain is 467.84. Designing for 101 gain (Av1 ) in
the first non-inverting amplification stage and setting R3 = 2.7 kΩ,R4 = (Av1 − 1)R3 =
100R3 = 270kΩ. The second stage amplification gain Av2 must be 4.62 to obtain the
required total gain. Setting R6 = 39 kΩ means that R5 = Av2 R6
−1
= 10.77 kΩ. To account
CHAPTER 3. SIGNAL CONDITIONING 11

for tolerances in practical resistors a 22 kΩ potentiometer will be used to obtain desired

output voltage. The final stage employs an active peak detector to obtain the analogue DC
output. The configuration used is exactly the same as the one used in voltage transducer.
Vanalogue
Ipeak = = 0.071225 × Vanalogue [mA]
468 × 30 × 10−3
∴ δIpeak = 0.071225δVanalogue
If the accuracy of the current transducer must be within 1mV then the ADC noise must
1×10−3
be less than 0.071225 = 14mV and as long as the peak to peak noise levels are less than 10
mV (5mV resolution) then the design requirements are met.

Figure 3.4: Current transducer circuit diagram.

3.2.2 Simulation
Figures 3.5b and 3.5a show simulation results for mid-sized load current and no load
current. theoretically, the current at no load is expected to be zero and so is the DC
analogue output. Due to inherent DC offset of operational amplifiers there is still DC
output even though the input voltage is zero [6]. This is apparent in Fig 3.5b.

(a) (b)

Figure 3.5: Current transducer simulated results. (a) No load simulated. (b) Mid-load
simulated.
CHAPTER 3. SIGNAL CONDITIONING 12

3.2.3 Measurement
Figure 3.6a show the amplified current signal of a mid-sized load and its DC analogue
representation. The no load DC analogue level is shown in Figure 3.6b. Note that when
the current signal is zero there is still an appreciable DC offset. This can be attributed to
non ideal effects (DC offset at zero input) of operational amplifiers. Figure 3.3c shows a
rippled DC analogue signal. It is apparent that the noise levels cannot the accuracy of the
readings because they are very smaller than the limiting conditions discussed in section
3.2.1. Current transducer unit test results are shown in Table 3.3 while Measurement
results are tabulated in table 3.4.

(a) (b)

(c)

Figure 3.6: Current transducer measured results. (a) Mid-load measured. (b) No-load
measured. (c) AC measured.

Table 3.3: Current Transducer Unit Test Results.

Emulated Level–Signal Generator Signal generator Analogue Output Deduced input Difference
mA mV mV V DC mA mA
0 0 0 0.235 18.431 18.431
50 1.5 1.556 0.802 62.902 12.902
100 3 2.97 1.42 111.373 11.373
101 3.03 3.11 1.43 112.157 11.157
102 3.06 3.253 1.45 113.725 11.725
200 6.00 6.081 2.66 208.627 8.627
285 8.55 8.627 3.73 292.549 7.549
CHAPTER 3. SIGNAL CONDITIONING 13

Table 3.4: Current Transducer measurement results.

Measurement–Load R Load R2 Measured VR Actual Input Analogue Output Deduced input Difference
Ω Ω mVpeak mApeak V DC mApeak mA
No Load Open - - -
Full Load 100 - 9.53 317.67 4.32 335.47 17.8
Mid Range 1k - 0.454 15.13 0.205 15.91 0.787
Mid + δ 1k 24k 0.4595 15.65 0.232 18.01 2.366
Mid + 2δ 1k 12k 0.4653 15.51 0.248 19.25 3.75

3.3 Phase-shift transducer

3.3.1 Design

Figure 3.7: Phase transducer circuit diagram.

The design requirements state that the voltage transducer must measure the phase
angle from 0° to 45° with analogue output within the range of 0VDC and a 5VDC. To
achieve this both the amplified current signal and scaled down voltage signal must be
passed through the high pass filters to eliminate the DC offset that may be present. Then
the signals must be fed to comparators to convert them to digital signals. The outputs
of digital signals are fed to the CD4077B XOR gate to obtain the phase difference of the
two signals. The PWM output of an XOR gate is passed through a low pass filter to
filter out high frequency components of the signal. The DC obtained is generally small
and therefore needs to be amplified to meet certain design requirements. The gain Av
is determined by the ratio of maximum DC obtained when phase difference is 45° and
4VDC.
The respective components of a high pass filters are calculated as follows [6]. Setting
R1 = R2 = R = 10 kΩ and high cut off frequency of 16Hz all lower frequency components
of the signal will be filtered out.
1
fHC =
2π × RCf

1
∴ Cf = = 0.995µF
2π × RfHC
CHAPTER 3. SIGNAL CONDITIONING 14

1 µF Will be used for this purpose. The low pass filter is required at the output of
an XOR gate to convert the variable PWM signal into DC. To filter all high frequency
components of the signal the cut-off frequency must be designed to be close to zero as
possible. Selecting R3 = 100 kΩ and design low cut-off frequency of 0.02 Hz.
1
Cc = = 79.6µF
2π × R3 fLC
A standard 100 µF will work just fine. The maximum DC component of the PWM
occurs when the phase difference is 45°. The theoretical RMS value should be 180 45
×
5 = 1.25VDC and therefore needs to be amplified to meet the 5V analogue limit. The
maximum measured phase difference is designed to be represented by 4V and therefore
the gain Av = 1.254
= 3.2. Using a non-inverting operational amplifier configuration and
setting R4 = 27 kΩ, 3.2 = (1 + R 4
R3
) and R3 = 12.27 kΩ. A 22 kΩ potentiometer will be
used to get as close as possible to R3 and ensure that at maximum phase the DC analogue
output is 4V. The theoretical relationship between the analogue output and phase angle
is as follows:
5θ 27
Vanalogue = × (1 + ) = 0.0889θ.
180 12.27
Practical measurements reveal that there is an inherent phase difference in current and
voltage from the source and therefore further adjustments are necessary. A purely resistive
mid-load the pulse has a thickness of 240µS which is equivalent to 0.24×180
10
= 4.32° and
the relationship is as follows.

θ = 10.582Vanalogue − 4.32°

∴ δθ = 10.582δVanalogue
This means that the noise level of the phase transducer analogue output must be less
than 10.582
1
= 94.5mV for change in 1°.

3.3.2 Simulation
Figures 3.8a and 3.8b show simulation results at no load and mid-sized capacitive load.
Figure 3.8b clearly shows the inputs of an XOR gate as well the DC analogue represen-
tation of phase.

(a)
(b)

Figure 3.8: Phase-shift transducer results. (a) Resistive load simulated. (b) Mid-sized
capacitive load simulated. Inputs and outputs of an XOR gate shown.
CHAPTER 3. SIGNAL CONDITIONING 15

3.3.3 Measurement
Measurement results are shown in table 3.5. It can be seen that the difference is too big
due to the fact that the signals are out of phase by a huge margin at no load condition.
Figure 3.9a shows a DC analogue and the output of an XOR gate when a purely resistive
mid-sized load is connected. It is apparent that the voltage across the load is sightly out
of phase with the load current. This is because the power from ESKOM is not purely
real. Figure 3.9b show the output of an XOR gate and DC analogue when a capacitive
load (1kΩ + 3.3 µF) is connected. The noise levels are shown in figure 3.9c.

(a) (b)

(c)

Figure 3.9: Phase-shift transducer results. (a) Resistive load measured. (b) 1k + 3.3µF
load measured. (c) Analogue signal noise measured.

Table 3.5: Phase Shift Results.

Measurement–Load R Load C Measured shift Applied shift Output level Conversion Difference
Ω µF ms [°] V DC [°] [°]
No Load 1k none 1 0 2.4 18 18
Full Load 1k 3.3 3.04 43.97 5.15 54.72 10.75
Mid Range 1k 22 1.56 8.23 3.55 28.08 19.85
Mid + δ 1k 33 1.36 5.51 3.09 24.48 18.97
Mid + 2δ 1k 47 1.4 3.87 2.88 25.2 21.33
CHAPTER 3. SIGNAL CONDITIONING 16

3.4 Summary and implementation

The performance of all transducers is remarkable. The noise levels are lower than ex-
pected. The voltage transducer can detect the peaks of load voltage and out an analogue
signal with relative ease. The current transducer does the amplification of minute cur-
rent signals across the current sense resistor quite well and output an analogue signal
proportion to the amplitude of current through the load. The phase transducer operates
exceptionally as the other two transducers. In general the signal conditioning circuitry
performs as expected. Figure 3.10a show the voltage and current transducer circuitry
while Figure 3.10b show the implementation of phase shift transducer.

(a)
(b)

Figure 3.10: Implementation of the transducers circuitry. (a) Voltage load and current
transducers implementation. (b) Phase shift transducer implementation.
Chapter 4

Over-current protection

Over-current protection is employed in many applications ranging from high voltage elec-
trical power systems to micro-electronics.It is generally used to protect appliances from
short circuit and ground faults. Over-current is undesirable because large currents cause
heating even at low voltages and thereby causing damage to valuable appliances. Of
course in this project the load is assumed to a resistor or series combination of a resistor
and capacitor but it could be any appliance. Therefore over-current protection is imper-
ative. In this project a simple trip circuit is used to electrically isolate the load from the
source voltage when the load current exceeds the reference current (200 mA RMS) [7].
The trip circuit also entails the trip override functionality which connects the load back
to the source.

4.1 Design

Figure 4.1: Over-Current Protection circuit diagram

We want a circuit that can allow certain currents through the load and disconnects
the load when current exceeds a certain predetermined value of which in this case is 200
mA RMS. A simple way of implementing this functionality is through the use of an SR
latch in conjunction with the MOC3020 triac. In Figure 4.1 the SR latch circuit [8] is

17
CHAPTER 4. OVER-CURRENT PROTECTION 18

represented by two identical simple BJT circuits. When the RESET node is high while
SET is low, that is when it is pulled up to 5VDC the node Q is pulled to ground through
the transistor Q1. When node Q is low the transistor Q2 cuts off thereby pulling Q high.
When Q the transistor Q3 is on and therefore the MOC3020 triac is on and the current
flows through the load. The converse is true when the SET node is pulled high. The SET
and RESET nodes need not be high for significant amounts of time and a short period
single pulse could suffice.
For two identical SET and RESET BJT circuits current is insignificant but voltage levels
are of utmost importance. Current limiting resistors R1 and R4 are selected as 1kΩ.
Resistors R3 and R7 sink current when either Q or Q is high therefore selecting 100kΩ
will limit current at:
5
I= = 45µA
10 + 100 + 1
. This current is obviously drawn from 5VDC rail and is very small. Since the MOC3020
optocoupler is used the recommended connection diagram is given in the manufacturer’s
datasheet along with the value of the resistor R9 = 10 kΩ. The value of the resistor R1 2
is not given but can be determined from design considerations. From the datasheet [give
reference]it is specified that the input trigger current for MOC3020 optoisolator should
range between 15 m to 30 mA [9]. Assuming transistor Q3 is in saturation VCE(sat) = 0.2
V and assuming Vdiode = 1.2 V. The design input trigger current is 16 mA and therefore
the resistance R12 can be calculated as follows:
5 − 1.2 − 0.2
R12 = = 225Ω
16 × 10−3
The 220 Ω standard will work just fine and it will allow a slightly larger current. The
SET 5V pulse essentially comes from the trigger comparator circuit shown in Figure
4.2. The output is normally low and only goes high when the DC analogue output goes
beyond the reference voltage of 4VDC. This occurs when current is greater than 200mA
RMS. Resistors R11 and R12 are selected such that the reference voltage VREF _+4VDC and
high enough to sink minute current from the +5VDC rail. Neglecting the non-inverting
terminal current the current sourced for the positive rail is I = 82+22
5
= 48 µA which is
negligibly small. A 100kΩ potentiometer is used in place of the 82 kΩ fixed resistor to
get as close as possible to 4VDC reference voltage.

Figure 4.2: Comparator circuit diagram for over-current protection

CHAPTER 4. OVER-CURRENT PROTECTION 19

4.2 Simulation
The SET pulse is basically the output of the comparator circuit shown in Figure 4.2 and
can be considered as a pulse because it goes from low to high and instantaneously goes
low when electrical isolation occurs. In the simulation the SET single pulse goes high at
t = 150ms as shown in Figure 4.3a. At this instance the load is isolated from the voltage
source and therefore no current flow through the load. At time t = 300ms the RESET
pulse kicks in and activates the load to normal operation. Figure 4.3b shows the source
voltage while Figure 4.3c shows the load voltage.

(a)
(b)

(c)

Figure 4.3: Over-current protection simulation results. (a) Simulation of SET and RESET
single pulses. (b) Input voltage at terminal 6 of the optoisolator. (c) Voltage across the
load.

4.3 Measurements
Figure 4.4a show the measured SET pulse that is generated when the load trips. The
signal is normally low and momentarily goes high when Iload exceeds 200 mA. The reaction
time of the trip circuits is 26.8 ms as seen in Figure 4.4b.It meets design specifications
since the allowable reaction time should be less than 150 ms [7].
CHAPTER 4. OVER-CURRENT PROTECTION 20

(a) (b)

Figure 4.4: Reaction time of the trip circuit. (a) Set pulse measurement. (b) Measure
time for trip to occur.
Chapter 5

Reporting

5.1 Design
5.1.1 Arduino Code Flow diagram
Arduino code flow diagram is shown in Figure 5.1.

Figure 5.1: Arduino Code Flow diagram

5.1.2 Python Code psuedocode

-START
-Connect

21
CHAPTER 5. REPORTING 22

–>Check connection status

—>if connected and Reset button pressed
—->send ’R’ and print status and feedback.

5.1.3 Arduino Beetle Over-voltage protection

The Beetle over-voltage and under-voltage circuit diagram is shown in Figure 5.2.All
Arduino analogue pins have similar connections. The basic operation of this circuit is
as follows. When the voltage at the analogue pin exceeds the diode voltage Vdiode the
diode D1 turns on thereby connecting the pin to +5VDC. The same is true when the pin
voltage goes below ground by Vdiode . When this happens the analogue pin is pulled to
ground and thereby protecting the pin from negative voltages.

Figure 5.2: Over-voltage protection circuit diagram

5.2 Results

(a) (b)

Figure 5.3: Graphical User Interface results. (a) GUI display in debug mode with load
at normal operation. (b) GUI display showing normal load operation before tripping and
after tripping.
Chapter 6

Extra functionality

No extra functionalities.

23
Chapter 7

System and conclusion

7.1 System

Figure 7.1: Complete PCB.

7.2 Lessons learned

• Time management is the most important thing in design process.
• Having multiple design solutions helps in case of inevitable limitations such current
supply limitation.
• Start the design process as soon as possible.
• Always go for simple solutions that meet the design requirements.
• Don’t overthink the problem.

24
References

[1] DIODE: 1n4001-1n4007 1a rectifier. 2014.

Available at: https://www.diodes.com/assets/Datasheets/ds28002.pdf

[2] Texas-Instruments: Lm2595 simple switcher® power converter 150-khz 1-a step-down volt-
age regulator. 2016.
Available at: http://www.ti.com/lit/gpn/lm2595

[3] Jameco: Arduino micro. 2019.

Available at: https://www.jameco.com/Jameco/Products/ProdDS/2207700.pdf

[4] maker: Introduction to linear voltage regulators. 2019.

Available at: https://www.digikey.pl/en/maker/blogs/introduction-to-linear-voltage-regulators

[5] TEXAS-INSTRUMENTS: Tlc227x, tlc227xa: Advanced lincmos rail-to-rail operational

amplifiers. 2016.
Available at: https://learn.sun.ac.za/pluginfile.php/1690419/mod-resource/content/0/tlc2272.p

[6] Neamen, D.A.: Microelectronics, Circuit Analysis and Design by Donald A. Neamen, 4th
edition. Semiconductor Physics and Devices: Basic Principles. McGraw-Hill, 2010. ISBN
978–0–07–338064–3.

[7] mjbooysen: E344 assignment3. 2019.

Available at: https://learn.sun.ac.za/pluginfile.php/1724249/modresource/content/3/E344-Ass3.

[8] Hrishav: Flip-flop circuit (transistor-transistor sr latch circuit). 2019.

Available at: https://www.instructables.com/id/Flip-Flop-Circuit-Transistor-Transistor-SR-Lat

[9] Texas-Instruments: Moc3020 thru moc3023 optocouplers/optoisolators. 1995.

Available at: https://pdf1.alldatasheet.com/datasheet-pdf/view/27235/TI/MOC3020.html

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Appendix A: GitHub Activity Heatmap

26