IS31FL3235A

28 CHANNELS LED DRIVER

August 2020

GENERAL DESCRIPTION FEATURES

IS31FL3235A is comprised of 28 constant current  2.7V to 5.5V supply
channels each with independent PWM control,  I2C interface, automatic address increment
designed for driving LEDs, PWM frequency can be function
3kHz or 22kHz. The output current of each channel  Internal reset register
can be set at up to 38mA (Max.) by an external resistor
 Modulate LED brightness with 256 steps PWM
and independently scaled by a factor of 1, 1/2, 1/3 and
1/4. The average LED current of each channel can be  Each channel can be controlled independently
changed in 256 steps by changing the PWM duty cycle  Each channel can be scaled independently by 1,
through an I2C interface. 1/2, 1/3 and 1/4
 PWM frequency selectable
The chip can be turned off by pulling the SDB pin low or
by using the software shutdown feature to reduce - 3kHz (Default)
power consumption. - 22kHz
 -40°C to +85°C temperature range
IS31FL3235A is available in QFN-36 (4mm × 4mm)
 ESD HBM 8kV
package. It operates from 2.7V to 5.5V over the
temperature range of -40°C to +85°C.  QFN-36 (4mm × 4mm) package
APPLICATIONS
 Mobile phones and other hand-held devices for
LED display
 LED in home appliances

TYPICAL APPLICATION CIRCUIT

Figure 1 Typical Application Circuit

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*Note 1
*Note 3 *Note 1
5V
31 33
5V
VCC 36
30 OUT1
1 F AD 91
0.1 F 1
OUT2
*Note 2
2 33
VIH OUT3

4.7k 4.7k

34
SDA
35
Micro
Controller
SCL IS31FL3235A
29
SDB
100k

26 33
OUT26
33 91
R_EXT 27
REXT OUT27
3.3k 14 28 33
GND OUT28
32

Figure 2 Typical Application Circuit (VCC=5V)

Note 1: VLED+ should be same as VCC voltage.

Note 2: VIH is the high level voltage for IS31FL3235A, which is usually same as VCC of Micro Controller, e.g. if VCC of Micro Controller is 3.3V,
VIH=3.3V. If VCC=5V and VIH is lower than 2.8V, recommend to add a level shift circuit.
Note 3: These resistors are optional to help reduce the power of IS31FL3235A only (values are for VLED+=5V).
Note 4: The maximum global output current is set up to 23mA when REXT = 3.3kΩ. The maximum global output current can be set by external
resistor, REXT. Please refer to the detail information in Page 11.
Note 5: The IC should be placed far away from the mobile antenna in order to prevent the EMI.

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PIN CONFIGURATION
Package Pin Configuration (Top View)

QFN-36

PIN DESCRIPTION
No. Pin Description
1 ~ 13 OUT2 ~ OUT14 Output channel 2~14 for LEDs.
14, 32 GND Ground.
15 ~ 28 OUT15 ~ OUT28 Output channel 15~28 for LEDs.
29 SDB Shutdown the chip when pulled low.
30 AD I2C address setting.
31 VCC Power supply.
Input terminal used to connect an external resistor.
33 R_EXT
This regulates the global output current.
34 SDA I2C serial data.
35 SCL I2C serial clock.
36 OUT1 Output channel 1 for LEDs.
Thermal Pad Connect to GND.

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ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Order Part No. Package QTY/Reel

IS31FL3235A-QFLS2-TR QFN-36, Lead-free 2500

Copyright © 2020 Lumissil Microsystems. All rights reserved. Lumissil Microsystems reserves the right to make changes to this specification and its
products at any time without notice. Lumissil Microsystems assumes no liability arising out of the application or use of any information, products or
services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and
before placing orders for products.
Lumissil Microsystems does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in
such applications unless Lumissil Microsystems receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Lumissil Microsystems is adequately protected under the circumstances

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ABSOLUTE MAXIMUM RATINGS
Supply voltage, VCC -0.3V ~ +6.0V
Voltage at SCL, SDA, SDB, OUT1 to OUT28 -0.3V ~ VCC+0.3V
Maximum junction temperature, TJMAX +150°C
Storage temperature range, TSTG -65°C ~ +150°C
Operating temperature range, TA=TJ -40°C ~ +85°C
Package thermal resistance, junction to ambient (4 layer standard test
53°C/W
PCB based on JESD 51-2A), θJA
ESD (HBM) ±8kV
ESD (CDM) ±1kV
Note 6: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
Typical values are TA = 25°C, VCC = 3.6V.
Symbol Parameter Condition Min. Typ. Max. Unit
VCC Supply voltage 2.7 5.5 V
VCC= 4.2V, VOUT= 0.8V
IMAX Maximum global output current 38 mA
REXT= 2kΩ, SL= “00” (Note 7)
VOUT= 0.6V
IOUT Output current 23 mA
REXT= 3.3kΩ, SL= “00”
ICC Quiescent power supply current REXT= 3.3kΩ 9 mA
VSDB= 0V or software shutdown
ISD Shutdown current 3 5 μA
TA= 25°C, VCC= 3.6V
0x4B= 0x00 2.9 kHz
fOUT PWM frequency of output
0x4B= 0x01 21.6 kHz
VSDB= 0V or software shutdown,
IOZ Output leakage current 0.2 μA
VOUT= 5.5V

TSD Thermal shutdown (Note 8) 160 °C

TSD_HYS Thermal shutdown hysteresis (Note 8) 20 °C

VEXT Output voltage of R_EXT pin 1.3 V

Logic Electrical Characteristics (SDA, SCL, SDB)

VIL Logic “0” input voltage VCC= 2.7V~5.5V 0.4 V
VIH Logic “1” input voltage VCC= 2.7V~5.5V 1.4 V

IIL Logic “0” input current VINPUT= 0V (Note 8) 5 nA

IIH Logic “1” input current VINPUT= VCC (Note 8) 5 nA

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DIGITAL INPUT SWITCHING CHARACTERISTICS (NOTE 8)
Symbol Parameter Condition Min. Typ. Max. Unit

fSCL Serial-Clock frequency 400 kHz

Bus free time between a STOP and a START
tBUF 1.3 μs
condition
tHD, STA Hold time (repeated) START condition 0.6 μs
tSU, STA Repeated START condition setup time 0.6 μs
tSU, STO STOP condition setup time 0.6 μs
tHD, DAT Data hold time 0.9 μs
tSU, DAT Data setup time 100 ns
tLOW SCL clock low period 1.3 μs
tHIGH SCL clock high period 0.7 μs
Rise time of both SDA and SCL signals,
tR (Note 9) 20+0.1Cb 300 ns
receiving
Fall time of both SDA and SCL signals,
tF (Note 9) 20+0.1Cb 300 ns
receiving
Note 7: The recommended minimum value of REXT is 2kΩ, or it may cause a large current.
Note 8: Guaranteed by design.
Note 9: Cb= total capacitance of one bus line in pF. ISINK ≤ 6mA. TR and tF measured between 0.3×VCC and 0.7×VCC.

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DETAILED DESCRIPTION

I2C INTERFACE The 8-bit chip address is sent next, most significant bit
first. Each address bit must be stable while the SCL
The IS31FL3235A uses a serial bus, which conforms to
level is high.
the I2C protocol, to control the chip’s functions with two
wires: SCL and SDA. The IS31FL3235A has a 7-bit After the last bit of the chip address is sent, the master
slave address (A7:A1), followed by the R/W bit, A0. checks for the IS31FL3235A’s acknowledge. The
Since IS31FL3235A only supports write operations, A0 master releases the SDA line high (through a pull-up
must always be “0”. The value of bits A1 and A2 are resistor). Then the master sends an SCL pulse. If the
decided by the connection of the AD pin. IS31FL3235A has received the address correctly, then
it holds the SDA line low during the SCL pulse. If the
The complete slave address is:
SDA line is not low, then the master should send a
Table 1 Slave Address (Write only): “STOP” signal (discussed later) and abort the transfer.
Bit A7:A3 A2:A1 A0 Following acknowledge of IS31FL3235A, the register
address byte is sent, most significant bit first.
Value 01111 AD 0 IS31FL3235A must generate another acknowledge
AD connected to GND, AD = 00; indicating that the register address has been received.
AD connected to VCC, AD = 11; Then 8-bit of data byte are sent next, most significant
AD connected to SCL, AD = 01; bit first. Each data bit should be valid while the SCL
AD connected to SDA, AD = 10; level is stable high. After the data byte is sent, the
IS31FL3235A must generate another acknowledge to
The SCL line is uni-directional. The SDA line is
indicate that the data was received.
bi-directional (open-collector) with a pull-up resistor
(typically 4.7kΩ). The maximum clock frequency The “STOP” signal ends the transfer. To signal “STOP”,
specified by the I2C standard is 400kHz. In this the SDA signal goes high while the SCL signal is high.
discussion, the master is the microcontroller and the
ADDRESS AUTO INCREMENT
slave is the IS31FL3235A.
To write multiple bytes of data into IS31FL3235A, load
The timing diagram for the I2C is shown in Figure 3.
the address of the data register that the first data byte
The SDA is latched in on the stable high level of the
is intended for. During the IS31FL3235A acknowledge
SCL. When there is no interface activity, the SDA line
of receiving the data byte, the internal address pointer
should be held high.
will increment by one. The next data byte sent to
The “START” signal is generated by lowering the SDA IS31FL3235A will be placed in the new address, and
signal while the SCL signal is high. The start signal will so on. The auto increment of the address will continue
alert all devices attached to the I2C bus to check the as long as data continues to be written to IS31FL3235A
incoming address against their own chip address. (Figure 6).

Figure 3 Interface Timing

Figure 4 Bit Transfer

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Figure 5 Writing to IS31FL3235A (Typical)

Figure 6 Writing to IS31FL3235A (Automatic Address Increment)

REGISTERS DEFINITIONS
Table 2 Register Function
Address Name Function Table Default
00h Shutdown Register Set software shutdown mode 3
0000 0000
05h~20h PWM Register 28 channels PWM duty cycle data register 4
Load PWM Register and LED Control Register’s
25h PWM Update Register - xxxx xxxx
data
2Ah~45h LED Control Register Channel 1 to 28 enable bit and current setting 5
0000 0000
4Ah Global Control Register Set all channels enable 6
Output Frequency
4Bh Set all channels operating frequency 7 0000 0000
Setting Register
4Fh Reset Register Reset all registers into default value - xxxx xxxx

Table 3 00h Shutdown Register Table 4 05h~20h PWM Register (OUT1~OUT28)

Bit D7:D1 D0 Bit D7:D0
Name - SSD Name PWM
Default 0000 000 0 Default 0000 0000
The Shutdown Register sets software shutdown mode The PWM Registers adjusts LED luminous intensity in
of IS31FL3235A. 256 steps.
The value of a channel’s PWM Register decides the
SSD Software Shutdown Enable average output current for each output, OUT1~OUT28.
0 Software shutdown mode The average output current may be computed using
the Formula (1):
1 Normal operation
I OUT 7
I PWM    D[n]  2 n (1)
256 n0
Where “n” indicates the bit location in the respective
PWM register.

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For example: D7:D0 = 10110101, Table 6 4Ah Global Control Register
IOUT = IMAX (20+22+24+25+27)/256 Bit D7:D1 D0
The IOUT of each channel is setting by the SL bit of LED
Control Register (2Ah~45h). Please refer to the detail Name - G_EN
information in Page 11. Default 0000 000 0
The Global Control Register set all channels enable.
25h PWM Update Register
The data sent to the PWM Registers and the LED
Control Registers will be stored in temporary registers. G_EN Global LED Enable
A write operation of “0000 0000” value to the Update 0 Normal operation
Register is required to update the registers (05h~20h, 1 Shutdown all LEDs
2Ah~45h).
Table 7 4Bh Output Frequency Setting Register
Table 5 2Ah~45h LED Control Register
(OUT1~OUT28) Bit D7:D1 D0

Bit D7:D3 D2:D1 D0 Name - OFS

Default 0000 000 0
Name - SL OUT
Default 0000 0 00 0 The Output Frequency Setting Register selects a fixed
PWM operating frequency for all output channels.
The LED Control Registers store the on or off state of
each LED and set the output current.
OFS Output Frequency Setting
0 3kHz
SL Output Current Setting (IOUT)
1 22kHz
00 IMAX
01 IMAX/2
4Fh Reset Register
10 IMAX/3
Once user writes “0000 0000” data to the Reset
11 IMAX/4 Register, IS31FL3235A will reset all registers to default
value. On initial power-up, the IS31FL3235A registers
OUT LED State are reset to their default values for a blank display.
0 LED off
1 LED on

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IS31FL3235A
FUNCTIONAL BLOCK DIAGRAM

VCC
Scaling Data

SDA PWM&EN
I2C Registers EN Data &Scaling
SCL Logic
Interface
AD Current
PWM Data R_EXT
CMP Control

OSC Counter

Bias Output OUT1~OUT28

SD_Chip
SDB

GND

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TYPICAL APPLICATION INFORMATION

PWM CONTROL Table 8 32 Gamma Steps With 256 PWM Steps

The PWM Registers (05h~2Ah) can modulate LED C(0) C(1) C(2) C(3) C(4) C(5) C(6) C(7)
brightness of 28 channels with 256 steps. For example, 0 1 2 4 6 10 13 18
if the data in PWM Register is “0000 0100”, then the C(8) C(9) C(10) C(11) C(12) C(13) C(14) C(15)
PWM is the fourth step. 22 28 33 39 46 53 61 69
Writing new data continuously to the registers can C(16) C(17) C(18) C(19) C(20) C(21) C(22) C(23)
modulate the brightness of the LEDs to achieve a 78 86 96 106 116 126 138 149
breathing effect.
C(24) C(25) C(26) C(27) C(28) C(29) C(30) C(31)
REXT 161 173 186 199 212 226 240 255
The maximum output current of OUT1~OUT28 can be 256
adjusted by the external resistor, REXT, as described in
224
Formula (2).
192
V
I MAX  x  EXT (2)

PWM Data
160
REXT 128

x = 58.5, VOUT = 0.8V, VEXT = 1.3V. 96

The recommended minimum value of REXT is 2kΩ. 64

CURRENT SETTING 32

The current of each LED can be set independently by 0

0 4 8 12 16 20 24 28 32
the SL bit of LED Control Register (2Ah~45h). The
Intensity Steps
maximum global current is set by the external register
REXT. Figure 7 Gamma Correction (32 Steps)

When channels drive different quantity of LEDs, adjust Choosing more gamma steps provides for a more
maximum output current according to quantity of LEDs continuous looking breathing effect. This is useful for
to ensure average current of each LED is the same. very long breathing cycles. The recommended
configuration is defined by the breath cycle T. When
For example, set REXT= 3.3kΩ then IMAX= 23mA. If T=1s, choose 32 gamma steps, when T=2s, choose
OUT1 drives two LEDs and OUT2 drives four LEDs, set 64 gamma steps. The user must decide the final
the SL bit of LED Control Register (2Ah) to “01” and SL number of gamma steps not only by the LED itself, but
bit of LED Control Register (2Bh) to “00”. So the current also based on the visual performance of the finished
of OUT1 is IOUT1= IMAX/2= 11.5mA and the current of product.
OUT2 is IOUT2= IMAX= 23mA. The average current of
Table 9 64 Gamma Steps With 256 PWM Steps
each LED is the same.
C(0) C(1) C(2) C(3) C(4) C(5) C(6) C(7)
GAMMA CORRECTION
0 1 2 3 4 5 6 7
In order to perform a better visual LED breathing effect C(8) C(9) C(10) C(11) C(12) C(13) C(14) C(15)
we recommend using a gamma corrected PWM value 8 10 12 14 16 18 20 22
to set the LED intensity. This results in a reduced
number of steps for the LED intensity setting, but C(16) C(17) C(18) C(19) C(20) C(21) C(22) C(23)
causes the change in intensity to appear more linear to 24 26 29 32 35 38 41 44
the human eye. C(24) C(25) C(26) C(27) C(28) C(29) C(30) C(31)
Gamma correction, also known as gamma 47 50 53 57 61 65 69 73
compression or encoding, is used to encode linear C(32) C(33) C(34) C(35) C(36) C(37) C(38) C(39)
luminance to match the non-linear characteristics of 77 81 85 89 94 99 104 109
display. Since the IS31FL3235A can modulate the
C(40) C(41) C(42) C(43) C(44) C(45) C(46) C(47)
brightness of the LEDs with 256 steps, a gamma
correction function can be applied when computing 114 119 124 129 134 140 146 152
each subsequent LED intensity setting such that the C(48) C(49) C(50) C(51) C(52) C(53) C(54) C(55)
changes in brightness matches the human eye’s 158 164 170 176 182 188 195 202
brightness curve.
C(56) C(57) C(58) C(59) C(60) C(61) C(62) C(63)
209 216 223 230 237 244 251 255

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256
generate an AC ripple on the power supply which
224 cause stress to the decoupling capacitors.
192 When the AC ripple is applied to a monolithic ceramic
capacitor chip (MLCC) it will expand and contract
PWM Data

160
causing the PCB to flex and generate audible hum in
128 the range of between 20Hz to 20kHz, To avoid this
96
hum, there are many countermeasures, such as
selecting the capacitor type and value which will not
64 cause the PCB to flex and contract.
32 An additional option for avoiding audible hum is to set
0
the IS31FL3235A’s output PWM frequency above the
0 8 16 24 32 40 48 56 64 audible range. The Output Frequency Setting Register
Intensity Steps 4Bh bit D0 can be used to set the switching frequency
Figure 8 Gamma Correction (64 Steps)
to 22kHz, which is beyond the audible range. Figure 9
below shows the variation of output PWM frequency
Note, the data of 32 gamma steps is the standard value and the data across supply voltage and temperature.
of 64 gamma steps is the recommended value.
30
SHUTDOWN MODE

Output PWM Frequency (kHz)

25
Shutdown mode can be used as a means of reducing 85°C
power consumption. During shutdown mode all
registers retain their data. 20
25°C
Software Shutdown
15
By setting SSD bit of the Shutdown Register (00h) to “0”, -40°C
the IS31FL3235A will operate in software shutdown
10
mode. When the IS31FL3235A is in software shutdown
mode, all current sources are switched off.
5
Hardware Shutdown
The chip enters hardware shutdown mode when the 0
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SDB pin is pulled low.
VCC (V)
PWM FREQUENCY SELECT
Figure 9 VCC vs. Output PWM Frequency
The IS31FL3235A output channels operate with a
default PWM frequency of 3kHz. Because all the OUTx
channels are synchronized, the DC supply will
experience large instantaneous current surges when
the OUTx channels turn ON. These current surges will

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CLASSIFICATION REFLOW PROFILES
Profile Feature Pb-Free Assembly

Preheat & Soak

150°C
Temperature min (Tsmin)
200°C
Temperature max (Tsmax)
60-120 seconds
Time (Tsmin to Tsmax) (ts)

Average ramp-up rate (Tsmax to Tp) 3°C/second max.

Liquidous temperature (TL) 217°C
Time at liquidous (tL) 60-150 seconds
Peak package body temperature (Tp)* Max 260°C
Time (tp)** within 5°C of the specified
Max 30 seconds
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax) 6°C/second max.
Time 25°C to peak temperature 8 minutes max.

Figure 10 Classification Profile

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PACKAGE INFORMATION

QFN-36

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IS31FL3235A
RECOMMENDED LAND PATTERN

QFN-36

Note:
1. Land pattern complies to IPC-7351.
2. All dimensions in MM.
3. This document (including dimensions, notes & specs) is a recommendation based on typical circuit board manufacturing parameters. Since
land pattern design depends on many factors unknown (eg. User’s board manufacturing specs), user must determine suitability for use.

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REVISION HISTORY
Revision Detail Information Date
A Initial release 2016.12.22
B Correct wrong package information 2017.01.22
C Update land pattern 2017.06.16
D Update functional block’s pin name 2017.12.12
1. Update θJA value
E 2. Revise VIL, VIH test condition to VCC = 2.7V~5.5V 2018.08.03
3. Update Figure 1 and add Figure 2 for RGB application
F Update logo to LUMISSIL 2019.09.20
G Update to new Lumissil logo 2019.12.26
H Update land pattern 2020.08.20

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