Circuits and Elektroniks

6.
002
CIRCUITS AND
ELECTRONICS
Introduction and Lumped Circuit Abstraction
6.002 Fall 2000 Lecture
1
1
ADMINISTRIVIA
Lecturer: Prof. Anant Agarwal
Textbook: Agarwal and Lang (A&L)
Readings are important!
Handout no. 3
Assignments
Homework exercises
Labs
Quizzes
Final exam
1
2
Two homework assignments can
be missed (except HW11).
Collaboration policy
Homework
You may collaborate with
others, but do your own
write-up.
Lab
You may work in a team of
two, but do you own write-up.
Info handout
Reading for today
Chapter 1 of the book
1
3
What is engineering?
Purposeful use of science
What is 6.002 about?
Gainful employment of
Maxwells equations
From electrons to digital gates
and op-amps
1
4
6
.
0
0
2
Simple amplifier abstraction

Instruction set abstraction
Pentium, MIPS
Software systems
Operating systems, Browsers
Filters
Operational
amplifier abstraction
abstraction
-
+
Digital abstraction
Programming languages
Java, C++, Matlab 6.001
Combinational logic
f
Lumped circuit abstraction
R S
+
Nature as observed in experiments
0.4 0.3 0.2 0.1 I
12 9 6 3 V
Physics laws or abstractions
Maxwells
Ohms
V = R I
abstraction for
tables of data
Clocked digital abstraction
Analog system
components:
Modulators,
oscillators,
RF amps,
power supplies 6.061
Mice, toasters, sonar, stereos, doom, space shuttle
6.170
6.455
6.004
6.033
M L C V
1
5
Lumped Circuit Abstraction
Consider
I
The Big Jump
from physics
to EECS
+
-
V
?
Suppose we wish to answer this question:
What is the current through the bulb?
1
6
We could do it the Hard Way
Apply Maxwells
Differential form Integral form
Faradays
E =
B

E dl =
B
t
t
Continuity J =

t

J dS =

q
t
Others
E =

E dS =
q
0

1
7
Instead, there is an Easy Way
First, let us build some insight:
Analogy
F
a ?
I ask you: What is the acceleration?
You quickly ask me: What is the mass?
I tell you: m
F
You respond:
a =
m
Done ! ! !
1
8
Instead, there is an Easy Way
First, let us build some insight:
F
a ?
Analogy
In doing so, you ignored
the objects shape
its temperature
its color
point of force application
Point-mass discretization
1
9
The Easy Way
Consider the filament of the light bulb.
A
B
We do not care about
how current flows inside the filament
its temperature, shape, orientation, etc.
Then, we can replace the bulb with a
discrete resistor
for the purpose of calculating the current.
1
10
The Easy Way
A
B
Replace the bulb with a
discrete resistor
for the purpose of calculating the current.
+

V
A
I
R
and I =
V
R
B
In EE, we do things
the easy way
R represents the only property of interest!
Like with point-mass: replace objects
F
with their mass m to find
a =
m
1
11
The Easy Way
+

V
A
I
R
and I =
V
R
B
In EE, we do things
the easy way
R represents the only property of interest!
R relates element v and i
V
I =
R
called element v-i relationship
1
12
R is a lumped element abstraction
for the bulb.
1
13
R is a lumped element abstraction
for the bulb.
Not so fast, though
A
B
A
S
B
S
I
+

V
black box
Although we will take the easy way
using lumped abstractions for the rest
of this course, we must make sure (at
least the first time) that our
abstraction is reasonable. In this case,
ensuring that
V I
are defined
for the element
1
14
A
V I
must be defined
B
A
S
B
S
I
+

V
for the element
black box
1
15
l
I
must be defined. True when
I
into S
A
= I out of
S
B
True only when
q
= 0 in the filament!
t

J dS
S
A

J dS
S
B

J dS

J dS =
q
S
A
S
B
t
I
A
I
B
I
A
= I
B
only if
0 =

t
q
So lets assume this
1
16
f
r
o
m
M
a
x
w
e
l

V
Must also be defined.
s
e
e
A
&
L

So lets assume this too
V
AB
So
V
AB
=
AB
E dl
defined when
0 =
t
B
outside elements
1
17
Lumped Matter Discipline (LMD)
0 =

t
B

outside
0 =

t
q
inside elements
bulb, wire, battery
Or self imposed constraints:
More in
Chapter 1
of A & L
Lumped circuit abstraction applies when
elements adhere to the lumped matter
discipline.
1
18
Demo
Lumped element examples
whose
captured by their VI
relationship.
only for the
sorts of
questions we
as EEs would
like to ask!
is completely behavior
Demo
Exploding resistor demo
cant predict that!
Pickle demo
cant predict light, smell
1
19
So, what does this buy us?
Replace the differential equations
with simple algebra using lumped
circuit abstraction (LCA).
For example
a
+

1
R
2
R
3
R
b
d
R
4
V
R
5
c
What can we say about voltages in a loop
under the lumped matter discipline?
1
20
What can we say about voltages in a loop
under LMD?
+

1
R
2
R
3
R
a
b
d
R
4
V
R
5
c

E dl =
t
B
under DMD
0

E dl +

E dl +

E dl = 0
ca ab bc
+ V
ca
+ V
ab
+ V
bc
=
0
Kirchhoffs Voltage Law (KVL):
The sum of the voltages in a loop is 0.
1
21
What can we say about currents?
Consider
S
I
ca
I
da
ba
I
a
1
22
What can we say about currents?
ca da
ba
I
a
I
S
I
S
J dS =
t
q

under LMD
0

I
ca
+ I
da
+ I
ba
= 0
Kirchhoffs Current Law (KCL):
The sum of the currents into a node is 0.
simply conservation of charge
1
23
KVL and KCL Summary
KVL:

j

j
= 0
loop
KCL:

j
i
j
= 0
node
1
24
1
2
6.002
CIRCUITS AND
ELECTRONICS
Basic Circuit Analysis Method
(KVL and KCL method)
2
2
0 =
t
B
0 =
t
q
Outside elements
Inside elements
Allows us to create the lumped circuit
abstraction
wires
resistors
sources
Review
Lumped Matter Discipline LMD:
Constraints we impose on ourselves to simplify
our analysis
3
2
LMD allows us to create the
lumped circuit abstraction
Lumped circuit element
+
-
v
i
power consumed by element =
vi
Review
4
2
KVL:
loop
KCL:
node
0 =
j
j
0 =
j
j
i
Review
Review
Maxwells equations simplify to
algebraic KVL and KCL under LMD!
5
2
KVL
0 = + +
bc ab ca
v v v
0 = + +
ba da ca
i i i
KCL
DEMO
1
R
2
R
4
R
5
R
3
R
a
b
d
c
+
Review
6
2
Method 1:
Basic KVL, KCL method of
Circuit analysis
Goal: Find all element vs and is
write element v-i relationships
(from lumped circuit abstraction)
write KCL for all nodes
write KVL for all loops
1.
2.
3.
lots of unknowns
lots of equations
lots of fun
solve
7
2
Method 1:
Basic KVL, KCL method of
Circuit analysis
For R,
For voltage source,
For current source,
Element Relationships
IR V =
0
V V =
0
I I =
3 lumped circuit elements
R
0
V
o
I
+
J
8
2
KVL, KCL Example
The Demo Circuit
+
1
R
2
R
4
R
5
R
3
R
a
b
d
c
0 0
V =
+
+
2

9
2
Associated variables discipline
i
+
-
Element e
Then power consumed
by element e
i = is positive
Current is taken to be positive going
into the positive voltage terminal
10
2
KVL, KCL Example
The Demo Circuit
+
1
R
2
R
4
R
5
R
3
R
a
b
d
c
0 0
V =
+
+
1 L
2 L
4 L
3 L
2
2
i
1
i
0
i
5
i
3
i
4
i
11
2
Analyze
12 unknowns
5 0 5 0
,
1. Element relationships
3. KVL for loops
0 0
V v =
1 1 1
R i v =
2 2 2
R i v =
3 3 3
R i v =
4 4 4
R i v =
5 5 5
R i v =
given
2. KCL at the nodes
redundant
0
4 3 1
= + v v v
0
2 1 0
= + + v v v
0
2 5 3
= + v v v
0
5 4 0
= + + v v v redundant
0
4 1 0
= + + i i i
0
1 3 2
= + i i i
0
4 3 5
= i i i
0
5 2 0
= i i i
a:
b:
d:
e:
6 equations
3 independent
equations
3 independent
equations
1
2

u
n
k
n
o
w
n
s
1
2

e
q
u
a
t
i
o
n
s
/
u
g
h
@
#
!
( ) i v,
L1:
L2:
L3:
L4:
12
2
Other Analysis Methods
Method 2
Apply element combination rules
B
C
D
N
R R R + + +
2 1
1
G
2
G
N
G
N
G G G + +
2 1
i
i
R
G
1
=
+ + +
1
V
2
V
2 1
V V +
J J
1
I
2
I
2 1
I I +
J
A
1
R
2
R
3
R
N
R
Surprisingly, these rules (along with superposition, which

you will learn about later) can solve the circuit on page 8
13
2
Other Analysis Methods
Method 2
Apply element combination rules
V
I
3 2
3 2
R R
R R
+
V
I
3 2
3 2
1
R R
R R
R R
+
+ =
+
V
? = I
1
R
3
R
2
R
+
R
Example
1
R
R
V
I =
14
2
1.
2.
3.
4.
5.
Select reference node ( ground)
from which voltages are measured.
Label voltages of remaining nodes
with respect to ground.
These are the primary unknowns.
Write KCL for all but the ground
node, substituting device laws and
KVL.
Solve for node voltages.
Back solve for branch voltages and
currents (i.e., the secondary unknowns)
Particular application of KVL, KCL method
Method 3Node analysis
15
2
Example: Old Faithful
plus current source
0
V
1
R
2
R
4
R
5
R
3
R
J
1
I
0
V
+
1
e
2
e
Step 1
Step 2
16
2
plus current source
0 ) ( ) ( ) (
2 1 3 2 1 1 0 1
= + + G e G e e G V e
KCL at
1
e
0 ) ( ) ( ) (
1 5 2 4 0 2 3 1 2
= + + I G e G V e G e e
KCL at
2
e
for
convenience,
write
i
i
R
G
1
=
0
V
1
R
2
R
4
R
5
R
3
R
J
1
e
1
I
0
V
+
2
e
Step 3
17
2
plus current source
0 ) ( ) ( ) (
2 1 3 2 1 1 0 1
= + + G e G e e G V e
KCL at
1
e
0 ) ( ) ( ) (
1 5 2 4 0 2 3 1 2
= + + I G e G V e G e e
KCL at
2
l
move constant terms to RHS & collect unknowns
) ( ) ( ) (
1 0 3 2 3 2 1 1
G V G e G G G e = + + +
1 4 0 5 4 3 2 3 1
) ( ) ( ) ( I G V G G G e G e + = + + +
i
i
R
G
1
=
2 equations, 2 unknowns Solve for es
(compare units)
0
V
1
R
2
R
4
R
5
R
3
R
J
1
e
1
I
0
V
+
2
e
Step 4
18
2
In matrix form:
(
+
=
(
+ +
+ +
1 0 4
0 1
2
1
5 4 3 3
3 3 2 1
I V G
V G
e
e
G G G G
G G G G
conductivity
matrix
unknown
node
voltages
sources
( )( )
2
3 5 4 3 3 2 1
1 0 4
0 1
3 2 1 3
3 5 4 3
2
1
G G G G G G G
I V G
V G
G G G G
G G G G
e
e
+ + + +
(
+
(
+ +
+ +
=
(
Solve
( )( ) ( )( )
5
G
3
G
4
G
3
G
2
3
G
5
G
2
G
4
G
2
G
3
G
2
G
5
G
1
G
4
G
1
G
3
G
1
G
1
I
0
V
4
G
3
G
0
V
1
G
5
G
4
G
3
G
1
e
+ + + + + + + +
+ + + +
=
( )( ) ( )( )
5 3 4 3
2
3 5 2 4 2 3 2 5 1 4 1 3 1
1 0 4 3 2 1 0 1 3
2
G G G G G G G G G G G G G G G G G
I V G G G G V G G
e
+ + + + + + + +
+ + + +
=
(same denominator)
Notice: linear in , , no negatives
in denominator
0
V
1
I
19
2
Solve, given
K 2 . 8
1
G
G
5
1
=
)
`
K 9 . 3
1
G
G
4
2
=
)
`
K 5 . 1
1
G
3
=
0
1
= I
( )( )
( ) ( )
2
3
G
5
G
4
G
3
G
3
G
2
G
1
G
1
I
0
V
4
G
3
G
2
G
1
G
0
V
1
G
3
G
2
e
+ + + + +
+ + + +
=
1
5 . 1
1
9 . 3
1
2 . 8
1
3
G
2
G
1
G = + + = + +
1
2 . 8
1
9 . 3
1
5 . 1
1
G G G
5 4 3
= + + = + +
0
2
2
V
5 . 1
1
1
9 . 3
1
1
5 . 1
1
2 . 8
1
e
+
=
0 2
6 . 0 V e =
If
, then
V V 3
0
=
0 2
8 . 1 V e =
Check out the
DEMO
1
3
6.002
CIRCUITS AND
ELECTRONICS
Superposition, Thvenin and Norton
2
3
0 =
loop
i
V
Review
Circuit Analysis Methods
z Circuit composition rules
z Node method the workhorse of 6.002
KCL at nodes using V s referenced
from ground
(KVL implicit in )
( )
j i
e e G
z KVL: KCL:
0 =
node
i
I
VI
3
3
Consider
Linearity
Write node equations
V
I
1
R
2
R
+
J
0
2 1
= +
I
R
e
R
V e
Notice:
linear in
I V e , ,
VI , eV No
terms
e
4
3
Consider
Linearity
Write node equations --
Rearrange --
V
I
1
R
2
R
+
J
0
2 1
= +
I
R
e
R
V e
I
R
V
e
R R
+ =
+
1 2 1
1 1
G e
S
=
conductance
matrix
node
voltages
linear sum
of sources
linear in
I V e , ,
5
3
Linearity
or I
R R
R R
V
R R
R
e
2 1
2 1
2 1
2
+
+
+
=
+ + + + + =
2 2 1 1 2 2 1 1
I b I b V a V a e
Write node equations --
Rearrange --
0
2 1
= +
I
R
e
R
V e
I
R
V
e
R R
+ =
+
1 2 1
1 1
G e
S
=
conductance
matrix
node
voltages
linear sum
of sources
linear in
I V e , ,
Linear!
6
3
Linearity
Homogeneity
Superposition

7
3
Linearity
Homogeneity
Superposition
Homogeneity
1
x
2
x
y
.
.
.
1
x
2
x
y
.
.
.

8
3
Linearity
Homogeneity
Superposition
Superposition
a
x
1
a
x
2
a
y
.
.
.
.
.
.
b
x
1
b
x
2
b
y
b a
x x
1 1
+
b a
x x
2 2
+
b a
y y +
.
.
.
9
3
Linearity
Homogeneity
Superposition
Specific superposition example:
1
V
0
1
y
0
2
V
2
y
0
1
+ V
2
0 V +
2 1
y y +

10
3
Method 4: Superposition method
The output of a circuit is
determined by summing the
responses to each source
acting alone.
i
n
d
e
p
e
n
d
e
n
t

s
o
u
r
c
e
s
o
n
l
y
11
3
i
+
0 = V
+
-
v
i
short
+
-
v
i
0 = I
J
+
-
v
i
open
+
-
v
12
3
Back to the example
Use superposition method
V
I
1
R
2
R
+
J
e
13
3
Back to the example
Use superposition method
V acting alone
V
0 = I
2
R
+
e
1
R
I acting alone
0 = V
I
1
R
2
R
J
e
V
R R
R
e
V
2 1
2
+
=
I
R R
R R
e
I
2 1
2 1
+
=
I
R R
R R
V
R R
R
e e e
I V
2 1
2 1
2 1
2
+
+
+
= + =
sum superposition
Voil !
14
3
salt
water
output shows
superposition
Demo
constant
+
sinusoid
+
?
15
3
Consider
Yet another method
resistors
no
units
By setting
0
, 0
=
=
i
I
n n
0
, 0
=
=
i
V
m m
All
0
, 0
=
=
m m
n n
V
I
J
+
m
V
n
I
A
r
b
i
t
r
a
r
y
n
e
t
w
o
r
k

N
By superposition
Ri I V v
n
n
n m
m
m
+ + =

+
-
v J
i
i
resistance
units
independent of external
excitation and behaves like a
voltage
TH
v
also
independent
of external
excitement &
behaves like
a resistor
16
3
Or
i R v v
TH TH
+ =
As far as the external world is concerned
(for the purpose of I-V relation),
Arbitrary network N is indistinguishable
from:
i
+
TH
R
TH
v
J
+
-
v
Thvenin
equivalent
network
TH
R
TH
v open circuit voltage
at terminal pair (a.k.a. port)
resistance of network seen
from port
( s, s set to 0)
m
V
n
I
N
17
3
Method 4:
The Thvenin Method
Replace network N with its Thvenin
equivalent, then solve external network E.
E
Thvenin equivalent
+
TH
R
TH
v
+
-
v
i
E
J
+
i
+
-
v
N
18
3
Example:
1
R
V
+
1
i
1
R
V
+
1
i
TH
TH
R R
V V
i
+
=
1
1
I
2
R
J
I
TH
R
TH
V +

19
3
Example:
:
TH
R
:
TH
V
2
IR V
TH
=
2
R R
TH
=
+
-
TH
V
2
R
J
I
+
-
TH
R
2
R
20
3
Graphically, i R v v
TH TH
+ =
i
Open circuit
( ) 0 i
TH
v v =
OC
V
Short circuit
( ) 0 v
TH
TH
R
v
i

=
SC
I
v
TH
R
1
TH
v
SC
I
OC
V

21
3
Method 5:
The Norton Method
in recitation,
see text
J
+
i
+
-
v
Norton
equivalent
TH
TH
N
R
V
I =
N TH
R R =
N
I
J
22
3
Summary
101100
Discretize matter
LMD LCA
Physics EE
R, I, V Linear networks
Analysis methods (linear)
KVL, KCL, I V
Combination rules
Node method
Superposition
Thvenin
Norton
Next
Nonlinear analysis
Discretize voltage
1
4
6.002
CIRCUITS AND
ELECTRONICS
The Digital Abstraction
2
4
Review
z Discretize matter by agreeing to
observe the lumped matter discipline
zAnalysis tool kit: KVL/KCL, node method,
superposition, Thvenin, Norton
(remember superposition, Thvenin,
Norton apply only for linear circuits)
Lumped Circuit Abstraction
3
4
Discretize value Digital abstraction
Interestingly, we will see shortly that the
tools learned in the previous three
lectures are sufficient to analyze simple
digital circuits
Reading: Chapter 5 of Agarwal & Lang
Today
4
4
Analog signal processing
But first, why digital?
In the past
By superposition,
The above is an adder circuit.
2
2 1
1
1
2 1
2
0
V
R R
R
V
R R
R
V
+
+
+
=
If
,
2 1
R R =
2
2 1
0
V V
V
+
=
1
V
1
R
2
R
+
2
V
+
0
V
and
might represent the
outputs of two
sensors, for example.
1
V
2
V
5
4
Noise Problem
noise hampers our ability to distinguish
between small differences in value
e.g. between 3.1V and 3.2V.
Receiver:
huh?
add noise on
this wire
t
6
4
Value Discretization
Why is this discretization useful?
Restrict values to be one of two
HIGH
5V
TRUE
1
LOW
0V
FALSE
0
like two digits 0 and 1
(Remember, numbers larger than 1 can be
represented using multiple binary digits and
coding, much like using multiple decimal digits to
represent numbers greater than 9. E.g., the
binary number 101 has decimal value 5.)
7
4
Digital System
sender receiver
S
V
R
V
noise
S
V
0 0 1
0V
2.5V
5V
HIGH
LOW
t
R
V
0 0 1
0V
2.5V
5V
t
V V
N
0 =
N
V
S
V
0 0 1
2.5V t
With noise
V V
N
2 . 0 =
S
V
0 0 1
0V
2.5V
5V
t
0.2V
t
8
4
Digital System
Better noise immunity
Lots of noise margin
For 1: noise margin 5V to 2.5V = 2.5V
For 0: noise margin 0V to 2.5V = 2.5V
9
4
Voltage Thresholds
and Logic Values
1
0
1
0
sender receiver
1
0
0V
2.5V
5V
10
4
forbidden
region
V
H
V
L
3V
2V
But, but, but
What about 2.5V?
Hmmm create no mans land
or forbidden region
For example,
sender receiver
0V
5V
1 1
0 0
1 V 5V
0 0V V
H
L
11
4
sender receiver
But, but, but
Wheres the noise margin?
What if the sender sent 1: ? V
H
Hold the sender to tougher standards!
5V
0V
1
1
0
0
V
0H
V
0L
V
IH
V
IL
12
4
sender receiver
V
H
But, but, but
Wheres the noise margin?
What if the sender sent 1: ?
Hold the sender to tougher standards!
5V
0V
1 noise margin:
0 noise margin:
V
IH
-
V
0H
V
IL
-
V
0L
1
1
0
0
V
0H
V
0L
V
IH
V
IL
Noise margins
13
4
Digital systems follow static discipline: if
inputs to the digital system meet valid input
thresholds, then the system guarantees its
outputs will meet valid output thresholds.
sender
receiver
0 1 0 1
t
5V
V
0H
V
0L
0V
V
IH
V
IL
0 1 0 1
t
5V
V
0H
V
0L
0V
V
IH
V
IL
14
4
Processing digital signals
Recall, we have only two values
Map naturally to logic: T, F
Can also represent numbers
1,0
15
4
Processing digital signals
Boolean Logic
If X is true and Y is true
Then Z is true else Z is false.
Z = X AND Y
X, Y, Z
are digital signals
0 , 1
Z = X Y
Boolean equation
Enumerate all input combinations
Truth table representation:
Z X Y
AND gate
Z
X
Y
0 0 0
0 1 0
1 0 0
1 1 1
16
4
Adheres to static discipline
Outputs are a function of
inputs alone.
Combinational gate
abstraction
Digital logic designers do not
have to care about what is
inside a gate.
17
4
Demo
Noise
Z
X
Y
Z = X Y
Z
Y
X
18
4
Z = X Y
Examples for recitation
X
t
Y
t
Z
t
19
4
In recitation
Another example of a gate
If (A is true) OR (B is true)
then C is true
else C is false
C = A + B
Boolean equation
OR
OR gate
C
A
B
Z
X
Y
NAND
Z = X Y
More gates
B B
Inverter
20
4
Boolean Identities
AB + AC = A (B + C)
X 1 = X
X 0 = X
X + 1 = 1
X + 0 = X
1 = 0
0 = 1
output
B
C
B C
A
Digital Circuits
Implement: output = A + B C
1
5
6.002
CIRCUITS AND
ELECTRONICS
Inside the Digital Gate
2
5
Review
z Discretize value 0, 1
z Static discipline
meet voltage thresholds
Specifies how gates must be designed
sender receiver
forbidden
region
OL
V
OH
V
IL
V
IH
V
The Digital Abstraction
3
5
Review
C A B
0 0 1
0 1 1
1 0 1
1 1 0
A
B
C
NAND
Combinational gate abstraction
outputs function of input alone
satisfies static discipline
4
5
For example:
a digital circuit
Demo
D
A
B
C
A Pentium III class microprocessor
is a circuit with over 4 million gates !!
The RAW chip
being built at the
Lab for Computer Science at MIT
has about 3 million gates.
3 gates here
( ) ( )
B A C D
=
B A

5
5
How to build a digital gate
Analogy
A
B
C
l
i
k
e
p
o
w
e
r
s
u
p
p
l
y
(
l
i
k
e

s
w
i
t
c
h
e
s
)
taps
if A=ON AND B=ON
C has H 0
else C has no H 0
2
2
Use this insight to build an AND gate.
6
5
How to build a digital gate
C
B
A
OR gate
7
5
Electrical Analogy
+
Bulb C is ON if A AND B are ON,

else C is off
Key: switch device
V
A B
C
8
5
Electrical Analogy
Key: switch device
C
in
out
control
3-Terminal device
if C = 0
short circuit between in and out
else
open circuit between in and out
For mechanical switch,
control mechanical pressure
in
out
1
=
C
equivalent ckt
0 = C
in
out
9
5
Consider
=
S
V
1
+
S
V
L
R
C
IN
OUT
OUT
V
S
V
0 = C
OUT
V
S
V
1 = C
OUT
V
S
V
L
R
C
OUT
V
Truth table for
C
0 1
1 0
OUT
V
10
5
What about?
Truth table for
O
V
2
c
0 0 1
0 1 1
1 0 1
1 1 0
1
c
Truth table for
O
V
2
c
0 0 1
0 1 0
1 0 0
1 1 0
1
c
S
V
OUT
V
1
c
2
c
S
V
OUT
V
1
c
2
c
11
5
What about?
can also build compound gates
S
V
D
A
B
C
( ) C B A D + =
12
5
The MOSFET Device
3 terminal lumped element
behaves like a switch
Metal-Oxide
Semiconductor
Field-Effect
Transistor
: control terminal
: behave in a symmetric
manner (for our needs)
G
S D,
gate

source
D
S
G
drain
13
5
The MOSFET Device
Understand its operation by viewing it
as a two-port element
Switch model (S model) of the MOSFET
D
S
G
i
G
GS
v
+
DS
v
DS
i
+
C
h
e
c
k

o
u
t
t
h
e

t
e
x
t
b
o
o
k
f
o
r

i
t
s

i
n
t
e
r
n
a
l
s
t
r
u
c
t
u
r
e
.
T GS
V v <
T GS
V v
V V
T
1 typically
on
G
D
S
DS
i
G off
D
S
14
5
Check the MOS device
on a scope.
Demo
GS
v
+
DS
v
DS
i
+
T GS
V v
DS
i
DS
v
T GS
V v <
DS
i
DS
v
vs
15
5
A MOSFET Inverter
S
V
L
R
A
IN
B
A
B
V 5 =
Note the power of abstraction.
The abstract inverter gate representation
hides the internal details such as power
supply connections, , , etc.
(When we build digital circuits, the
and are common across all gates!)
L
R GND
v
OUT
16
5
The T1000 model laptop desires gates that satisfy
the static discipline with voltage thresholds. Does
out inverter qualify?
IN
v
OUT
v
OUT
v
IN
v
5V
5V
0V
=1V
T
V
= 0.5V
OL
V
= 4.5V
OH
V
= 0.9V
IL
V
= 4.1V
IH
V
Our inverter satisfies this.
receiver
OL
V
OH
V
IL
V
IH
V
5
4.5
0.5
0
sender
5
4.1
0.9
0
1:
0:
1
0
Example
17
5
E.g.:
Does our inverter satisfy the static
discipline for these thresholds:
= 0.2V
OL
V
= 4.8V
OH
V
= 0.5V
IL
V
= 4.5V
IH
V
= 0.5V
OL
V
= 4.5V
OH
V
= 1.5V
IL
V
= 3.5V
IH
V
yes
no
x
18
5
Switch resistor (SR) model
of MOSFET
more accurate MOS model
D
S
G
D
S
T GS
V v <
G
T GS
V v
ON
R
D
S
G
e.g. = K R
ON
5
19
5
SR Model of MOSFET
MOSFET
S model
T GS
V v
T GS
V v <
DS
i
DS
v
MOSFET
SR model
T GS
V v
T GS
V v <
DS
i
DS
v
ON
R
1
D
S
G
D
S
T GS
V v <
G
T GS
V v
ON
R
D
S
G
20
5
Using the SR model
=
S
V
1
+
S
V
L
R
C
IN
OUT
OUT
v
S
V
0 = C
OUT
v
S
V
1 = C
OUT
v
S
V
L
R
C
OUT
v
Truth table for
C
0 1
1 0
OUT
V
T GS
V v
ON
R
ON
R
OL
V
L
R
ON
R
ON
R
S
V
OUT
v
+
=
L
R
L
R
Choose R
L
, R
ON
, V
S
such that:
1
6
6.002
CIRCUITS AND
ELECTRONICS
Nonlinear Analysis
2
6
Discretize matter t LCA
m1 X KVL, KCL, i-v
m2 X Composition rules
m3 X Node method
m4 X Superposition
m5 X Thvenin, Norton
any
circuit
linear
circuits
Review
3
6
Discretize value t Digital abstraction
X Subcircuits for given switch
setting are linear! So, all 5
methods (m1 m5) can be
applied
1
1
=
=
B
A
A
B
S
V
L
R
C
S
V
L
R
C
ON
R
ON
R
SR MOSFET Model
Review
4
6
Today
Nonlinear Analysis
X Analytical method
based on m1, m2, m3
X Graphical method
X Introduction to incremental analysis
5
6
How do we analyze nonlinear
circuits, for example:
D
v
+
-
D
D
i
D
v
D
i
0 , 0
D
bv
D
ae i =
a
D
v
+
-
V
+
Hypothetical
nonlinear
device
D
D
i
(Expo Dweeb )
(Curiously, the device supplies power when v
D
is negative)
6
6
Method 1: Analytical Method
Using the node method,
(remember the node method applies for linear or
nonlinear circuits)
D
bv
D
ae i =
2
0 = +
D
D
i
R
V v
1
2 unknowns 2 equations
Solve the equation by
trial and error
numerical methods
7
6
Method 2: Graphical Method
Notice: the solution satisfies equations
and
2 1
D
v
D
i
a
D
bv
D
ae i =
2
D
v
D
i 1
R
v
R
V
i
D
D
=
R
V
V
R
slope
1
=
8
6
Combine the two constraints
1
4
1
1
1
=
=
=
=
b
a
R
V e.g.
A i
V v
D
D
4 . 0
5 . 0
=
=
D
v
D
i
5 . 0 ~
4 . 0 ~
R
V
V
1
1
a
called loadline
for reasons you
will see later
9
6
Method 3: Incremental Analysis
Motivation: music over a light beam
Can we pull this off?
LED: Light
Emitting
expoDweep
D
v
+
-
) (t v
I
+
D
i
LED
R
i
AMP
light intensity I
R
in photoreceiver
R R
I i
light
intensity
D D
i I
I
v
t
music signal
) (t v
I
light sound ) (t i
R
) (t i
D
nonlinear
linear
problem! will result in distortion
10
6
Problem:
The LED is nonlinear distortion
I D
v v =
D
v
D
i
v
D
t
t
D
i
v
D
D
i
t
11
6
If only it were linear
v
D
t
D
i
D
v
D
i
it wouldve been ok.
What do we do?
Zen is the answer
next lecture!
1
7
6.002
CIRCUITS AND
ELECTRONICS
Incremental Analysis
2
7
Nonlinear Analysis
X Analytical method
X Graphical method
Today
X Incremental analysis
Reading: Section 4.5
Review
3
7
Method 3: Incremental Analysis
Motivation: music over a light beam
Can we pull this off?
LED: Light
Emitting
expoDweep
D
v
+
-
) (t v
I
+
D
i
LED
R
i
AMP
light intensity I
R
in photoreceiver
R R
I i
light
intensity
D D
i I
I
v
t
music signal
) (t v
I
light sound ) (t i
R
) (t i
D
nonlinear
linear
problem! will result in distortion
4
7
Problem:
The LED is nonlinear distortion
I D
v v =
D
v
D
i
v
D
t
t
D
i
v
D
D
i
t
5
7
Insight:
D
v
D
i
D
I
D
V
DC offset
or DC bias
Trick:
d D D
i I i + =
I
V
D
v
+
-
) (t v
i
+
LED
+
I
v
d D D
v V v + =
I
V
i
v
small region
looks linear
(about V
D
, I
D
)
6
7
Result
v
d
very small
D
i
D
v
d
i
D
I
D
V
7
7
Result
t
D
v
D
V
I D
v v =
t
D
I
D
i
~linear!
Demo
d
v
d
i
D
i
8
7
total
variable
DC
offset
small
superimposed
signal
The incremental method:
(or small signal method)
1. Operate at some DC offset
or bias point V
D
, I
D
.
2. Superimpose small signal v
d
(music) on top of V
D
.
3. Response i
d
to small signal v
d
is approximately linear.
Notation:
d D D
i I i
+ =
9
7
( )
D D
v f i =
What does this mean
mathematically?
Or, why is the small signal response
linear?
We replaced
D D D
v V v + =
using Taylors Expansion to expand
f(v
D
) near v
D
=V
D
:
( )
D
V v
D
D
D D
v
dv
v df
V f i
D D
+ =
=
) (
" + +
=
2
2
2
) (
! 2
1
D
V v
D
D
v
dv
v f d
D D
large DC
increment
about V
D
nonlinear
d
v
neglect higher order terms
because is small
D
v
10
7
( )
D
V v
D
D
D D
v
v d
v f d
V f i
D D
+
=
) (
equating DC and time-varying parts,
D
V v
D
D
D
v
v d
v f d
i
D D
=
=
) (
constant
w.r.t. v
D
constant w.r.t. v
D
slope at V
D
, I
D
( )
D D
V f I = operating point
constant w.r.t. v
D
X :
We can write
( )
D
V v
D
D
D D D
v
v d
v f d
V f i I
D D
+ +
=
) (
so,
D D
v i

By notation,
d D
i i
=
d D
v v
=
11
7
Equate DC and incremental terms,
D
bv
D
e a i =
From X :
constant
In our example,
d
bV bV
d D
v b e a e a i I
D D
+ +
D
bV
D
e a I =
d
bV
d
v b e a i
D
=
operating point
d D d
v b I i =
small signal
behavior
linear!
aka bias pt.
aka DC offset
12
7
D
bV
D
e a I =
operating point
d D d
v b I i =
D
v
D
i
D
I
D
V
slope at
V
D
, I
D
operating
point
we are
approximating
A with B
A
B
d
v
d
i
Graphical interpretation
13
7
We saw the small signal
D
I
I
V
D
V
+
-
+
LED
D
bV
D
e a I =
Large signal circuit:
Small signal response:
d D d
v b I i =
graphically
mathematically
now, circuit
small signal circuit:
Linear!
d
i
i
v
d
v
+
- b I
D
1
+
behaves like:
d
v
+
-
d
i
b I
1
R
D
=
6.002 Fall 2002: Lecture 8
1
6.002
CIRCUITS AND
ELECTRONICS
Dependent Sources
and Amplifiers
2
Nonlinear circuits can use the
node method
Small signal trick resulted in linear
response
Today
Dependent sources
Reading: Chapter 7.1, 7.2
Review
Amplifiers
3
Dependent sources
+
v
R
i
R
v
i =
Resistor
2-terminal 1-port devices
+
v
i
I i =
I
Independent
Current source
Seen previously
control
port
output
port
I
i
I
v
O
i
O
v
+
New type of device: Dependent source

2-port device
E.g., Voltage Controlled Current Source
Current at output port is a function of voltage
at the input port
) v ( f
I
4
Dependent Sources: Examples
independent
current
source
Example 1: Find V
0
I I =
+
V
R
R I V
0
=
5
voltage
controled
current
source
Example 2: Find V
( )
V
K
V f I = =
+
V
R
I
i
I
v
O
i
O
v
+
V
R
( )
I
I
v
K
v f =
6
voltage
controled
current
source
R
V
K
IR V = =
KR V =
2
KR V =
3 3
10 10 =

Volt 1 =
or
or
Example 2: Find V
( )
V
K
V f I = =
+
V
R
e.g. K = 10
-3
AmpVolt
R = 1k
7
Another dependent source example
I
v
+
( )
IN D
v f i =
L
R
+
S
V
e.g.
( )
IN D
v f i =
( )
2
IN
1 v
2
K
=
for v
IN
1
IN
i
IN
v
D
i
O
v
+
otherwise
0 i
D
=
Find v
O
as a function of v
I
.
8
I
v
+
( )
IN D
v f i =
L
R
S
V
e.g.
( )
IN D
v f i =
( )
2
IN
1 v
2
K
=
for v
IN
1
IN
i
IN
v
D
i
O
v
+
otherwise
0 i
D
=
Find v
O
as a function of v
I
.
9
Find v
O
as a function of v
I
.
I
v
+
I
v
S
V
O
v
L
R
( )
2
IN D
1 v
2
K
i =
for v
IN
1
otherwise
0 i
D
=
10
0 = + +
O L D S
v R i V
KVL
L D S O
R i V v =
( )
L I S O
R v
K
V v
2
1
2
= for v
I
1
S O
V v = for v
I
< 1
I
v
+
I
v
S
V
O
v
L
R
( )
2
IN D
1 v
2
K
i =
for v
IN
1
otherwise
0 i
D
=
Hold that thought
11
Next, Amplifiers
12
Why amplify?
Signal amplification key to both analog
and digital processing.
Analog:
Besides the obvious advantages of being
heard farther away, amplification is key
to noise tolerance during communication
AMP
IN OUT
Input
Port
Output
Port
13
Why amplify?
Amplification is key to noise tolerance
during communication
useful
signal
huh?
1 mV
n
o
i
s
e
10 mV
No amplification
14
AMP
Try amplification
not bad!
n
o
i
s
e
15
Why amplify?
Digital:
IN
OUT
Digital System
IL
V
IH
V
5V
0V
OL
V
OH
V
5V
0V
t
5V
0V
IL
V
IH
V
IN
OUT
t
5V
0V
OL
V
OH
V
Valid region
16
Why amplify?
Digital:
Static discipline requires amplification!
Minimum amplification needed:
IL
V
IH
V
OL
V
OH
V
IL IH
OL OH
V V
V V

17
An amplifier is a 3-ported device, actually
We often dont show the power port.
Also, for convenience we commonly observe
the common ground discipline.
In other words, all ports often share a
common reference point called ground.
How do we build one?
POWER
IN OUT
Amplifier
Power port
Input
port
Output
port
I
i
I
v
O
i
O
v
+

18
Remember?
0 = + +
O L D S
v R i V
KVL
L D S O
R i V v =
( )
L I S O
R v
K
V v
2
1
2
= for v
I
1
S O
V v = for v
I
< 1
Claim: This is an amplifier
I
v
+
I
v
S
V
O
v
L
R
( )
2
IN D
1 v
2
K
i =
for v
IN
1
otherwise
0 i
D
=
19
So, wheres the amplification?
Lets look at the v
O
versus v
I
curve.
amplification
1 >
I
O
v
v
= = = k 5 R ,
V
mA
2 K , V 10 V
L
2
S
e.g.
O
v
I
v
( )
2
1
2
=
I L S O
v R
K
V v
( )
2
1 5 10 =
I O
v v
( )
2
3 3
1 10 5 10
2
2
10 =

I
v
1
I
v
S
V
O
v
20
Plot v
O
versus v
I
( )
2
I O
1 v 5 10 v =
10.00 1.0
~ 0.00 2.4
1.50 2.3
2.80 2.2
4.00 2.1
5.00 2.0
8.75 1.5
10.00 0.0
v
O
v
I
0.1 change
in v
I
1V change
in v
O
Gain!
Measure v
O
.
Demo
21
One nit
1
I
v
O
v
Mathematically,
( )
2
1
2
=
I L S O
v R
K
V v
What
happens
here?
So is mathematically predicted behavior
22
One nit
D
i
S
V
O
v
L
R
VCCS
1
I
v
O
v
For v
O
>0, VCCS consumes power: v
O
i
D
For v
O
<0, VCCS must supply power!
( )
2
1
2
=
I L S O
v R
K
V v
( )
2
1
2
=
I D
v
K
i for v
I
1
However, from
What
happens
here?
23
If VCCS is a device that can source
power, then the mathematically
predicted behavior will be observed
( )
2
1
2
=
I L S O
v R
K
V v i.e.
where v
O
goes -ve
I
v
O
v
24
If VCCS is a passive device,
then it cannot source power,
so v
O
cannot go -ve.
So, something must give!
Turns out, our model breaks down.
( )
2
1
2
=
I D
v
K
i
Commonly
will no longer be valid when v
O
0 .
e.g. i
D
saturates (stops increasing)
and we observe:
I
v
O
v
1
1
9
6.002
CIRCUITS AND
ELECTRONICS
MOSFET Amplifier
Large Signal Analysis
2
9
Amp constructed using dependent source
Superposition with dependent sources:
one way tleave all dependent sources in;
solve for one independent source at a
time [section 3.5.1 of the text]
Next, quick review of amp
Reading: Chapter 7.37.7
+
a
v
b
b
) (v f i =
a
b
b control
port
DS
output
port
Dependent source in a circuit
Review
3
9
Amp review
L D S O
R i V v =
( )
2
I
1 v
2
K
for v
I
1V
= 0 otherwise
S
V
O
v
L
R
+
( )
2
I D
1 v
2
K
i =
I
v
VCCS
4
9
Key device Needed:
Lets look at our old friend, the MOSFET
A
B
v
C
( ) v f i =
voltage controlled
current source
5
9
Key device Needed:
Our old friend, the MOSFET
First, we sort of lied. The on-state behavior of the
MOSFET is quite a bit more complex than either the
ideal switch or the resistor model would have you believe.
D
S
G
D
S
T GS
V v <
G
T GS
V v
?
6
9
Graphically
DS
v
DS
i
T GS
V v
T GS
V v <
T GS
V v
1 GS
v
Saturation
region
T
r
i
o
d
e

r
e
g
i
o
n
S MODEL
DS
v
DS
i
SR MODEL
DS
v
DS
i
Demo
T GS
V v <
T GS
V v <
2 GS
v
3 GS
v
+
DS
v
+
DS
i
GS
v
.
.
.
T GS DS
V v v =
Cutoff
region
7
9
Graphically
DS
v
DS
i
T GS
V v
T GS
V v <
T GS
V v
1 GS
v
Saturation
region
T
r
i
o
d
e

r
e
g
i
o
n
S MODEL
DS
v
DS
i
SR MODEL
DS
v
DS
i
T GS
V v <
T GS
V v <
2 GS
v
3 GS
v
+
DS
v
+
DS
i
GS
v
.
.
.
T GS DS
V v v =
Notice that
MOSFET
behaves like a
current source
when
T GS DS
V v v
8
9
MOSFET SCS Model
D
S
G
D
S
T GS
V v <
G
( )
2
2
T GS
V v
K
=
when
T GS DS
V v v
( )
GS DS
v f i =
T GS
V v
D
S
G
When
the MOSFET is in its saturation region, and the
switch current source (SCS) model of the MOSFET is
more accurate than the S or SR model
T GS DS
V v v
9
9
Reconciling the models
T GS DS
V v v
T GS DS
V v v <
use SCS model
use SR model
Note: alternatively (in more advanced courses)
or, use SU Model (Section 7.8 of A&L)
S MODEL SR MODEL SCS MODEL
for fun!
for digital
designs
for analog
designs
When to use each model in 6.002?
DS
v
DS
i
T GS
V v
T GS
V v <
T GS
V v
1 GS
v
Saturation
region
T
r
i
o
d
e

r
e
g
i
o
n
DS
v
DS
i
DS
v
DS
i
T GS
V v <
T GS
V v <
2 GS
v
3 GS
v
.
.
.
T GS DS
V v v =
10
9
Back to Amplifier
in saturation
region
I
v
O
v
AMP
S
V
S
V
L
R
I
v
O
v
G
D
S
( )
2
2
T I DS
V v
K
i =
To ensure the MOSFET operates as a VCCS,
we must operate it in its saturation region
only. To do so, we promise to adhere to the
saturation discipline
11
9
MOSFET Amplifier
in saturation
region
S
V
L
R
I
v
O
v
G
D
S
( )
2
2
T I DS
V v
K
i =
To ensure the MOSFET operates as a VCCS,
we must operate it in its saturation region
only. We promise to adhere to the
saturation discipline.
In other words, we will operate the amp
circuit such that
v
GS
V
T
and v
DS
v
GS
V
T
at all times.
v
O
v
I
v
T
12
9
Lets analyze the circuit
First, replace the MOSFET with its
SCS model.
for
T I O
V v v I GS
v v =
G
I
v
+
S
V
O
v
L
R
D
S
A
( )
2
2
T I DS
V v
K
i =
13
9
Lets analyze the circuit
for
T I O
V v v I GS
v v =
G
I
v
+
S
V
O
v
L
R
D
S
A
( )
2
2
T I DS
V v
K
i =
or ( )
L T I S O
R V v
K
V v
2
2
=
for
T I
V v
T I O
V v v
S O
V v =
for
T I
V v <
(MOSFET turns off)
L DS S O
R i V v = B
1
Analytical method: I O
v vs v
(v
O
= v
DS DS
in our example in our example) )
14
9
2
Graphical method
:
B
From A ( ) ,
2
2
T I DS
V v
K
i = :
2
O DS
DS
O
T I O
v
2
K
i
K
i 2
v
V v v

for
I O
v vs v
L
0
L
S
DS
R
v
R
V
i
=
15
9
2
Graphical method
:
B
Constraints and must be met A B
A ( ) ,
2
2
T I DS
V v
K
i = :
S
V
DS
i
O
v
2
2
O DS
v
K
i
L
S
R
V
L
o
a
d

l
i
n
e
B
for
GS
v =
I
v
A
2
2
O DS
v
K
i
L
O
L
S
DS
R
v
R
V
i
=
I O
v vs v
16
9
2
Graphical method
Constraints and must be met.
Then, given V
I
, we can find V
O
, I
DS
.
A B
S
V
DS
i
O
v
L
S
R
V
B
I
v
A
2
2
O DS
v
K
i
I O
v vs v
I
V
DS
I
O
V
17
9
of Amplifier
(under saturation discipline)
1 v
O
versus v
I
2
Valid input operating range and
valid output operating range
18
9
1 v
O
versus v
I
I
v
S
V
( )
L T I S
R V v
K
V
2
2

O
v
T
V
gets into
triode region
T I O
V v v =
19
9
2
What are valid operating ranges
under the saturation discipline?
DS
i
O
v
2
2
O DS
v
K
i
S
V
L
S
R
V
L
O
L
S
DS
R
v
R
V
i =
T I O
T I
V v v
V v

2
2
O DS
v
K
i
Our
Constraints
=
T I
0
=
DS
i
=
S O
V v
V v
and
?
I
v
( )
2
2
T I DS
V v
K
i =
20
9
=
T I
0
=
DS
i
=
S O
V v
V v
and
2
What are valid operating ranges
under the saturation discipline?
DS
i
O
v
2
2
O DS
v
K
i
L
O
L
S
DS
R
v
R
V
i =
I
v
( )
2
2
T I DS
V v
K
i =
L
S L
T I
KR
V KR
V v
2 1 1 + +
+ =
L
S L
O
KR
V KR
v
2 1 1 + +
=
L
O
L
S
DS
R
v
R
V
i =
21
9
Valid input range:
L
S L
T
KR
V KR
V
2 1 1 + +
+
v
I
: V
T
to
corresponding output range:
L
S L
KR
V KR 2 1 1 + +
v
O
: V
S
to
2
Valid operating ranges under the
saturation discipline?
Summary
1 v
O
versus v
I
( )
L
2
T I S O
R V v
2
K
V v =
6.002
CIRCUITS AND
ELECTRONICS
Amplifiers --
Small Signal Model
10
1
Review
MOSFET amp
S
V
L
R
DS
i
v
O
v
I
Saturation discipline operate
MOSFET only in saturation region
Large signal analysis
1. Find v
O
vs v
I
under saturation discipline.
2. Valid v
I
, v
O
ranges under saturation discipline.
Reading: Small signal model -- Chapter 8
10
2
Large Signal Review
1
v
O
vs v
I
v
O
= V
S

K
(v
I
1)
2
R
L
2
valid for v
I
V
T
and
v
O
v
I
V
T
(same as i
DS

K
v
O
2
)
2
10
3
Large Signal Review
2
Valid operating ranges
v
V
5V
corresponding
v
I
V
T
interesting
v
I
V
T
region for v
O
v
I
V
T
S
O
O
v =
O
v >
O
v <
1V
v
I
V
T
1V 2V
interesting region
for v
I
. Saturation
discipline satisfied.
10
4
But
S
V
O
v
O
v =
I
v
5V
1V
v
I
V
T
v
I
v
O
Demo
V
T
1V 2V
Amplifies alright,
but distorts
v
I
v
O
t
Amp is nonlinear /
10
5
Small Signal Model
~ 5V
V
S
~1V
Hmmm
( )
L
T I
S O
R
V v K
V v
2
2
=
Amp all right, but nonlinear!
I
v
O
v
T
V
V 1 V 2 ~
Insight:
( )
O I
V , V
Focus on this line segment
So what about our linear amplifier ???
But, observe v
I
vs v
O
about some
point (V
I
, V
O
) looks quite linear !
10
6
Trick
o
v
i
v
I
V
O
V
( )
O I
V V ,
O
v
looks
linear
v
I
Operate amp at V
I
, V
O
DC bias (good choice: midpoint
of input operating range)
Superimpose small signal on top of V
I
Response to small signal seems to be
approximately linear
10
7
Trick
o
v
i
v
I
V
O
V
( )
O I
V V ,
O
v
looks
linear
v
I
Operate amp at V
I
, V
O
DC bias (good choice: midpoint
of input operating range)
Superimpose small signal on top of V
I
Response to small signal seems to be
approximately linear
Lets look at this in more detail
I
III from a circuit viewpoint
graphically
next
II mathematically
week
10
8
I Graphically
We use a DC bias V
I
to boost interesting input
signal above V
T
, and in fact, well above V
T
.
interesting
input signal
+

+

S
V
L
R
v
O
v
I
V
I
Offset voltage or bias
10
9
Graphically
interesting
v
O
v
I
S
V
L
R
+

+

input signal
V
I
S
V
O
v
O
V
operating
point
O I
V V ,
I
V
T
V
O
v v =
0
I
V
T
v
I
Good choice for operating point:
midpoint of input operating range
10
10
Small Signal Model
aka incremental model
aka linearized model
Notation
Input:
total
v
I
= V
I
+ v
i
DC small
variable bias signal (like v
I
)
bias voltage aka operating point voltage
Output: v
O
= V
O
+ v
o
Graphically,
v
v
v
i
v
o
V
I
V
O
I
O
0 t
0
t
10
11
II Mathematically
( watch my fingers)
v
O
= V
S

R
L
K
(v
I
V
T
)
2
V
O
= V
S

R
L
K
(V
I
V
T
)
2
2
2
substituting v
I
= V
I
+ v
i
v
i
<< V
I
v
O
= V
S

R
L
K
( [V
I
+ v
i
] v
T
)
2
2
= V
S

R
L
K
( [V
I
V
T
]+ v
i
)
2
2
= V
S

R
L
K
([V
I
V
T
]
2
+ 2[V
I
v
T
]v
i
2
i
v + )
2
O
V + v
o
= (
2
T I
L
S
V V
2
K R
V ) R
L
K (V
I
V
T
)v
i
From ,
v
o
= R
L
K (
T I
) V V v
i
g
m
related to V
I
10
12
Mathematically
v
o
= R
L
K (
T I
) V V v
i
g
m
related to V
I
v
o
= g
m
R
L
v
i
For a given DC operating point voltage V
I
,
V
I
V
T
is constant. So,
v
o
= A v
i
constant w.r.t. v
i
In other words, our circuit behaves like a linear amplifier
for small signals
10
13

Another way
v
O
= V
S

R
L
K
(v
I
V
T
)
2
2
v
o
=
dv
d
I
V
S

R
L
2
K
(v
I
V
T
)
2

v
i
I I
v = V
slope at V
I
v
o
= R
L
K (V
I
V
T
) v
i
g
m
= K (V
I
V
T
)
A = g
m
R
L
amp gain
Also, see Figure 8.9 in the course notes
for a graphical interpretation of this result
10
14
More next lecture
Demo
DS
i
I
V
O
v
load line
operating point
input signal response
V
O
How to choose the bias point:
1. Gain component g
m
V
I
2. v
i
gets big distortion.
So bias carefully
3. Input valid operating range.
Bias at midpoint of input operating
range for maximum swing.
10
15
1
11
6.002
CIRCUITS AND
ELECTRONICS
Small Signal Circuits
2
11
Small signal notation
v
A
= V
A
+ v
a
total operating
point
small
signal
( )
i
V v
I
I
out
I OUT
v v f
dv
d
v
v f v
I I
=
=
=
) (
S
V
L
R
o O O
v V v + =
I
V
+
i I I
v V v + =
i
v
Review:
3
11
I Graphical view
(using transfer function)
behaves linear
for small
perturbations
I
v
O
v
Review:
4
11
II Mathematical view
( )
L
T I
S O
R
V v K
V v
2
2
=
( )
i
V v
L T I S
I
o
v
R V v
K
V
dv
d
v
I I

=
=
2
2
related to V
I
constant for fixed
DC bias
( )
i L T I o
v R V V K v =
g
m
Review:
5
11
Demo
Choosing a bias point:
DS
i
O
v
L
S L
T I
KR
V KR
V v
2 1 1 + +
+ =
T I
V v =
2
O DS
v
2
K
i <
load line
L
O
L
S
DS
R
v
R
V
i =
How to choose the bias point,
using yet another graphical view
based on the load line
O
V
I
V
input signal
response
I L m
V R g 1. Gain
2. Input valid operating range for amp.
3. Bias to select gain and input swing.
6
11
III The Small Signal Circuit View
We can derive small circuit equivalent
models for our devices, and thereby conduct
small signal analysis directly on circuits
( )
2
T I D
V v
2
K
i =
+
R
OUT
v
V
S
+
I
v
1
e.g. large signal
circuit model
for amp
We can replace large signal models with
small signal circuit models.
Foundations: Section 8.2.1 and also in the
last slide in this lecture.
7
11
Small Signal Circuit Analysis
1 Find operating point using DC bias
inputs using large signal model.
Develop small signal (linearized)
models for elements.
Replace original elements with small
signal models.
2
3
Analyze resulting linearized circuit
Key: Can use superposition and other
linear circuit tools with linearized
circuit!
8
11
Small Signal Models
MOSFET
A
large
signal
( )
2
2
T GS DS
V v
K
i =
D
S
GS
v
Small signal?
9
11
Small Signal Models
MOSFET
A
large
signal
( )
2
2
T GS DS
V v
K
i =
D
S
GS
v
Small signal:
small
signal
D
S
gs
v
( )
gs T GS ds
v V V K i =
gs m ds
v g i =
( )
2
2
T GS DS
V v
K
i =
( )
gs
V v
T GS
GS
ds
v V v
K
v
i
GS GS
=
=
2
2
( )
gs T GS ds
v V V K i =
g
m
i
ds
is linear in v
gs
!
10
11
DC Supply V
S
B
large
signal
S S
V v =
s
I i
S
S
s
i
i
V
v
S S
=
=
0 v
s
=
+
S S
V v =
S
i
+
s
v
s
i
DC source behaves
as short to small
signals.
Small signal
11
11
Similarly, R C
large
signal
small
signal
R
+
R
v
R
i
R
+
r
v
r
i
R R
i R v =
( )
r
I i
R
R
r
i
i
Ri
v
R R
=
=
r r
i R v =
12
11
Large signal
( )
2
2
T I DS
V v
K
i =
( )
L T I S O
R V v
K
V v
2
2
=
L
R
O
v
+
I
v
+
S
V
DS
i
L
R
o
v
+
i
v
ds
i
( )
i T I ds
v V V K i =
0 = +
o L ds
v R i
L ds o
R i v =
( )
i L T I o
v R V V K v =
i L m
v R g =
Small signal
Amplifier example:
Notice, first we need to find operating
point voltages/currents.
Get these from a large signal analysis.
13
11
To find the relationship between the small signal parameters of
a circuit, we can replace large signal device models with
corresponding small signal device models, and then analyze the
resulting small signal circuit.
Foundations: (Also see section 8.2.1 of A&L)
KVL, KCL applied to some circuit C yields:
III The Small Signal Circuit View
b B out OUT a A
v V v V v V + + + + + + +
" " "
Replace total variables with
operating point variables plus small signal variables
Operating point variables themselves satisfy the
same KVL, KCL equations
B OUT A
V V V + + + +
" " "
so, we can cancel them out
B OUT A
v v v
+ + + + + + " " " "
1
b out a
v v v + + + +
" " "
Leaving
2
Since small signal models are linear, our linear tools will now
apply
But is the same equation as with small signal
variables replacing total variables, so must reflect same
topology as in C, except that small signal models are used.
2
1
2
1
12
6.002
CIRCUITS AND
ELECTRONICS
Capacitors
and First-Order Systems
2
12
5V
0V
C
A
B
5V
A
B
C
5
0
5
0
5
0
Reading:
Chapters 9 & 10
Demo
5V
Expected
Observed
Expect this, right?
But observe this!
Delay!
Motivation
3
12
The Capacitor
G
D
S
n-channel MOSFET
symbol
n-channel
MOSFET
n-channel
s
i
l
i
c
o
n
n
m
e
t
a
l
+
+
+
+
+
+
o
x
i
d
e
drain
gate
source
C
GS
G
D
S
n
p
4
12
Ideal Linear Capacitor
obeys DMD!
total charge on
capacitor
0 q q = + =
d
EA
C =
+ +
+ + + +
- -
- - - - -
A
E
d
coulombs farads volts
v C q =
i
C
q
+
v
5
12
Ideal Linear Capacitor
dt
dq
i =
( )
dt
Cv d
=
dt
dv
C =
i
v C q =
C
q
+
v
A capacitor is an energy storage device
memory device history matters!
=
2
2
1
Cv E
6
12
Apply node method:
C
+
( ) t v
C
( ) t v
I
+
R
Thvenin Equivalent:
0 = +
dt
dv
C
R
v v
C I C
I C
C
v v
dt
dv
C R = +
0
t t
( )
0
t v
C
given
units
of time
Analyzing an RC circuit
7
12
Lets do an example:
( )
I I
V t v =
( )
0
0 V v
C
= given
I C
C
V v
dt
dv
C R = +
X
C
+
( ) t v
C
( ) t v
I
+
R
8
12
Example
Method of homogeneous and particular
solutions:
1
2
3
Find the particular solution.
Find the homogeneous solution.
The total solution is the sum of
the particular and homogeneous
solutions.
Use the initial conditions to solve
for the remaining constants.
( )
I I
V t v =
( ) ( ) ( ) t v t v t v
CP CH C
+ =
total homogeneous particular
( )
0
0 V v
C
= given
I C
C
V v
dt
dv
C R = +
X
9
12
1 Particular solution
I CP
CP
V v
dt
dv
C R = +
I CP
V v = works
I I
I
V V
dt
dV
C R = +
0
In general, use trial and error.
v
CP
: any solution that satisfies the
original equation X
10
12
2 Homogeneous solution
0 = +
CH
CH
v
dt
dv
C R
Y
v
CH
: solution to the homogeneous
equation
(set drive to zero)
Y
0 = +
st
st
e A
dt
e dA
C R
0 = +
st st
e A e s CA R
st
CH
e A v =
assume solution
of this form. A, s ?
Discard trivial A = 0 solution,
0 1= + s C R
Characteristic equation
RC
s
1
=
RC
t
CH
Ae v

= or
RC
called time
constant

11
12
3 Total solution
Find remaining unknown from initial
conditions:
CH CP C
v v v + =
RC
t
I C
e A V v

+ =
also
( )
RC
t
I 0 C
C
e
R
V V
dt
dv
C i

= =
thus
Given,
so,
or
0 C
V v =
at t = 0
A V V
I 0
+ =
I 0
V V A =
( )
RC
t
I 0 I C
e V V V v

+ =
12
12
t
C
v
I
V
0
V
( )
RC
t
I 0 I C
e V V V v

+ =
RC
0
13
12
t
C
v
V 5
V 0
V V
I
5 =
V V
O
0 =
5
0
V V
I
0 =
V V
O
5 = 5
0
t
C
v
V 5
V 0
RC
t
e
+5 5
RC
t
e

5
RC =
Remember
demo
B
Examples
1
13
6.002
CIRCUITS AND
ELECTRONICS
Digital Circuit
2
13
C
+
C
v
I
v
+
R
t
C
v
O
V
I
V
( )
RC
t
I O I C
e V V V v

+ =
1
( )
O C
V v = 0
t
I
V
I
v
0
Review
time constant RC
RC
3
13
Lets apply the result to
an inverter.
A
B
V
S
V
S
X
C
GS
t
A
v
V 5
0
1 0 at A
A B
X
First, rising delay t
r
at B
4
13
A
B
V
S
V
S
X
C
GS
ideal
t
A
v
V 5
0
1 0 at A
r
at B
observed
t
B
v
V 5
0
5
13
A
B
V
S
V
S
X
C
GS
t
A
v
V 5
0
1 0 at A
OH
V
r
t
rising delay of X
r
at B
t
B
v
V 5
0
6
13
Equivalent circuit for 01 at B
+
B
v
S I
V v =
+
L
R
GS
C
( )
GS L
C R
t
S S B
e V V v

+ = 0
1 From
Now, we need to find t for which
v
B
= V
OH
.
S I
V v =
for t 0
( ) 0 0 =
B
v
7
13
GS L
C R
t
S S OH
e V V v

=
Or
Find t
r
:
OH S
C R
t
S
V V e V
GS L
r
=
S
OH S
GS L
r
V
V V
C R
t
=
ln
S
OH S
GS L r
V
V V
C R t

= ln
8
13
GS L
C R
t
S S OH
e V V v

=
Or
Find t
r
:
OH S
C R
t
S
V V e V
GS L
r
=
S
OH S
GS L
r
V
V V
C R
t
=
ln
S
OH S
GS L r
V
V V
C R t

= ln
e.g. K R
L
1 =
pF C
GS
1 . 0 =
V V
S
5 =
V V
OH
4 =
5
4 5
ln 10 1 . 0 10 1 t
12 3
r

=

ns 16 . 0 =
! 1 . 0 ns RC =
9
13
Falling Delay t
f
S
V
+
L
R
+
B
v
GS
C
ON
R
( )
( ) V
V v
S B
5
0 =
X
Falling delay t
f
is
the t for which v
B
falls to V
OL
Equivalent circuit for 1 0 at B
10
13
Falling Delay t
f
Equivalent circuit for 1 0 at B
ON L TH
R R R || =
L ON
ON
S TH
R R
R
V V
+
=
Thvenin replacement
+
B
v
TH
V
TH
R
GS
C
+
S
V
+
L
R
+
B
v
GS
C
ON
R
( )
( ) V
V v
S B
5
0 =
X
11
13
( )
GS TH
C R
t
TH S TH B
e V V V v

+ =
1 From
Falling decay t
f
is
the t for which v
B
falls to V
OL
( )
GS TH
f
C R
t
TH S TH OL
e V V V V

+ =
or
TH S
TH OL
GS TH f
V V
V V
C R t
= ln
12
13
TH S
TH OL
GS TH f
V V
V V
C R t
= ln
e.g.
5
1
ln 10 1 . 0 10
12
=
f
t
ps 6 . 1 =
! 1 ps RC =
K R
L
1 =
pF C
GS
1 . 0 =
V V
S
5 =
V V
OL
1 =
=10
ON
R
V V R
TH TH
0 , 10
13
13
For recitation: Slow may be better
Problem
pin 2
pin 1
chip
L
C
So the engineers decided to speed it up
made R
L
small
made R
ON
small
R
L
R
ON
ideal slow! observed
v:
v
14
13
For recitation: Slow may be better
Problem
pin 2
pin 1
chip
L
C
ideal slow! observed
but, disaster!
v:
v
expected
v:
V
IL
observed
15
13
Why? Consider
1 Case
1
R
0
R
pin1
ok
Demo
16
13
Why? Consider
2 Case
1
R
0
R
pin1
2
R
pin2
P
C
crosstalk!
Demo
model for crosstalk:
+
v
R
P
C
+

17
13
3 Case
6.002 expert saw the solution

Detailed analysis in recitation.
P
C
1
R
0
R
2
R
+
slower transitions!
6.002
CIRCUITS AND
ELECTRONICS
State and Memory
6.002 Fall 2000 Lecture 14
1
Review
Recall
v
I
C
+

R
+
v
C
v
I
=
V
I
for t

0
v
C
( )
0
t
v
C
=
V
I
+(
v
C
( )
V
I
)
e
RC
0
1
Reading: Section 10.3 and Chapter 11
2
This lecture will dwell on the
memory property of capacitors.
For the RC circuit in the previous slide
I
v
0
I
v
I
V
0 t

t
t
)
e
RC
t
0
Notice that the capacitor voltage for
t

0
is
independent of the form of the input voltage
before t
=
0 . Instead, it depends only on the
capacitor voltage at
t
=
0
, and the input voltage
for
t

0
.
3
C
v
I
V
( ) 0
C
v
(
I I C
V V v
+ = ( )
C
v 0
State
State : summary of past inputs relevant
to predicting the future
q = CV
for linear capacitors,
capacitor voltage V
is also state variable
state variable, actually
4
State
Back to our simple RC circuit
1
v
C
= f (v
C
(0), v
I
(t ))
t
v
C
= V
I
+(v
C
( ) V
I
) e
RC
0
Summarizes the past input relevant
to predicting future behavior
5
State
We are often interested in circuit
response for
zero state v
C
(0) = 0
zero input v
I
(t) = 0
Correspondingly,
zero state response or ZSR
t
v
C
= V
I
V
I
e
RC
zero input response or ZIR
t
v
C
= v
C
( )e
RC
0
2
3
6
One application of STATE
DIGITAL MEMORY
Why memory?
Or, why is combinational logic insufficient?
Examples
Consider adding 6 numbers on your
calculator
2 + 9 + 6 + 5 + 3 + 8
M+
Remembering transient inputs
7
A 1-bit memory element
Memory Abstraction
IN
d
OUT
d
store M
The
6.004
view
The
NEC
View

$

Remembers input when store goes high.
Like a camera that records input (d
IN
) when the
user presses the shutter release button.
The recorded value is visible at d
OUT
.
d
IN
store
d
OUT remembers the 1
8
Building a memory element
A First attempt
d
IN
*
storage
node
d
OUT
store
C
9
A
d
IN
*
v
C
d
OUT
C
store = 1
d
IN
*
v
C
d
OUT
Stored value leaks away
v
C
t
5V
V
OH
store = 0
C
R
L
t
T
v
C
= 5 e
R
L
C
from
T = R
L
C ln
V
OH
5
2
store pulse width >> R
ON
C
10
Second attempt buffer
B
R
IN
buffer
d
IN
d
OUT
C
*
store
Input resistance R
IN
T = R
IN
C ln
V
OH
5
R
IN
>> R
L
Better, but still not perfect.
Demo
11
C
Third attempt buffer + refresh
store
d
IN
store
d
OUT
C
*
Does this work?
No. External value can
influence storage node.
12
D
Fourth attempt buffer + decoupled
refresh
store
d
IN
store
d
OUT
C
*
Works!
13
A Memory Array
IN
4-bit memory
store
Address
OUT
Decoder
IN
d
OUT
d
S
IN
d
OUT
d
S
IN
d
OUT
d
S
IN
d
OUT
d
S
A
B
C
D
0 0
1 0
0 1
1 1
IN store
OUT
A
B
C
M
M
M
M
a
0
a
1
2
Address
D
14
Truth table for decoder
a
0
a
1
A C D
0 0 0 0
0 1 0 0
1 0 1 0
1 1 0 1
B
0 1
1 0
0 0
0 0
15
Agarwals top 10 list on memory
10 I have no recollection, Senator.
9 I forgot the homework was due today.
8 Adlibbing

ZSR
7 I think, therefore I am.
6 I think that was right.
5 I forgot the rest
16
1
15
6.002
CIRCUITS AND
ELECTRONICS
Second-Order Systems
2
15
C
A
B
5V
+
5V
C
GS
large
loop
2K
50
2K
Demo
Our old friend, the inverter, driving another.
The parasitic inductance of the wire and
the gate-to-source capacitance of the
MOSFET are shown
[Review complex algebra appendix for next class]
S
3
15
C
A
B
5V
+
5V
C
GS
large
loop
2K
50
2K
Demo
+
5V
C
GS
2K
B
L
Relevant circuit:
S
4
15
Now, lets try to speed up our inverter by
closing the switch S to lower the effective
resistance
t
v
A
5
0
v
B
0 t
v
C
0
t
Observed Output
2k
2k
5
15
t
v
A
5
0
v
B
0 t
v
C
0
t
Observed Output
~50
50
Huh!
6
15
v, i state variables
+
C
L
+
) (t v
) (t v
I
) (t i
Node method:
dt
dv
C t i = ) (
dt
dv
C dt v v
L
t
I
=

) (
1
2
2
) (
1
dt
v d
C v v
L
I
=
I
v v
dt
v d
LC = +
2
2
time
2
dt
di
L v v
I
=
i dt v v
L
t
I
=

) (
1
Recall
First, lets analyze the LC network
7
15
Recall, the method of homogeneous and
particular solutions:
( ) ( ) t v t v v
H P
+ =
1
2
3
Find the particular solution.
Find the homogeneous solution.
L
4 steps
The total solution is the sum of the
particular and homogeneous.
Use initial conditions to solve for the
remaining constants.
Solving
8
15
And for initial conditions
v(0) = 0 i(0) = 0 [ZSR]
I
v
0
V
0
t
Lets solve
I
v v
dt
v d
LC = +
2
2
For input
9
15
1 Particular solution
0
2
2
V v
dt
v d
LC
P
P
= +
0
V v
P
= is a solution.
10
15
0
2
2
= +
H
H
v
dt
v d
LC
Solution to
Homogeneous solution 2
Recall, v
H
: solution to homogeneous
equation (drive set to zero)
Four-step method:
D
t j
2
t j
1 H
o o
e A e A v

+ =
General solution,
Roots C
o
j s =
LC
1
o
=
Assume solution of the form
*
A
? s , A , Ae v
st
H
= =
so, 0
2
= +
st st
Ae e LCAs
*
Differential equations are commonly
solved by guessing solutions
1 = j
LC
j s
1
=
B
LC
s
1
2
=
characteristic
equation
11
15
Total solution 3
Find unknowns from initial conditions.
t j
2
t j
1 0
o o
e A e A V ) t ( v

+ + =
) ( ) ( ) ( t v t v t v
H P
+ =
0 ) 0 ( = v
2 1 0
0 A A V + + =
0 ) 0 ( = i
t j
o 2
t j
o 1
o o
e j CA e j CA ) t ( i

=
dt
dv
C t i = ) (
so,
o 2 o 1
j CA j CA 0 =
or,
2 1
A A =
A V 2
0
=
2
0
1
V
A =
( )
t j t j
0
0
o o
e e
2
V
V ) t ( v

+ = so,
12
15
Remember Euler relation
(verify using Taylors
expansion)
x j x e
jx
sin cos + =
x
e e
jx jx
cos
2
=
+

t sin CV ) t ( i
o o 0
=
t cos V V ) t ( v
o 0 0
= so, where
LC
1
o
=
Total solution 3
The output looks sinusoidal
13
15
) (t v
0
2V
0
V
0
2
2
3
2
t
o
) (t i
o 0
CV
0
2
2
3
2
t
o
o 0
CV
Plotting the Total Solution
14
15
Summary of Method
1
2
3
Write DE for circuit by applying
node method.
Find particular solution v
P
by guessing
and trial & error.
Find homogeneous solution v
H
4 Total solution is v
P
+ v
H
,
solve for remaining constants using
initial conditions.
Assume solution of the form Ae
st
.
Obtain characteristic equation.
Solve characteristic equation
for roots s
i
.
Form v
H
by summing A
i
e
s
i
t
terms.
D
C
A
B
15
15
What if we have:
We can obtain the answer directly from
the homogeneous solution (V
0
= 0).
V v
C
= ) 0 (
0 ) 0 ( =
C
i
C
L
C
i
+
C
v
Example
16
15
We can obtain the answer directly from
the homogeneous solution (V
0
= 0).
t j
2
t j
1 C
o o
e A e A ) t ( v

+ =
V v
C
= ) 0 (
0 ) 0 ( =
C
i
2 1
A A V + =
o 2 o 1
j CA j CA 0 =
or
2
2 1
V
A A = =
( )
t j t j
C
o o
e e
2
V
v

+ = or
t cos V v
o C
=
t sin CV i
o o C
=
V v
C
= ) 0 (
0 ) 0 ( =
C
i
C
L
C
i
+
C
v
Example
17
15
t
o
2
C
v
V
C
i
t
o
2
o
CV
o
CV
Example
18
15
2
2 2
2
1
2
1
2
1
CV Li Cv
C C
= + Notice
Energy
2
2
1
:
C
Cv C
2
2
1
:
C
Li L
t
o
2
C
E
2
2
1
CV
t
o
2
L
E
2
2
1
CV
Total energy in the system is a constant,
but it sloshes back and forth between the
Capacitor and the inductor
19
15
RLC Circuits
See A&L Section 13.2
add R
no R
+
C
R L
+
) (t v
) (t v
I
) (t i
) (t v
t
Damped sinusoids with R remember demo!
6.002
CIRCUITS AND
ELECTRONICS
Sinusoidal Steady State
16
1
Review
We now understand the why of:
5V
C
R
L
v
Today, look at response of networks
to sinusoidal drive.
Sinusoids important because signals can be
represented as a sum of sinusoids. Response to
sinusoids of various frequencies -- aka frequency
response -- tells us a lot about the system
16
2
Motivation
For motivation, consider our old friend,
the amplifier:
S
V
v
O
v
i
C
v
+

+

GS
C
R
V
BIAS
Observe v
o
amplitude as the frequency of the
input v
i
changes. Notice it decreases with
frequency.
Also observe v
o
shift as frequency changes
(phase).
Need to study behavior of networks for
sinusoidal drive.
Demo
16
3
Sinusoidal Response of RC Network
Example:
+

R
i
C
+
v
I
v
C

v
I
(t) = V
i
cost for t 0 (V
i
real)
= 0 for t < 0
v
C
(0) = 0 for t = 0
I
v
0
t
16
4
1
1
1
1
e
c
t
u
r
Example:
+

R
Our Approach
i
C
+
v
I
v
C
Determine v
C
(t)
I
n
d
u
lg
e
m
e
!
E
f
f
o
r
t
l
e
c
t
u
r
e

sneaky approach
very
sneaky
Usual
approach
agony
easy
t
e

0
:
0
:
0
0
2
1
0
:
2
l
s
h
i
T
t
x
e
N
16
5
Lets use the usual approach
1 Set up DE.
2 Find v
p
.
3 Find v
H
.
4 v
C
= v
P
+ v
H
, solve for unknowns
using initial conditions
16
6
Usual approach
1
Set up DE
RC
dv
C
+ v
C
= v
I
dt
= V
i
cost
That was easy!
16
7
2 Find v
p
RC
dv
P
+
dt
v
P
= V
i
cost
First try:
v
P
= A
nope
Second try:
v
P
= A cost
nope
Third try:
v
P
= A cos(
amplitude
+ t
frequency
)
phase
RCA sin(t +) + A cos(t +) = V
i
cost
RCA sin t cos RCA cost sin +
A cost cos Asint sin = V
i
cost
.
.
gasp !
.
works, but trig nightmare!
16
8
6.002 ll 2000 Lecture
9
16
Lets get sneaky!
Try solution
st
p PS
e V v =
st
i
st
p
st
p
e V e V
dt
e dV
RC = +
st
i
st
p
st
p
e V e V e sRCV = +
i p
V V ) 1 sRC ( = +
sRC 1
V
V
i
p
+
=
Nice
property
of
exponentials
IS PS
PS
v v
dt
dv
RC = + (S: sneaky :-))
st
i
e V =
Find particular solution to another input
p
V complex amplitude
Thus,
st
i
PS
e
sRC 1
V
v
+
=
st
i
e V is particular solution to
easy!
where we replace s = j
ly
t j
i
e V
solution for
t j
i
e
RC j
V

+ 1
Fa
2 Fourth try to find v
P

using the sneaky approach
Fact 1: Finding the response to
V
i
e
jt
was easy.
Fact 2: v
I
= V
i
cos t
= real[V
i
e
jt
] = real[v
IS
]
from Euler relation,
j
I
v
P
v
response
IS
v
PS
v
response
real
part
real
part
e
jt
= cost + sin t
an inverse superposition argument,
assuming system is real, linear.
16
10

2 Fourth try to find v
P

so, complex
P
v = Re[v
PS
] = Re[V
p
e
jt
]
V
i
= Re

1+ jRC
e
jt

= Re
V
i
(1 jRC)
e
jt

1+
2
R
2
C
2

= Re
C R 1
2 2 2
+
V
i
e
j
e
jt

, tan = RC
= Re
+
2 2 2
C R 1
V
i
e
j( t + )

v
P
=
C R 1
2 2 2
+
V
i
cos(t + )
Recall, v
P
is particular response to V
i
cost .
16
11
3 Find v
H
t
Recall, v
H
= Ae
RC
16
12
4 Find total solution
v
C
=
P
v + v
H
t

v
C
=
2 2 2
C R 1 +
V
i
cos( t + ) + Ae
RC
where = tan
1
( RC )
Given v
C
(0) = 0 for t = 0
so,
A =
1
2 2 2
C R +
V
i
cos()
Done! Phew!
16
13
We are usually interested only in the
particular solution for sinusoids,
i.e. after transients have died.
t
Notice when t , v
C
v
P
as e
RC
0
2 2 2
i
C
cos(
C R 1
V
+
=
tan where =
A =
p
V
RC
t
Ae ) t
+ +
) RC (
1

cos(
1
2 2 2

C R
V
i
+
0
v
)
Described as
SSS: Sinusoidal Steady State
p
V
16
14
All information about SSS is contained
in V
p
, the complex amplitude!
Recall
RC j 1
V
V
i
p
+
=
Steps 3 ,
were a waste of
time!
4
V
p
1
=
V
i
1+ jRC
V
p
2 2 2
i
C R 1
V
+
=
1
e
j
where
= tan
1
RC
2 2 2
1
1
C R
V
V
i
p
+
=
RC
V
V
i
p

1
tan : phase
=
magnitude
16
15
Visualizing the process of finding the
particular solution v
P
sneak
in
V
i
e
jt
drive
algebraic
equation
+
complex
algebra
take
real
part
t j
p
e V

particular
solution
t V
i
cos
D.E.
+
nightmare
trig.
drive
[
p
V t V + cos
p
]
the sneaky path!
16
16
Magnitude Plot
transfer function
V
H ( j) =
V
p
i
2 2 2
1
1
C R
V
V
i
p
+
=
V
p
1
V
i
log
scale

log
1
=
scale
RC
From demo: explains v
o
fall off
for high frequencies!
16
17
Phase Plot
= tan
1
RC
V
=
p
V
i
0
RC
1
=
log scale
16
18
1
17
6.002
CIRCUITS AND
ELECTRONICS
The Impedance Model
2
17
Sinusoidal Steady State (SSS)
Reading 14.1, 14.2
+
O
v t V v
i I
cos =
+
R
C
Focus on steady state, only care
about v
P
as v
H
dies away.
Focus on sinusoids.
Reading: Section 14.3 from course notes.
SSS
Review
Sinusoidal Steady State (SSS)
Reading 14.1, 14.2
3
17
3
4
H
v
total
Review
V
p
contains all the information we need:
p
p
V
V
Amplitude of output cosine

phase
sneak
in
V
i
e
jt
drive
complex
algebra
take
real
part
The Sneaky Path
p
V
t V
i
cos [ ]
p p
V t V + cos
set
up
DE
usual
circuit
model
nightmare
trig.
1
v
P
t j
p
e V

RC j
V
i
+ 1
2
4
17
i
p
V
V
transfer
function
( )
j H
RC j V
V
i
p
=
+
=
1
1
( )
p p O
V t V v + = cos
2 2 2
1
1
C R +
break frequency
Bode plot
RC
1
=
1
RC
1
2
1
remember
demo
RC
1
=
4
0
i
p
V
V
1
RC
tan
1

The Frequency View
Review
5
17
Is there an even simpler way
to get V
p
?
RC j
V
V
i
p
+
=
1
Divide numerator and denominator by jC.
R
C j
C j
V V
i p
+
=
1
1
Lets explore further
Hmmm looks like a voltage divider
relationship.
R Z
Z
V V
C
C
i p
+
=
6
17
The Impedance Model
Is there an even simpler way to get V
p
?
Consider:
t j
r R
e I i

=
t j
r R
e V v

=
R R
Ri v =
t j
r
t j
r
e RI e V

=
r r
RI V =
R
R
i
+
R
v
Resistor
t j
C C
e I i

=
t j
C C
e V v

=
C
C
i
+
C
v
Capacitor
C C
I
C j
1
V
=
dt
dv
C i
C
C
=
t j
C
t j
C
e j CV e I

=
C
Z
L
L
i
+
L
v
t j
l L
e I i

=
t j
l L
e V v

=
dt
di
L v
L
L
=
t j
l
t j
l
e j LI e V

=
Inductor
l l
I L j V =
L
Z
7
17
In other words,
For a drive of the form V
c
e
jt
,
complex amplitude V
c
is related to the
complex amplitude I
c
algebraically,
by a generalization of Ohms Law.
inductor
L j Z
l
=
l l l
I Z V =
l
I
+
l
V
L
Z
resistor
r r r
I Z V =
R Z
r
=
R
Z
r
I
+
r
V
capacitor
C j
1
Z
C
=
c C c
I Z V =
impedance
c
I
+
c
V
C
Z
The Impedance Model
8
17
Impedance model:
All our old friends apply!
KVL, KCL, superposition
Back to RC example
i
R C
C
i c
V
Z Z
Z
V
R
C j
1
C j
1
V
+
=
+
=
i c
V
RC j 1
1
V
+
=
Done!
+
C
v
I
v
+
R
C
+
c
V
i
V
+
R Z
R
=
C j
Z
C
1
=
c
I
9
17
Another example, recall series RLC:
We will study this and other functions
in more detail in the next lecture.
R
C j
L j
R V
V
i
r
+ +
=
1
R C L
R i
r
Z Z Z
Z V
V
+ +
=
CR j LC
CR j V
V
i
r

+ +
=
1
2
+
L
r
I
C
R
+
r
V
i
V
t j
r
e V

( )
r r
V t V + cos
t j
i
e V

t V
i
cos
Remember, we want only the steady-state
response to sinusoid
10
17
The Big Picture
t V
i
cos [ ]
p p
V t V + cos
set
up
DE
usual
circuit
model
nightmare
trig.
11
17
The Big Picture
t V
i
cos [ ]
p p
V t V + cos
set
up
DE
usual
circuit
model
nightmare
trig.
V
i
e
jt
drive
complex
algebra
take
real
part
12
17
The Big Picture
No D.E.s, no trig!
t V
i
cos [ ]
p p
V t V + cos
set
up
DE
usual
circuit
model
nightmare
trig.
V
i
e
jt
drive
complex
algebra
take
real
part
complex
algebra
impedance-based
circuit model
13
17
Back to
LC RC j 1
RC j
V
V
2
i
r

+
=
( )
( )
( ) RC j LC 1
RC j LC 1
RC j LC 1
RC j
2
2
2

+
=
( ) ( )
2
2
2
i
r
RC LC 1
RC
V
V

+
=
: Low RC
: High
L
R
: 1 LC = 1
Lets study this transfer function
+
L
r
I
C +
r
V
i
V
R
LC RC j 1
RC j
V
V
2
i
r

+
=
Observe
14
17
Graphically
( ) ( )
2
2
2
1 RC LC
RC
V
V
i
r

+
=
More next week
: Low RC
: High
L
R
: 1 LC = 1
i
r
V
V
LC
1

L
R
RC
1 Band Pass
Remember this trick to sketch the form of
transfer functions quickly.
1
18
6.002
CIRCUITS AND
ELECTRONICS
Filters
2
18
Review
+
C
v
I
v
+
R
C
Reading: Section 14.5, 14.6, 15.3 from A & L.
+
c
V
i
V
+
R
Z
C
Z
i
R C
C
c
V
Z Z
Z
V
+
=
RC j 1
1
R
C j
1
C j
1
V
V
i
c
+
=
+
=
3
18
A Filter
RC j 1
1
V
Z Z
Z
V
i
R C
C
c
+
=
+
=
Low Pass Filter
1
( )
i
c
V
V
H =
Demo
with audio
+
c
V
i
V
+
R
Z
C
Z
4
18
Quick Review of Impedances-
Just as
2 1
ab
ab
AB
R R
I
V
R + = =
L j R
I
V
Z
1
ab
ab
AB
+ = =
1
R
ab
I
+
ab
V
2
R
A
B
1
R
ab
I
+
ab
V
L j
A
B
5
18
Quick Review of Impedances
Similarly
L 2 C 1 AB
Z R || Z R Z + + =
L
2 C
2 C
1
Z
R Z
R Z
R +
+
+ =
L j
CR j 1
R
R
2
2
1

+
+
+ =
1
R
L
A
B
2
R C
6
18
We can build other filters by
combining impedances
( ) Z
L
R
C

Z
7
18
We can build other filters by
combining impedances
HPF
High Pass Filter
( ) H
( ) H
LPF
Low Pass Filter
( ) H
HPF
( ) Z
L
R
C
Z
+

8
18
Check out:
R
C j
1
L j
R
V
V
i
r
+ +
=
RC j LC 1
RC j
2

+
=
( ) ( )
2
2
2
i
r
RC LC 1
RC
V
V

+
=
L
C
R
+
r
V
i
V
LC
1
o
=
At resonance,
=
o
and
Z
L
+ Z
C
= 0,
so V
i
sees
only R!
More later
Intuitively:
i
r
V
V
1
C

b
lo
c
k
s

h
i
g
h

f
r
e
q

L

b
l
o
c
k
s

l
o
w

f
r
e
q

9
18
What about:
+
L
C
R
+

lc
V
i
V
Band Stop Filter
i
lc
V
V
1
C open
L open
Check out V
l
and V
c
in the lab.
10
18
Another example:
+
L
R
i
V
C
o
V
i
o
V
V
o

BPF
C

s
h
o
r
t
L

s
h
o
r
t
Application: see AM radio coming up shortly
11
18
AM Radio Receiver
crystal radio demo
Thvenin
antenna
model
+
L
R
i
V C
demodulator
amplifier
antenna
12
18
AM Receiver
Selectivity important
relates to a parameter Q for the filter. Next
+
L
R
i
V C
demodulator
amplifier
f
signal
strength
540 1000 1010 1020 1030 1600 KHz
10 KHz
filter
WBZ
News
Radio
13
18
Recall,
Selectivity:
Look at series RLC in more detail
+
L
C
R
+
r
V
i
V
C j
1
L j R
R
V
V
i
r
+ +
=
i
r
V
V
2
1
higher Q
1
Define quality factor
=
Q
o

bandwidth
Q high
more selective
14
18
=
o
Q
LC
1
o
=
Quality Factor Q
+
=
+ +
=
CR
1
R
L
j 1
1
C j
1
L j R
R
i
V
r
V
?

at =0
:
15
18
Note that abs magnitude is
2
1
when
1 j 1
1
CR
1
R
L
j 1
1
V
V
i
r
+
=
i.e. when
1
CR
1
R
L
=
0
LC
1
L
R
2
=
=
o
Q
Quality Factor Q
Looking at the roots of both equations,
LC
4
L
R
2
1
L 2
R
2
2
1
+ + =
LC
4
L
R
2
1
L 2
R
2
2
2
+ + =
L
R
= =
2 1

16
18
R
L
L
R
Q
o o

= =
The lower the R (for series R),
the sharper the peak
=
o
Q
Quality Factor Q
LC
1
o
=
17
18
Another way of looking at Q :
cycle per lost energy
stored energy
2 = Q
0
2
r
2
r
2
R I
2
1
I L
2
1
2
=
R
L
Q
o
=
Quality Factor Q
1
19
6.002
CIRCUITS AND
ELECTRONICS
The Operational Amplifier
Abstraction
2
19
MOSFET amplifier 3 ports
power
port
input
port
output
port
+
I
v
+
O
v
+
S
V
Amplifier abstraction
+
I
v
+
S
V
+
O
v
I
v
O
v
Function of v
I
Review
3
19
Can use as an abstract building block for
more complex circuits (of course, need
to be careful about input and output).
Today
Introduce a more powerful amplifier
abstraction and use it to build more
complex circuits.
Reading: Chapter 16 from A & L.
I
v
O
v
Function of v
I
Review
4
19
Operational Amplifier
Op Amp
OUT
v
+
IN
v
More abstract representation:
input
port
S
V
output
port
power
port
S
V
+

5
19
Circuit model (ideal):
i.e. input resistance
0 output resistance
A virtually
No saturation
O
v
Av
A
+
v
v
+
v
0 = i
+
0 = i

6
19
(Note: possible confusion with MOSFET saturation!)
Using it
+
V V
S
12 =
L
R
O
v
+
12V
+
12V
V V
S
12 =
Demo
IN
v
V 10 V 10
O
v
V 12
V 12
6
10 ~ A
but unreliable,
temp. dependent
saturation
active region
IN
v
7
19
Let us build a circuit
Circuit: noninverting amplifier
Equivalent circuit model
1
R
O
v
+
2
R
IN
v
+
v
v
( )
+
v v A
+
0 = i
+
0 = i
o
p

a
m
p
1
R
O
v
+
2
R
IN
v
+
+
v
v
8
19
Let us analyze the circuit:
Find v
O
in terms of v
IN
, etc.
What happens when A is very large?
( )
+
= v v A v
O
+
=
2 1
2
R R
R
v v A
O IN
IN
2 1
2
O
Av
R R
AR
1 v =
+
+
2 1
2
IN
O
R R
AR
1
Av
v
+
+
=
9
19
Lets see When A is large
Gain:
determined by resistor ratio
insensitive to A, temperature, fab variations
2 1
2
IN
O
R R
AR
1
Av
v
+
+
=
( )
2
2 1
IN
R
R R
v
+
gain
Demo
Suppose
6
10 A =
R 9 R
1
=
R R =
2
R R 9
R 10
1
v 10
v
6
IN
6
O
+
+

=
10 v v
IN O

10
1
10 1
v 10
6
IN
6
+

=
2 1
2
IN
R R
AR
Av
+

10
19
e.g. v
IN
= 5V
Suppose I perturb the circuit
(e.g., force v
O
momentarily to 12V somehow).
Stable point is when v
+
v
-
.
Key: negative feedback portion of
output fed to ve input.
e.g. Car antilock brakes
small corrections.
Why did this happen?
Insight:
+
R
IN O
v 2 v =
+
R
IN
v
+
v
v
negative
feedback
2
v
O
5V
5V
10V
0 i =
A
12V
6V
6V
11
19
Question: How to control a
high-strung device?
Antilock brakes
Michelin
no
yes
f
e
e
d
b
a
c
k
yes/no
is it
turning?
its
all about
control
d
i
s
c
v. v. powerful brakes
apply
release
12
19
More op amp insights:
Observe, under negative feedback,
0
A
v
R
R R
A
v
v v
IN
1
2 1
O
+
= =
+
+
v v
We also know
i
+
0
i
-
0
yields an easier analysis method
(under negative feedback).
13
19
Insightful analysis method
under negative feedback
+
1
R
O
v
+
2
R
IN
v
IN
v
c
2
2 1
IN O
R
R R
v v
+
=
g
IN
v
b
0 = i
e
2
IN
R
v
d
2
IN
R
v
f
0 i
0 i
v v
+
+
IN
v
a
14
19
Question:
+
O
v
+
IN
v
+
v
v
?
0
1
= R
=
2
R
2
2 1
R
R R
v v
IN O
+
= or
with
IN O
v v
IN
v
c
IN
v
b
IN
v
a
15
19
Buffer
voltage gain = 1
input impedance =
output impedance = 0
current gain =
power gain =
+
O
v
+
IN
v
IN O
v v
Why is this circuit useful?
1
20
6.002
CIRCUITS AND
ELECTRONICS
Operational Amplifier Circuits
2
20
Operational amplifier abstraction
Building block for analog systems
We will see these examples:
Digital-to-analog converters
Filters
Clock generators
Amplifiers
Adders
Integrators & Differentiators
Reading: Chapter 16.5 & 16.6 of A & L.
+
Review
input resistance
0 output resistance
Gain A very large
3
20
Consider this circuit:
+
=
v
R R
R
v v
2 1
2
1
1
2
R
v v
i

=
2
iR v v
OUT
=

2
1
2
R
R
v v
v
1
2
2
1
2
1
R
R
v
R
R
v
+ =

1
2
2
1
2 1
2 1
2
1
R
R
v
R
R R
R R
R
v
+
+
=
( )
2 1
1
2
v v
R
R
=
subtracts!
+
2
R
+
1
R
+
1
R
2
R
+
v
v
i
i
OUT
v
+
1
v
2
v
4
20
Another way of solving
use superposition
1
2 1
1
R
R R
v v
OUT
+
=
+
1
2 1
2 1
2 1
R
R R
R R
R v +
=
1
2
1
R
R
v =
2
1
2
2
v
R
R
v
OUT
=
+
2 1
|| R R
+
1
R
2
R
2
OUT
v
2
v
+
1
R
2
R
1
OUT
v
1
v
2
R
+
v
1
R
2 1
OUT OUT OUT
v v v + =
( )
2 1
1
2
v v
R
R
=
0
1
v 0
2
v
Still subtracts!
5
20
Lets build an intergrator
dt i
C
1
v
t
O

=
Lets start with the following insight:
v
O
is related to dt i
I
v
+
O
v
+

dt
i
+
i
+
O
v
C
But we need to somehow convert
voltage v
I
to current.
6
20
But, v
O
must be very small compared
to v
R
, or else
R
v
i
I
When is v
O
small compared to v
R
?
First try use resistor
i
R
v
I
O
O
v
dt
dv
RC >> when
I
O
v
dt
dv
RC
dt v
RC
1
v
t
I O

or
I O
O
v v
dt
dv
RC = +
R
v
larger the RC,
smaller the v
O
for good
integrator
RC >> 1
I
v
+
i
+
O
v
C
R
v
+

R
Demo
7
20
Theres a better way
R
v
i
I
=
so,
+
R
I
v
+
R
R
v
I
I
v
C
v
+

+
O
v
i
i
under negative feedback V 0 v
Notice
C O
v v =
dt
R
v
C
1
v
t
I
O

=
We have our integrator.
+

8
20
Now, lets build a differentiator
I
v
+
O
v
+
dt
d
But we need to somehow convert current
to voltage.
i is related to
dt
dv
I
Lets start with the following insights:
dt
dv
C i
I
=
+
I
v
i
C
9
20
Demo
C I
v v =
dt
dv
C i
I
=
dt
dv
RC v
I
O
=
Recall
+
i
i
current
to
voltage
iR v
O
=
V 0
+
R
I
v +

O
v
C
C
v
i
Differentiator
+
i
+
R
v
O
1
21
6.002
CIRCUITS AND
ELECTRONICS
Op Amps Positive Feedback
2
21
Consider this circuit negative feedback
+
1
R
1
R
v
IN
IN
v
+
IN OUT
v
R
R
v
1
2
=
2
R
Whats the difference?
Consider what happens when there is a pertubation
Positive feedback drives op amp into saturation:
S OUT
V v
and this positive feedback
+
1
R
IN
v
+
2
R
IN OUT
v
R
R
v
1
2
=

s
e
e

a
n
a
l
y
s
i
s
o
n

n
e
x
t

p
a
g
e
Negative vs Positive Feedback
3
21
+
1
R
IN
v
2
R
OUT
v
( )
+
= v v A v
OUT
+
+
=
IN 1
2 1
IN OUT
v R
R R
v v
A
IN
2 1
IN 1
OUT
2 1
1
Av
R R
v AR
v
R R
AR
+
+
+
=
+
= Av
IN
1
2
IN
2 1
1
2 1
1
OUT
v
R
R
Av
R R
AR
R R
R
1
v =
+
=
2 1
1
IN
2 1
1
OUT
R R
R
1 A v
R R
AR
1 v
+
1
R
IN
v
2
R
OUT
v
+
v
v
( )
+
v v A
+
Static Analysis of Positive Feedback Ckt

4
21
Representing dynamics of op amp
+
v
v
o
v
*
Av
+
*
v
) (
+
v v
R
C
+

5
21
Representing dynamics of op amp
Consider this circuit and lets analyze its
dynamics to build insight.
+
1
R
2
R
o
v
3
R
4
R
Lets develop equation representing time
behavior of v
o
.
Circuit model
1
R
2
R
3
R
4
R
+
*
v
) (
+
v v
R
C
+
o
v
+
v
v
A
v
o
6
21
A
v
v Av v
o
o
= =
* *
or
) ( A
RC
T where 0
T
v
dt
dv
o o
+
= = + or
o
o
v
R R
R v
v
+
=
+
=
+
2 1
1
o
o
v
R R
R v
v

=
+
=
4 3
3
0 ) ( =
+
+
o
o
v
RC
A
dt
dv
1
time
0 ) (
1
=
+ +
o
o
v
RC
A
RC dt
dv
or
neglect
_ *
*
v v v
dt
dv
RC = +
+
o
v ) (

+
=
Dynamics of op amp
_
v v
A
v
dt
dv
A
RC
o o
= +
+
0 ) 0 ( v
o
=
7
21
Consider a small disturbance to v
o
(noise).
Now, lets build some useful circuits with
positive feedback.
+
>
if
stable e K v
positive is T
T
t
o

=
>
+
if
unstable e K v
negative is T
T
t
o
=
=
+
if
neutral K v
large very is T
o
=
o
v
t
neutral
stable
K
disturbance
unstable
8
21
One use for instability: Build on the
basic op amp as a comparator
+
+
v
o
v
S
V +
S
V
v
+
v v
o
v
S
V +
S
V
0
t
0 v
+
v
o
v
9
21
Now, use positive feedback
+
2
R
o
v
1
R
i
v
2 1
1
R R
R v
v
o
+
=
+
5 . 7 v =
+
5 . 7 v =
15 v
o
=
15 v
o
=
15
e.g.
2 1
=
=
S
V
R R
5 . 7 v
5 . 7 ) v v (
i
>
> =
5 . 7 <
<
+
v
v v
i
v
10
21
Now, use positive feedback
+
2
R
o
v
1
R
i
v
2 1
1
R R
R v
v
o
+
=
+
2 1
1
R R
R V
v
S
+
=
+
2 1
1
R R
R V
v
S
+
S o
V v + =
15
S o
V v =
15
15
e.g.
2 1
=
=
S
V
R R
5 . 7 v
v ) v v (
i
>
> =
+
5 . 7 <
<
+
v
v v
i
v
11
21
Why is hysteresis useful?
e.g., analog
to digital
o
v
i
v
S
V
S
V
0 5 . 7 5 . 7
15
15
hysteresis
Demo
Demo
t
i
v
5 . 7
5 . 7
o
v
12
21
Without hysteresis
analog
to digital
t
i
v
5 . 7
5 . 7
i
v
o
v
13
21
Oscillator can create a clock
Demo
+
R
C
v
1
R
1
R
o
v
2
o
v
C
0
0 at
=
= =
C
S o
v
t V v Assume
t
S
V
S
V
2
S
V
2
S
V
o
v
+
v
+
v
v
C
v
v
C
v
14
21
We built an oscillator using an op amp.
t
Why do we use a clock in a digital system?
(See page 735 of A & L)
sender receiver
1 1 0
a 1,1,0?
b When is the signal valid?
Discretization of time
one bit of information associated with
an interval of time (cycle)
Clocks in Digital Systems
can use as a clock
common timebase -- when to look at a signal
(e.g. whenever the clock is high)
clock
1
22
6.002
CIRCUITS AND
ELECTRONICS
Energy and Power
2
22
Why worry about energy?
small batteries
good
Today:
How long will the battery last?
in standby mode
in active use
Will the chip overheat and self-destruct?
-
3
22
Look at energy dissipation in
MOSFET gates
Let us determine
standby power
active use power
Lets work out a few related examples first.
C: wiring capacitance and
C
GS
of following gate
V
S
C
R
O
v
+
I
v
+

4
22
Example 1:
Power
Energy dissipated in time T
R
V
VI P
2
= =
VIT E =
+
R
I
V
+
V
5
22
Example 1:
for our gate
ON L
S
R R
V
P
+
=
2
0 = P
O
v
S
V
ON
R
L
R
I
v high
S
V
ON
R
L
R
O
v
I
v
low
6
22
Example 2:
Consider
Find energy dissipated in each cycle.
Find average power .
P
S
V
+
1
R
C
2
R
1
S
2
S
open S
closed S
2
1
t
closed S
open S
2
1
1
T
2
T
T
7
22
T
1
: S
1
closed, S
2
open
t
C
v
S
V
C R
t
1
S
1
e
R
V

t
i
1
S
R
V
+
C
v
+
1
R
C
S
V
i
assume
v
C
= 0 at t = 0
8
22
Total energy provided by source during T
1
dt i V E
1
T
0
S
=
dt e
R
V
C R
t
T
0
1
2
S
1
1

=
1
1
T
0
C R
t
1
1
2
S
e C R
R
V

=
|
|
.
|
\
|
=

C R
T
2
S
1
1
e 1 V C
1
2
S 1
2
S
R in dissipated V C
2
1
E
, C on stored V C
2
1
=
C R T if V C
1 1
2
S
>>
I.e., if we wait long enough
Independent
of R!
9
22
T
2
: S
2
closed, S
1
open
+
C
v
2
R
C
So, initially,
2
S
CV
2
1
= energy stored in capacitor
Assume T
2
>> R
2
C
So, capacitor discharges ~fully in T
2
So, energy dissipated in R
2
during T
2
2
S 2
CV
2
1
E =
E
1
, E
2
independent of R
2
!
Initially, v
C
= V
S
(recall T
1
>> R
1
C)
10
22
Putting the two together:
Energy dissipated in each cycle
2
S
2
S
CV
2
1
CV
2
1
+ =
2 1
E E E + =
C g dischargin & charging
in dissipated energy CV E
2
S
=
Assumes C charges and discharges fully.
frequency
T
f
1
=
T
E
P =
T
CV
S
2
=
f CV
S
2
=
Average power
11
22
Back to our inverter
O
v
IN
v
C
S
V
L
R
ON
R
t
2
T
T
2
T
IN
v
f
T
1
=
What is for the following input? P
12
22
Equivalent Circuit
S
V
+
L
R
C
ON
R
t
2
T
T
2
T
IN
v
f
T
1
=
What is for the following input? P
13
22
We can show (see section 12.2 of A & L)
( )
( )
2
ON L
2
L
2
S
ON L
2
S
R R
R
f CV
R R 2
V
P
+
+
+
=
f CV
R 2
V
P
2
S
L
2
S
+ =
when R
L
>> R
ON
What is for gate? P
r
e
m
e
m
b
e
r
r
e
m
e
m
b
e
r
STATIC
P
DYNAMIC
P
related to switching
capacitor
independent of f.
MOSFET ON half
the time.
14
22
f CV
R
V
P
S
L
S
2
2
2
+ =
when R
L
>> R
ON
In standby mode,
half the gates in a
chip can be
assumed to be on.
So per
gate is still .
Relates to standby
power.
STATIC
P
L
2
S
R 2
V
What is for gate? P
In standby mode,
f 0 ,
so dynamic power
is 0
15
22
Some numbers
a chip with 10
6
gates clocking
at 100 MHZ
V 5 V
10 100 f
k 10 R
F f 1 C
S
6
L
=
=
=
=
(
=
6 15
4
6
10 100 25 10
10 2
25
10 P
| | microwatts 5 . 2 milliwatts 25 . 1 10
6
+ =
problem!
1.25KW! 2.5W
not bad
mW 150 W 5 . 2
V 1 V 5
V reduce
f
V
S
2
S
next
lecture
must get rid of this
1
23
6.002
CIRCUITS AND
ELECTRONICS
Energy, CMOS
2
23
Reading: Section 12.5 of A & L.

S
V
+
1
R
C
2
R
1
S
2
S
f
T T T
1
2 1
= + =
f CV P
S
2
=
T
1
: closed
T
2
: open
open
closed
ON L
S
R R
V
P
+
=
2
O
v
S
V
ON
R
L
R
I
v
Review
3
23
Inverter
O
v
I
v
C
S
V
L
R
ON
R
f CV
R
V
P
S
L
S
2
2
2
+ =
related to switching
capacitor.
independent of f.
MOSFET ON half
the time.
STATIC
P
DYNAMIC
P
constant time
" RC "
2
T
R R
ON L
>>
>>
Square wave input
f
T
1
=
Demo
Review
In standby mode, half
the gates in a chip can
be assumed to be on.
So per gate is
still .
STATIC P
L
2
S
R 2
V
In standby mode,
f 0 ,
so dynamic power is 0
4
23
f CV
R
V
P
S
L
S
2
2
2
+ =
Chip with 10
6
gates clocking at 100 MHz
V 5 V , 10 100 f , K 10 R F, f 1 C
S
6
L
= = = =
problem!
1.25KWatts 2.5Watts
not bad
+
independent of f
also standby power
(assume MOSFETs
ON if f 0)
must get rid of this!
f
V
S
2
reduce V
S
5V1V
2.5V150mW
[ ] watts 5 . 2 milliwatts 25 . 1 10
6
+ =
+

=
6 2 15
3
2
6
10 100 5 10
10 10 2
5
10 P
gates
Review
5
23
How to get rid of static power
Intuition:
O
v
S
V
ON
R
L
R
I
v high low
i
idea!
O
v
S
V
I
v high low
S
V
L
R
O
v
I
v
low
off
MOSFET
high
6
23
New Device PFET
N-channel MOSFET (NFET)
D
S
G
on when v
GS
V
TN
off when v
GS
< V
TN
e.g. V
TN
= 1V
P-channel MOSFET (PFET)
on when v
GS
V
TP
off when v
GS
> V
TP
e.g. V
TP
= -1V
S
D
G
ON when
less than 4V
5V
7
23
S
D
G
D
S
G
O
v
I
v
+
S
V
PU = pull up
PD = pull down
works like an inverter!
IN OUT
8
23
v
I
= 0V (input low)
V 5
v
O
=
V 5 V
S
=
V 0 v
I
=
+
p
ON
R
v
I
= 5V (input high)
V 0
v
O
=
V 5 V
S
=
V 5 v
I
=
+
n
ON
R
Called CMOS logic
Complementary
MOS
(our previous logic was called NMOS)
works like an inverter!
IN OUT
9
23
O
v
I
v
S
V
C
t
T
I
v
T
f
1
=
From f CV P
S
2
=
Key: no path from V
S
to GND!
no static power!
Lets compute DYNAMIC
P
S
V
+
p
ON
R
C
n
ON
R
closed for
v
I
low
closed for
v
I
high
10
23
For our previous example
1 , MHz 100 f , V 5 V F, f 1 C
S
= = =
keep
all
else
same
f CV P
S
2
=
6 2 15
10 100 5 10 =

gate per watts 5 . 2 =
chip gate 10 for watts 5 . 2
6
= P
P
PIII?
~240
watts 1.2 GHz 8x10
6
PIV?
~1875
watts 3 GHz 25x10
6
PII?
~30
watts
600
MHz 2x10
6
PII?
~15
watts
300
MHz 2x10
6
Pentium?
~2.5
watts
100
MHz 10
6
f Gates
g
a
s
p
!
11
23
and use big heatsink
How to reduce power
A V
S
5V 3V 1.8V 1.5V
~PIV 170 watts better, but high
next time:
power supply
B Turn off clock when not in use.
C Change V
S
depending on need.
12
23
CMOS Logic
NAND:
Z A B
0 0 1
0 1 1
1 0 1
1 1 0
S
D
G
V 0
on
V 5
S
D
G
V 5
off
V 5
A
S
V
B
A B
Z
13
23
B A B A F + = = e.g.
In general, if we want to implement F
short when
A = 0 or B = 0,
open otherwise
short when
A B is true,
else open
A
B
short
when F
is true,
else open
S
V
Z
short
when F
is true,
else open
r
e
m
e
m
b
e
r
D
e
M
o
r
g
a
n
s
l
a
w
1
24
6.002
CIRCUITS AND
ELECTRONICS
Power Conversion Circuits
and Diodes
2
24
Power Conversion Circuits (PCC)
Power efficiency of converter important,
so use lots of devices:
MOSFET switches, clock circuits,
inductors, capacitors, op amps, diodes
Reading: Chapter 17 of A & L.
PCC
110V
60Hz
+
5V DC
solar cells,
battery
PCC
+
5V DC
3V
DC
DC-to-DC UP converter
R
3
24
First, lets look at the diode
Can use this exponential model with
analysis methods learned earlier
analytical graphical incremental
(Our fake expodweeb was modeled after this device!)
D
v
D
i
D
v
D
i
S
I mV
V
D
v
+
D
i
= 1 e I i
T
D
V
v
S D
A 10 I
12
S

=
V 025 . 0 V
T
=
q
T k
V
T
=
Boltzmanns constant
temperature in Kelvins
charge of an electron
4
24
Another analysis method:
piecewiselinear analysis
PL diode models:
D
v
D
i
0
Ideal diode model
i
D
= 0
open
or
off
v
D
< 0
v
D
= 0
short
or
on
i
D
0
5
24
D
v
D
i
V 6 . 0
0 v
D
=
0 i
D
=
Practical diode model
ideal with offset
V 6 . 0
+

Open segment
Short segment
6
24
Replace nonlinear characteristic with
linear segments.
Perform linear analysis within each
segment.
Piecewiselinear analysis method
7
24
(We will build up towards an AC-to-DC converter)
R
O
v
+
I
v
V 6 . 0
+
Example
Consider
v
I
is a sine wave
8
24
0 v
O
=
0 i
D
=
Open segment:
R
+
I
v
+
V 6 . 0
6 . 0 v
I
<
R
O
v
+
I
v
( ) R / 6 . 0 v i
I D
=
6 . 0 v v
I O
=
Short segment:
R
+
V 6 . 0
6 . 0 v
I

I
v
Example
V 6 . 0
+
Equivalent
circuit
9
24
Example
t
6 . 0
I
v
O
v
10
24
Now consider a half-wave rectifier
I
v
R
O
v
+
V 6 . 0
+
C
11
24
A half-wave rectifier
t
diode on diode off
C
current
pulses
charging
capacitor
MITs supply shows
snipping at the peaks
(because current drawn
at the peaks)
I
v
O
v
Demo
12
24
DC-to-DC UP Converter
The circuit has 3 states:
I. S is on, diode is off
i increases linearly
II. S turns off, diode turns on
C charges up, v
O
increases
III. S is off, diode turns off
C holds v
O
(discharges into load)
t
S
v
S
closed
S
open
T
p
T
O
v
+
DC
I
V
C
S
v
load
i
switch
S
D
o
n
o
t
u
s
e
r
e
s
is
t
iv
e
e
le
m
e
n
t
s
!
13
24
More detailed analysis
I. Assume i(0) = 0, v
O
(0) > 0
S on at t = 0, diode off
+
I
V
C
i
L
O
v
t
i
L
T V
T i
I
= ) (
T
dt
di
L V
I
=
i is a ramp
L
V
I
= slope
2
) T ( Li
2
1
: T t at stored energy E = =
L
T V
E
I
2
2
2
=
14
24
II. S turns off at t = T
diode turns on (ignore diode voltage drop)
+
I
V
C
L
O
v
S
i
Diode turns off at T when i tries to go negative.
t
i
T
0
L
T V
I
LC
O
1
=
T
P
T
State III starts here
15
24
II. S turns off at t = T, diode turns on
Diode turns off at T when I tries to go negative.
LC
O
1
=
ignore
diode
drop
) (T v
O
O
v
T
t
T
0
Capacitor voltage
P
T
O
v
t
i
T
0
L
T V
I
T
P
T
LC
O
1
=
III.
Lets look at the voltage profile
16
24
II. S turns off at t = T, diode turns on
Diode turns off at T when I tries to go negative.
LC
O
1
=
ignore
diode
drop
) (T v
O
O
v
T
t
T
0
Capacitor voltage
P
T
O
v
t
i
T
0
L
T V
I
T
P
T
LC
O
1
=
III.
Lets look at the voltage profile
17
24
C holds v
O
after T
i is zero
+
I
V
C
S
O
v
+
Eg, no load
O
v
T
t
0
Capacitor voltage
P
T
18
24
C holds v
O
after T
i is zero
until S turns ON at T
P
, and cycle repeats
I II III I II III
Thus, v
O
increases each cycle, if there is no load.
t
O
v
) (n v
O
P
T 2
P
T 3
+
I
V
C
S
O
v
+
Eg, no load
P
T
19
24
What is v
O
after n cycles v
O
(n) ?
Use energy argument (KVL tedious!)
Each cycle deposits E in capacitor.
2
) T t ( i L
2
1
E = =
2
I
L
T V
L
2
1
=
L
T V
2
1
E
2
2
I
=
After n cycles, energy on capacitor
L 2
T nV
E n
2
2
I
=
This energy must equal
2
O
) n ( Cv
2
1
or
LC
T nV
) n ( v
2
2
I
O
=
LC
1
O
=
n T V ) n ( v
O I O
=
so,
L 2
T nV
) n ( Cv
2
1
2
2
I
2
O
=
20
24
How to maintain v
O
at a given value?
recall
L
T V
E
I
2
2
2
=
Another example of negative feedback:
( )
( )

T v v
T v v
ref O
ref O
then if
then if
O
v
+
I
V
load
control
change T
T
p
T
pwm
+
ref
v
compare
O
v
1
25
6.002
CIRCUITS AND
ELECTRONICS
Violating the Abstraction Barrier
2
25
Case 1: The Double Take
Problem
R
i
V
O
V
0 1
t
O
V
0
1
t
O
V
0
1
observed expected
in forbidden region!
huh?
3
25
(a) DC case
R
i
V
O
V
1
V
very high
impedance,
like open
circuit
OK
DC V 5 V
i
=
DC V 5 V
O
=
DC V 5 V
1
=
4
25
t
V 5 . 2 =
O
V
t
i
V
(b) Step
not ok!
t
1
V
looks ok!
b.1
b.3
b.2
V 0
V 5
0 = t
0 = t
0 = t T
T 2
V 5
V 5
R
i
V
O
V
1
V
very high
impedance,
like open
circuit
O
V
5
25
R
i
V
. . . .
instantaneous R divider
finite propagation speed
of signals
characteristic
impedance
R
T 2
T
5
2.5
0
V 5
0
V 5
0
V 5
6
25
Question: So why did our circuits work?
More in 6.014
t
V 5
V 5 . 2
3. Termination
P
a
r
a
l
l
e
l
t
e
r
m
i
n
a
t
i
o
n
D
E
M
O
a
d
d

R

a
t

t
h
e
e
n
d
0
V
O
2. Keep wires short
t
V 5
0
0
V
O
D
E
M
O
u
s
e

s
m
a
l
l

w
i
r
e
S
o
u
r
c
e
T
e
r
m
i
n
a
t
i
o
n
1. Look only at V
1
t
0 T
V 5
0
V
1
D
E
M
O
7
25
Case 2: The Double Dip
Problem strange spikes on supply
driving a 50
resistor!
V
0
1
0
1
OK
Why?
input
driving a 50
resistor!
V
0
8
25
V
dt
Ldi
Drop across inductor
Inverter current
v inductor
solution 1. short wires
2. low inductance wires
3. avoid big current swings
V
S
V
S
9
25
Case 3: The Double Team, or,
Slower may be faster!
Problem
a given chip
worked,
but was slow.
Lets try speeding it up by using stronger
drivers
actual
ideal
ideal
C
Disaster!
L
actual
10
25
Why?
Consider
crosstalk!
1
R
0
R
DEMO
2
R
C
dt
dV
DEMO
ok
dt
dV
C
11
25
How does this relate to chip?
Load output!
put cap on outputs of chip
jitter edges
slew edges
dt
dV
small
DEMO
Solution
12
25
Case 4: The Double Jump
Careful abstraction violation for the
better
Recall
o
V
i
V
o
V
i
V
expect
but, observe
o
V
i
V
13
25
Case 4: The Double Jump
Careful abstraction violation for the
better
i
V
V 5
5V
0V
3V 5V+
3V
So, pullup has
stronger drive
as output rises

Circuits and Elektroniks

Uploaded by

Copyright:

Available Formats

Circuits and Elektroniks

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Circuits and Elektroniks

Uploaded by

Copyright:

Available Formats

6.

Simple amplifier abstraction

6.002 Fall 2000 Lecture

Surprisingly, these rules (along with superposition, which

6.002 Fall 2000 Lecture

6.002 Fall 2000 Lecture

6.002 Fall 2000 Lecture

6.002 Fall 2000 Lecture

6.002 Fall 2000 Lecture

Bulb C is ON if A AND B are ON,

New type of device: Dependent source

6.002 Fall 2002: Lecture 8

6.002 Fall 2002: Lecture 8

6.002 Fall 2000 Lecture

6.002 Fall 2000 Lecture

6.002 expert saw the solution

Amplitude of output cosine

6.002 Fall 2000 Lecture

6.002 Fall 2000 Lecture

6.002 Fall 2000 Lecture

6.002 Fall 2000 Lecture

6.002 Fall 2000 Lecture

Static Analysis of Positive Feedback Ckt

6.002 Fall 2000 Lecture

6.002 Fall 2000 Lecture

Reading: Section 12.5 of A & L.

Another analysis method:

You might also like