Physical Slot Page 13-16

Alcatel-Lucent GSM
9130 BSC Evolution Hardware

Description
BSC & TC Document

Sub-System Description
Release B10
3BK 21280 AAAA TQZZA Ed.08

BLANK PAGE BREAK
Status RELEASED
Short title 9130 BSC Evolution HW Description

All rights reserved. Passing on and copying of this document, use
and communication of its contents not permitted without written
authorization from Alcatel-Lucent.
2 / 138 3BK 21280 AAAA TQZZA Ed.08

Contents
Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1 Cabinet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2 Subracks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3 Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3.1 Alcatel-Lucent 9130 BSC Evolution Naming Conventions . . . . . . . . . . . . . . . . . . 13
1.3.2 Stand Alone Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3.3 Rack Shared Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.3.4 Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2 Cabinet Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.1 Layout and Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2 Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3 Dimensions and Weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4 Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4.1 Temperature and Humidity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4.2 Atmospheric Pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4.3 Solar Radiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4.4 Dust and Particles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.4.5 Lighting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.4.6 Cooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.4.7 Green Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3 Power System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1 Power Distribution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1.2 Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1.3 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1.4 Power Station Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1.5 Connection to the Hosted Shelves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.6 Earthing Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.7 Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.8 Provision for Future Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.9 JSXPDU Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.10 Power Distribution Cable Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2 Cooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4 ATCA Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1 ATCA Shelf Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.1.1 Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1.2 Node Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.3 Hub Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.4 Rear Transition Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.5 Power Entry Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.6 Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.7 Blowers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1.8 Shelf Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1.9 Personality Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1.10 Air Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1.11 Backplane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.1.12 Distribution Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.1.13 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.2 JBXOMCP/JBXCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2.2 Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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Contents
4.2.3 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2.4 Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.2.5 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.3 JBXSSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.3.2 Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.3.3 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.3.4 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.3.5 Reset Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.3.6 Backplane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.4 JAXSSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.4.1 Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.4.2 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.4.3 Ethernet Uplink Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.5 JBXTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.5.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.5.3 Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.5.4 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.5.5 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.6 JBXTP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.6.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.6.3 Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.6.4 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.6.5 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.7 JAXSMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.7.2 Payload Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.7.3 Shelf Management Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.7.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.7.5 Frame Ground and ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.7.6 Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.7.7 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.7.8 Ethernet Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.8 JAXPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.8.2 Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.8.3 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.8.4 Alarm I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.8.5 Handle Toggle Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.8.6 Alarm Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.8.7 Shelf Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.9 JBXPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.9.1 JBXPS Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.9.2 Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.9.3 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.9.4 Handle Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.10 JBXFAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.10.1 Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.10.2 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.10.3 Handle Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.11 ATCA Fillers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.11.1 JBXFILL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.11.2 JAXFILL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5 JSXLIU/JSXLIUB Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.1 JSXLIU/JSXLIUB Shelf Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
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5.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

5.1.2 Shelf Position in the System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.1.3 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.1.4 Mechanical Housing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.1.5 JSXLIU/JSXLIUB Shelf Internal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.2 JBXLIU/JBLIU75 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.2.2 Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.2.3 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.2.4 Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.2.5 Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.3 JBXMUX Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.3.2 JBXMUX Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.3.3 Front Panel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.3.4 Backplane Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.3.5 Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.3.6 Power Supply Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.3.7 Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.4 JBXPEM Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.4.2 JBXPEM Architecture and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.4.3 Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.4.4 Back Plane Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
5.4.5 Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.5 Dummy Panel (JBXDUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.6 LIU Filler (JMXF1U) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.7 LIUB Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
3BK 21280 AAAA TQZZA Ed.08 5 / 138

Figures
Figures
Figure 1: Alcatel-Lucent 9130 BSC Evolution 1000 TRX Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 2: Alcatel-Lucent 9130 BSC Evolution Rack Shared by Two BSCs Configuration . . . . . . . . . . . . . . . . 18
Figure 3: Cabinet Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 4: Alcatel-Lucent 9130 BSC Evolution Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5: JSXPDU Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 6: JSXPDU Front View and Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 7: Shelf Airflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 8: Block Diagram of a Blower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9: ATCA Shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 10: ATCA Subrack Front View for Variants Before 3BK 27291 ABxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 11: ATCA Subrack Front View from Variant 3BK 27291 ABxx On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12: ATCA Subrack Back View for Variants Before 3BK 27291 ABxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 13: ATCA Subrack Back View from Variant 3BK 27291 ABxx On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 14: Low Power Distribution System for Shelf Variants Before 3BK 27291 ABxx . . . . . . . . . . . . . . . . . . 40
Figure 15: Low Power Distribution System from Shelf Variant 3BK 27291 ABxx On . . . . . . . . . . . . . . . . . . . . 41
Figure 16: High Power Distribution System for Shelf Variants Before 3BK 27291 ABxx . . . . . . . . . . . . . . . . . 42
Figure 17: High Power Distribution System from Shelf Variant 3BK 27291 ABxx On . . . . . . . . . . . . . . . . . . . . 44
Figure 18: JBXOMCP/JBXCCP Front Plate Before JBXOMCP Version 3BK 27236 AACA and JBXCCP
Version 3BK 27231 AACA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 19: JBXOMCP/JBXCCP Front Plate from JBXOMCP Version 3BK 27236 AACA and JBXCCP Version
3BK 27231 AACA On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 20: Location of Front Plate LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 21: Location of Reset Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 22: Location of USB Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 23: Blade Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 24: JBXSSW Front Plate Before JBXSSW Version 3BK 27237 AACA . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 25: JBXSSW Front Plate from JBXSSW Version 3BK 27237 AACA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 26: JBXSSW LED Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 27: Base Interface LED Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 28: Connector Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 29: Reset Key Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 30: Front Plate for JAXSSW Before Version 3BK 27235 AACA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 31: Front Plate for JAXSSW from Version 3BK 27235 AACA On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 32: JAXSSW Front Plate LEDs and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 33: BSC Global Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 34: JBXTP Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 35: BSC Global Architecture with JBXTP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 36: JBXTP3 Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 37: JAXSMM Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6 / 138 3BK 21280 AAAA TQZZA Ed.08

Figures
Figure 38: JAXSMM Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 39: JAXPC Hardware for Board Variant Before 3BK 27226 AACA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 40: JAXPC Hardware from Board Variant 3BK 27226 AACA On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 41: JAXPC Front Panel for Board Variant Before 3BK 27226 AACA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 42: JAXPC Front Panel from Board Variant 3BK 27226 AACA On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 43: Rotary Switches on JAXPC Board Variant Before 3BK 27226 AACA . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 44: Rotary Switches on JAXPC Board from Variant 3BK 27226 AACA On . . . . . . . . . . . . . . . . . . . . . . 95
Figure 45: JBXPS Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 46: JBXPS Front Plate for Variants Before 3BK 27342 AACA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 47: JBXPS Front Plate from Variant 3BK 27342 AACA On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 48: JBXFAN Front Plate for Variants Before 3BK 27352 AACA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 49: JBXFAN Front Plate from Variants 3BK 27352 AACA On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 50: JBXFILL View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 51: JAXFILL View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 52: JSXLIU/JSXLIUB Shelf in the BSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 53: JSXLIU/JSXLIUB Shelf Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 54: JSXLIU/JSXLIUB Shelf Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 55: LIU Hosted Strips and Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 56: JSXLIU/JSXLIUB Shelf Back-Plane Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 57: Platform Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 58: JBXLIU/JBLIU75 Board Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 59: JBXLIU/JBLIU75 Board Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 60: LIU Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 61: JBXMUX Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 62: 1000 Base-T RJ45 Connector Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 63: JBXMUX Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 64: ESD Mitigation Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 65: JBXPEM Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 66: JBXPEM Board Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 67: JBXPEM Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 68: JBXPEM Side View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 69: JBXDUM Front and Side Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 70: JMXF1U Front View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 71: JSXLIUB Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
3BK 21280 AAAA TQZZA Ed.08 7 / 138

Figures
8 / 138 3BK 21280 AAAA TQZZA Ed.08

Preface
Preface
Purpose The Alcatel-Lucent 9130 BSC Evolution Hardware Description describes the
cabinets, subracks and modules of the 9130 BSC Evolution.
What’s New In Edition 08

Description improvement in:
ATCA Shelf (Section 4)
JBXOMCP/JBXCCP (Section 4.2)
JBXSSW (Section 4.3)
JAXSSW (Section 4.4)
LEDs (Section 4.5.4)

LEDs (Section 4.6.4)
JAXPC (Section 4.8)
JBXPS (Section 4.9)
JBXFAN (Section 4.10)
ATCA Fillers (Section 4.11).
In Edition 07
JBXSSW (Section 4.3)
LEDs (Section 4.9.3).
In Edition 06
JBXSSW (Section 4.3).
3BK 21280 AAAA TQZZA Ed.08 9 / 138

Preface
In Edition 05
Update for new equipment naming.
In Edition 04
Overall document quality was improved following a quality review.
In Edition 03
Section JBXTP3 (Section 4.6) was added.
In Edition 02
The description was improved in Alcatel-Lucent 9130 BSC Evolution Naming
Conventions (Section 1.3.1).
In Edition 01
First official release of the document.
Audience This manual is intended for:
Commissioning personnel
System support engineers

Training department personnel (for reference use)
Any other personnel requiring an overview of the Alcatel-Lucent 9130

BSC Evolution hardware.
Assumed Knowledge The reader must have a general knowledge of telecommunications systems,
terminology and Alcatel-Lucent 9130 BSC Evolution functions.
10 / 138 3BK 21280 AAAA TQZZA Ed.08

1 Overview
1 Overview
The Overview provides information needed by project managers and foremen,

for presentation to the customer and for site planning.
3BK 21280 AAAA TQZZA Ed.08 11 / 138

1 Overview
1.1 Cabinet
The Alcatel-Lucent 9130 BSC Evolution hardware consists of an indoor cabinet
which is housed in a telecommunications building. It contains subracks, power
distribution unit, PBAs, modules and cabling.
The cabinet is designed for buildings with a minimum ceiling height of 2.7
meters.
Cable entry to the cabinet can be from:
The top
If the cabinet is mounted on a solid floor, cable ducts in the ceiling carry the
cables to the top of the cabinet.
The bottom
If the cabinet is mounted on a raised floor, cable ducts in the floor carry the
cables to the bottom of the cabinet.
The cabinet consists of a rack fitted with front and rear doors. When the
doors are closed, the equipment is EMI protected. The doors can be easily
removed for maintenance.
The arrangement of the subracks in the cabinet takes into account the
requirements for:
Thermal cooling, achieved with forced-air cooling
Minimization of floor space
Ease of access for maintenance, from the front of the cabinets

Future system expansion.
1.2 Subracks
The Alcatel-Lucent 9130 BSC Evolution uses the following types of subracks:
ATCA
The ATCA 19" subrack is made of stainless steel. There is one mounting
bracket on each side of the shelf, designed for front-mounting into a rack.
Depending on the rack in which the shelf is installed, there are two possible
locations for the mounting brackets on the side of the shelf.
For more information about ATCA subracks and hosted boards, refer to
ATCA Shelf (Section 4).
Line Interface Unit (JSXLIU/JSXLIUB)

The JSXLIU/JSXLIUB subrack assumes the concentration of 256 E1 on one
Giga Ethernet link.
For more information about JSXLIU/JSXLIUB subracks and hosted boards,
refer to JSXLIU/JSXLIUB Shelf (Section 5).
Power Distribution Unit (JSXPDU).

The JSXPDU provides power distribution inside the cabinet.
For more information about the JSXPDU, refer to Power Distribution Unit
(Section 3.1).
12 / 138 3BK 21280 AAAA TQZZA Ed.08

1 Overview
1.3 Configurations
1.3.1 Alcatel-Lucent 9130 BSC Evolution Naming Conventions
The following table lists the naming conventions used for Alcatel-Lucent 9130
BSC Evolution configurations.
Configuration Description
200 TRX This configuration requires 1 active JBXCCP board and 1 standby JBXCCP board.
Table 1: Alcatel-Lucent 9130 BSC Evolution Configuration Naming Conventions
The following table describes the board allocation for the ATCA shelf.
Physical slots
Boards Qty 1 2 3 4 5 6 7 8 9 10 11 12 13 14
JBXSSW 2 x x
JBXCCP 1 to 5 x x x x x x u u
+1 spare
JBXTP 2 x x
JBXOMCP 2 u x x u u u
JAXSSW 2 u u u u u x x u u u u u u
u : Slot is not used and is closed with a filler

Table 2: Board Allocation for ATCA shelf
JBXCCP in slot 10 is always present to support the redundancy function, but it

must be considered as a floating spare during operations.
The logical slot numbering is different. For more information, refer to
the following tables which list the logical slot numbers as well as the
Board/Area/Slot/SBL mapping for the modules used in the 9130 BSC Evolution.
3BK 21280 AAAA TQZZA Ed.08 13 / 138

1 Overview
The following table gives the ATCA Shelf Front View Board-Area-Slot-SBL
mapping.
JBXFAN area
Board JBXFAN1 JBXFAN2
Slot 81 82
number
SBL FAN1 FAN2
Board JBXFAN3 JBXFAN4
Slot 83 84
number
SBL FAN3 FAN4
Slot area
Board J J J J J J J J J J J J
B B B B B B B B B B B B
X X X X X X X X X X X X
T T C C C O S S O C C C
P P C C C M S S M C C C
1 2 P P P C W W C P P P
6 4 1 P 1 2 P 2 3 5
1 2
Physical 1 2 3 4 5 6 7 8 9 10 11 12 13 14
slot
number
Logical 13 11 9 7 5 3 1 2 4 6 8 10 12 14
slot
number
SBL T T C C C C S S C C C C
P P P P P P S S P P P P
- - - - - - W W - - - -
H H H H H H - - H H H H
W W W W W W H H W W W W
1 2 8 6 3 1 W W 2 4 5 7
1 2
Table 3: ATCA Shelf Front View Board-Area-Slot-SBL Mapping
14 / 138 3BK 21280 AAAA TQZZA Ed.08

1 Overview
The following table gives the ATCA Shelf Rear View Board-Area-Slot-SBL
mapping.
Rear area
Board ... JAXSSW2 JAXSSW1 ...
Physical 14 ... 8 7 ... 1

slot number
Logical slot 30 ... 24 23 ... 17

number
SBL SSW-HW2 SSW-HW1
JBXPS area JAXSMM area JAXPC area
Board JBXPS1 JBXPS2 JBXPS3 JBXPS4 JAXSMM2 JAXSMM1 JAXPC2 JAXPC1
Physical 1 2 3 4 1 2 1 2
slot number
Logical slot 33 34 35 36 66 65 50 49
number
SBL PEM1 PEM2 PEM3 PEM4 SMM2 SMM1 BSC ENV3 BSC ENV2
Table 4: ATCA Shelf Rear View Board-Area-Slot-SBL Mapping
3BK 21280 AAAA TQZZA Ed.08 15 / 138

1 Overview
The following table gives the LIU Shelf Board-Slot-SBL mapping.
Board J J J J J J J J J J J J J J J J J J J J
B B B B B B B B B B B B B B B B B B B B
X X X X X X X X X X X X X X X X X X X X
P L L L L L L L L M M L L L L L L L L P
E I I I I I I I I U U I I I I I I I I E
M U U U U U U U U X X U U U U U U U U M
1 1 2 3 4 5 6 7 8 1 2 9 10 11 12 13 14 15 16 2
Slot 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Nb.
SBL P E E E E E E E E E E E E E E E E E E P
E T T T T T T T T C C T T T T T T T T E
M U U U U U U U U U U U U U U U U U U M
5 1 2 3 4 5 6 7 8 1 2 9 10 11 12 13 14 15 16 6
Table 5: LIU Shelf Board-Slot-SBL Mapping
16 / 138 3BK 21280 AAAA TQZZA Ed.08

1 Overview
1.3.2 Stand Alone Configuration

The following figure shows the rack layout for an Alcatel-Lucent 9130 BSC
Evolution 1000 TRX configuration.
JSXPDU
Free space
(JSXATCA Shelf 4)
CLOSED / OPEN H/S OOS CLOSED / OPEN H/S OOS
JSXATCA
JBXOMCP
JBXOMCP
Not Used
Not Used
JBXSSW
JBXSSW
JBXCCP
JBXCCP
JBXCCP
JBXCCP
JBXCCP
JBXCCP
JBXTP
JBXTP
Shelf 3
12345678901234567890
12345678901234567890
12345678901234567890
Air inlet
12345678901234567890
Free space
(JSXLIU Shelf 2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
XPEM XLIU XLIU XLIU XLIU XLIU XLIU XLIU XLIU XMUX XMUX XLIU XLIU XLIU XLIU XLIU XLIU XLIU XLIU XPEM
JSXLIU
Shelf 1 −48 / 60
VDC
−48 / 60
VDC
4A
4A
Figure 1: Alcatel-Lucent 9130 BSC Evolution 1000 TRX Configuration
3BK 21280 AAAA TQZZA Ed.08 17 / 138

1 Overview
1.3.3 Rack Shared Configuration

The following figure shows the rack layout for two Alcatel-Lucent 9130 BSC
Evolution rack, shared by two BSCs configuration.
JSXPDU
JSXATCA
JBXOMCP
JBXOMCP
Not Used
Not Used
JBXSSW
JBXSSW
JBXCCP
JBXCCP
JBXCCP
JBXCCP
JBXCCP
JBXCCP
Shelf 4
JBXTP
JBXTP
(BSC2)
12345678901234567890
12345678901234567890
12345678901234567890
Air inlet
12345678901234567890

JBXOMCP
JBXOMCP
JSXATCA
Not Used
Not Used
JBXSSW
JBXSSW
JBXCCP
JBXCCP
JBXCCP
JBXCCP
JBXCCP
JBXCCP
JBXTP
JBXTP
Shelf 3
(BSC1)
12345678901234567890
12345678901234567890
12345678901234567890
Air inlet
12345678901234567890
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
JSXLIU
Shelf 2
(BSC2)
−48 / 60
−48 / 60 VDC
VDC
4A
4A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
JSXLIU
Shelf 1 −48 / 60
(BSC1)
−48 / 60 VDC
VDC
4A
4A
Figure 2: Alcatel-Lucent 9130 BSC Evolution Rack Shared by Two BSCs

Configuration
18 / 138 3BK 21280 AAAA TQZZA Ed.08

1 Overview
1.3.4 Standards
The complete system is fully compliant with:
PICMG 3.0 R1.0 (AdvancedTCA) specifications defining mechanics, board

dimensions, power distribution, power and data connectors and system
management.
EN 60950 - Safety of Information Technology Equipment safety standard.
EN 55022 - EMC requirements on system level
ANSI/IPC - A610 Rev.C Class 2 Manufacturing Requirements.
3BK 21280 AAAA TQZZA Ed.08 19 / 138

1 Overview
20 / 138 3BK 21280 AAAA TQZZA Ed.08

2 Cabinet Description
This section describes the Alcatel-Lucent 9130 BSC Evolution cabinet and the
required environmental conditions.
3BK 21280 AAAA TQZZA Ed.08 21 / 138

2.1 Layout and Facilities

The Alcatel-Lucent 9130 BSC Evolution equipment is housed in a single 19’’
standard rack. The rack provides:
Mechanical housing for up to two ATCA shelves

Connection of the secondary power supply, via duplicated -48V or -60V
distribution, through a power distribution shelf called the JSXPDU
Connection of the external links, essentially comprised of E1 interfaces and

Giga Ethernet on balanced pairs
Safety protection to industry standards.
The following figure shows the layout of the cabinet.
JSXPDU
JSXATCA Shelf 4
Cable
Pipes
JSXATCA Shelf 3
JSXLIU Shelf 2
JSXLIU Shelf 1
Plinth
Figure 3: Cabinet Layout
The front door is 80% perforated (the maximum possible perforation for the
allowed space).
A 100 mm plinth is provided to allow site installation without opening the
equipment, or to allow back cable entry on a concrete floor. Four levelling
screws provided to allow rack levelling.
22 / 138 3BK 21280 AAAA TQZZA Ed.08

The front upright racking is welded 100 mm from the front door internal face to
allow space for cables. The back racking upright position can be adjusted to fit
the depth of the ATCA shelves hosted in the cabinet.
The top of the cabinet can be completely removed (including when cable
entry is located at the top of the equipment) to allow easy access for on-site
cabling. It is reversible (front to back) to allow access from the left or right sides,
depending on the configuration. For a corner installation, part of the installation
kit is bolted to the racks using the ring hooks of the cabinet, therefore allowing
the use of a vertical cable guide.
The following facilities are provided for site cabling:
When cable entry is from the bottom, a rectangular pipe is installed on
each side, between the front and the back upright racking, to easily allow
14 power cables (14 mm in diameter ) to be fed from the bottom to the
top (seven on each side)
When cable entry is from the top, these pipes are used to feed 32 PCM
cables (9 mm in diameter and equipped with a 12 x 66 mm connector) from
the top to the bottom (16 on each side). In this case, up to six Ethernet
cables (8 mm in diameter) can also be fed through these pipes.
The bottom of the rack has three windows for bottom cable entry:
One window at the front, covering the complete usable width of the
JSXLIU/JSXLIUB shelf and dedicated principally to PCM cables access
One window on each side, under the pipes, used for power cables routing in
case of bottom access and for PCM cables routing in case of top access.
3BK 21280 AAAA TQZZA Ed.08 23 / 138

2.2 Hardware Architecture

The following figure shows the hardware architecture of the Alcatel-Lucent
9130 BSC Evolution.
JBXTP
w
JBXTP r
JBXCCP
JBXSSW 1
(duplicated)
JBXMUX
1
(duplicated)
JBXCCP
n
Radio Network links
JBXLIU
1
E1
JBXOMCP
w
(duplicated) JBXOMCP r
JBXLIU n
JSXLIU Shelf
(21 slots) ATCA Shelf (14 slots)
External Ethernet Links

Figure 4: Alcatel-Lucent 9130 BSC Evolution Hardware Architecture
The following table lists the functions provided by each functional block.
Functional Block Function
Gigabit Ethernet switch (JBXSSW) Allows exchanges between all

platform elements and external
IP/Ethernet equipment.
O&M Control Processing board Acts as system manager for the whole
(JBXOMCP) platform and for O&M applications.
Call Control Processing board Controls the call functions for the
(JBXCCP) platform.
Transmission Processing board Provides telecom

(JBXTP) transmission/transport interfaces to
the platform.
24 / 138 3BK 21280 AAAA TQZZA Ed.08

Functional Block Function
Line Interface Unit (JSXLIU/JSXLIUB) Multiplexes/demultiplexes and cross

shelf connects all E1 external links to/from
NE multiplexed links (n E1 over
Ethernet) on the JBXTP board.
Equipped with two JBXMUX boards
and n JBXLIU/JBLIU75 boards,
depending on capacity.
JBXLIU/JBLIU75 boards (the These links correspond to the user

interface for radio network links) plane interfaces.
Ethernet links on the IP ports of the These links connect the platform to
JBXSSW switch external IP equipment (i.e. OMC-R,
external alarm box).
Table 6: Hardware Functions
2.3 Dimensions and Weight

The following table describes the cabinet’s external physical dimensions.
Dimension Overall Size (mm)
Height 2000 (including a 100 mm plinth)
Width 600
Depth 600
Maximum weight 300 kg
Table 7: Cabinet Dimensions and Weight
3BK 21280 AAAA TQZZA Ed.08 25 / 138

2.4 Environment
The equipment must not be exposed to extremes of temperature, or to relative
humidity. To meet the required environmental conditions, air conditioning
equipment may have to be installed.
The environmental conditions are:
Temperature and humidity
Atmospheric pressure
Solar radiation
Dust and particles

Lighting
Cooling
Safety standards
Green compliance.
2.4.1 Temperature and Humidity

For altitudes between sea level and 500 meters, the temperature must be
between + 5C and + 40C, within a relative humidity band of between 20 % to
80 %. The temperature gradient must be less than 0.5C per minute.
Electrostatic Danger
Electrostatics may cause minor shocks and/or damage to the equipment.
The relative humidity must be at least 20 % at manned sites or during
maintenance periods.
Cooling, EMI conditions and noise emission are respected only if the doors
are closed during operation.
2.4.2 Atmospheric Pressure

For normal operation of the equipment, the atmospheric pressure must be
between 65 kilopascals (kPa) and 120 kPa. Low pressure extremes must not
be allowed to coincide with upper temperature limits.
Note: An altitude of 3500 meters corresponds to a pressure of approximately 65.7

kPa.
2.4.3 Solar Radiation
Direct Solar Radiation

Exposure to direct solar radiation may result in damage to equipment due
to overheating.
Ensure that equipment is not subject to direct sunlight.
26 / 138 3BK 21280 AAAA TQZZA Ed.08

2.4.4 Dust and Particles

The equipment operates normally in the presence of solid (non-conductive,
non-ferromagnetic, non-corrosive) particles. The following table lists the
maximum sizes and concentrations of particles.
Size of Particles Concentration

(micrometers) (millions of particles per cubic meter)
0.5 14
1 0.7
3 0.24
5 0.13
Table 8: Dust and/or Sand Particle Concentration Levels
2.4.5 Lighting
All optical signals, displays and labels are visible with an ambient light intensity
of 800 lux.
2.4.6 Cooling
The Alcatel-Lucent 9130 BSC Evolution equipment uses forced air cooling.
2.4.7 Green Compliance

The Alcatel-Lucent 9130 BSC Evolution cabinet complies with the new
European directives concerning the environment:
Wastes of Electrical and Electronic Equipment (WEEE)
The requirements for re-use and recycling capabilities are applicable to the
complete 9130 BSC product line (not only for the cabinet).
Restriction of Hazardous Substances (RoHS).
3BK 21280 AAAA TQZZA Ed.08 27 / 138

28 / 138 3BK 21280 AAAA TQZZA Ed.08

3 Power System
3 Power System
Power System describes the power distribution system of the Alcatel-Lucent

9130 BSC Evolution.
3BK 21280 AAAA TQZZA Ed.08 29 / 138

3 Power System
3.1 Power Distribution Unit

3.1.1 Introduction
The new generation of BSC equipment referred to as 9130 BSC Evolution is
housed in a single 19’’ standard rack called the JRXCAB. Power distribution
inside this cabinet is handled by the Power Distribution Unit (JSXPDU) shelf,
which provides:
Connection to a duplicated secondary -48V or -60V power supply

distribution, through 35 mm2 double skin cables
Breakers and power supply distribution to ATCA shelves (75A each) and
JSXLIU/JSXLIUB shelves (10A each)
Safety protection to industry standards.
In order to supply the two JSXATCA shelves and the two JSXLIU/JSXLIUB
shelves of an 9130 BSC cabinet, the JSXPDU shelf meets the following
external requirements:
19’’ standard shelf
Connection to the power plant via 12 double skin 35 mm2 cables, with an
overall diameter of 14 mm each
2
Connection to the loads via 24 x 16 mm cables with an overall diameter
of 7 mm each
2
Connection to ground via one double skin 35 mm cable with an overall
diameter of 14 mm
Cabling access from the top back part of the equipment
Paint color according to Alcatel-Lucent standards
The front panel is covered by a light grey label (the other face is not painted)
EMC shielding is not required (no active part)

Earthquake protection
Fire protection
Compliance with the new European directives concerning the environment
Meets the RoHS and WEEE requirements
Safety protection is provided via two independent covers.
30 / 138 3BK 21280 AAAA TQZZA Ed.08

3 Power System
3.1.2 Mechanical Characteristics

The JSXPDU is a standard 19’’ shelf, 2U in height. The racking brackets are
mounted 60 mm behind the front panel. The overall depth is approximately
250 mm.
3.1.3 Schematic
The JSXPDU consists of two independent branches, the BATA and BATB.
Each branch of the JSXPDU shelf is composed of three independent
distribution systems, independently powered by two 35 mm2 wires with double
skin insulation:
Each distribution system (1 or 2) includes:

One 75A breaker with two outputs
One 10A breaker with one output.
Each distribution system includes one 75A breaker and two outputs.
Each branch comprises:
Three 75A breakers, to supply up to two ATCA shelves. The third 75A
breaker is equipped for future use.
Two 10A breakers, to supply up to two JSXLIU/JSXLIUB shelves.
Branch A Branch B
BATA 1 BATA 2 BATA 3 BATB 1 BATB 2 BATB 3
BATaR 1 BATaR 2 BATaR 3 BATbR 1 BATbR 2 BATbR 3
ATCA shelf 1
ATCA shelf 2
ATCA shelf 3
LIU shelf 2
ATCA shelf 1
ATCA shelf 3
LIU shelf 1
ATCA shelf 2
LIU shelf 1
LIU shelf 2
A1 A2 A3 A4 A5 B1 B2 B3 B4 B5
Figure 5: JSXPDU Overview
3.1.4 Power Station Connection

2
Connection to the power station is via two or more 35 mm double skin wires
per ATCA shelf and per branch. The JSXPDU therefore provides connection to
the power station via 12 x 14 mm power cables and one 14 mm ground cable.
3BK 21280 AAAA TQZZA Ed.08 31 / 138

3 Power System
3.1.5 Connection to the Hosted Shelves

Each ATCA shelf is connected to the JSXPDU via eight 16 mm2 wires (7
mm in diameter).
Each JSXLIU/JSXLIUB shelf is connected to the JSXPDU by two 7 mm (three
1.5 mm2 wires ) cords, including the ground.
3.1.6 Earthing Connection

The building’s ground is connected to the JSXPDU by a double stud. This
earthing conductor is distributed to the JSXLIU/JSXLIUB shelves through the
power cord, and to the mechanics of the cabinet via a double stud. A specific
label is added near the connection of the earthing conductor.
3.1.7 Safety
The JSXPDU meets the EN 60950 safety standards. Branch A and branch B are
be independently protected by two separate covers so that service personnel
can safely access one power branch when the other branch is operational.
3.1.8 Provision for Future Use

In the case where an alarm function will be added in the JSXPDU, a free space
of approximately 25 mm width of the whole height (2U) is reserved between
both branches A and B. The front plate is bored with a column of five 4 mm
holes. These holes will be hidden by the label which covers the whole front
panel and bears the marking.
3.1.9 JSXPDU Front View

The following figure shows the front view of the JSXPDU.
A1 A2 A3 A4 A5 B1 B2 B3 B4 B5
I I I I I I I I I I
O O O O O O O O O O
Shelf 4 Shelf 2 Shelf 3 Shelf 1 Shelf 4 Shelf 2 Shelf 3 Shelf 1
Figure 6: JSXPDU Front View and Marking
3.1.10 Power Distribution Cable Characteristics

3.1.10.1 ATCA Shelves Supplying
The power entry on ATCA shelves is done via 6 mm studs. The power cables
coming from the JSXPDU shelf are terminated by lugs rings.
The cable used is a two wire, 16 mm2 cable. The blue wire corresponds to
VBAT. The black marked wire corresponds to the Battery Return.
The required cable lengths are:
1.5 m for the upper ATCA shelf

2.1 m for the second ACTA shelf.
32 / 138 3BK 21280 AAAA TQZZA Ed.08

3 Power System
3.1.10.2 ATCA Shelf Grounding

The ATCA grounding point is a double lug, spaced at 19 mm. The 16 mm2
yellow/green ground cable is terminated by a lug with two holes.
There are two possibilities for the ground connection:
One cable between each ATCA shelf and the JSXPDU (same length as
power cable), or
The frame of the cabinet is used as ground, and the JSXPDU and the ATCA
shelves are connected to the frame by a cable.
3.1.10.3 JSXLIU/JSXLIUB Shelf Supply and Grounding

The power connection on the JSXLIU/JSXLIUB shelves is done through three
pin UP connectors. The connector is composed of a moulding and three
contacts.
3.2 Cooling
The JSXATCA shelf provides fault tolerant cooling to front mounted Advanced
Telecom Computing Architecture (Advanced TCA) blades, and to rear transition
modules based on four front-maintainable, intelligent fan trays, with one fan
per tray.
Blower trays are mounted in the shelf top. The following figure shows the
general airflow for the ATCA system. The cooling type is front to rear.
Blowers
Air Outlet
Front Rear
Air Inlet
Figure 7: Shelf Airflow
The cooling system is designed to manage a heat dissipation of 200W per

front slot and an additional 20-30W per rear slot.
3BK 21280 AAAA TQZZA Ed.08 33 / 138

3 Power System
Each of the fan tray units contains an IPMC, which is located on both the
IPMB-A and IPMB-B buses. Individual fan failures are detected by monitoring
the fan rotation speed. Rotation which is 15% below demand is deemed to be a
fan failure. Usually the cooling system runs the fans at 40%. In the case of a
single fan failure, the fans run at 100% to still provide full air pressure within the
area between the fans and the boards.
Each fan tray monitors and reports air temperature and failure conditions to the
shelf manager. The shelf manager controls the fan speed based on sensor
and failure information acquired from the fan and board sensors. If a fan
tray looses IPMI communication with the shelf manager, it will automatically
run the fans at full speed.
The following figure shows the block diagrams with the main components
of the blower.
C
HA o
Tach
n
B t
l IPMC Bus 1
r
PWM
o o
w l
IPMC Bus 2
e RiCool − 2
LEDs
r Controller I
Enables n
P Hot Swap Switch
t
C e
B Flame Sensor
r
Flame Sensor − 48 A f
− 48 B a
+ V_A c
+ V_B e
Figure 8: Block Diagram of a Blower
JSXLIU/JSXLIUB shelf cooling is managed by natural convection.
34 / 138 3BK 21280 AAAA TQZZA Ed.08

4 ATCA Shelf
4 ATCA Shelf
This section describes the ATCA shelf and its components.
3BK 21280 AAAA TQZZA Ed.08 35 / 138

4 ATCA Shelf
4.1 ATCA Shelf Description

The ATCA shelf is designed for "five nines" uptime (99.999%).
The shelf provides 14 slots which can be equipped with Advanced TCA blades
and corresponding Rear Transition Modules (RTM) at the rear of the system.
The 14 slots are typically set up as two hub slots and 12 node slots.
This is shown in the following figure.
Fan Trays
Air Inlet
Figure 9: ATCA Shelf
The system is always equipped with:
A dual star backplane providing connector interfaces for power distribution,

input/output connectivity between front blades, and mechanical alignment
and support
A backplane with base and fabric interface
A subrack providing attachment points for the backplane, alignment and

support, and a mechanical engagement for insertion and extraction of
the front blades and RTMs
Two JAXSMM shelf manager boards. Each blade and Field Replaceable
Unit (FRU) provides links to the shelf manager through an Intelligent
Platform Management Bus (IPMB)
12 node slots which can be equipped with Advanced TCA node blades
Two hub slots which can be equipped with Advanced TCA hub blades
14 slots at the system’s rear side which can be populated with 14 RTMs.
These RTM connections provide user defined input and output connectivity
to the corresponding front blades
Four IPMC-enabled intelligent blowers

Four single entry DC Feed intelligent JBXPSs with 90 Amp / 50 Amp
breakers and line filters for ATCA shelf variants before 3BK 27291 ABxx
36 / 138 3BK 21280 AAAA TQZZA Ed.08

4 ATCA Shelf
or two single entry DC Feed intelligent JBXPSs for ATCA shelf variants
starting with 3BK 27291 ABxx
Two alarm boards
An air filter
Rear ESD wrist strap sockets and grounding studs.
The following figures show the ATCA subrack front and back views.
JBXOMCP
JBXOMCP
Not Used
Not Used
JBXSSW
JBXSSW
JBXCCP
JBXCCP
JBXCCP
JBXCCP
JBXCCP
JBXCCP
JBXTP
JBXTP
12345678901234567890123456789012
12345678901234567890123456789012
Air inlet
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
Figure 10: ATCA Subrack Front View for Variants Before 3BK 27291 ABxx
H/S OOS H/S OOS
H/S OOS H/S OOS
12345678901234567890123456789012
12345678901234567890123456789012
Air inlet
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
Figure 11: ATCA Subrack Front View from Variant 3BK 27291 ABxx On
3BK 21280 AAAA TQZZA Ed.08 37 / 138

4 ATCA Shelf
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
Air outlet
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
JAXPC JAXPC
OOS OOS
Telco Alarms & Relays

GND
−(POWER)
−(POWER)
−(POWER)
−(POWER)
OK OK
ACT ACT
Alarm/ Alarm/
Reset Reset
H/S H/S
+(RETURN)
+(RETURN)
+(RETURN)
+(RETURN)
Handle
Handle
Closed Closed
A TCA A TCA Open Open
M100 M100
OOS OOS
H/S H/S OK OK
JAXSMM
JAXSMM
JBXPS JBXPS JBXPS JBXPS
JAXPC
JAXPC
Figure 12: ATCA Subrack Back View for Variants Before 3BK 27291 ABxx
12345678901234567890123456789012
12345678901234567890123456789012
12345678901234567890123456789012
Air outlet
12345678901234567890123456789012
12345678901234567890123456789012
JAXSMM JAXSMM JAXPC JAXPC

OOS OOS OOS OOS
H/S
OOS
I H/S
OOS
I OK
ACT
OK OK OK GND
ACT 2
345
2
345
6
6
789
789
F 01
MS
F 01
MS
OK OK BC DE
A
BCDE
A
SGA SGA
345 345
2 2
6
LS LS
789
789
F 01
F 01
A A
BC DE BCDE
+
H/S H/S H/S H/S

JAXSMM
JAXSMM
JBXPS JBXPS
JAXPC
JAXPC
Figure 13: ATCA Subrack Back View from Variant 3BK 27291 ABxx On
4.1.1 Shelf
The 13U (577 mm) and 440 mm deep shelf for 19" racks is made of stainless
steel.
There is one mounting bracket on each side of the shelf, designed for
front-mounting the shelf into a rack.
The system can be installed in a standard 19’’ rack.
38 / 138 3BK 21280 AAAA TQZZA Ed.08

4 ATCA Shelf
4.1.2 Node Slots

The node slots are equipped with Advanced TCA blades.
Advanced TCA blades used in BSC configuration are the following
high-performance, single slot, hot-swap node boards:
JBXOMCP
JBXSSW.
Advanced TCA blades offer a high processing performance. They are ideal
for telecommunication applications.
4.1.3 Hub Slots

The hub slots are equipped with JBXSSW switches. The JBXSSW is a Gigabit
Ethernet switch.
4.1.4 Rear Transition Modules

The Advanced TCA blades can be connected to Rear Transition Modules
(RTM) to provide easy access to I/O signals through the zone 3 connector
defined by the Advanced TCA specifications.
RTMs can be used as a rear expansion board for the JBXSSW switch to access
the different interfaces on an AdvancedTCA blade through the JAXSSW
front plate.
4.1.5 Power Entry Modules

Four field hot-swap intelligent JBXPSs with a 50 Amp breaker and line filter are
installed beneath the rear slots of the backplane for ATCA shelf variants before
3BK 27291 ABxx. The four JBXPSs are used to provide split power distribution.
For details about the JBXPS refer to JBXPS (Section 4.9).
Starting with ATCA shelf variant 3BK 27291 ABxx, only two JBXPSs with a 60
Amp breaker and line filter are used to supply the comlpete shelf.
4.1.6 Power Distribution System

The shelf has two different power distribution systems that run throughout the
shelf. The first is a low power (3.4VVDC) system that provides power to all of
the IPMCs. The second is a high power (-48VDC) system that provides power
to all of the blades, blowers and shelf managers.
4.1.6.1 Low Power Distribution System

Four JBXPS power distribution system is used for Shelf Variants Before
3BK 27291 ABxx.
The shelf’s low power distribution system powers the IPMCs engines. This
low power source (3.4V DC) manifests itself in the form of a redundant
interconnect. The first (V_A) is sourced from the JAXSMM in the J3 location.
The second (V_B) is sourced from the JAXSMM in the J11 location. The IPMCs
are expected to OR the two sources to allow for redundancy. Current on each
source is limited by the 2 mm connector to approximately 1.5 A.
The inclusion of the low power distribution system is to allow for powering the
IPMCs without having to include an isolated DC-DC and all of its related
circuitry in each IPMC. This is most useful in FRUs such as the blowers and
3BK 21280 AAAA TQZZA Ed.08 39 / 138

4 ATCA Shelf
JAXPCs, where their size essentially prohibits the inclusion of such power
conversion circuitry.
The voltage from the power distribution system can also be found on the
optional IPMC expansion connectors found throughout the shelf.
The following figures show the low power distribution system found in the
JBXPS shelf.
J J
J J
B B
B B
X X
X X
O O
S S
M M
S S
C C
W W
P P
Physical Slot 1 2 3 4 5 6 7 8 9 10 11 12 13 14
JAXSMM
JAXSMM
JAXPC
JAXPC
JBXFAN
JBXFAN
JBXFAN
JBXFAN
JBXPS1 JBXPS2 JBXPS3 JBXPS4

A1 B1 A2 B2
Figure 14: Low Power Distribution System for Shelf Variants Before 3BK 27291 ABxx
Two JBXPS power distribution system is used from Shelf Variant 3BK
27291 ABxx on.
The shelf’s low power distribution system is used for powering the IPMCs
engines of shelf FRUs. This low power source (3.4V DC) manifests itself in
the form of a redundant interconnection. The first (V_A) is sourced from the
ShMC in the J3 location. The second (V_B) is sourced from the ShMC in the
J11 location. The IPMCs are expected to OR the two sources to allow for
redundancy. Current on each source is limited to 1.0 A.
40 / 138 3BK 21280 AAAA TQZZA Ed.08

4 ATCA Shelf
The low power distribution system allows powering the IPMCs without having
to include an isolated DC-DC converter including all of its related circuitry as
defined in the PICMG specification in each FRU. This is most useful for FRUs
such as blowers and JAXPCs where the size essentially prohibits the inclusion
of such power conversion circuitries.
The voltage from the power distribution system can also be found on the
optional IPMC expansion connectors on the distribution board.
J J
J J
B B
B B
X X
X X
O O
S S
M M
S S
C C
W W
P P
Physical Slot 1 2 3 4 5 6 7 8 9 10 11 12 13 14
JAXSMM
JAXSMM
JAXPC
JAXPC
JBXFAN
JBXFAN
JBXFAN
JBXFAN
JBXPS1 JBXPS2
A1 B1
Figure 15: Low Power Distribution System from Shelf Variant 3BK 27291 ABxx On
3BK 21280 AAAA TQZZA Ed.08 41 / 138

4 ATCA Shelf
4.1.6.2 High Power Distribution System

Four JBXPS power distribution system is used for Shelf Variants Before
3BK 27291 ABxx.
The shelf’s high power distribution system is for powering the blade, JAXSMMs
and blowers. This high power source (-48V DC - nominal) manifests itself in
the form of one or two sets of redundant interconnects. The JBXPS shelf has
two set of redundant interconnects.
The following figures show the high power distribution system.
J J
J J
B B
B B
X X
X X
O O
S S
M M
S S
C C
W W
P P
Physical Slot 1 2 3 4 5 6 7 8 9 10 11 12 13 14
JAXSMM
JAXSMM
JAXPC
JAXPC
JBXFAN
JBXFAN
JBXFAN
JBXFAN
JBXPS1 JBXPS2 JBXPS3 JBXPS4

A1 B1 A2 B2
Battery
Outside the chassis Battery plant B
plant A
Figure 16: High Power Distribution System for Shelf Variants Before 3BK 27291 ABxx
42 / 138 3BK 21280 AAAA TQZZA Ed.08

4 ATCA Shelf
The first redundant interconnect is made up of the A1 and B1 feeds. The first
feed (-48V_A1) is sourced from the A1 JBXPS in the far left (as viewed from the
rear of the shelf). The second feed (-48V_B1) is sourced from the B1 JBXPS to
the right of the first one. Both feeds are individually routed to each JAXSMM,
blower and odd numbered slots. The second redundant interconnect is made
up of the A2 and B2 feeds. The third feed (-48V_A2) is sourced from the A2
JBXPS (to the right of the B1 JBXPS). The fourth feed (-48V_B2) is sourced
from the B2 JBXPS (to the right of the A2 JBXPS). These feeds only route to
the even numbered slots. In both interconnects, the FRUs are expected to OR
the two sources to allow for redundancy.
The A1 and B1 JBXPS locations are capable of supplying 90 A of current,
although the JBXPSs will only allow for 50 A. The A2 and B2 JBXPS locations
are capable of supplying 50 A. This allows for a single JBXPS in each
interconnect, to support the full power requirement of the interconnect.
For the blowers, the A1 and B1 feeds are capable of supplying 12 A when
derated for a 30 C temperature rise. For the JAXSMMs, the A1 and B1 feeds
are limited by the 2 mm connector to approximately 1.5 A (per feed).
Two JBXPS power distribution system is used from Shelf Variant 3BK
27291 ABxx on.
The shelf’s high power distribution system is used for powering the blade,
ShMCs and blowers.
This high power source (-48V DC - nominal) manifests itself in the form of
two sets of redundant interconnects.
The redundant interconnect is made up of the A1 and B1 feeds. The first feed
(-48V_A1) is sourced from the A1 PEM in the leftmost location (as viewed from
the rear of the shelf). The second feed (-48V_B1) is sourced from the B1
PEM to the right of the first. Both feeds are individually routed to each shelf
manager, blower and slots. The FRUs are expected to OR the two sources to
allow for redundancy.
The A1 and B1 PEMs locations are capable of supplying 90 A of current
although the PEMs will only allow for 50 A. This allows for a single PEM in each
interconnect to support the full power requirement of the interconnect.
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4 ATCA Shelf
For the blowers, the A1 and B1 feeds are capable of supplying 12 A when
derated for a 30ºC temperature rise. For the ShMCs, the A1 and B1 feeds are
limited by the 2 mm connector to approximately 1.5 A (per feed).
The following figure shows the high power distribution system.
J J
J J
B B
B B
X X
X X
O O
S S
M M
S S
C C
W W
P P
Physical Slot 1 2 3 4 5 6 7 8 9 10 11 12 13 14
JAXSMM
JAXSMM
JAXPC
JAXPC
JBXFAN
JBXFAN
JBXFAN
JBXFAN
JBXPS1 JBXPS2
A1 B1
Battery Battery
Outside the chassis plant B
plant A
Figure 17: High Power Distribution System from Shelf Variant 3BK 27291 ABxx On
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4 ATCA Shelf
4.1.7 Blowers
The system provides fault-tolerant cooling by using four front accessible,
hot-swap intelligent fan trays. Each fan tray contains one blower with built-in
speed control. A toggle switch is provided to allow supervision interruption
for maintenance reasons.
From blower (JBXFAN) variant 3BK 27352 AACA on, the toggle switch is
removed.
4.1.8 Shelf Manager

The shelf manager (JAXSMM) is designed to be used in Advanced TCA
systems. It is the central management unit of the shelf. It monitors, controls
and ensures the proper operation of the shelf and all other components of
the Advanced TCA shelf.
It reports anomalies and errors and takes corrective actions if required (e.g.
increases the speed of the blowers). The JAXSMM has access to detailed
inventory information as well as to sensor status information concerning the
shelf and all the components of the shelf.
4.1.9 Personality Card

The personality card (JAXPC) is a shelf configuration and alarm board used
with AdvancedTCA systems. The JAXPC personality card is designed for rear
access applications. It is located below the Rear Transition Module (RTM) area.
4.1.10 Air Filter

The air filter is located in the lower part of the shelf. It ensures that the shelf
operates properly. Regular cleaning and replacement is mandatory.
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4 ATCA Shelf
4.1.11 Backplane
The backplane provides the following features:
Two hub slots
12 node slots
14-slot fabric interface with a dual star interconnect

A base interface with a dual star interconnect
An update interface between physical adjacent slots
A base interface to the shelf manager slots
Bused IPMB-0 connections
Synchronization of clock buses.
4.1.12 Distribution Board

The distribution board has the following features:
Power lugs and studs for power transfer to the backplane
Blower interface
Interface for two shelf manager boards
Support for up to four JBXPSs

Interfaces for two JAXPC personality cards (Telco I/O).
4.1.13 Mechanical Data

The following table describes the dimensions and the weight of the system.
Measurement Value
Height 577 mm (13U)
Width 438 mm (14 x 6HP)
Rack mounting 482.6 mm (19’’)
Depth from rack mounting pane Top: Towards the front 60 mm in the
blower area
Middle: The wiring area is compliant
with PICMG 3.0
Bottom: Towards the rear 415 mm in
the JBXPS area
Weight 38kg (Without ATCA blades and

RTMs)
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4.2 JBXOMCP/JBXCCP
4.2.1 Introduction
The JBXOMCP/JBXCCP is an Advanced TCA compliant single board computer
offering high processing performance. Four on-board PMC sites, a redundant
GBit Ethernet connection to the ATCA Base interface and standard I/O
interfaces make it ideal for telecommunication and datacom applications.
It provides the following features:
A Pentium M processor with up to 1.8 GHz speed
Up to 4 GByte main memory SDRAM with ECC protection

Redundant ATCA Base interface
Two USB 2.0 interfaces on the front plate
60 GByte hard disk (available only on JBXOMCP boards) or 80 GByte hard

disk available starting from JBXOMCP version 3BK 27236 AACA
Support for Carrier Grade Linux Ed. 3.1
On-board IPMC compliant to IPMI V.1.5 with redundant IPMB support
Different Rear Transition Modules (RTM) available separately
A CMC module providing two serial interfaces on the front plate.
Starting from JBXOMCP version 3BK 27236 AACA and JBXCCP version 3BK
27231 AACA the following items are removed:
PMCs
Front Panel & I/Os

The two micro USB connections and all corresponding electronics are
removed.
The Front Panel Reset PB is removed. Reset of the blade will still be
possible through IPMI command.
The Front Panel is to be changed to make it simpler to produce from a
mechanical viewpoint (No cut for PMCs, Reset PB, USB connectors).
Debug Connectors
DC/DC Power Supply Unit
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4.2.2 Front Plate

The following figure shows the connectors, keys and LEDs available on the
front plate.
o
o
s P
M
C
O 1
K
A
C
T
H
D
D
U
S P
B M
1 C
2
U
S
B
2
P
M
C
3
R
E
S
E
T
H
/
S
P
M
C
4
Figure 18: JBXOMCP/JBXCCP Front Plate Before JBXOMCP Version 3BK

27236 AACA and JBXCCP Version 3BK 27231 AACA
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27231 AACA the keys and LEDs available on front plate are as shown in
the following figure.
o
o
s
O
K
A
C
T
H
D
D
H
/
S
Figure 19: JBXOMCP/JBXCCP Front Plate from JBXOMCP Version 3BK

27236 AACA and JBXCCP Version 3BK 27231 AACA On
3BK 21280 AAAA TQZZA Ed.08 49 / 138

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4.2.3 LEDs
The following figure shows all LEDs available on the front plate.
o
o
s
O
K
A
C
T
P
H M
D C
D 2
H
/
S
Figure 20: Location of Front Plate LEDs
The following table describes the JBXOMCP/JBXCCP LEDs.
LED Description
OOS Out Of Service

Red: The blade is out of service
OFF: The blade is working properly
OK Power status
Green: Supply voltages are within threshold values
OFF: Supply voltages are outside threshold values
ACT Redundancy status

Amber: The blade is active
OFF: The blade is stand-by
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LED Description
HDD During booting this LED indicates the boot status. Later
it indicates the combined parallel/serial ATA activity or is
used as user LED. Toggling between both modes is done
via the LED control register.
In user mode:
Depending on the FPGA LED control register, the LED
is either red, green or OFF.
In parallel/serial ATA activity mode:
Red: Combined activity of parallel and serial ATA
interfaces.
OFF: No activity.
H/S Hot swap

During blade installation:
Permanently blue: On-board IPMC powers up
Blinking blue: Blade communicates with the Shelf
Management controller
OFF: Blade is active
During blade removal:
Blinking blue: The lower handle is open, no other meaning.
Permanently blue: Blade is ready to be extracted.
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4.2.4 Keys
The blade provides one front plate reset key. This is shown in the following
figure.
P
M
C
3
R
E
S
E
T
H
/
S
Figure 21: Location of Reset Key
On pressing the reset key, a hard reset is triggered and all attached on-board
devices are reset.
Note: The IPMC is not reset via this key.

27231 AACA the front panel reset Push Button is removed.
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4.2.5 Connectors
4.2.5.1 Front Plate Connectors
The blade provides two mini USB 2.0 connectors (type AB) on its front plate.
They correspond to the USB interfaces 1 and 2. These interfaces are not
used for BSC application.
A
C
T
H
D
D
U
S P
B M
1 C
2
U
S
B
2
Figure 22: Location of USB Connectors
27231 AACA the two micro USB connections are removed.
4.2.5.2 On-Board Connectors

The blade provides the following on-board connectors:
CompactFlash
PMC
Parallel ATA
Serial ATA
CMC
ATCA backplane connectors.
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4.2.5.3 ATCA Backplane Connectors

The ATCA backplane connectors reside in zones 1 to 3, as specified in the
ATCA standards.
The connector located in zone 1 is used to draw power from the backplane.
Zone 2 contains the 3 connectors P20, P21 and P23. P20 is used to support
telephony clocking. P21 and P23 are used to connect the blade to the standard
ATCA interfaces. All these connectors are standard and therefore are not
documented in this guide.
Zone 3 contains the 3 connectors P30 to P32. They are used to connect an
RTM to the blade and carry the following signals:
Serial (RS232)
Serial ATA
USB
Keyboard/Mouse
IPMI
Power
PMC user I/O.
In case of BSC application only the JBXSSW blades use the RTM.
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4.3 JBXSSW
4.3.1 Introduction
The blade provides the following features:
Advanced TCA compliant switch
Managed 24-port Layer 2 Gigabit switch for the base interface
Gigabit Ethernet support for 14 payload slots

Eight base and one fabric Gigabit Ethernet uplinks via the rear transition
module
16-port Layer 2 Gigabit Ethernet switch for the fabric interface
ATCA Management Controller (IPMI version 1.5) which communicates

with Shelf Management controllers
SNMP agent for switch management
Option for TDM clock generation and synchronization via CGM module
Designed for NEBS level 3 and ETSI requirements.
The fabric interface and clock generation and synchronization module are not
used for BSC application.
The following figure shows the main function blocks of the blade.
PMC Slot for

Compact Clock
RTC Flash Generation
Card Module
Boot
Flash
Base Base
Interface Interface
Processor Switch Switch
Fabric
Interface
Switch
Power Module
Figure 23: Blade Functional Blocks
Starting from JBXSSW version 3BK 27237 AACA the following items are
removed:
Telco Clock PMC
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4 ATCA Shelf
Front Panel & I/Os

The FP ETH1 Ethernet connection is removed. All corresponding
electronics is removed.
The FP serial line is removed.
FC & Fabrics support

Zone 2 P21 & P22 connectors are removed.
Debug Connectors
Several connectors used for Lab debug or programming are installed on
the blade. They are e removed.
Local shelf Manager Support

The blade was designed in a way that the local processor can be used as
Shelf Manager. All corresponding electronics is removed.
DC/DC PSU
The DC/DC brick and the hold-on capacitor are to be replaced by lower
power DC/DC brick and smaller hold-on capacitor.
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4.3.2 Front Plate

The following figure shows:
Position of the Ethernet interface
LEDs
Reset key
Serial interface on the front plate.
P
M
C
OOS
OK
ACT
I
F N
1 T
A
2 B E
3 R R
I F
4 A
5 C
C
ABC E
1 I
2 N
B T
3
A E
4 R
5 S
E F
6 A
7 C
E
8
E
T
H
1
S L A
H/S ETH2
RESET
S
E
R
I
A
L
ABC
ST
Figure 24: JBXSSW Front Plate Before JBXSSW Version 3BK 27237 AACA
3BK 21280 AAAA TQZZA Ed.08 57 / 138

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Starting from JBXSSW version 3BK 27237 AACA the front plate is as shown in
the following figure.
OOS
OK
ACT
1 I
2 N
B T
3
A E
4 R
5 S
E F
6 A
7 C
E
8
E
T
H
1
S L A
H/S ETH2
RESET
ABC
ST
Figure 25: JBXSSW Front Plate from JBXSSW Version 3BK 27237 AACA
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4.3.3 LEDs
The following LEDs are available on the front plate:
Status and Ethernet LEDs
Base interface LEDs.
The Fabric Interface LEDs are not used and starting from JBXSSW version
3BK 27237 AACA these LEDs are removed.
4.3.3.1 Status and Ethernet LEDs
The following figure shows the location of the status and Ethernet LEDs.
OOS
OK
ACT
E
T
H
1
SLA
H/S ETH2
RESET
S
E
R
I
A
L
ABC
ST
Figure 26: JBXSSW LED Location
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The following table describes the LEDs.
Name Color Description
OOS Red Out Of Service

Off: The blade is working properly
OK Green Power OK
Green: The blade is operating properly
Off: Otherwise
ACT Amber Active

Amber: The blade is active
Off: The blade is in standby mode
H/S Blue Blue: The blade is ready to be extracted

Blinking: The blade communicates with the
JAXSMM during insertion or notifies that the
lower handle is open during extraction.
Off: The blade is not ready to be extracted. Do
not remove the board during this state.
ETH2 S - Speed Green 10 BaseT

Orange 100 Base Tx
ETH2 L - Link Green On: Link up

Off: Link down
ETH2 A - Activity Orange On: Activity

Off: No activity
During power-up
ST A Red Power good 3

Green FPGA initialized
ST B Red Power good 2

Green Power good of all DC/DCs
ST C Red Power good 1

Green Power up command from IPMC
Orange Power good 1 and power up command from
IPMC are indicated
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During operation
ST A Indicates general activity via

UART between both boards:
Green No activity
Orange Activity
ST B Indicates the status at the

Ethernet heartbeat connection:
Red Heartbeat connection is dead

Green Active
Orange Warning
ST C Indicates the status at the UART

heartbeat connection:
Red Heartbeat connection is dead

Green Active
Orange Warning
Table 9: JBXSSW LED Description
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4.3.3.2 Base Interface (BIF) LEDs

There is one LED per physical port, located on the front plate.
1 I
2 N
3 B T
A E
4
S R
5 F
E
6 A
7 C
E
8
Figure 27: Base Interface LED Location
Color Description
Green Port-performed linkup but no activity
Orange Port-performed linkup and there is

activity
Table 10: Color Coding of Base Interface LEDs
The following table describes the mapping of the physical port to the front
plate LEDs.
LED Interface/Port LED Interface/Port LED Interface/Port

(BIF) (BIF) (RTM)
A1 1 B1 9 C1 17
A2 2 B2 10 C2 18
A3 3 B3 11 C3 19
A4 4 B4 12 C4 20
A5 5 B5 13 C5 21
A6 6 B6 14 C6 22
A7 7 B7 15 C7 23
A8 8 B8 16 C8 24
Table 11: Base Interface and RTM LEDs
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4.3.4 Connectors
The front plate provides the following connectors:
RJ-45, which is used for debugging only
Serial, which is used for factory settings.
E
T
H
1
SLA
H/S ETH2
RESET
S
E
R
I
A
L
Figure 28: Connector Location
Starting from JBXSSW version 3BK 27237 AACA serial connector is removed.
4.3.5 Reset Key

The front plate provides one mechanical reset key. This is shown in the
following figure.
SLA
H/S ETH2
RESET
S
E
R
I
A
L
Figure 29: Reset Key Location
A reset of all on-board I/O devices and the CPU is performed when the reset
key is set to the active position. The reset is maintained until the key is returned
to the inactive position, however at least 200 ms are guaranteed by a local timer.
3BK 21280 AAAA TQZZA Ed.08 63 / 138

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4.3.6 Backplane
The backplane provides the following connectors:
Zone 1: power connector

Zone 1 connectors are used to implement the power supply interface.
Zone 2: data transport interface

Zone 2 connectors are used to implement the base and fabric interface.
Starting from JBXSSW version 3BK 27237 AACA the fabric interface is
removed.
Zone 3: access to RTM.

The Zone 3 connectors provide access to the JAXSSW rear transition
module.
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4.4 JAXSSW
4.4.1 Front Plate
The following figure shows the front plate of the blade.blade for JAXSSW
before version 3BK 27235 AACA.
E
T1
H
E
T2
H
E
O
T3
O
H S
E
T4
O
H K
E
T5 A
H C
T
E
T6
H
E
T7
H
E
T8
H
HS
Figure 30: Front Plate for JAXSSW Before Version 3BK 27235 AACA
3BK 21280 AAAA TQZZA Ed.08 65 / 138

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The following figure shows the front plate of the blade for JAXSSW from
version 3BK 27235 AACA on.
JAXSSW
E
T1
H
E
T2
H
E
T3 O
O
H S
E
T4
O
H K
E
T5 A
H C
T
E
T6
H
E
T7
H
E
T8
H
HS
Figure 31: Front Plate for JAXSSW from Version 3BK 27235 AACA On
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4.4.2 LEDs
The RTM provides four LEDs on the front plate, as shown in the following figure.
All LEDs are standard ATCA LEDs.
E E
O O
T3 T3 O
O
H S H S
E E
T4 T4
O O
H K H K
E E
T5 A
T5 A
H C H C
T T
E E
T6 T6
H H
HS HS
Variant before 3BK 27235 AACA From variant 3BK 27235 AACA on
Figure 32: JAXSSW Front Plate LEDs and Connectors
LED Description
OOS Out Of Service

Off: The blade is working properly
OK Power OK
Green: The blade is operating
properly
Off: Otherwise
ACT Not used
H/S Hot Swap

Blue: The blade is ready to be
extracted
Off: The blade is not ready to be
extracted. Do not remove the board
during this state.
Table 12: Front Plate LED Description
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4.4.3 Ethernet Uplink Connectors

The JAXSSW provides eight Ethernet uplink connectors (ETH1 to ETH8) on
the front plate. ETH1 to ETH8 are routed to the base channel switch located on
the JBXSSW, and provide access to the shelf′s base channel interfaces.
ETH1 to ETH8 are available as RJ-45 connectors and constitute
10/100/1000BaseTX interfaces.
For Ethernet uplink connectors location refer to Figures 30 and 31.
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4.5 JBXTP
4.5.1 Introduction
The JBXTP board is located in the BSC. Together with the BTS, it performs the
radio-related functions in the BSS.
These features are implemented on a centralized JBXTP board, working in 1+1
redundancy, and ensure the following main functions:
Handling of up to 252 E1 or 4 x STM-1 (STM1 interfaces will be provided in

a future release with a daughter board)
E1 framing and supervision
TDM bit-switching (n x 8 kbps)
HDLC, SS7, QMUX, Ring Control, Ater alarm (Alarm Octet) handling
NE1oE function for up to 252 E1.
The following figure shows the global architecture for the BSC.
External E1 Links
O&M + TELECOM
E1 Termination Shelf
JBXCCP
P
JBXOMCP P JBXCCP
N
JBXTP
JBXOMCP P
W JBXCCP
JBXTP 1
W
NE1oE
JBXSSW
W
JBXSSW 1 Gigabit Ethernet −ATCA Base Interface

P
Figure 33: BSC Global Architecture
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4.5.2 Architecture
The JBXTP board can be split into the following functional modules:
OBC module
HDLC, SS7, QMUX, R/W bits termination module
Bit switch module

E1 framer module
Ethernet switch module
NE1OE module
STM1 daughter board (Optional)
Clock module
IPMC module
Reset module
Power supply module.
4.5.2.1 OBC Module

The OBC module supports all the processing for the JBXTP.
4.5.2.2 HDLC, SS7, QMUX, R/W Bits Termination Module

The module provides the following features:
Handling of the LAPD and PPP layers related to the GSM protocols between
the BTS, BSC and MSC equipment
Handling of the MTP1 and MTP2 layers of the SS7 protocol between the
BSC and the MSC
Handling of the Qmux proprietary asynchronous transmission protocol

used for communication between the TSC function (OMCP) and remote
Network Elements (BTS)
R/W bits handling related to Ring Control and the Ater Alarm (Alarm Octet).
This function is handled in the TBS.
4.5.2.3 Bit Switch Module

The module implements the N x 8kbps synchronous switch which interconnects
the 2.048Mbps links of the Ater or Abis interfaces and the termination modules
(Q1, HDLC, R/W and SS7).
It is a 72448-subchannel (8kbps) x 72448-subchannel (8kbps) non blocking
unidirectional switch with the following interconnections:
252 x 2.048Mbps links for the Ater or Abis interfaces
16 x 2.048Mbps links for HDLC
Two 2.048Mbps links for the SS7 signalling

Three 2.048Mbps links for the QMUX
10 x 2.048Mbps links for the R/W bits.
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4.5.2.4 E1 Framer Module

This module includes:
Four 63 E1 framers terminating up to 252 E1links
Eight ESD FPGAs to perform the adaptation between the Data + Clock line
interfaces of the framers and the two 16 serial links of the NE1oE module.
4.5.2.5 Ethernet Switch Module

Based on the single-chip, eight-port Gigabit switch, this module interconnects
the Ethernet ports of the OBC, the NE1oE module of the baseboard, and the
NE1oE module of the STM1 optional daughter board with the backplane
Base Interfaces.
4.5.2.6 NE1OE Module

The nE1 over Ethernet module provides the transport of the E1 links payload
over a Giga Ethernet link between the LIU shelf (256 E1) and the JBXTP
board coming through the SSW Ethernet switch boards and the standard
1000-BaseT Base interfaces.
4.5.2.7 STM1 Daughter Board (Optional)

The JBXTP provides a PMC site for an STM1 daughter board.
The power consumption budget allocated to the STM1 daughter board is 25W,
and generally supports the following distribution:
4A on 3.3V.
0,8A on 2.5V
6.4A on 1.5V.
4.5.2.8 Clock Module

This module gathers the clock functions related to the following domains:
PCI bus
PDH
NE1oE
Local Ethernet switch
IMPC.
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4.5.2.9 IPMC Module

All Advanced TCA boards support an intelligent hardware management system,
based on the "Intelligent Platform Management Interface Specification". The
hardware management system provides the ability to manage power and
interconnect requirements for intelligent devices, to monitor events and to
log events to a central repository.
The IPMC module manages:
Communication with the shelf managers via the two IPMB interfaces
The FRU state of the JBXTP board
The blue LED and the handle switch state for the hot-swap
The power-on and power-off sequences of the payload
The FRU RI EEPROM.
4.5.2.10 Reset Module

The logic reset of the JBXTP board resides in the EPLD.
In addition, this EPLD:
Handles the access to the registers of the Ethernet switch through the
SPI bus from the local bus
Can ask to the CLU FPGA to start the FPGA downloading and retrieve the
downloading status when completed
Also controls the ATCA application LEDs on the front panel.
4.5.2.11 Power Supply Module

The power supply module provides the secondary power supply for the overall
board. On-board DC/DC converters and regulators provide the necessary
power supply to the board from two -48V DC redundant primary feeds. The
power supply module is enabled/disabled by the IPMC.
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4.5.3 Front Plate

The following figure shows the front plate of the JBXTP board.
JBXTP
Handle
H1
H2
H3
L1
L2
L3
X3
H4
X2
Handle
X1
Figure 34: JBXTP Front Plate
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4.5.4 LEDs
The following table describes the LEDs available on the JBXTP board front
plate.
LED Color Description
H1 Red/Amber Out of service (OOS)

Indicates a failure or other an out of service
state.
ON: Board is out of service (OOS)
OFF: Board is operational
H2 Yellow Power Status

ON: All supplies on the board are present
OFF: At least one supply is failed
H3 Amber Master/Slave
ON: Board is active (Master)
OFF: Board is standby (Slave)
H4 Blue Hot-swap
ON: On board IPMC powers up or board ready
to be extracted
Blinking: Activation ongoing after board insertion
or notifies that the lower handle is open during
extraction
OFF: Board active or board not ready to be
extracted
L1 Red Fault Status

ON: Fault
OFF: No fault
L2 Yellow Ethernet Activity Status

ON (BLINKING): IP activity detected
OFF: No IP activity detected
L3 Yellow Physical Ethernet Connection Status

ON: Physical Ethernet connection established
OFF: No physical Ethernet connection
established
Table 13: JBXTP Board LEDs
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4.5.5 Connectors
The following table describes the connectors available on the JBXTP board
front plate.
Connector Description
X1 One RJ45 connector for a Fast

Ethernet link for debugging
X2 One RJ45 connector for three debug

RS232 links
X3 One HE5-37pins connector to access

to eight E1 (maximum).
Table 14: JBXTP Board Connectors
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4.6 JBXTP3
4.6.1 Introduction
The JBXTP3 board is a new functional variant of the JBXTP board.
The JBXTP3 board is located in the BSC. Together with the BTS, it performs
the radio-related functions in the BSS.
These features are implemented on a centralized JBXTP3 board, working in
1+1 redundancy, and ensure the following main functions:
Handling of up to 252 E1 or 4 x STM-1 ( STM1 interfaces provided on

the Mother board)
E1 framing and supervision
TDM bit-switching (n x 8 kbps)
HDLC, SS7, QMUX, Ring Control, Ater alarm (Alarm Octet) handling
NE1oE function for up to 252 E1
IP function for up to 252 E1.
Note: The TDM bit-switch shares the 252 E1 capacity between HDLC/SS7/QMUX/ring
control functions from one side and the IP function from the other side.
The following figure shows the global architecture for a BSC with JBXTP3.
External E1 Links
O&M + TELECOM
E1 Termination Shelf
4 STM−1 P Links
JBXCCP
4 STM−1 W Links P
JBXOMCP P JBXCCP
N
JBXTP
JBXOMCP P
W JBXCCP
JBXTP 1
W
NE1oE
JBXSSW
W

P
Figure 35: BSC Global Architecture with JBXTP3
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4.6.2 Architecture
The JBXTP3 board is split into the following functional modules:
OBC module
HDLC, SS7, QMUX, R/W bits termination module
TDM switch module

E1 framer/E1 VC12 module
Ethernet switch module
NE1OE module
IP module (Optional)
Clock module
IPMC module
Reset module
Power supply module.
4.6.2.1 OBC Module

The OBC module, based on the Cheetah Processor, supports the control
part of the JBXTP3.
4.6.2.2 HDLC, SS7, QMUX, R/W Bits Termination Module
The module provides the following features:
Handling of the LAPD and PPP layers related to the GSM protocols between
the BTS, BSC and MSC equipment
Handling of the MTP1 and MTP2 layers of the SS7 protocol between the
BSC and the MSC
Handling of the Qmux proprietary asynchronous transmission protocol

used for communication between the TSC function (OMCP) and remote
Network Elements (BTS)
R/W bits handling related to Ring Control and the Ater Alarm (Alarm Octet).
This function is handled in the TBS.
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4.6.2.3 TDM Switch Module

The module implements the N x 8kbps synchronous switch which interconnects
the 2.048Mbps links of the Ater or Abis interfaces and the termination modules
(Q1, HDLC, R/W and SS7).
It is a 72448-subchannel (8kbps) x 72448-subchannel (8kbps) non blocking
unidirectional switch with the following interconnections:
252 x 2.048Mbps links for the Ater or Abis interfaces
16 x 2.048Mbps links for HDLC
Two 2.048Mbps links for the SS7 signalling

Three 2.048Mbps links for the QMUX
10 x 2.048Mbps links for the R/W bits.
The TBS3 introduces a 252x252 E1 switch, configurable by OBC through PCI

to select E1 number between the E1 LIU and the E1 STM-1.
4.6.2.4 E1 Framer/E1 VC12 Module

This module includes:
Four 63 E1 framers terminating up to 252 E1 with Data + Clock or four
STM-1 links
Eight ESD FPGAs to perform the adaptation between the Data + Clock line
interfaces of the framers and the two 16 serial links of the NE1oE module
One SPF cage supporting hot insertion of 4 STM-1 electro/optic modules

(multi-mode or mono-mode Fiber optic transceivers).
The E1 VC12 module supports the Automatic Protection Switch (APS)
function, required for optical line interface. The APS decision is independent
for each STM-1 link.
4.6.2.5 Ethernet Switch Module

Based on the single-chip, eight-port Gigabit switch, this module interconnects
the Ethernet ports of the OBC, the NE1oE module of the baseboard, and the IP
module of the optional IP daughter board with the backplane Base Interfaces.
4.6.2.6 NE1OE Module
The nE1 over Ethernet module provides the transport of the E1 links payload
over Ethernet.
The new JGXEOE2 introduces a 252x252 E1 switch, configurable by OBC
through PCI and a switch command through PCI (JGXTBS3) to manage E1
number between the E1 LIU and the STM-1.
4.6.2.7 IP module (Optional)

The optional IP forwarding module handles IP packets transported from/to BTS,
through E1 interface (Abis) and routes them towards the Ethernet interface
towards/from the TC or MFS.
This module is composed of the JAXIP daughter board, including:
The JGXIPTP FPGA for IP transport over Ethernet

Flash, DDR and QDR2 memories.
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4.6.2.8 Clock Module

This module gathers the clock functions related to the following domains:
PCI bus
PDH
NE1oE
Local Ethernet switch

IMPC.
4.6.2.9 IPMC Module

All Advanced TCA boards support an intelligent hardware management
system, based on the Intelligent Platform Management Interface Specification.
The hardware management system provides the ability to manage power and
interconnect requirements for intelligent devices, to monitor events and to
log events to a central repository.
The IPMC module manages:
Communication with the shelf managers via the two IPMB interfaces
The FRU state of the JBXTP3 board
The blue LED and the handle switch state for the hot-swap
The power-on and power-off sequences of the payload
The FRU RI EEPROM.
4.6.2.10 Reset Module

The logical reset of the JBXTP3 board resides in the EPLD.
In addition, this EPLD:
Handles the access to the registers of the Ethernet switch through the
SPI bus from the local bus
Can ask the CLU FPGA to start the FPGA downloading and retrieve the
downloading status when completed
Controls the ATCA application LEDs on the front panel.

power supply to the board from two -48V DC redundant primary feeds. The
power supply module is enabled/disabled by the IPMC.
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4.6.3 Front Plate

The following figure shows the front plate of the JBXTP3 board.
JBXTP
Handle
H1
H2
H3
L1
L2
L3 JAXIP
1
LINE 2
SFP Cage
3
4
H4
X2
Handle
X1
Figure 36: JBXTP3 Front Plate
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4.6.4 LEDs
The following table describes the LEDs available on the JBXTP3 board front
plate.
H1 Red/Amber Out of service (OOS)

Indicates a failure or other an out of
service state.
ON: Board is out of service (OOS)
OFF: Board is operational
H2 Green JBXTP3 (without IP module)

ON: All supplies on the board are
present
OFF: At least one supply is failed

JBXTP3I (with IP module)
ON: IP module operational
BLINKING: IP status failed.
H3 Green Master/Slave
ON: Board is active (Master)
OFF: Board is standby (Slave)
H4 Blue Hot-swap
ON: On board IPMC powers up or board
ready to be extracted
Blinking: Activation ongoing after board
insertion or notifies that the lower handle
is open during extraction
OFF: Board active or board not ready to
be extracted
L1 Red Fault Status

ON: Fault
OFF: No fault
L2 Green Ethernet Activity Status

ON (BLINKING): IP activity detected
OFF: No IP activity detected
L3 Red Physical Ethernet Connection Status

ON: Failure detected
OFF: Board is operational.
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LINE 1 Green/Yellow Green: Used in Protect mode OK
Green BLINKING: Used in Working

mode OK
Yellow: LOS
OFF: Not configured or not used.

mode OK
Yellow: LOS

mode OK
Yellow: LOS
LINE 4 Green: Used in Protect mode OK

mode OK
Yellow: LOS
Table 15: JBXTP3 Board LEDs
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4.6.5 Connectors
The following table describes the connectors available on the JBXTP3 board
front plate.
Connector Description
X1 One RJ45 connector for a Fast

Ethernet link for debugging
X2 One RJ45 connector for three debug

RS232 links
Table 16: JBXTP3 Board Connectors
4.7 JAXSMM
4.7.1 Introduction
The JAXSMM is a 2U shelf manager board used in AdvancedTCA systems. It
plugs into a dedicated shelf management slot of an advancedTCA system. The
board provides management for up to 16 advancedTCA front blades as well as
for blowers, power entry modules, alarm modules, and shelf FRU info modules
that are used in an advancedTCA system. In a redundant configuration the
JAXSMM are used as redundant shelf manager.
The JAXSMM is a main component of the shelf management system. The shelf
management system is used in AdvancedTCA systems and its purpose is to
ensure proper operation of AdvancedTCA blades and other system components
like blowers, power entry modules (PEMs) and rear transition modules (RTMs).
The shelf manager board possesses a backplane connector and is plugged
into a 2U slot.
The alignment protrusion offers a guide rail to the slot and a coding mechanism
to ensure the installation of the board in the matching slot. It also prevents bent
pins, which can occur during installation.
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The following figure shows the JAXSMM hardware architecture.

Backplane Front Plate
Ethernet
Ethernet
Ethernet
Serial Payload
Interface
Serial
Interface
Block Transfer
Interface
Hardware
Address ATCA LEDs
Shelf Management
IPMB0 A Controller
Handle
IPMB0 B Switch
48V
48V
Figure 37: JAXSMM Hardware Architecture
The shelf manager JAXSMM hardware consists of:
Payload hardware with:

Ethernet interfaces to the backplane and to the front plate
Redundant connection between two shelf managers via the backplane
Block transfer interface to the JAXSMM
Shelf management controller with:

IPMB0-A and IPMB0-B interface to the backplane
Handle switch and status LED interface to the front plate
Option signals to the backplane
Support logic for testing and debugging as well as local and remote
programming of all programmable devices on the board
Power supply with 3.3V feed to the backplane for external devices
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4.7.2 Payload Hardware

The payload hardware on the shelf manager board is always powered when
power supply is present. During power on, the JAXSMM keeps the payload in a
reset state. The following interfaces are available:
Three Ethernet interfaces
Two redundancy interfaces (serial)
Block transfer interface.
4.7.2.1 Ethernet Interfaces

The shelf manager board has three Ethernet ports which are available
concurrently.
One 10/100 BaseT out-of-band interface is accessible via a RJ45 connector at
the front plate. Link and activity status LEDs are integrated into the connector.
Two 10 BaseT interfaces are connected to the backplane connector at the pins
Eth1-Hub Tx/Rx and Eth2-Hub Tx/Rx.
These ports connect to the base interface of up to two AdvancedTCA switch
boards (e.g. SSW) in the hub slots of an AdvancedTCA shelf.
The green LEDs (Ethernet LEDs) on the front plate indicate the link status of
the Ethernet ports.
4.7.2.2 Redundancy Interfaces

JAXSMM uses a private, redundant, high-speed, full duplex serial connection
for heart beating and data replication between the two shelf manager boards.
The redundancy interface is routed to the backplane via differential line LVDS
transceivers. The physical interface of both channels are compliant with the
AdvancedTCA specifications for the update interface.
Each of the serial inputs of the redundancy interface triggers an interrupt to the
PowerQUICC when the other shelf manager board:
Initiates a break-in condition on the serial line
Experiences a power failure
Switches in the reset state
Is extracted.
4.7.2.3 Block Transfer Interface

The payload CPU is connected to the JAXSMM via a parallel interface with
interrupt support implemented in a FPGA.
The block transfer (BT) interface is compliant with IPMI specification v1.5.
4.7.3 Shelf Management Controller

The JAXSMM part is derived from IPMC building block and consists of two
coupled microcontrollers:
IPMC master controller (IMC)
IPMC Slave Controller (ISC).
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4.7.3.1 IPMB0 Interface

IPMB0-A is connected to the I2C controller of the IMC.
IPMB0-B is connected to the I2C controller of the ISC of the JAXSMM. Both
have their own I2C controller and handle message transmission and reception
independently, including bus error handling and bus arbitration.
Received messages from both the IMC and the ISC channels are collected by
the IMC. The IMC dispatches messages which have to be sent either to its
own I2C interface or to the ISC for transmission.
4.7.3.2 IPMC Standard Functions
The following functions of the IPMCs are available on the IPMC of the JAXSMM:
Hardware address input from the backplane connector (HA 0 ...7)
Handle switch.
The handle switch is generally activated by a lever which moves when one
of the front plate fastening screws is loosened or fastened.
4.7.4 Power Supply

The JAXSMM is powered by:
A dual redundant -48V to -60V from the backplane connector

48V-A, 48V-ARTN
48V-B, 48V-BRTN
Each of the 4 power connections is separately fused.
The fuse rating is 1 Amp. An EME filter at the power input ensures conducted
emission levels below EN 55022 class B.
4.7.4.1 Onboard and External Supply
The JAXSMM makes no provision for switching off the power input. The board
is powered when the power input is in the operating range of -36 to -72V.
An on-board DC/DC converter supplies all on-board circuitry, and provides:
A 3.3V power supply to external circuits with a consumption of no more

than 4W
V3.4 management on the backplane pins
GND on the backplane pins.
Output voltage is slightly above 3.3V to compensate for losses caused by

ORing circuits, which may be present on the external load.
The board satisfies the standby power limit of 10W for AdvancedTCA FRUs,
even when supplying 4W to external loads. Typical power consumption of
the JAXSMM board is 2W.
4.7.4.2 Power Supply Holdup
The JAXSMM complies with the requirements for board level voltage transients.
It meets the requirements for uninterrupted operation during a power failure of
5ms, while supplying 4W to external circuits.
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4.7.5 Frame Ground and ESD

The frame ground connection is provided by the FrameGND backplane
connector.
The front plate mounting holes of the board are connected to frame ground.
An ESD strip, for rear transition modules (RTMs), is provided on one edge of
the PCB.
4.7.6 Front Plate

The following figure shows the position of connector and LEDs on the front
plate of the board.
JAXSMM
OOS
OK
ACT
Eth 3 Activity
Eth 2
Eth 3 Linkup
Eth 1
H/S
Figure 38: JAXSMM Front Plate
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4.7.7 LEDs
The following LEDs are used on the front plate of the board.
OOS Red Failure

Red: The shelf manager board is out of service
OFF: The shelf manager board is working properly
OK Green Power
Green: The shelf manager board is operating properly
Green blinking: The board boots up
OFF: Otherwise
ACT Amber Active

Amber: The shelf manager board is active
OFF: The shelf manager board is in standby mode
H/S Blue Blue: The shelf manager board is ready to be extracted

OFF: The shelf manager board is not ready to be extracted. Do
not remove the board during this state.
Eth 2 Green Green: Link to backplane Ethernet 2 is available

Green blinking: Link and activity
OFF: Otherwise
Eth 1 Green Green: Link to backplane Ethernet 1 is available

Green blinking: Link and activity
OFF: Otherwise
Ethernet 3 Activity Green Green: Link to Ethernet is available

OFF: Otherwise
Ethernet 3 Linkup Amber Amber: Activity

OFF: No activity
Table 17: JAXSMM LEDs
4.7.8 Ethernet Connector

One 10/100 Mbps Ethernet port is provided via the Ethernet connector on the
front plate. It allows external system managers to access the shelf manager.
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4.8 JAXPC
4.8.1 Introduction
The JAXPC is a shelf configuration and alarm board used with AdvancedTCA
systems. The JAXPC alarm board is a 4 Horizontal Pitch (HP) wide x 87 mm
high card and is designed for rear access applications. It is located below the
Rear Transition Module (RTM) area. The communication with the JAXPC alarm
board takes place via Intelligent Platform Management Bus (IPMB).
The JAXPC is a general purpose device providing the functions not
implemented by the other Field Replaceable Units (FRUs).
The JAXPC alarm board:
Contains the Shelf FRU Information Store
Contains rotary switches for setting SGAs

Provides HA, SGA and configuration bit inputs
Visualizes the states and alarms via LEDs on the front panel
Provides interface to IPMB0-A and IPMB0-B.
The following figures show the JAXPC board.
Figure 39: JAXPC Hardware for Board Variant Before 3BK 27226 AACA
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Figure 40: JAXPC Hardware from Board Variant 3BK 27226 AACA On
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4.8.2 Front Panel

The following figure shows the position of connectors and LEDs on the front
panel of the board.
JAXPC

Alarm I/O Connector
Alarm Reset Push Button

Alarm/
Reset Hot Swap LED
H/S
Handle
Closed
Open
Failure LED
Power LED
OOS
OK
Figure 41: JAXPC Front Panel for Board Variant Before 3BK 27226 AACA
JAXPC
Failure LED
OOS
Power LED
OK
Rotary Switch to Set

MS 345
2 the SGA (MS)
6
789
F01
A
BCDE
SGA
Rotary Switch to Set
LS 345
the SGA (LS)
6
789
F 01
BCD
Hot Swap LED

H/S
Figure 42: JAXPC Front Panel from Board Variant 3BK 27226 AACA On
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4.8.3 LEDs
OOS Red Failure

On: The JAXPC alarm board is out of service
Red blinking: the shelf FRU information is invalid
Off: The JAXPC alarm board is working properly
OK Green Power
On: The IPMC has initialized properly
Off: Otherwise
H/S Blue On steady: The JAXPC alarm board is ready to be

extracted
Blue blinking: The IPMC is attempting to communicate
with the JAXSMM
Off: The JAXPC alarm board is operating and not ready
to be extracted. Do not remove the board during this
state.
Table 18: JAXPC LEDs
4.8.4 Alarm I/O Connector

The DB15 connector on the front panel provides access to the dry contact
inputs and outputs.
Starting with board variant 3BK 27226 AACA the alarm I/O connector is
removed.
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4.8.5 Handle Toggle Switch

There is one handle toggle switch located on the front panel. It mimics the
function of the ejector handle on a front panel, as described in the following
table.
Switch Position Function
Upper position Handle is closed
Lower position Handle is open
Table 19: Handle Toggle Switch
Starting with board variant 3BK 27226 AACA the handle toggle switch hardware
implementation is changed, handle opening and closing is triggered by bottom
fixation screw loosening and tightening.
4.8.6 Alarm Reset Push Button

The JAXPC provides an alarm reset push button on the front panel. It is used
to reset a cleared alarm condition.
Starting with board variant 3BK 27226 AACA the alarm reset push button is
removed.
4.8.7 Shelf Addressing

On an ATCA system there are 8 bits allocated for a Shelf Geographic Address
(SGA). The SGA on the JAXPC alarm board is set via two SGA rotary switches.
The two JAXPC in the same shelf must always be set to the same SGA.
S1 (bottom switch in Figure 43) or LS (bottom switch in Figure 44) sets the
lower nibble and S2 (top switch in Figure 43) or MS (top switch in Figure 44)
sets the upper nibble. Use a screwdriver to set the switches by turning them. A
little arrow on the switch shows you the value to which the switch is set.
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S2
S1
Figure 43: Rotary Switches on JAXPC Board Variant Before 3BK 27226 AACA
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MS
LS
Figure 44: Rotary Switches on JAXPC Board from Variant 3BK 27226 AACA On
Optionally, the Shelf Geographic Address can be set by the backplane.
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4.9 JBXPS
For ATCA shelves variants before 3BK 27291 ABxx, four field maintainable
intelligent Power Entry Modules (JBXPS) are installed beneath the rear slots of
the backplane. The JBXPSs A1 and B1 supply the odd numbered slots, and
the JBXPSs A2 and B2 supply the even numbered slots.
Each feed has two power attachment points, each of which is capable of
supplying 50 A.
At the minimum operating voltage (-40 V), this power entry supports 4000 W.
For ATCA shelves from variant 3BK 27291 ABxx on, two field-maintainable
intelligent PEMs are installed beneath the rear slots of the backplane. The
PEMs A1 and B1 supply the slots, the blowers and shelf manager boards.
The JBXPSs provide the following features and functions:
Redundancy so that a single JBXPS failure will still provide full power
to the system
Hot-swap
Not available from board variant from 3BK 27342 AACA on.
Providing monitoring information to the shelf manager
Power feed voltage and current measurement
Temperature sensing
Power filtering
IPMC for input power monitoring within the power distribution path. IPMC
is located on both IPMB-A and IPMB-B buses.
Each JBXPS connects to the distribution board via a Positronic PLC series 3x6
connector and a 3x10 connector. The DIN connector has multiple levels of
mating to allow hot insertion and removal. The panel I/O is comprised of a
power feed input and a hot swap toggle switch, and hot swap and status LEDs.
All JBXPSs are a single width module with dual M6 insulated studs and power
filtering. The four-JBXPS system includes a full IPM interface for 50A.
A toggle switch is provided to allow supervision interruption for maintenance
reasons.
The following figure shows the functional blocks of the JBXPS.
− 48V DC − 48V DC
Current
Breaker Filter
Sensing
Distribution Board
Front Plate
LEDs
Curr/Voltg TEMP
GA
LEDs, Switch
IPMC
Switch
IPMB_0
* : From JBXPS variant 3BK 27342 AACA on, the breaker was removed
Figure 45: JBXPS Functional Blocks
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4 ATCA Shelf
4.9.1 JBXPS Specifications

4.9.1.1 Power Input
The external power is connected to the JBXPS via dual, isolated power studs.
The studs are sized to support a maximum of 90 A when derated for a 30
C temperature rise.
The JBXPS is designed to operate from 36V to 75V and can withstand 100V
transients for at least 100ms, 200V transients for at least 5µs, and 1500V fast
transients. On JBXPS variants before 3BK 27342 AACA, a breaker (depending
on the model) is used to provide shelf protection. The breaker is equipped with
finger guards and a push-to-reset feature to avoid accidental tripping. From
JBXPS variant 3BK 27342 AACA on, the breaker is removed.
4.9.1.2 Power Filtering

The JBXPS is equipped with input power filtering. The filter is designed to
support 50A.
The filter provides transient voltage immunity, in accordance with the IEC
1000-4-4 Part 4 for electronic fast transient/burst immunity specifications, and
test level 1 in accordance with generic EMC requirements.
For details about power distribution system refer to Power Distribution System
(Section 4.1.6).
3BK 21280 AAAA TQZZA Ed.08 97 / 138

4 ATCA Shelf
4.9.2 Front Plate

The following figure shows the front plate of the JBXPS.
closed
handle
open
− (POWER)
H/S
OOS
Rev. Power
ON
OK
I
O
OFF
+(RETURN)
Operating Voltage − 44V to −72 VDC

Maximum Current 50A
Torque Nut 7.12 Nm (8 lbf.in) Max
Figure 46: JBXPS Front Plate for Variants Before 3BK 27342 AACA
H/S
_ (POWER)
_
OOS
ON
OK I
O
OFF
+(RETURN)
Operating Voltage − 44V to −72 VDC

Maximum Current 60A
Torque Nut 7.12 Nm (8 lbf.in) Max
Figure 47: JBXPS Front Plate from Variant 3BK 27342 AACA On
98 / 138 3BK 21280 AAAA TQZZA Ed.08

4 ATCA Shelf
4.9.3 LEDs
OOS Red Out of Service

On: The JBXPS is out of service
OFF: The JBXPS is working properly
OK Green IPMI Status

ON: IPMI is OK
OFF: IPMI has some malfunctions, and the
JBXPS must be replaced.
Rev. Power Red Polarity

ON: Power-feed cables of the JAXPS is reversed
connected.
OFF: Power-feed cables of the JAXPS are correct
connected.
H/S Blue Hot Swap

On JBXPS insertion:
ON: On boards IPMC powers up
Blue blinking: The JBXPS communicates with
the JAXSMM
OFF: The JBXPS is active
On JBXPS extraction:
Blue blinking: The JBXPS notifies the JAXSMM
its request to deactivate
OFF: The JBXPS can be removed.
Table 20: JBXPS LEDs
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4 ATCA Shelf
4.9.4 Handle Switch

The handle switch is located on the front plate in the left upper corner. It has
two positions as described in the following table.
Position Description
Open Out of JAXSMM control
Closed Under JAXSMM control
Table 21: Handle Switch Positions
The handle switch is removed from board variant 3BK 27342 AACA on.
4.10 JBXFAN
The JSXATCA shelf is equipped with four fan modules, JBXFAN.
4.10.1 Front Plate

The following figure shows the JBXFAN font plate.
H/S OOS
CLOSED / OPEN
Figure 48: JBXFAN Front Plate for Variants Before 3BK 27352 AACA
H/S OOS
Figure 49: JBXFAN Front Plate from Variants 3BK 27352 AACA On
100 / 138 3BK 21280 AAAA TQZZA Ed.08

4 ATCA Shelf
4.10.2 LEDs
The following LEDs are used on the front plate of the JBXFAN unit.
OOS Red Out of Service

On: The JBXFAN is out of service
Off: The JBXFAN is working properly
H/S Blue Hot Swap

On JBXFAN insertion:
On: On board IPMC powers up
Blue blinking: The JBXFAN communicates with the JAXSMM
Off: The JBXFAN is active
On JBXFAN extraction:
On: The JBXFAN is ready to be removed.
Blue blinking: The JBXFAN notifies the JAXSMM its request
to deactivate
Off: The JBXFAN is active
Table 22: JBXFAN LEDs
4.10.3 Handle Switch

The handle switch is located on the front plate in the left upper corner. It has
two positions as described in the following table.
Position Description
Open Out of JAXSMM control
Closed Under JAXSMM control
Table 23: Handle Switch Positions
From JBXFAN variants 3BK 27352 AACA on, the handle switch was removed.
4.11 ATCA Fillers

All unused slots are covered with filler blades. These blades ensure a
consistent airflow per slot whether or not the neighboring slot contains an
AdvancedTCA blade.
The system comes delivered with unused slots at the system’s rear covered
with RTM filler blades. These RTM filler blades are necessary to provide
proper airflow.
Front and rear filler blades must be removed before RTM or AdvancedTCA
blade installation.
3BK 21280 AAAA TQZZA Ed.08 101 / 138

4 ATCA Shelf
From ATCA shelf variant 3BK 27291 ABxx on, the rear unused slots are
closed by cover sheets.
4.11.1 JBXFILL
Front unused slots are covered with font fillers, JBXFILL. The following figure
shows the front filler.
Figure 50: JBXFILL View
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4 ATCA Shelf
4.11.2 JAXFILL
Rear unused slots are covered with rear fillers, JAXFILL. The following figure
shows the rear filler.
Figure 51: JAXFILL View
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4 ATCA Shelf
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5 JSXLIU/JSXLIUB Shelf
JSXLIU/JSXLIUB shelf provides basic information about the:
JSXLIU/JSXLIUB shelf
JBXLIU/JBLIU75 board
JBXMUX
JBXPS
Dummy panel.
3BK 21280 AAAA TQZZA Ed.08 105 / 138

5.1 JSXLIU/JSXLIUB Shelf Description

5.1.1 Introduction
The JSXLIU/JSXLIUB shelf ensures the concentration of 256 E1 on a 1 Giga
Ethernet link.
The JSXLIU/JSXLIUB shelf hosts:
Two JBXPS boards supporting the connection from - 40 up to 72VDC

secondary voltage, the EMI filtering, the down conversion in a 12V SELV
voltage, and collects the alarms through a I2C link
Two JBXMUX boards which collect the E1 links from the 16 JBXLIU/JBLIU75
boards on 16 serial links at 36.864 Mbit/s and build packets sent towards up
to 32 directions (125ms each) on a Giga Ethernet link
Up to 16 JBXLIU/JBLIU75 boards converting 16 plesiochronous E1 links
into a synchronous link at 36.864 Mbits (4B/5B coded).
5.1.2 Shelf Position in the System

The JSXLIU/JSXLIUB shelf is located between the DDF and the ATCA shelf
hosting the BSC functions.
It is connected to the DDF through up to 16 cables, each in 32 pairs. The
PCM interfaces are balanced 120 or unbalance 75 , in accordance with
G703 standards.
It is powered from two sources (48/60VDC).
The JSXLIU/JSXLIUB shelf has its own EMI enclosure and fire protection. It
can be hosted in the same cabinet as the ATCA shelf or can be stand-alone.
106 / 138 3BK 21280 AAAA TQZZA Ed.08

This is shown in the following figures.

External E1 Links
O&M + TELECOM
JSXLIU Shelf
JBXCCP
P
JBXOMCP JBXTP JBXCCP
P P N
JBXOMCP JBXTP JBXCCP
W W 1
NE1oE
JBXSSW
W

P
Figure 52: JSXLIU/JSXLIUB Shelf in the BSC
Power Power
Source A Source B
JBXPEM A JBXPEM B JSXATCA SHELF
32 pairs cable
DDF JBXLIU
NE1OE ETHERNET
X 16 JBXMUX A
SWITCH A
16 cables
NE1OE
JBXMUX B ETHERNET
SWITCH B
Figure 53: JSXLIU/JSXLIUB Shelf Environment
3BK 21280 AAAA TQZZA Ed.08 107 / 138

5.1.3 Main Features

The LIU is composed of:
A mechanical housing designed to hold the JBXMUX, the LIU and the
JBXPS pluggable items:
Width compatible with a standard 19” cabinet
Overall height : 3U
Depth : to accommodate the pluggable boards depth of 160 mm.
Two JBXPS slots
Two JBXMUX slots
16 LIU slots
One unused position referred to as the shelf address slot.
The power input is -48/60VDC, redundant with the A + B power feed. The
consumption is less than 100W (fully loaded).
For thermal requirements, natural convection is sufficient. This assumes that
there is 1U free space up one side and down the other side of the shelf.
A single backplane provides all the internal connections between the hosted
boards. All the external accesses to the JSXLIU/JSXLIUB shelf are made
through the front plate of the boards.
JBXPEM JBXLIU JBXLIU JBXLIU JBXLIU JBXLIU JBXLIU JBXLIU JBXLIU JBXMUX JBXDUMMJBXMUX JBXLIU JBXLIU JBXLIU JBXLIU JBXLIU JBXLIU JBXLIU JBXLIU JBXPEM
−48 / 60
−48 / 60
VDC
VDC
4A
4A
Figure 54: JSXLIU/JSXLIUB Shelf Front View
108 / 138 3BK 21280 AAAA TQZZA Ed.08

5.1.4 Mechanical Housing Description

21 slots are available (20 are required) and the spacing is 20.32 mm. The slot
numbering marking is added on a 1U filler on top of the shelf , including the
slot numbers from 1 to 21.
Board guides are plastic and are made with an ESD clip. The board’s
mechanical size is a 3U small form factor.
JBXLIU JBXPEM JBXMUX JBXDUM
Power/Fail Power/Fail
Power/Fail
Active
TEST
E
1
/
T
− 48/60VDC
1
4A
GbE
Figure 55: LIU Hosted Strips and Marking
The following table lists the backplane sizes.
JSXLIU/JSXLIUB Shelf Backplane Weight and Dimensions
Length 426.72 mm
High 128.7 mm
Thickness 3.2 mm
Weight Less than 10 Kg
Table 24: JSXLIU/JSXLIUB Shelf Backplane Weight and Dimensions
3BK 21280 AAAA TQZZA Ed.08 109 / 138

JBXMUX slots position are fitted with a P1 connector and a P2 connector .

Other slots (LIU & JBXPEM) are fitted with only one P1 connector. On the slot
address shelf (slot #11), the P2 connector is replaced by a set of eight jumpers
used to configure the shelf address. Sub-equipment of JBXLIU/JBLIU75 board
is possible and requires no specific recommendations. The JBXDUM filler for
EMI compliance is used to close the unused slot. In terms of hot insertion, the
design of the boards takes account the inrush current.
LIU 14
LIU 16
LIU 10
LIU 12
LIU 13
LIU 15
PEM A
MUX A
PEM B
LIU 11
MUX B
LIU 6
LIU 4
LIU 7
LIU 8
LIU 2
LIU 3
LIU 5
LIU 9
LIU 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Figure 56: JSXLIU/JSXLIUB Shelf Back-Plane Front View
5.1.5 JSXLIU/JSXLIUB Shelf Internal Connection

5.1.5.1 - 48/60 Volts Power Supply
The power supply is in the range -38.4/-72V. It is composed of two independent
lines (VBATA and VBATB), and a common return VBATR. The battery return
is normally not connected to the mechanic ground but to a jumper on each
JBXPEM which can provide the link if requested. The logical ground GND and
the mechanic ground MGND are connected together on the backplane by
screws in a basic configuration. For specific markets, it is possible to separate
them by removing the dedicated screws.
5.1.5.2 VBAT Power Supply Distribution

VBAT power supply enters the front panel of each JBXPEM on the left and
right sides of the shelf . It also is distributed to the other JBXPEM boards. The
VBATO of JBXPEMA is connected to the VBATI of JBXPEMB (and reciprocally).
5.1.5.3 12 Volts Power Supply Distribution

12 V power supply is distributed by each JBXPEM to all the other boards
via a complete plan.
P12VA is the +12 voltage generated by the left JBXPEM. It is connected to
P12Vi on the right JBXPEM.
P12VB is the +12 voltage generated by the right JBXPEM. It is connected to
P12Vi on the left JBXPEM.
110 / 138 3BK 21280 AAAA TQZZA Ed.08

5.1.5.4 Serial Data Interface Between JBXMUX and JBXLIU/JBLIU75 Boards

The serial link carrying data and control between JBXLIU/JBLIU75 boards and
JBXMUX board is encoded 4B/5B. It needs only one pair for each direction.
Two additional pairs are provided for any future use.
The upward interface is composed of UDATPxx and UDATNxx pairs carrying
uplinks A and B from the LIU to the corresponding input or JBXMUX board
A and B.
The downward interface is composed of DDATPxx and DDATNxx pairs carrying
the downlink from JBXMUX A and B to the corresponding LIU input A and B.
5.1.5.5 I2C Link

This link allows the JBXMUX to read the RI EEPROM, the alarm register and
the temperature on the adjacent JBXPEM board. It is composed of the SCL
and SDL signals. Arbitration of I2C master is performed via the active/standby
signal.
The LIU RI data is read by the JBXMUX board through the serial 4B/5B
interface.
5.1.5.6 Active/Standby Control JBXMUX

This link allows selection of the active JBXMUX, depending on the JBXMUX A
and B help and software requests.
5.1.5.7 Board Presence and Reset Links
This link allows each JBXMUX (A or B) to detect whether a LIU is plugged
into a slot, and to restart it.
5.1.5.8 Slot Address

Each slot in the JSXLIU/JSXLIUB shelf backplane is individually identified by a
specific polarization of the SLA signals. “X” indicates that the jumper is present
and lowers the corresponding SLA pin of JBX* board. It is left open, so that the
selected board will detect a logical level “1” via the adequate pull up resistor.
5.1.5.9 Shelf Address

Each JSXLIU/JSXLIUB shelf belonging to a given system can be individually
identified by a specific polarization of SHA signals on the JSXLIU/JSXLIUB
shelf backplane. “X” indicates the jumper is present and lowers the
corresponding SHA (0 to 3) pin of the two JBXMUX boards.
3BK 21280 AAAA TQZZA Ed.08 111 / 138

5.2 JBXLIU/JBLIU75 Board

There are two version of LIU boards, identical from functional point of view
but different by the type of cables that can be connected on it. JBXLIU
supports the 120 Ohm cables connection and JBLIU75 supports the 75 Ohm
cables connection.
5.2.1 Introduction
The JBXLIU/JBLIU75 board ensures the interfacing of 16 plesiochronous E1
links in the JSXLIU/JSXLIUB shelf. The JSXLIU/JSXLIUB shelf hosts 16
JBXLIU/JBLIU75 boards.
The JBXLIU/JBLIU75 board functions are:
In the ingress direction:

2048 kHz clock recovery
HDB3 decoding
LOS detection
Stuffing
Multiplexing 16 lines and board control into a serial signal at 36.864 Mbit/s
Encoding the serial signal 4B/5B at 46.08 Mbauds.
In the egress direction:

46.08 MHz clock recovery
5B/4B decoding
De-multiplexing
De-stuffing
HDB3 encoding.
The E1 interface is compliant with the G.703 recommendations in 120

or 75 termination.
112 / 138 3BK 21280 AAAA TQZZA Ed.08

5.2.1.1 System Description

The JBXLIU/JBLIU75 board is part of the JSXLIU/JSXLIUB shelf which
belongs to the ATCA based platform. It is shown in the following figure in an
BSC environment.
External E1/T1 Links
JBXLIU
JSXLIU Shelf
JBXCCP P
JBXTP JBXCCP
P N
OMCPPP
JBXOMCP
JBXTP JBXCCP
JBXOMCP
OMCP W W 1
W
NE1oE
JBXSSW W
JBXSSW 1 Gigabit Ethernet ATCA Base Interface

P
Figure 57: Platform Architecture
5.2.1.2 LIU Environment

The JBXLIU/JBLIU75 board is hosted in the JSXLIU/JSXLIUB shelf. It is
powered from two redundant +12 V from two JBXPEM boards.
The interface with the two JBXMUX boards through the backplane is composed
of:
One point to point bi-directional encoded serial link 4B/5B carrying both
payload and control data. This link is supported by two pairs with LVDS
signals.
One point to point bi-directional link for board presence indication and
reset functions
Two point to multipoint signals to indicate which is the active JBXMUX (SELA
and SELB). SELA and SELB signals always display a complementary state,
and only SELA is used.
3BK 21280 AAAA TQZZA Ed.08 113 / 138

The JBXLIU/JBLIU75 board provides 16 balanced E1 interfaces on its front

panel via one 68 pin sub-D connector.
− 48V A − 48V B
JSXLIU Shelf
ATCA Shelf
JBXPEM
+12 V +12 V
4B/5B up
4B/5B down
JBXLIU JBXMUX GE Link GE S witch
16 E1/T1
PRSET
MUX Select
Figure 58: JBXLIU/JBLIU75 Board Environment
5.2.2 Hardware Architecture

The JBXLIU/JBLIU75 board provides the following functions:
Power supply
Line Interface
LIU reference clock generation
Mux selection
E1/T1 configuration
Stuffing
Multiplexing
Serialization
4B/5B encoding
Loop-back facilities
RI.
114 / 138 3BK 21280 AAAA TQZZA Ed.08

RI I2C
RI
EEPROM
EEPROM
SELA/B
SELASELB
Electrical E1 MUX
Electrical
protection&& OCTAL
OCTAL Control Bus E1 MUX
Protection LIU E1/T1 Control Bus ++ Serial link 1
Transformer
Transformer LIU E1/T1
Bit stuffing
Bit stuffing
Electrical E1 MUX
E1 MUX
Electrical OCTAL
OCTAL Data
Data ++ Clock ++ Serial link 2
Protection &
Transformer
LIU E1/T1
LIU E1/T1 Bit stuffing
Bit stuffing
JGXESD
Board presence
and reset
E1/T1
E1/T1 selection
selection EPLD
EPLD
EEPROM
EEPROM
2048
2048 1544
1544
kHz kHz
kHz DC/DC
DC/DC 12V (A)
converters
Converters
JSXLIU Board
JSXLIU Board 12V (B)
Figure 59: JBXLIU/JBLIU75 Board Architecture
5.2.2.1 Power Supply

The board is powered from two separated +12 V inputs. The + 3.3 voltage
is obtained via a non isolated converter (the isolation is performed on the
JBXPEM board). The 1.5 voltage required for the JGXESD FPGA is provided
via a linear regulator.
5.2.2.2 Line Interface

The JBXLIU/JBLIU75 provides 16 balanced 120 or unbalanced 75 E1
lines, compliant with G.703.
The line interface is provided by two octal E1 short hall JBXLIU/JBLIU75s in
the PBGA package. These LIUs are associated with four octal transformers
ensuring the galvanic isolation.
Tripolar protection is provided on the PCB to prevent difficulties with regard to
meeting K41 requirements. It is assumed that if this protection is not required, it
will not be equipped.
5.2.2.3 LIU Reference Clock
For clock recovery and jitter attenuation, the E1/T1 LIU needs a 2048 kHz
reference clock when used in E1 mode, and a 1544 kHz reference clock
when used in T1. In order to permit the dual mode, two crystal free running
oscillators are implemented on the board. On the current board, only the 2048
kHz oscillator is equipped.
3BK 21280 AAAA TQZZA Ed.08 115 / 138

5.2.2.4 E1/T1 Configuration

The LIU functions are as follows:
In the ingress direction:

Clock recovery
HDB3 decoding
LOS detection.
In the egress direction:

HDB3 encoding
Jitter attenuation.
The configuration of the LIU is achieved via the non-multiplexed bus type
emulated by the JGXESD. Depending on the configured mode, the LIU
reference clock is switched to 2048 kHz or 1544 kHz. In the current design,
the JGXESD only provides E1 capability. This configuration is downloaded
into the LIU upon hardware reset.
The LIUs are configured as follows:
AIS disabled on LOS
LOS criteria is G.775

HDB3 coding enabled
Jitter attenuator depth 32 bits
Jitter transfer bandwidth 1.7 Hz
Jitter attenuator in transmit path.
In the egress direction, the JGXESD extracts the orders of local or a remote
loop-back on each E1 link from the serial link. It transfers these orders into the
LIU loop-back configuration register. In the ingress, it reads the loop-back and
LOS status registers of the LIU and inserts the information in the serial link.
5.2.2.5 JGXESD Reference Clock

The JGXESD component requires a 36864 kHz transport clock for the 4B/5B
recovery clock function. It is provided via a VCXO used in free run mode.
5.2.2.6 JBXMUX Selection

Depending on the status of the SELA input, the E1 or T1 output signal comes
from the serial link A or B. This function is performed inside the JGXESD
component. The link A is active when SELA is low.
In the ingress direction, the 16 E1 are converted and sent on both serial links.
5.2.2.7 Stuffing
33 bytes of payload are allowed to each E1 or T1 link every 125 ms. Depending
on the phase relationship between each line clock and transport clock, these
33 bytes carry 255, 256, or 257 bits. This function is performed inside the
JGXESD component.
116 / 138 3BK 21280 AAAA TQZZA Ed.08

5.2.2.8 Multiplexing and Serialization

In the ingress direction, the JGXESD multiplexes the data coming from the
16 lines, RI data, and LIU status information on a serial link at 36864 kbit/s.
In the egress direction, the JGXESD extracts the data from the 16 lines and
controls the LIU of the serial link
5.2.2.9 4B/5B Encoding

In the ingress direction, the serial link is encoded 4B/5B. In the egress direction,
the clock is recovered from the received signal, the frame alignment is checked
and the data is decoded 5B/4B. This function is performed by the JGXESD
component.
5.2.2.10 Remote Inventory

An EEPROM with I2C access is dedicated to RI data. It can be read by the
JGXESD component. A specific connector allows the factory to write the
data when the board is not powered.
5.2.2.11 Board Presence

A pull down indicates the presence of the JBXLIU/JBLIU75 board to the
JBXMUX boards. The active JBXMUX board can reset the JBXMUX board
by driving this access high.
5.2.2.12 Hot Insertion
The JBXLIU/JBLIU75 board can be plugged into the JSXLIU/JSXLIUB shelf
without perturbing the other boards of the shelf.
5.2.2.13 ESD Discharge Circuit

An ESD discharge circuit allows a progressive discharge of the board before
complete insertion.
5.2.2.14 Start Policy

The board starts when powered on.
5.2.2.15 Reset Policy

The board is reset at power on, or by the active JBXMUX by PRSET access.
The LIU can be reset through the serial egress link.
5.2.2.16 Boundary Scan Chain (JTAG)

The boundary scan chain includes the JGXESD and the two octal LIU. The
chain is accessible on a dedicated connector for factory use. For future
improvements, a “Firecron“ scan path component is implemented (not
equipped). This component can provide access to the boundary scan chain
from a backplane bus reserved for this application.
3BK 21280 AAAA TQZZA Ed.08 117 / 138

5.2.3 Interfaces
5.2.3.1 Internal Interfaces
The following internal interfaces are available:
Data + clock interface between the LIU and JGXESD

Ingress data + clock interface between the LIU and JGXESD
Egress data + clock interface between JGXESD and the LIU.
Control interface between the LIU and JGXESD
I2C interface
Board type interface.
5.2.3.2 External Interfaces

The following external interfaces are available:
Line interface (X6)

Backplane Interface (X1)
Visual interface (H0201)
Remote inventory interface (X2)
JTAG Interface (X4)
Programming Interface (X3).
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5.2.4 Front Panel

The following figure shows the LIU board front panel for the 120 ohm and 75
ohm solutions.
JBXLIU JBLIU75
Power/Fail
E E
1 1
/ /
T 7
1 5
Power/Fail
Figure 60: LIU Front Panel
5.2.5 Safety
The JBXLIU/JBLIU75 board belongs to the JSXLIU/JSXLIUB shelf and meets
the required safety specifications.
The E1 accesses are TNV1 voltages.
Other circuits are SELV voltage.
Mechanical ground and logic ground are separated on the board. These two
ground types can be connected together at the backplane level.
3BK 21280 AAAA TQZZA Ed.08 119 / 138

5.3 JBXMUX Board

5.3.1 Introduction
The JBXMUX board, which is part of the JSXLIU/JSXLIUB shelf, ensures the
concentration of 256 E1 PCM links on a Gb Ethernet external interface.
This board performs the following functions:
Multiplexing and de-multiplexing of up to 16 E1 trunks (1 per LIU card)

for a total capacity of 256 E1 lines
Overall timing synchronization generation via the nE1oE mechanism

NE1oE packing/ unpacking
Control, supervision and data frame management through the GbE link
Control management and supervision of LIU cards
One GbE physical interface

Active/ standby communication link with the second JBXMUX card for 1+1
protection purpose
Debug interface
RI data storage
Hot insertion.
5.3.2 JBXMUX Hardware Architecture

The JBXMUX card architecture can be described as follows:
The NE1OE block, which provides emission/reception of the E1 links over

Ethernet, along with control management (also over Ethernet). It also
performs Active/ Standby JBXMUX control.
The NE1oE master clock, which provides synchronization timing for the
overall MX platform
One Gb Ethernet physical interface
Control management and supervision of JBXLIU/JBLIU75 cards
Active/ standby communication link with the second JBXMUX card for
1+1 protection purposes
One Flash memory block for FPGA bit stream, and boot firmware
FPGA configuration
One 16MX32 bit SDRAM block attached to the nE1oE system on the
chip processor
One RS232 test interface for the nE1oE SOC processor
One I2C interface for RI data storage
The reset module, which provides the reset logic for the FPGA (JGXEOE
and JGXCLU) and the GbE transceiver
120 / 138 3BK 21280 AAAA TQZZA Ed.08

The power supply module, which provides all the required on-board power
from the backplane 12V A and B rails. It also manages the power/failure
front plate LED.
12V A/B Power

Supply Reset
Front
panel
JGXEOE access
Serial data links
Back
plane Timing
access Active/ standby generation
nE1oE / User & TWSI
LIU cards presence SMbus Control planes
I2C management
RGMII Ethernet
Physical interface
JGXCLU module
RI
EEPROM Debug
System On RS232
FPGA /
Chip transceiver
configuration
FLASH RAM
8 MB 16MX32b
Address/ data/ ctrl Address/ data/ ctrl
Figure 61: JBXMUX Architecture
5.3.2.1 NE1OE Block

The nE1oE function constitutes the main part of the JBXMUX card and is
housed in the JGXEOE FPGA. This function provides, along with the E1
interface/ alignment/ Mux function setting on each LIU card, an overall E1
cross-connect capability for 256 E1 PCM links over Ethernet transport.
The nE1oE can be split into the following sub-blocks:
16E1 data interfaces 4B-5B coding

Each of the 16 serial data links in connection with the 16 LIU cards in
the shelf are 4B-5B coded/decoded for reducing the backplane access
connector pin-count and ultimately simplifying the backplane physical
design. The nominal bit rate before coding is 36.864Mbps and the line
bit-rate is 46.08Mbps. Data out and data in signals are conveyed to/from
each LIU card after single to differential signal conversion (100 Ohm
balanced pairs), ending up with a two pair backplane interconnection per
data stream. Data and synchronization signals are recovered from the 4B5B
code itself via an over-sampling technique.
Ethernet frames packing/ unpacking and E1 cross-connect with physical

entities within the MX platform perimeter (JBXTP, JBXOMCP)
Gb Ethernet MAC/Physical interfacing, with auto-negotiation 10/100/1000

base-T with Reduced Pin count GMII (RGMII) interfacing on the MAC side
Communication with the second JBXMUX card for mutual active/ standby
switching-over process control
Control and user plane management to/from the Gb Ethernet link.
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This part is achieved by an embedded processor (SOC) also in charge of

the SDRAM, the Flash, the I2C, the RS232 debug link, the in-band reset
and shelf address management.
5.3.2.2 Timing Generation

NE1oE Master clock: The designated active JBXMUX card in the
selected JSXLIU/JSXLIUB shelf is by definition also the master, in terms of
synchronization for the entire nE1oE function on the MX platform. As a result,
all other entities present in the system are necessarily synchronized with the
8kHz rhythm sent by the JBXMUX through the nE1oE framing mechanism.
A 36.864MHz VCXO used as a free run oscillator is dedicated to this end, and
provides the clock signal used by the JGXEOE as the reference for all nE1oE
sub-blocks. The 8KHz frame synchronization signal is also internally built
from this reference.
Given that the JGXEOE architecture is common to the different applications
(JBXTP or JBXMUX), the internal PLL tracking is disabled in the JBXMUX case
and the phase comparator output pulse width is set to its mid-range value. An
analog low pass filter (cut-off at approximately 10Hz) provides the VCXO with a
DC voltage, setting the output frequency to its mid-range value.
System clock: A 25MHz system clock signal is produced by a free run
oscillator for the JGXEOE, the JGXCLU and the GbE transceiver. The
JGXEOE Mac interface sub-block uses the 25MHz input clock to produce the
125MHz reference clock necessary for the 10/100/1000base-T application. The
frequency multiplication is managed via an internal broadband PLL embedded
in the FPGA matrix. The same artifact is used on the transceiver Mac side.
5.3.2.3 Ethernet Physical Interface Module

The gigabit Ethernet physical access is performed via the Marvell 88E1111
transceiver. This transceiver use a Reduced pin count GMII (RGMII) interface
with the JGXEOE, and has its MDI interface connected directly to an
1000base-T RJ45 module integrating the filtering magnetics and two LEDs .
RGMII interface:
Upward: TXD[3:0], TXEN, GTX CLK

Downward: RXD[3:0], RXDV, XCLK.
For alarm collection and register programming, the transceiver TWSI interface
is also connected to the JGXEOE.
5.3.2.4 Active/ Standby Communication

In the 1+1 protection scheme philosophy adopted on the MX platform, the
active/ standby switchover provides a very important function of the JBXMUX. It
gives each of the 16 LIU cards in the shelf clear information as to which of the
incoming data streams (from either JBXMUX card A or B) is the valid one.
The active/ standby communication link concerns the two JBXMUX cards
present in the JSXLIU/JSXLIUB shelf as part of a shared RS flip-flop function).
This function provides each JBXMUX with an exclusive mechanism for
triggering one JBXMUX in Active or Standby modes, whereas the second
JBXMUX is automatically set to the opposite state.
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Switchover triggering events:

Master request from the MX platform management entity. The order is
received from the JBXOMCP through the Ethernet and is decoded as such
by the JGXEOE control plane management.
Card in error (see below).
These two events are processed in an autonomous fashion vis-a-vis the MX

platform management entity. In both cases, a report of the JBXMUX state
change is sent to the MX platform management entity through the Ethernet
control frames.
A JBXMUX card is declared in error after any of the following events:
Card currently in reset mode (nE1oE functions are unavailable until the end
of this sequence)
FPGA download sequence NOK (monitoring of JGXEOE init done signal

along with watchdog time-out) or card absent
Boot operational status not validated (specific bit and watchdog time-out
monitoring)
No supervision frame received for more than n X T seconds, whereby T =

mX100 ms and n is a positive integer.
5.3.2.5 Flash Memory Block

The Flash memory contains the FPGA configuration files and the boot code of
the processor embedded in the JGXEOE.
The Flash is accessed via a data path of 8 bits wide at a frequency of 12,5 MHz.
The Flash is split in two main areas
A permanent area programmed in the factory (write protected)

An update area which can be programmed by the SoC processor.
The programming process is controlled by the JGXCLU EPLD but the update
configuration is managed by the embedded processor of the JGXEOE FPGA
and is received through the Ethernet communication.
5.3.2.6 SDRAM Memory Block
The SDRAM is used by the SoC processor to store its executable program
and eventually to store data (constants, variables) if the JGXEOE internal
memory is not sufficient.
The SDRAM capacity is 512 Mbits. It is organized in 16 Mega words of 32
bits each and is accessed via a data bus of 32 bits at the frequency of the
processor (i.e. 66 MHz). The SDRAM memory is built with two 16Mbit*16
memory components.
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5.3.2.7 RS232 Test Interface

Connected to the JGXEOE, this serial interface provides test access through a
dedicated RJ45 connector setting on the front plate.
Communication port settings:
Speed : 115200 baud

Parity : No
Data bits: 8
Stop bit: 1
Flow control: No.
5.3.2.8 LIU Cards Presence Detection

The JGXEOE is in charge of collecting, via the I2C interface, card presence
information for each LIU card slot in the JSXLIU/JSXLIUB shelf. In order to
do so, a I2C decoder able to manage 16 I/O is used to detect the 16 signals
PRST_1 to 16 present on the backplane connectors.
LIU present: PRST_xx = Voltage logic level low (LVTTL)
LIU absent: PRST_xx = Voltage logic level high (forced on the JBXMUX card
input by a pull-up resistor to 3.3V).
5.3.2.9 I2C Interface

A single master I2C interface managed by the JGXEOE is used to communicate
with the :
RI component
JBXPEM in the JSXLIU/JSXLIUB shelf (local RI and alarms polling)
External components in charge of detecting the JBXLIU/JBLIU75 board’s

presence.
For the different I2C items to be accessed properly, each item of the same
type (i.e. RI EEPROM, temperature controller, I2C GPIO) have a unique
hardware address code within this type.
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5.3.2.10 Reset Logic

Two types of reset are implemented on the JBXMUX:
Power-On reset
This is a global hardware reset of the entire card. A power supply
supervisory circuit supervisor monitors the main power supply rail (3.3V).
As soon as it reaches a certain threshold, it maintains the JGXEOE, the
JGXCLU and the GbE transceiver (PHY) in reset. As soon as the JGXCLU
reset is released, it performs the JGXEOE download operation from the
FLASH down to the FPGA. As soon as the JGXEOE bit stream is loaded,
the component “Init-done” signal is activated and the JGXEOE master reset
is released, followed by the boot loader execution
JBXMUX reset
This is a single reset bit carried out by the nE1oE control frames. It is
also used as a global hardware reset for the JBXMUX card. This reset
being conveyed by the FPGA, which is a target for this reset action, the
FPGA JBXMUX reset output falling edge is detected and converted into a
calibrated negative pulse driving the power supply supervisory circuit
(MAX708S) responsible of delivering the master reset pulse. A discrete
component (TLC7701) is responsible for performing this function.
5.3.2.11 FPGA Download

The FPGA download is performed by the JGXCLU EPLD. This device is also
used on the JBXTP card. The behavior of the JGXCLU depends on the type of
the board. Selection of the board type is made with the BRD_SEL(1:0) input pin.
voltage rails from two 12V DC redundant primary feeds.
Start-up, shut-down and supervisory voltage rails are provided via a dedicated
EPLD.
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5.3.3 Front Panel Interface

5.3.3.1 RS232 Test Interface (X5)
The connector type is a 10/100/1000 base T-RJ45 single port.
5.3.3.2 GbE Interface (X6)

The GbE interface provides:
Connector type: 10/100/1000 base T-RJ45 single port with integrated

LEDs and magnetics.
The mechanical ground is connected via the PCB to the connector shield.

Top LED (Link Satus
up/down)
PCB pin side
Bottom LED (1000 base T
link activity)
Figure 62: 1000 Base-T RJ45 Connector Front View
5.3.3.3 LEDs
Four LEDs are visible on the front panel (from the top to the bottom):
Power On/Off/failure LED (L1)

This is a bi-colour, red/green LED. When the card is powered on and all the
monitored power supply rails voltages are at least at 0.9xVcc, the green
LED is turned on. If any of the power supply rails drop below 0.9xVcc, the
green LED is turned off and the red LED is turned on
Active/ standby LED (L2)

This is a yellow LED driven by the JGXEOE SEL signal. When the JBXMUX
card is in active mode, the signal SEL is set to 3.3V, saturating a switching
transistor and turning the LED on. When the JBXMUX card is back in
standby mode, the LED is turned off.
Two additional LEDs are associated with the GbE RJ45 front panel connector:
Upper LED (L3): Link status. Green LED:

LED on: Link up
LED off: Link down.
When up, the link is operational, in either idle or transmission modes.
Lower LED (L4): 1000 base-T Link activity. Yellow LED

LED on: Transmitting
LED off: Not transmitting or negotiated mode is 10base-T or 100base-T.
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5.3.4 Backplane Interface

Two connectors share the overall height of the card on the back.
The backplane accesses are as follows:
JBXLIU/JBLIU75/ JBXMUX 16E1 serial differential links
JBXMUX active/ standby link
I2C link
Slot address
Shelf address
12V Power supply A & B
JBXLIU/JBLIU75 card presence
Provision for JSXLIU/JSXLIUB shelf unused slot communication.
3BK 21280 AAAA TQZZA Ed.08 127 / 138

5.3.5 Front Panel

The following figure shows the JBXMUX front panel.
JBXMUX
GREEN/ RED Led
YELLOW Led
TEST
Test access
GbE
Link status (L3)
GbE access
Link activity (L4)
Figure 63: JBXMUX Front Panel
5.3.6 Power Supply Description

This block is responsible for converting the incoming 12V A and 12V B DC
voltages to the following DC voltage rails:
+3.3V / GND powers the RAM, the Flash, the JGXCLU, the JGXEOE I/O,
the ISPPAC and all the discrete components
+1.5V / GND is for the JGXEOE core
+1.2V / GND is for the GbE transceiver core
+2.5V / GND is for the GbE transceiver I/O and the JGXEOE I/O.
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5.3.6.1 TNV/ SELV Galvanic Isolation

The incoming 12V rails are provided by each JBXPEM card in the
JSXLIU/JSXLIUB shelf. The -48V to +12V DC/DC converters used for this
purpose feature a galvanic isolation between the two classes of voltages
handled in the system. For this reason, the DC/DC converter block used on
the JBXMUX card does not have to exhibit any galvanic isolation, thereby
reducing its overall cost.
5.3.6.2 Power Supply Management
A specialized IC monitors and controls each secondary power supply voltage
rail used by the card:
Card plug-in (hot insertion) whereby all the secondary voltages rails are
enabled at the same time and a smooth start is programmed to limit the
inrush current
DC rail voltage failure, whereby any secondary power supply rail whose
voltage value is below 10% of its nominal value ( factory programmable
threshold) triggers a global disabling of all the secondary rails.
5.3.7 Safety
The JBXMUX board belongs to the JSXLIU/JSXLIUB shelf, and meets the
safety specifications, according to the LIU Product Integration Qualification
Specification:
The Gigabit Ethernet access is TNV1 voltage class
Other circuits are SELV voltage class.
Mechanical ground and logic ground are kept separated on the board. These
two ground types can be connected together at the backplane level by addition
of dedicated screws.
With regard to the ESD discharges for the front plate and the electrical ground
planes. The Compact PCI standard [16] ensures a soft discharge of any
hazardous ESD buildup by the use of 3 copper stripes laid down the PCB card,
and one metallic card guide clip placed within mechanical rails in the shelf.
When the card is plugged into its slot, the stripes are successively in contact
with the clip, ensuring an electrical path towards the mechanical ground.
Consequently, the front plate is connected to stripe 1 (nearest to the front plate)
through a 10M Ohm resistance, the ground planes are connected to the second
stripe, and the third stripe (nearest to the back side) connects the front plate
directly to the mechanical ground (no resistance).
3BK 21280 AAAA TQZZA Ed.08 129 / 138


Card enclosure Chassis
ESD Stripes
10 M Ohm
Font plate 1
GND planes 2
Mechanical ground
Card guide clip
Figure 64: ESD Mitigation Mechanism
130 / 138 3BK 21280 AAAA TQZZA Ed.08

5.4 JBXPEM Board

5.4.1 Introduction
The JBXPEM board handles the power for the JSXLIU/JSXLIUB shelf. Each
JBXPEM receives front input from - 40V up to - 72 VDC, redundant A + B
power feeds. Each JBXPEM board distributes the +12VDC supply to the
JBXLIU/JBLIU75 and JBXMUX boards. The global consumption is less than
100W (fully loaded).
The JBXPEM board is part of the JSXLIU/JSXLIUB shelf, which belongs
to the MX platform.
The JBXPEM board is hosted in the JSXLIU/JSXLIUB shelf in slots 1 and 21.
Each JBXPEM board receives -48/60 VDC on the front panel. The redundant
function between both JBXPEMs is provided through the backplane.
JSXLIU Shelf
− 48V Redundant
A Input link
JBXPEM A
JBXPEM B − 48V
B Input
I2C
+12V link +12V
JBXLIU JBXMUX A&B

1 to 16 + unused slot
Figure 65: JBXPEM Environment
3BK 21280 AAAA TQZZA Ed.08 131 / 138

5.4.2 JBXPEM Architecture and Functions

The JBXPEM board functions are as follows:
EMI filter
DC/DC converter with basic insulation (-40/72VDC into +12Vdc)
Alarm connection
Temperature detection
RI EEPROM
Current limitation device for hot insertion.
The following figure shows the JBXPEM board architecture.
− 48V Back input

− 48V EMI filter to the other PEM B
EMI filter
front input
Power coupling DC/DC
+
Current limitation DC/DC
Current limitation isolated converter
isolated converter 12V (A or B)
+
Protection
− 48V Back input ALA12
+
from other PEM B Input monitoring ALA48 Ala collect
Input monitoring Alarm Slot Address
collection
Local +12V
Temperature
Logic alim sensor
Logic alim +3.3V
Remote + 12V
I2C
RI
I2C
Power Entry Module EEPROM
Figure 66: JBXPEM Board Architecture
5.4.2.1 Hot Insertion Device

The JBXPEM board can be plugged into the JSXLIU/JSXLIUB shelf without
disturbing the other boards in the shelf. A specific device suppresses the
inrush input current.
5.4.2.2 EMI Filter

An EMI filter is required in order to be compliant with the 73/23/EEC directive,
to obtain the CE marking label.
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5.4.2.3 48V / 12V Conversion

Two incoming separated input power supplies feed each board:
Front input -48/60Vdc
Back panel input -48/60Vdc (VBATI).
12 V power supply is distributed by each JBXPEM to all the other boards

via a complete plan.
P12VA is the +12 voltage generated by the left JBXPEM. It is connected to
P12Vi on the right JBXPEM.
P12VB is the +12 voltage generated by the right JBXPEM. It is connected to
P12Vi on the left JBXPEM.
5.4.2.4 12V /3.3V Conversion

The 12V to 3.3V conversion is made by a bipolar low drop device to feed the
logical alarm supervision. The regulator is powered by two 12V. The first is the
local 12V of the JBXPEM and the second is the 12V of the second JBXPEM.
5.4.2.5 Hardware Management
A multi-master I2C interface, managed by the JGXEOE of the JBXMUX,
is used to communicate with the:
RI component (EEPROM 512X8, 10ms)

JBXPEM in the JSXLIU/JSXLIUB shelf (local RI and alarms polling)
External components in charge of detecting the JBXLIU/JBLIU75 boards’

presence.
Each item of the same type (i.e. RI EEPROM, temperature controller, I2C
GPIO) has a single hardware address code within this type.
Slot Address: Each slot in the JSXLIU/JSXLIUB shelf backplane is individually
identified by a specific polarization of the SLA signals. “X” indicates that the
jumper is present and drives the corresponding SLA pin of JBX* board. When
it is left open, the selected board detects a logical level “1” via an adequate
pull up resistor.
The address number of the JBXPEM board is:
1 for JBXPEM A
21 for JBXPEM B.
RI EEPROM: An EEPROM with I2C access is dedicated to RI data. It can be

read by the active JBXMUX board component. A specific connector allows the
factory to write the data when the board is not powered.
3BK 21280 AAAA TQZZA Ed.08 133 / 138

Alarm Collection: The different alarms come from:

-48/60Vdc of JBXPEM board A
-48/60Vdc of JBXPEM board B
12V
The temperature sensor.
All the alarms are connected to a I²C/SMBus device. This I2C link allows the
JBXMUX to read the RI EEPROM, the alarm register and the temperature on
the adjacent JBXPEM board. It is composed of the SCL and SDL signals.
Arbitration of the I2C master is performed via active/standby signals.
Temperature Sensor: The LM75 temperature sensor provides the local
temperature at all times to the JBXPEM board. When the temperature exceeds
80C, the device generates a temperature alarm.
5.4.2.6 Redundant A+B Power Feed

The VBAT power supply enters the front panel of each JBXPEM on left and
right sides of the shelf. It is also distributed to the other JBXPEM board. The
VBATO of JBXPEM A is connected to VBATI of JBXPEM B (and reciprocally).
Each JBXPEM board generates 12V (A & B). All the other boards are powered
by two 12V:
P12VA from JBXPEM A
P12VB from JBXPEM B.
5.4.2.7 ESD Discharge Circuit

An ESD discharge circuit allows a progressive discharge through a resistor
(10 MW) on the board before complete insertion.
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5.4.3 Front Panel

The front panel shows the:
Front board connector
Visual interface
RI.
JBXPEM
Power/Fail
− 48/60VDC
4A
Figure 67: JBXPEM Front Panel
5.4.3.1 Front Board Connector

The front board connector (X3) type UPI has three pins:
Pin 1 for -48/60VDC input (VBAT)
Pin 2 for 0VCR input (VBATR)
Pin 3 for MMECA (or MGND) input (shelf ground).
3BK 21280 AAAA TQZZA Ed.08 135 / 138

5.4.3.2 Visual Interface

A LED indicator on the front plate shows the board’s status, as described in
the following table.
Color Description
Off The board is not powered.
Green The board is powered and OK.
Amber One input -48/60VDC is missing.
Red Board failure is detected (local +12V

failure).
5.4.3.3 Remote Inventory

The interface for RI factory access is via a CONAN 9-pin connector.
5.4.4 Back Plane Connector

The board connector (J1) is a compact PCI type A.
160 mm
100 mm
3U board format
J1
X3
Figure 68: JBXPEM Side View
136 / 138 3BK 21280 AAAA TQZZA Ed.08

5.4.5 Safety
The JBXPEM board meets safety standards.
The front input -48/60VDC access is a classified TNV2 circuit. The output of
the DC/DC and the other circuits are classified as SELV.
Mechanical ground (MGND) and logic ground (GND) are separated on the
board. These two grounds can be connected together through the backplane,
depending on the equipment.
5.5 Dummy Panel (JBXDUM)

Each unused slot in the JSXLIU/JSXLIUB shelf is closed by a dummy panel,
JBXDUM
The following figure shows the front and side view of the dummy panel.
JBXDUM
Figure 69: JBXDUM Front and Side Views
5.6 LIU Filler (JMXF1U)

Above each JSXLIU shelf, a JMXF1U filler is used to give the physical slot
number for the blades. It is not part of JSXLIU shelf.
The following figure shows the front view of the filler.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Figure 70: JMXF1U Front View
3BK 21280 AAAA TQZZA Ed.08 137 / 138

5.7 LIUB Label

On top of the front side of each JSXLIUB shelf, a label gives the physical slot
number for the blades. It is part of JSXLIUB shelf.
The following figure shows the JSXLIUB label.
JSXLIUB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Figure 71: JSXLIUB Label
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Alcatel-Lucent GSM

9130 BSC Evolution Hardware

BSC & TC Document

3BK 21280 AAAA TQZZA Ed.08

Short title 9130 BSC Evolution HW Description

2 / 138 3BK 21280 AAAA TQZZA Ed.08

3BK 21280 AAAA TQZZA Ed.08 3 / 138

4 / 138 3BK 21280 AAAA TQZZA Ed.08

5.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

3BK 21280 AAAA TQZZA Ed.08 5 / 138

6 / 138 3BK 21280 AAAA TQZZA Ed.08

Figure 38: JAXSMM Front Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

3BK 21280 AAAA TQZZA Ed.08 7 / 138

8 / 138 3BK 21280 AAAA TQZZA Ed.08

What’s New In Edition 08

JBXOMCP/JBXCCP (Section 4.2)

JBXSSW (Section 4.3)

JAXSSW (Section 4.4)

LEDs (Section 4.5.4)

JAXPC (Section 4.8)

JBXPS (Section 4.9)

JBXFAN (Section 4.10)

ATCA Fillers (Section 4.11).

JBXOMCP/JBXCCP (Section 4.2)

JBXSSW (Section 4.3)

LEDs (Section 4.9.3).

JBXOMCP/JBXCCP (Section 4.2)

JBXSSW (Section 4.3).

3BK 21280 AAAA TQZZA Ed.08 9 / 138

Audience This manual is intended for:

System support engineers

Any other personnel requiring an overview of the Alcatel-Lucent 9130

10 / 138 3BK 21280 AAAA TQZZA Ed.08

The Overview provides information needed by project managers and foremen,

3BK 21280 AAAA TQZZA Ed.08 11 / 138

Thermal cooling, achieved with forced-air cooling

Minimization of floor space

Ease of access for maintenance, from the front of the cabinets

Line Interface Unit (JSXLIU/JSXLIUB)

Power Distribution Unit (JSXPDU).

12 / 138 3BK 21280 AAAA TQZZA Ed.08

Table 1: Alcatel-Lucent 9130 BSC Evolution Configuration Naming Conventions

u : Slot is not used and is closed with a filler

JBXCCP in slot 10 is always present to support the redundancy function, but it

3BK 21280 AAAA TQZZA Ed.08 13 / 138

Board JBXFAN1 JBXFAN2

SBL FAN1 FAN2

Board JBXFAN3 JBXFAN4

SBL FAN3 FAN4

Table 3: ATCA Shelf Front View Board-Area-Slot-SBL Mapping

14 / 138 3BK 21280 AAAA TQZZA Ed.08

Board ... JAXSSW2 JAXSSW1 ...

Physical 14 ... 8 7 ... 1

Logical slot 30 ... 24 23 ... 17

SBL SSW-HW2 SSW-HW1

JBXPS area JAXSMM area JAXPC area

Board JBXPS1 JBXPS2 JBXPS3 JBXPS4 JAXSMM2 JAXSMM1 JAXPC2 JAXPC1

Table 4: ATCA Shelf Rear View Board-Area-Slot-SBL Mapping

3BK 21280 AAAA TQZZA Ed.08 15 / 138