DCT 2009.06 SG

CUSTOMER EDUCATION SERVICES
Design Compiler
Topographical/Graphical
Workshop
Student Guide
10-I-013-SSG-002 2009.06
Synopsys Customer Education Services

700 East Middlefield Road
Mountain View, California 94043
Workshop Registration: 1-800-793-3448
www.synopsys.com
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Design Compiler Topographical/Graphical Student Guide

Table of Contents
Unit i : Introduction & Overview

Introductions .................................................................................................................... i -2
Facilities ........................................................................................................................... i -3
Workshop Goal ................................................................................................................ i -4
Target Audience ............................................................................................................... i -5
Workshop Prerequisites ................................................................................................... i -6
Curriculum Flow .............................................................................................................. i -7
Agenda ............................................................................................................................. i -8
Workshop Objectives: Day 1 ........................................................................................... i -9
Icons Used in this Workshop ......................................................................................... i -10
Unit 1: DC-T Physical Elements

Unit Objectives ................................................................................................................ 1-2
Why DC-Topographical................................................................................................... 1-3
DC-Topographical ........................................................................................................... 1-4
DC-T Timing Correlation to Layout ................................................................................ 1-5
DC-T Area Correlation to Layout .................................................................................... 1-6
DC-T Power Correlation to Layout ................................................................................. 1-7
Measuring DC-T Results ................................................................................................. 1-8
Inputs and Outputs ........................................................................................................... 1-9
DC-T Physical Inputs ..................................................................................................... 1-10
Milkyway Library .......................................................................................................... 1-11
Technology File (.tf file) ................................................................................................ 1-12
TLUplus file ................................................................................................................... 1-13
Mapping File .................................................................................................................. 1-14
Floorplan ........................................................................................................................ 1-15
Checklist – Physical Files to Ask For ............................................................................ 1-16
Typical DC-T Flow: Preparing to Compile ................................................................... 1-17
Typical DC-T Flow: Post-Compile ................................................................................ 1-18
Interfacing with DC-T.................................................................................................... 1-19
Key GUI Elements: TopLevel Window ........................................................................ 1-20
Key GUI Elements: LayoutWindow .............................................................................. 1-21
DisplayingTopLevel and LayoutWindow...................................................................... 1-22
Cross-Window Probing.................................................................................................. 1-23
GUI: Displaying Reports ............................................................................................... 1-24
Summary ........................................................................................................................ 1-25
TFU ................................................................................................................................ 1-26
Additional Ways to Increase Correlation ....................................................................... 1-27
Lab 1: Examining DC-T Physical Elements .................................................................. 1-28
Synopsys 10-I-013-SLG-001 i Design Compiler Topographical/Graphical Workshop

Table of Contents
Unit 2: Setting Up and Running

Unit Objectives ................................................................................................................ 2-2
Input Files to Provide ....................................................................................................... 2-3
Creating Milkyway Design Library ................................................................................. 2-4
Add TLUplus Files .......................................................................................................... 2-5
Add Optional Floorplanning Information ........................................................................ 2-6
Create Seed Script ............................................................................................................ 2-7
Configure Your Seed Script ............................................................................................. 2-8
RMgen Files .................................................................................................................... 2-9
common_setup.tcl ........................................................................................................ 2-10
dc_setup.tcl .................................................................................................................... 2-11
./dc_scripts/dc.tcl (reading) ............................................................................................ 2-12
./dc_scripts/dc.tcl (transforming) ................................................................................... 2-13
./dc_scripts/dc.tcl (writing) ............................................................................................ 2-14
./dc_scripts/dc.tcl (reporting) ......................................................................................... 2-15
Checking Your Input to DC-T ....................................................................................... 2-16
Summary ........................................................................................................................ 2-17
Lab 2: Running DC-Topographical ............................................................................... 2-18
Unit 3: Typical Flows

Unit Objectives ................................................................................................................ 3-2
Conventions used in teaching the three flows.................................................................. 3-3
Flat Flow with Test and Power ........................................................................................ 3-4
set_ignored_layers .......................................................................................................... 3-5
extract_physical_constraints ............................................................................................ 3-6
set_power_prediction true ................................................................................................ 3-7
Test Ports in RTL and in Floorplan ................................................................................. 3-8
Reports ............................................................................................................................. 3-9
Before moving to the next flow… ................................................................................. 3-10
Test and Power Flow: If you need a .def file ................................................................. 3-11
Supported DCT Physical Constraints ............................................................................ 3-12
Defining Relative Core Shape: Aspect Ratio................................................................. 3-13
Defining Relative Core Size: Utilization ....................................................................... 3-14
Defining Exact Core Area .............................................................................................. 3-15
Defining Relative Port Sides .......................................................................................... 3-16
Defining Exact Ports, Macros, Bounds, Blockages, Wires........................................... 3-17
Before moving to the next flow… ................................................................................. 3-18
Sometimes a Hierarchical Flow is Necessary ................................................................ 3-19
Interface Logic Models (ILMs) ..................................................................................... 3-20
If Your Flow is Hierarchical .......................................................................................... 3-21
Before moving to Common Methodologies… ............................................................. 3-22
Methodologies Common to all Flows ............................................................................ 3-23
Drive Synthesis with Realistic Constraints .................................................................... 3-24
Synopsys 10-I-013-SLG-001 ii Design Compiler Topographical/Graphical Workshop

Table of Contents
DCT Automatic High Fanout Synthesis (AHFS) .......................................................... 3-25

DCT Automatic High Fanout Synthesis (AHFS) .......................................................... 3-26
Black-Box Support in DCT ........................................................................................... 3-27
Before moving to lab… ................................................................................................. 3-28
Summary ........................................................................................................................ 3-29
Lab 3: Variations: Running DC-T ................................................................................. 3-30
Unit 4: Handling Congestion

Unit Objectives ................................................................................................................ 4-2
What is congestion? ......................................................................................................... 4-3
How does DC-G calculate congestion ............................................................................. 4-4
Ensuring accurate congestion analysis............................................................................. 4-5
How do you analyze congestion? .................................................................................... 4-6
Report_congestion and worst hot spot ............................................................................. 4-7
Report_congestion and Percent GRCs ............................................................................. 4-8
Comparing Congestion Numbers ..................................................................................... 4-9
Fixing Congestion .......................................................................................................... 4-10
The GUI: Bringing up the Congestion View ................................................................. 4-11
The GUI: Using the Congestion View ........................................................................... 4-12
The GUI: Interpreting the Congestion Map ................................................................... 4-13
RTL Code Influencing Congestion ................................................................................ 4-14
Tracing from GUI back to possible RTL source ........................................................... 4-15
Recommended Congestion Fixing Flow ........................................................................ 4-16
compile_ultra -congestion ............................................................................................. 4-17
Summary ........................................................................................................................ 4-18
Lab 4: Congestion .......................................................................................................... 4-19
Unit 5: Ensuring the Integrity of Results

Review Elements, Flows, Congestion ............................................................................. 5-2
Unit Objectives ................................................................................................................ 5-3
Additional Options and Techniques................................................................................. 5-4
Name Matching: Why is it necessary?............................................................................. 5-5
Name Matching: Actions you can take ............................................................................ 5-6
Viewing a floorplan prior to compile_ultra ..................................................................... 5-7
Manually Matching DC-T and ICC Settings ................................................................... 5-8
Automatic Compare of Environment Settings ................................................................. 5-9
Consistency Checker Report: Variables ........................................................................ 5-10
Consistency Checker Report: Commands ..................................................................... 5-11
DC Graphical: Some additional power .......................................................................... 5-12
Concurrent Multi-Corner Multi-mode (MCMM) .......................................................... 5-13
Summary ........................................................................................................................ 5-14
Synopsys 10-I-013-SLG-001 iii Design Compiler Topographical/Graphical Workshop

Table of Contents
Unit CS: Customer Support

Synopsys Support Resources ........................................................................................ CS-2
SolvNet Online Support Offers..................................................................................... CS-3
SolvNet Registration is Easy ........................................................................................ CS-4
Support Center: AE-based Support ............................................................................... CS-5
Other Technical Sources ............................................................................................... CS-6
Summary: Getting Support ........................................................................................... CS-7
Synopsys 10-I-013-SLG-001 iv Design Compiler Topographical/Graphical Workshop

Design Compiler
2009.06

© 2009 Synopsys, Inc. All Rights Reserved Synopsys 10-I-013-SSG-002
Introduction & Overview i -1

Design Compiler Topographical/Graphical Workshop © 2009
Introductions
Name
Company
Job Responsibilities
EDA Experience
Main Goal(s) and Expectations for this Course
i -2
EDA = Electronic Design Automation

Facilities
Building Hours Phones
Emergency EXIT Messages
Restrooms Smoking
Meals Recycling
Please turn off cell phones and pagers
i -3

Workshop Goal
Use Design Compiler Topographical/Graphical

to bring physical constraints into logic
synthesis, thereby increasing correlation and
decreasing iterations with physical tools.
i -4

Target Audience
Engineers familiar with Design Compiler

using wireload models
i -5

Workshop Prerequisites
You should have experience in the following areas:

UNIX and X-Windows
A Unix-based text editor
Writing scripts using Tcl
Setting up and running Design Compiler with wireload
models
Analyzing Design Compiler results
i -6

Curriculum Flow
IC Compiler 2: CTS
IC Compiler 1 IC Compiler 2: HDP
The
The Power
Power of Tcl
The PowerofofTcl
3 workshops Tcl
3 workshops
Design Compiler 1 atat333skill
workshops
levels
at 3skill
skilllevels
levels
Design Compiler ere

You are h
PrimeTime 2: PrimeTime 2:
PrimeTime 1 Debugging & Constraining
Debugging Constraints
Custom Clocks
PrimeTime:
Signal Integrity
DFT Compiler 1 TetraMAX 1 TetraMAX 2: DSM
i -7
The entire Synopsys Customer Education Services course offering can be found at:
http://training.synopsys.com
Synopsys Customer Education Services offers workshops in two formats: The “classic”
workshops, delivered at one of our centers, and the virtual classes, that are offered conveniently
over the web. Both flavors are delivered live by expert Synopsys instructors.
In addition, a number of workshops are also offered as OnDemand playback training for FREE!
Visit the following link to view the available workshops:
http://solvnet.synopsys.com/training
(see under “Tool and Methodology Training”)

Agenda
DAY
1
1 DC-T Physical Elements
2 Setting up and Running
3 Typical Flows
4 Handling Congestion
5 Ensuring Integrity of Results
Synopsys 10-I-013-SIG-002 © 2009 Synopsys, Inc. All Rights Reserved i -8

Workshop Objectives: Day 1
Successfully load physical element files into DC-T

Configure, generate, and adapt ‘seed’ scripts to a
design
Modify scripts for common DC-T flows
Analyze and handle congestion
Access powerful supporting features and
methodologies
i -9

Icons Used in this Workshop
Lab Exercise ! Caution
Definition of
Recommendation
Acronyms
For Further Reference Question
“Under the Hood”

Group Exercise
Information
i - 10
Lab Exercise: A lab is associated with this unit, module, or concept.

Recommendation: Recommendations, tips, performance boost, etc.
For Further Reference: Identifies pointer or URL to other references or resources.
Under the Hood Information: Information about the internal behavior of the tool.
Caution: Warnings of common mistakes, unexpected behavior, etc.

Definition of Acronyms: Defines the acronym used in the slides.
Question: Marks questions asked on the slide.
Group Exercise: Test for Understanding (TFU), which may require you to work in groups.

Agenda
DAY
1
2 Setting up and Running
3 Typical Flows
Synopsys 10-I-013-SSG-002 © 2009 Synopsys, Inc. All Rights Reserved 1- 1
DC-T Physical Elements 1-1

Unit Objectives
After completing this unit, you should be able to:

Describe the problem solved by DC-T
Describe physical elements you provide DC-T
Describe where DC-T fits in the design flow
Describe the internal flow through DC-T
Navigate the DC-T GUI
1- 2

Why DC-Topographical
Problem: Too many iterations
Net delay is major component of path delay
Wireload-model-based net delay calculations do
HDL Coding
not correlate with post-layout net delay
Timing violations and congestion not visible until
after layout, resulting in excessive iterations
Synthesis
Impacts
QOR
Time to market
Physical Design
Need: Correlation & predictability

Identify and correct problems during logic
synthesis
1- 3

DC-Topographical
Requires DC Ultra
license
Uses “virtual placement” to calculate net RC

RC calculations based on routing
Correlated Results
Galaxy
Timing & Area Power Test
Design Shared Techology
with ICC
Compiler
Topographical
Signoff
Reduces iterations
Easily adaptable into

IC existing design flows
Compiler
Milkyway
1- 4
There is no DC-Topographical License.
DC-Topographical requires licenses for:

DC-Ultra
DesignWare Foundation
(V) HDL Compiler
DC–Topographical GUI requires licenses for:

Design Vision
DC Graphical

DC-T Timing Correlation to Layout
19% of designs have same timing as layout

Correlation
Average 2.8%
%
80% of designs correlate to within 5% of layout

2008.09 Timing Correlation to Layout
# of Designs
1- 5

DC-T Area Correlation to Layout
47% of designs correlate to within 5% of layout

Correlation
Average 5.8%
%
# of Designs
1- 6

DC-T Power Correlation to Layout
1- 7

Measuring DC-T Results
Functional
HDL Coding
Simulation
Functionally Realistic DC-T results may look

Correct? worse than wireload-based results
But, DC-T provides physical tools
with realistic starting place, ensuring
Synthesis
Correlation
Predictability
Physical Design
Overall TTR improves
Meaningful QOR measurements are
Final Analysis taken after layout (ICC place_opt)
Timing
Area
1- 8

Inputs and Outputs
Inputs
RTL design
Although an existing gate-level netlist can
also be used, RTL enables greater
RTL Constraints optimization
Timing and optimization constraints

If WLM are specified, they are ignored
Logical
Library
Design Logical library – Liberty (.db) format
Compiler®®
Physical Topographical
Library Physical library – Milkyway format
l
na
tio
op
Floorplan Outputs
Synthesized Design in DDC or Milkyway format
Design
Will contain annotated net RC based on
Topographic technology
Design in Verilog format (simple netlist)
1- 9

DC-T Physical Inputs
Milkyway
Reference
Libraries
•For the most realistic synthesis, provide physical information

•From the ASIC vendor
•Physical cell libraries
•A technology file
•Min and Max TLUplus files
•A mapping file, which maps the technology file layer
names to the TLUplus file layer names
•From your floorplanner
•A floorplan
1- 10

Milkyway Library
Milkyway
Design
Library
Milkyway
Reference
Libraries
Milkyway Library: A database consisting of a unix

directory structure
2 types of Milkyway libraries:
Reference Library: provided by your ASIC vendor
Contains data specific to a given technology
Is a DC-T input
Design Library: created by you
Contains data specific to a given design
Contains pointers to Reference Library
Is a DC-T database that can be handed off to ICC
1- 11

Technology File (.tf file)
Technology {
Describes metal layer name = "cb1314 "
technology for the physical cells dielectric = 3.73e-05
unitTimeName = "ns"
timePrecision = 1000
Number and name designations unitLengthName = "micron“
for each layer/via …
}
Dielectric constant for technology Layer "METAL" {
layerNumber = 14
Physical and electrical maskName
pitch
= "metal1"
= 0.41
characteristics of each layer/via defaultWidth = 0.16
minWidth = 0.16
Design rules for each layer/Via …
(Minimum wire widths and wire-to-

wire spacing, etc.)
Units and precision for electrical
units
1- 12

TLUplus file
Contain C and R look-up tables

Model UDSM process effects
Conformal Dielectric
Metal Fill
Shallow Trench Isolation
Copper Dishing:
Density Analysis
Width/Spacing
Trapezoid Conductor
# TECHNOLOGY=1314max
# CONDUCTOR cm4 { THICKNESS=0.90 WMIN=0.44 SMIN=0.46 RPSQ=0.060}
# CONDUCTOR cm { THICKNESS=0.26 WMIN=0.16 SMIN=0.18 RPSQ=0.109}
# CONDUCTOR poly { THICKNESS=0.18 WMIN=0.13 SMIN=0.20 RPSQ=10.965}
1- 13

Mapping File
The Mapping File maps the .tf (MW technology file)

layer/via names to the TLUplus layer/via names.
TLUplus file
# TLUplus File
# TECHNOLOGY=1314max
Tech file # CONDUCTOR cm { THICKNESS=0.26 WMIN=0.16 SMIN=0.18 RPSQ=0.109}
# CONDUCTOR poly { THICKNESS=0.18 WMIN=0.13 SMIN=0.20 RPSQ=10.965}
Technology {
name = "cb1314 " Map file
dielectric = 3.73e-05 cb13_4m.map
unitTimeName = "ns" ::::::::::::::
timePrecision = 1000 conducting_layers
unitLengthName = "micron“
… poly poly
} metal1 cm
Layer "METAL" { metal2 cm2
layerNumber = 14 metal3 cm3
maskName = "metal1" metal4 cm4
pitch = 0.41
defaultWidth = 0.16
minWidth = 0.16
…
1- 14

Floorplan
Floorplan elements enable more realistic synthesis

Ports
Macros such as
memory cells
Placeable core area

for standard cells
Hierarchical blocks such as ILMs or

.ddc files
1- 15

Checklist – Physical Files to Ask For
Physical shapes
– used by placer
From the ASIC Vendor
Physical library Layers, routing rules,
unit tile – used by
“Associated” Files placer
Technology File
Refines net UDSM
TLUplus files RC calculation
Mapping File
Maps layer
Optional – from your floorplanner names
Floorplan Constrains Virtual

Placing performed by
DC-T
1- 16

Typical DC-T Flow: Preparing to Compile
create_mw_lib -technology $TECH_FILE \

-mw_reference_library $mw_reference_library \
$mw_design_library
open_mw_lib $mw_design_library
check_library
Identify where the four
set_tlu_plus_files -max_tluplus $TLUPLUS_MAX_FILE \
-min_tluplus $TLUPLUS_MIN_FILE \ needed and one optional
-tech2itf_map $MAP_FILE physical file types are being
check_tlu_plus_files
specified.
set_svf ${RESULTS_DIR}/${DESIGN_NAME}.mapped.svf
define_design_lib WORK -path ./WORK

analyze -format vhdl ${RTL_SOURCE_FILES}
elaborate ${DESIGN_NAME}
write -hierarchy -format ddc -output ${RESULTS_DIR}/${DESIGN_NAME}.elab.ddc
link
extract_physical_constraints ${DESIGN_NAME}.def
set_fix_multiple_port_nets -all -buffer_constants

compile_ultra
1- 17
Extract_physical_constraints -- floorplan
Set_tlu_plus_files – tluplus, mapping
create_mw_lib – tech file, physical files

Typical DC-T Flow: Post-Compile
Identify the three commands used
specifically for DC-T
change_names -rules verilog -hierarchy
write -format ddc -hierarchy -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.ddc

write -f verilog -hierarchy -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.v
write_physical_constraints -output
${RESULTS_DIR}/${DESIGN_NAME}.mapped.physical_constraints.tcl
write_parasitics -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.spef
write_sdf ${RESULTS_DIR}/${DESIGN_NAME}.mapped.sdf
Why is write –format ddc
set write_sdc_output_lumped_net_capacitance false especially good for DC-T?
set write_sdc_output_net_resistance false
write_sdc -nosplit ${RESULTS_DIR}/${DESIGN_NAME}.mapped.sdc
report_qor > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.qor.rpt

report_timing -transition_time -nets -attributes -nosplit >
${REPORTS_DIR}/${DESIGN_NAME}.mapped.tm.rpt
report_area -physical -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.area.rpt
report_congestion > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.congestion.rpt
exit
1- 18
the .ddc file contains floorplan data

Write_physical_constraints, report_area –physical, report_congestion

Interfacing with DC-T
Compared with wireload-based DC:
Same shell as always, with a few extra commands
Same GUI as always, but with:
A few additional commands
Greater information-gathering capability Requires
Design Vision
Invoke with License
unix> dc_shell –topographical
dc_shell-topo> start_gui
1- 19

Key GUI Elements: TopLevel Window
Choose what part of logical To bring up To bring up
hierarchy is displayed TimingAnalysisDriver LayoutWindow
Logical
Hierarchy
1- 20

Key GUI Elements: LayoutWindow
Requires DC-G
Zoom License
Read-only Window: For Analysis

Select
To display
objects
1- 21

DisplayingTopLevel and LayoutWindow
Display both at once, or, toggle between them
with control back-tick (ctrl`)
1- 22

Cross-Window Probing
You can select a logical view Select in TimingAnalysisDriver,

display in LayoutWindow
and display a physical view
Other possibilities:
Select: Path Histogram
Display: LayoutWindow
Select: Schematic Window

Select: Logical Hierarchy

1- 23

GUI: Displaying Reports
Use the shell window, which remains open during GUI use
1- 24
What is typed in the shell is echoed in the GUI, and vice versa

Summary
DC-T increases correlation with physical tools

Uses physical information to calculate RC
From the vendor
Physical library
Associated files
– Technlogy file
– TLUplus file
– Mapping file
Optional – from your floorplanner
Floorplan (.def file) or physical_constraints.tcl
1- 25

TFU
The lab will enable you to work with the actual

elements
Quiz now: what are the five physical files and their
purposes?
1- 26

Additional Ways to Increase Correlation
DC-T, utilizing physical input, increases correlation

with downstream tools
Other approaches:
Scripting recommended by experts
Shared setup scripts among logical and physical tools
More information next module…
1- 27

Lab 1: Examining DC-T Physical Elements
Learning Objectives:
30 minutes Explore the physical elements read

into DC-T
Bring up and explore the DC-T GUI
Explore the scripting approach for loading
physical elements into DC-T
1- 28

Agenda
DAY
1
2 Setting Up and Running
3 Typical Flows
Setting Up and Running 2-1

Unit Objectives
After completing this unit and labs, you should be able to:
List the physical input files you need to provide
Describe how those files are read in
List the actions to be taken on the design
Configure and generate ‘seed scripts’ validated by
Synopsys
Modify those ‘seed scripts’ to a particular design
2- 2

Input Files to Provide
Milkyway
Design
Milkyway
Library
Reference
Libraries
Physical files
Physical Library
Associated files
– Technology file
– TLUplus file
– Mapping file
Optional: floorplan
You read all physical files into the database for
the chip you are designing: your Milkyway
Design Library.
2- 3

Creating Milkyway Design Library
Three steps
Create it
Tech File
Create
Open it once
Check it Physical
Library
create_mw_lib -technology $TECH_FILE \

-mw_reference_library $mw_reference_library \
$mw_design_library
Milkyway
open_mw_lib $mw_design_library Design Lib
check_library You open

every time
Check you run DC-T Common naming
once convention is
MyDesign_LIB
2- 4

Add TLUplus Files
Specify
TLUplus
Min
Max
Mapping file (maps TLUplus metal layers to Tech File

metal layers)
TLUplus
set_tlu_plus_files -max_tluplus $TLUPLUS_MAX_FILE \ files
-min_tluplus $TLUPLUS_MIN_FILE \
-tech2itf_map $MAP_FILE
Mapping
file
2- 5

Add Optional Floorplanning Information
Specify Floorplan
DC-T extracts data from it
Or
Specify physical constraints with Tcl
source physical_constraints_${DESIGN_NAME}.tcl
2- 6

Create Seed Script
Flow
https://solvnet.synopsys.com/rmgen/ Correlation
Predictability
Configure it
Or use the
default
2- 7

Configure Your Seed Script
Choose the
appropriate
settings
2- 8

RMgen Files
Shared by DC-T & ICC For DC & DC-T

Specifies Milkyway Sets up Milkyway
Design Library, search Your run
Reference Libraries script
and associated files, paths, target libraries,
logical libraries, etc link_libraries, RTL
source files, etc
2- 9

common_setup.tcl
set DESIGN_NAME "" ;# The name of the top-level design
set DESIGN_REF_DATA_PATH "" ;# Absolute path prefix variable for library/design data.
# Use this variable to prefix the common absolute path to
# the common variables defined below.
# Absolute paths are mandatory for hierarchical RM flow.
##########################################################################################
# Library Setup Variables A list of
##########################################################################################
variables
# For the following variables, use a blank space to separate multiple entries # Example: set
TARGET_LIBRARY_FILES "lib1.db lib2.db lib3.db"
set ADDITIONAL_SEARCH_PATH "" ;# Additional search path to be added to the default search path
set TARGET_LIBRARY_FILES "" ;# Target technology logical libraries

set ADDITIONAL_LINK_LIB_FILES "" ;# Extra link logical libraries not included in
TARGET_LIBRARY_FILES
set MIN_LIBRARY_FILES "" ;# List of max min library pairs "max1 min1 max2 min2 max3
min3"...
set MW_REFERENCE_LIB_DIRS "" ;# Milkyway reference libraries (include IC Compiler ILMs here)
set MW_REFERENCE_CONTROL_FILE "" ;# Reference Control file to define the MW ref libs
set TECH_FILE "" ;# Milkyway technology file

set MAP_FILE "" ;# Mapping file for TLUplus
set TLUPLUS_MAX_FILE "" ;# Max TLUplus file
set TLUPLUS_MIN_FILE "" ;# Min TLUplus file
Often defined by
P&R Team
2- 10

dc_setup.tcl
source -echo -verbose common_setup.tcl
set RTL_SOURCE_FILES "ORCA_TYPES.vhd \

BLENDER.vhd …
You define RTL files
set mw_reference_library ${MW_REFERENCE_LIB_DIRS}
set mw_design_library ${DESIGN_NAME}_LIB
if {[shell_is_in_topographical_mode]} {
# Only create new Milkyway design library if it doesn't already exist

if {![file isdirectory $mw_design_library ]} {
create_mw_lib -technology $TECH_FILE \ Script is
-mw_reference_library $mw_reference_library \ conditional
$mw_design_library
} else {
# If Milkyway design library already exists, open it
set_mw_lib_reference $mw_design_library -mw_reference_library $mw_ref_lib
}
open_mw_lib $mw_design_library
check_library
set_tlu_plus_files -max_tluplus $TLUPLUS_MAX_FILE \

-min_tluplus $TLUPLUS_MIN_FILE \
-tech2itf_map $MAP_FILE
} 2- 11

./dc_scripts/dc.tcl (reading)
set_svf ${RESULTS_DIR}/${DESIGN_NAME}.mapped.svf
define_design_lib WORK -path ./WORK Read

analyze -format vhdl ${RTL_SOURCE_FILES} design
elaborate ${DESIGN_NAME}
write -hierarchy -format ddc -output
${RESULTS_DIR}/${DESIGN_NAME}.elab.ddc Extract
floorplan
link data
set_ignored_layers -min_routing_layer ${MIN_ROUT_LAYER}

set_ignored_layers -max_routing_layer ${MAX_ROUT_LAYER}
report_ignored_layers
Runs on what was defined
Calculate RC based on in common_setup.tcl &
actual number of dc_setup.tcl
metal layers
2- 12

./dc_scripts/dc.tcl (transforming)
set_fix_multiple_port_nets -all -buffer_constants

compile_ultra
set uniquify_naming_style "${DESIGN_NAME}_%s_%d"

uniquify -force
change_names -rules verilog -hierarchy compile_ultra

(not compile) is
required

in common_setup.tcl &
dc_setup.tcl
2- 13

./dc_scripts/dc.tcl (writing)
write -format ddc -hierarchy -output

${RESULTS_DIR}/${DESIGN_NAME}.mapped.ddc
write -f verilog -hierarchy -output
${RESULTS_DIR}/${DESIGN_NAME}.mapped.v
${RESULTS_DIR}/${DESIGN_NAME}.mapped.physical_constraints.tcl
write_parasitics -output
${RESULTS_DIR}/${DESIGN_NAME}.mapped.spef
write_sdf ${RESULTS_DIR}/${DESIGN_NAME}.mapped.sdf
set write_sdc_output_lumped_net_capacitance false

set write_sdc_output_net_resistance false }
write_sdc -nosplit ${RESULTS_DIR}/${DESIGN_NAME}.mapped.sdc

dc_setup.tcl
2- 14

./dc_scripts/dc.tcl (reporting)
report_qor > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.qor.rpt

report_timing -transition_time -nets -attributes -nosplit
> ${REPORTS_DIR}/${DESIGN_NAME}.mapped.timing.rpt
report_area -physical -nosplit >

${REPORTS_DIR}/${DESIGN_NAME}.mapped.area.rpt
report_congestion >
${REPORTS_DIR}/${DESIGN_NAME}.mapped.congestion.rpt
exit

dc_setup.tcl
2- 15

Checking Your Input to DC-T
Catches incorrect
TLUPlus files
Consistency check
between logical and
check_tlu_plus_files physical libraries
check_library Lists physical

constraints that
report_physical_constraints you have read in
compile_ultra –check_only Quick Powerful Check

Tests that TLUPlus files exist
Checks that key floorplan elements exist
and have a defined location
Performs checks on hierarchical blocks
2- 16

Summary
RMgen creates three scripts

Common_setup.tcl – commonly populated by P&R team
dc_setup.tcl – you populate
./dc_scripts/dc.tcl – runs based on setup files
Checking your inputs
check_tlu_plus_files – most highly-leveraged check
check_library – consistency between logical and physical
libraries
report_physical_constraints – textual output of floorplan
compile_ultra –check_only – big time-saver
2- 17

Lab 2: Running DC-Topographical
30 minutes
Learning Objectives:
After completing this lab, you should be able to:
Run the RMgen utility
Adapt the seed scripts to your design
Run Design Compiler Topographical
Describe the benefits of using Reference
Methodology scripts
2- 18

Agenda
DAY
1
3 Typical Flows
Synopsys 10-I-013-SIG-002 © 2009 Synopsys, Inc. All Rights Reserved 3- 1
Typical Flows 3-1

Unit Objectives
After completing this unit and labs, you should be

able to:
Describe three frequently-used DC-T flows:
Classic flat (top-down) with Power and Test with .def
file
Classic flat (top-down) with Power and Test without
.def file
Hierarchical (bottom-up) flow
Describe the choices and list the commands
used in those flows
Describe DC-T methodologies common to all
flows
3- 2
Licenses required for power and test flows:
DFT Compiler
Power Compiler
DFT MAX
BSD Compiler
Typical Flows 3-2

Conventions used in teaching the three flows
In the following flows, commands shown are those

exclusively for DC-T.
Familiar DC commands from wireload-model DC are
not shown.
Where you would provide guidance for DFT or
Power, placeholders are provided.
3- 3
Typical Flows 3-3

Flat Flow with Test and Power
set_ignored_layers -min_routing_layer ${MIN_ROUTING_LAYER}
set_ignored_layers -max_routing_layer ${MAX_ROUTING_LAYER}
extract_physical_constraints ${DESIGN_NAME}.def Adds clock-tree estimation to
Low Power Flow: report_power
set_power_prediction true
Supply your standard Power Intent; enable power optimization: leakage and dynamic
DFT Flow:
include test ports in RTL code & physical constraints, if possible
compile_ultra –scan –gate_clock
DFT Flow: Recommended if test ports
create_port ScanPortName are not in the RTL
set_port_location -coordinate {x y} ScanPortName
Set your standard DFT constraints and specifications
insert_dft (uses placement-aware scan stitching)
compile_ultra –scan -incremental; # place new cells created by insert_dft

write_physical_constraints -output ${RSLT_DIR}/${name}.map.physical_constraints.tcl
write_parasitics -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.spef
report_area -physical
report_congestion
write_milkyway –overwrite –output ${DESIGN_NAME}_DCT
Low Power Flow:
Standard write commands, including report_power
DFT Flow:
Standard write commands
Handoff 3- 4
Typical Flows 3-4

set_ignored_layers
Often, not all of the metal layers in a given process are used
Tell DC-T to ignore the unused metal layers Ask the
set_ignored_layers physical team
-min_routing_layer ;# ignore all layers below this layer which layers
-max_routing_layer ;# ignore all layers above this layer are unused
Makes RC estimation and congestion analysis more realistic
set_ignored_layers –max_routing_layer METAL4

dc_shell-topo> report_preferred_routing_direction
Layer Name Library Design Tool understands

METAL Horizontal Not Set Horizontal
METAL2 Vertical Not Set Vertical
METAL3 Horizontal Not Set Horizontal
METAL5 Horizontal Not Set Horizontal
dc_shell-topo> report_ignored_layers
Ignored layers in congestion analysis and RC estimation: METAL5 METAL6
Min_routing_layer: METAL
Max_routing_layer: METAL4
3- 5
Ignoring metal layers can also impact QoR and Correlation.
Typical Flows 3-5

extract_physical_constraints
DC-T actions:
Extracts physical constraints from .def file
Applies to design
Saved when .ddc is written out
You can view constraints:
In the GUI layout window
With report_physical_constraints
Both report… and write…
You can write out to a .tcl file: display only what you
read in.
write_physical_constraints
You cannot pass

a .Tcl floorplan
to ICC.
3- 6
Typical Flows 3-6

set_power_prediction true
Increases power correlation of report_power
command by including clock-tree power
Specify before the last compile: compile_ultra or
compile_ultra –incremental
1. set_power_prediction true #; no power constraints
2. compile_ultra If you specify power constraints,
power prediction is automatically
3. report_power
enabled
Or
1. set_power_prediction true To save run time:
2. insert_dft enable power
prediction only
3. compile_ultra –scan –incremental for final compile
4. report_power
Affects report_power, not the netlist
3- 7
Typical Flows 3-7

Test Ports in RTL and in Floorplan
Interface in RTL and Floorplan should be the same

Preferred method:
Include the test ports in the RTL code
Everything downstream from RTL will have same
interface
Recommended alternate method: (prior to
insert_dft and compile_ultra –incremental -
scan)
Provide interface information (new ports) with
create_port
Provide floorplanning information (location) with
set_port_location
3- 8
Typical Flows 3-8

Reports
${RSLT_DIR}/${name}.map.physical_constraints.tcl
write_parasitics -output
${RESULTS_DIR}/${DESIGN_NAME}.mapped.spef Performs virtual route
if compile_ultra
report_area -physical was done without the
report_congestion –congestion option
write_milkyway –overwrite –output ${DESIGN_NAME}_DCT

Low Power Flow:
DFT Flow:
3- 9
Typical Flows 3-9

Before moving to the next flow…
For the first flow (Flat with Test and Power):

Name three ways to examine the objects in a floorplan
What is the easiest way to keep the interfaces (ports) in
RTL code and floorplans aligned with each other?
3- 10
Put the complete set of ports into the RTL so that everything downstream is in agreement with it
GUI layout window, report_physical_congestion, write_physical_congestion
Typical Flows 3-10

Test and Power Flow: If you need a .def file
Create a Netlist for Floorplanner
Specify what
set_ignored_layers -min_routing_layer ${MIN_ROUTING_LAYER} you know
set_ignored_layers -max_routing_layer ${MAX_ROUTING_LAYER}
source -echo -verbose ${DESIGN_NAME}.physical_constraints.tcl
DFT Flow:
Include your test ports in your RTL code, if possible
Save run time at this
Low Power Flow: early stage of design
set_power_prediction false
Supply your standard Power Intent; enable power optimization: leakage and dynamic
Standard netlist write for your floorplanning tool
ICC calls this Pass 1 of a 2-pass Floorplanning Flow:

Pass 1:
DC-T: using minimal physical constraints, synthesize netlist
Handoff ICC: using the netlist, create a floorplan
Pass 2:
DC-T: using the floorplan from ICC, synthesize again
3- 11
Typical Flows 3-11

Supported DCT Physical Constraints
Core Area Ports

Relative Constraints Relative Constraint
set_aspect_ratio and set_port_side
set_utilization Exact Constraint
Exact Constraint set_port_location
set_placement_area or
Placement Blockages
set_rectilinear_outline
Exact Constraint
Macros create_placement_blockage
Exact Constraint create_net_shape
set_cell_location create_wiring_keepout
Multi Voltage Design Placement Guidance
create_placement_area Exact Constraint
create_voltage_area create_bounds
Exact constraints have higher precedence
3- 12
List of DCT supported floorplan constraints
Typical Flows 3-12

Defining Relative Core Shape: Aspect Ratio
Aspect ratio is the height to width ratio of a block

Defines the block shape
Default aspect ratio is 1
width width
height
height
set_aspect_ratio 1 set_aspect_ratio 0.5
3- 13
Typical Flows 3-13

Defining Relative Core Size: Utilization
Utilization dictates how densely you want your cells

to be placed within the block
Increasing utilization reduces the core area
Default Utilization is 0.6
set_utilization 0.6 set_utilization 0.85
3- 14
Typical Flows 3-14

Defining Exact Core Area
Defining a Rectangular Defining a Rectilinear

Core Area Core Area
(0,400) (600,400) (0,400) (300,400)
(600,200)
(300,200)
(0,0) (600,0) (0,0) (600,0)
set_placement_area \ set_rectilinear_outline \
-coordinate {0 0 600 0 600 200 \
-coordinate {0 0 600 400}
300 200 300 400 0 400}
3- 15
Typical Flows 3-15

Defining Relative Port Sides
Port side dictates along which side a port is placed

Valid sides are left (L), right (R) top (T) or bottom (B)
DC-T places the port at any location along the specified
side
Port_N
set_port_side –side {R} Port_N
Port_M
set_port_side –side {B} Port_M
3- 16
Typical Flows 3-16

Defining Exact Ports, Macros, Bounds, Blockages, Wires
create_bounds \ set_cell_location \
-name my_area \ -coordinate {400 140} \
-coordinate {0 0 500 500} \ -orientation {N} –fixed RAM

create_net_shape \
{I_BLEND_0 I_BLEND_1 I_BLEND_2}
-type wire \
set_port_location \
-net VSS \
-coordinate {0 40} PortA1
-layer METAL6 \
create_wiring_keepouts
-origin {0 40} \
-coordinate {12 12 100 100} \
-length 10 \
-layer “METAL2”
-width 4
-name “my_keepout”
create_placement_blockage \
(300,280)
-name Blockage \
Blockage RAM
-bbox \
(50,160)
{50 160 300 280} (400,140)
PortA: (0, 40)
3- 17
Typical Flows 3-17

Before moving to the next flow…
For the 2nd flow (If you need a .def file)

1. Name three relative constraints that you might specify if
you do not yet have a .def file.
2. What exact constraints do you think you might use if
you do not yet have a .def file?
3- 18
Core placement area is a possibility; so is cell location (for a key RAM or two). 2.
Aspect ratio, utilization, port side 1.
Typical Flows 3-18

Sometimes a Hierarchical Flow is Necessary
To partition the workload among designers
Separate synthesis runs
Sub blocks
Top Level
Types of synthesized blocks
Top Level Design
DC-T DC-T ICC

ILM DDC ILM
3- 19
Typical Flows 3-19

Interface Logic Models (ILMs)
A X
B Y
CLK
A X
B Y
CLK
Internal logic is removed; interface timing is retained.

3- 20
Typical Flows 3-20

If Your Flow is Hierarchical
if { ${DDC_HIER_DESIGNS} != ""} {
At the top-level:
remove_design -hierarchy ${DDC_HIER_DESIGNS}
}
if { ${DC_ILM_HIER_DESIGNS} != ""} {
remove_design -hierarchy ${DC_ILM_HIER_DESIGNS}
}
if { ${ICC_ILM_HIER_DESIGNS} != ""} {
remove_design -hierarchy ${ICC_ILM_HIER_DESIGNS}
}
Can read DC-T ILMs or DC-T .ddc
foreach design ${DDC_HIER_DESIGNS} { files with read_ddc
read_ddc ${design}.mapped.ddc
}
foreach design ${DC_ILM_HIER_DESIGNS} {
read_ddc ${design}.mapped.ILM.ddc set mw_reference_library \
} ${MW_REFERENCE_LIB_DIRS MY_ILM_DIRS}
link
Link loads ICC ILMs from the foreach ICC_ILM_NAME ${ICC_ILM_HIER_DESIGNS} {
Milkway library. dc_setup.tcl lappend link_library ${ICC_ILM_NAME}.ILM
}
set_physical_hierarchy [sub_instances_of -hierarchy -of_references
${DDC_HIER_DESIGNS} ${DESIGN_NAME}]
Tell DC-T:
extract_physical_constraints ${DESIGN_NAME}.top_level.def Do not optimize
Do propagate the timing
Handoff 3- 21
Typical Flows 3-21

Before moving to Common Methodologies…
1. What is the difference between loading a DC-T ILM

and an ICC ILM?
2. After reading a .ddc subblock into a top-level DC-T
run, what guidance must you provide DC-T before
compiling?
3- 22
Tell DC-T not to optimize it using set_physical_hiearchy 2.

create_mw_lib must be extended to include he ICC ILM.
with create_mw_lib and then linked in with link. That is, the paths pointed to with
DC-T ILM is read in with read_ddc; ICC ILM , located in the Milkyway library, is pointed to 1.
Typical Flows 3-22

Methodologies Common to all Flows
Constraining
Automatic High Fanout Synthesis
Black boxes
3- 23
Typical Flows 3-23

Drive Synthesis with Realistic Constraints
Eliminate over-constrained margins in DC-T Synthesis

Expected DC-T/ICC Correlation
Timing (wns): 5%
Area: 5% 2008.09
Power: 10%
Constraints evolve over the life of the design

Update with the latest floorplan as it becomes available
3- 24
Typical Flows 3-24

DCT Automatic High Fanout Synthesis (AHFS)
WLM buffer tree Topographical buffer tree
Location of fanout
influences buffering
DC-T performs layout-based Automatic

High Fanout Synthesis
By default, nets with fanout above 100 are synthesized with
layout-based AHFS
Except for
Recommendation: allow DC-T to perform the
Ideal_nets
default AHFS.
DRC-disabled nets
ICC then automatically performs incremental
– Clocks
– Constants AHFS as needed during placement.
By default, DCT synthesis will:

Not perform AHFS on clock networks
Automatically buffer all other high-fanout nets like Reset, enable
Honor user constraints like dont_touch, dont_touch_network or
ideal_network
3- 25
Typical Flows 3-25

DCT Automatic High Fanout Synthesis (AHFS)
For improved correlation to ICC, you can configure AHFS to

use the same options as ICC
Use set_ahfs_options to fine tune AHFS options
set_ahfs_options
-default
-optimize_buffer_trees
-hf_threshold [Integer] ( default: 100)
-mf_threshold [Integer] ( default: -1)
-remove_effort [none(default)|medium|high]
-enable_port_punching[true(default) | false]
-default_reference [ buffer_lib_name]
These settings are saved in a .ddc file

Passed on to ICC
3- 26
By default, if buffers exist on HFNs, they will be removed only if the path is critical and new
AFHS trees will be built.
-remove_effort high removes all buffers/inverters from HF nets and builds new AHFS tree
Default_reference specifies library buffer cells preferred for AHFS optimization
Typical Flows 3-26

Black-Box Support in DCT
DC-T creates temporary physical library cells for:
Missing logical library cells that are instantiated in Design
Includes Leaf cells and Macros Typical application:
Empty hierarchy cells or black-boxed modules memories may not be
available early on –
Unlinked or unresolved cells use black boxes to
Unmapped cells continue design effort.
Warning message is issued when DCT creates physical library cells

Warning: Created physical library cell for logical library %s
(OPT-1413)
DC-T applies timing information from logical library
- Black Boxes can impact QoR and Correlation

• Should be used cautiously and only as a flow enabler
- Rerun DCT when complete Design and physical
library become available
3- 27
Typical Flows 3-27

Before moving to lab…
1. What changes must you make to the default AHFS

and black box behavior?
2. Which of the methods is most important to revisit
as your knowledge of the design becomes more
complete?
3- 28
become available.
Black box is most important – you want to replace them with complete components when they 2.
None 1.
Typical Flows 3-28

Summary
Describe three frequently-used DC-T flows:

Classic flat (top-down) with Power and Test with .def file
Classic flat (top-down) with Power and Test without .def
file
Hierarchical (bottom-up) flow
Describe the choices and list the commands used
in those flows
Describe DC-T methodologies common to all flows
3- 29
Typical Flows 3-29

Lab 3: Variations: Running DC-T
30 minutes
During this lab, you will:

modify basic flat (top-down) Reference Methodology
scripts to provide a floorplanner an initial netlist from
which to create a floorplan
modify hierarchical Reference Methodology scripts to
run a hierarchical (bottom-up) flow in which three sub-
blocks have been previously compiled with DC-T
3- 30
Typical Flows 3-30

Agenda
DAY
1
3 Typical Flows
Handling Congestion 4-1

Unit Objectives
After completing this unit and labs, you should be

able to:
Ensure the most accurate congestion analysis
Quantify congestion with a textual report
Qualify congestion using the GUI
Describe a recommended fixing flow
4- 2

What is congestion? Requires DC-G license
Routing needs exceed

routing capacity
Visible after global
routing
Visually displayed as
‘hotspots’ on layout
Need:
Can cause design Identify congestion prior to P&R
iterations: Reduce design iterations
Modify floorplan
Solution:
Resynthesize DC-Graphical
Recode RTL Can optimize netlist to handle congestion
4- 3

How does DC-G calculate congestion
Divides routable area into a

grid of Global Route Cells
(GRCs)
Based on tech file data,
calculates available routing for
each edge
Performs global routing
Global Route Cell (GRC)
Compares wires routed For each edge:
Required/available crossings
across each GRC edge with Hot colors indicate heavier
available routing congestion
Flags an overflow when

actual wire crossings exceed
capability
4- 4

Ensuring accurate congestion analysis
Apply the most complete physical constraints

available
Latest floorplanning data (.def file or .tcl file)
Metal layer utilization
In addition to set_ignored_layers (ignore entire Use the
layer), add info about percent of a layer that is available same
set_congestion_options setting as
ICC
-layer
-availability ;# what percent of this layer is

available for routing
report_congestion_options -all
4- 5

How do you analyze congestion?
Requires DC-G license
Quantify it with report_congestion
dc_shell-topo> report_congestion
****************************************
Report : congestion
Design : ORCA_TOP
Both Dirs: Overflow = 6158 Max = 41 (1 GRCs) GRCs = 1476 (12.20%)

H routing: Overflow = 3685 Max = 33 (1 GRCs) GRCs = 826 (6.83%)
V routing: Overflow = 2473 Max = 35 (3 GRCs) GRCs = 773 (6.39%)
Overall Congestion Worst Hot Spot GRCs with violations
4- 6

Report_congestion and worst hot spot
Most overflows How many GRCs

for a single GRC had an overflow of
this size

In how many directions did this

cell have overflows?
1
2
4- 7

Report_congestion and Percent GRCs
Number of GRCs Violating GRCs as a

with any overflow percent of total GRCs


Why is this number less than the sum of H routing: and V routing:
a. It is a bug
b. A GRC with overflows in both directions sums to a single violating GRC
4- 8

Comparing Congestion Numbers

Overall Congestion Worst Hot Spot GRCs with overflows
A revised synthesis may result in:

increased or decreased overflows
Compare
better or worse hotspots
with other
Best way to compare runs:
runs
Average overflows per congested GRC
Both Dirs: 6158/1476 = 4.17
Horizontal: 3685/826 = 4.46
Vertical: 2473/773 = 3.20
4- 9

Fixing Congestion
Three ways to fix congestion

Re-code the RTL
Re-do the floorplan
Use the –congestion option to compile_ultra
How to decide on a fix
Pinpoint the congestion areas before choosing a fix
Use the GUI to pinpoint the congestion areas
4- 10
compile_ultra –congestion requires DC-G licensing.

The GUI: Bringing up the Congestion View
4- 11

© 2009 Design Compiler Topographical/Graphical Workshop
4-12 Handling Congestion
Congestion map can be generated with report_congestion, or by pressing the Reload button
Objects – control what is displayed in floorplan; apply -- must be pressed after selecting objects to
view; white arrow – select mode; + and – magnifying glasses – zoom mode; layout window –
which window are we in; list cells in congested region – a way to pointpoint the exact cells in a
selected region; row of colored boxes – can check and uncheck these, displaying just the violations
you are interested in
4- 12
What is the purpose of each circled item?
button can generate a congestion map
Either report_congestion or the Reload
The GUI: Using the Congestion View
The GUI: Interpreting the Congestion Map
Congestion around macro Congestion in the placeable

edges: floorplan issue core area: RTL issue
4- 13

RTL Code Influencing Congestion
Concentrated areas with much data throughput

Lookup table logic
Coded as case statements
Create highly-connected structures in the netlist
Large MUX trees
Many ways to select
Large busses
Cause many high-fanout nets
Large sums of products (ROMS)
4- 14

Tracing from GUI back to possible RTL source
1 Click
2 Select
3 Apply
4 Examine module & cell

name
4- 15

Recommended Congestion Fixing Flow
Performs virtual global routing

and restructures the netlist
1. Try compile_ultra –congestion – if it fixes the

congestion, you are done.
2. If compile_ultra –congestion does not give
you the results you want, talk with your RTL coder
or floorplanner, sharing what information you have.
1. DC-T can do virtual placement, so what is the most obvious way

for a compile_ultra -congestion to address
congestion?
2. Why would you not use the –congestion option by default?
4- 16
Spreading the cells out can affect QoR 2.

same effect – it spreads the cells out.
It would spread the cells out. Sometimes it duplicates and divides the logic, which has the 1.

compile_ultra -congestion
Congested
Grid
MUX
Grid A
compile_ultra –congestion
Grid B
Grid A
Grid C
4- 17
Congestion Optimization capability primarily helps address scenarios where the design's RTL
logic structures result in congestion. This standard cell congestion is often caused by the topology
of the netlist. Minimizing the resulting congestion for such designs often require significant netlist
topology changes that can not be performed during place and route stage. For this design,
significant slicing of the muxes is needed to make big improvements in congestion and this is best
done early in the flow .i.e. during synthesis.
The Congestion-based Optimization in Design Compiler Graphical minimizes the impact of
congestion due to design RTL choice and constraints by performing congestion-aware logic-based
netlist optimizations during synthesis with minimal impact on other QoR aspects like timing and
area. Also, there is no need to change user constraints or restrict cell selection as this feature is
tuned to work with all available target library cells and identify the optimal structure and mapping
to generate a netlist topology with reduced congestion. The Design Compiler Graphical congestion
optimization feature is enabled by the -congestion option of synthesis command compile_ultra.
The congestion optimization capability is supported in conjunction with Test and Power flows.
For example
Lookup table logic (coded as case statements) can create highly connected sub graphs in the
netlist with its many-to-many mapping topology
Large MUX structures (many ways to select, large busses) cause many high-fanout nets

Summary
This module described how to:

Ensure the most accurate congestion analysis
Quantify congestion with a textual report
Qualify congestion using the GUI
Execute a recommended fixing flow
4- 18

Lab 4: Congestion
30 minutes
After completing this lab, you should be able to:

Bring up and interpret congestion reports, both textual
and graphical
Decide whether to fix a congestion problem in the RTL
code, the floorplan, or with a compile optimized for
congestion
4- 19

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Agenda
DAY
1
3 Typical Flows
Ensuring the Integrity of Results 5-1

Review Elements, Flows, Congestion
What are the five physical files you provide DC-T?

What is a utility that provides you with seed scripts
optimized for flow, correlation, and predictability for
specific versions of specific products?
What is a recommended approach to using black
boxes for missing physical designs?
What are three ways to fix congestion – how do you
decide which approach to use?
5- 2
appropriate file: RTL or floorplan.

option can handle the congestion, you may be all set. Otherwise, you need to change the
Congestion: change RTL, change floorplan, use compile_ultra –congestion. If the congestion
Black box: replace it with the real design as soon as it becomes available
Utility: RMgen
5 files: tluplus, tech, mapping, floorplan, physical libraries

Unit Objectives
After completing this unit, you should be able to:

Use additional options and resources for
Two as-needed situations
Detailed logical/physical synchronization
Synthesizing for multiple situations (scenarios)
5- 3

Additional Options and Techniques
Name matching: Post-compile floorplan objects to

pre-compile RTL objects
Viewing a Floorplan prior to compile_ultra
Manual Correlation Checking with ICC
Automatic Consistency Checking
Additional power with MCMM
5- 4

Name Matching: Why is it necessary?
Situation
Floorplan object names are based on post-compile netlist
Affected by
change_names
Compilation with automatic ungrouping
Floorplan is read into DC-T and applied to pre-compile RTL
Constraints on unrecognized objects are ignored
5- 5

Name Matching: Actions you can take
1. Verify the problem (what objects are not recognized)

extract_physical_constraints –verbose
Examine log file for missing objects
2. Apply name matching Show current Specify needed

name characters
matching
set_fuzzy_query_options -show
set_fuzzy_query_options -hierarchical_separators { / _ . } \
-bus_name_notations {[] __ ()} \
-class {cell pin port net}
set fuzzy_matching_enabled true
source -echo -verbose ${DESIGN_NAME}.physical_constraints.tcl
set fuzzy_matching_enabled false
Enable Disable after

constraints are read to
save run time
5- 6

Viewing a floorplan prior to compile_ultra
Issue
Is floorplan the correct one?
Are there mistakes in the floorplan?
Solution
1. Load design and floorplan
2. View the floorplan prior to compiling: need
1. Linked design 2009.06
2. Physical constraints applied before opening layout view
3. Fix the floorplan if needed
If you are not using 2009.06

Solvnet script 026740: Viewing the Floorplan Layout in Design
Compiler Topographical Mode Before Running the
compile_ultra Command
5- 7

Manually Matching DC-T and ICC Settings
For optimal synthesis results, align DC-T and ICC

Shared Commands
Shared Variables
Identify these features and their Effects
Solvnet Doc ID: 024814 “Aligning Design Compiler
Topographical Mode With IC Compiler”
5- 8

Automatic Compare of Environment Settings
To improve QoR correlation DC-T <-> ICC, match

Tool variables
User variables
Design settings and constraints
Shared physical constraints
Congestion options
Preferred routing directions
Use Consistency Checker script
Solvnet Doc Id: 026366 “Consistency Checker -
Automatic Environment Setting Comparison
Between two Tools”
5- 9

Consistency Checker Report: Variables
Found Found
Non Only Only
Variable Matched Matching in in
Group Values Values DCT_en ICC_en Total
------------------------------------------------------------------
HIERARCHY* 1 0 0 0 1
_Variable* 1 0 0 0 1
__err* 1 0 0 0 1
__mwui* 0 0 2 0 2
access* 0 1 0 0 1
alib* 1 0 0 0 1
allow* 1 0 0 0 1
annotation* 1 0 0 0 1
...
------------------------------------------------------------------
Total 396 9 328 430 1136
Text in blue is clickable for the HTML report; enabling to sort data,
expand table and get details on mismatches.
5- 10
Matched Values: matched count. How many variables are matched
Non Matching Values: variable with differences. How many variables mismatch
Found Only in DCT_en: variables found just in file 1. DCT_en are the first 6 characters of input
file 1.
Found Only in ICC_en: variables found just in file 2. ICC_en are the first 6 characters of input file
2.
./cc_html/ index.html have the same format as this text table, but titles are clickable to sort, ‘…’ is
clickable to expand and <var_name>* is clickable for more details (full variable name and also
details on the mismatch).

Consistency Checker Report: Commands
Found Found
Non Only Only
Matched Matching In In
Command Values Values DCT_en ICC_en Total
--------------------------------------------------------------------
create_clock 0 1 0 0 1
current_design 1 0 0 0 1
remove_wire_load_model 0 0 1 0 1
set_cell_parent_cluster 0 0 0 7 7
set_dont_touch 27 0 0 0 27
set_dont_use 27 0 0 0 27
set_tlu_plus_files 0 0 0 1 1
set_units 1 0 0 0 1
--------------------------------------------------------------------
Total 56 1 1 8 66
Text in blue is clickable for the HTML report; enabling to sort data
and get details on mismatches.
5- 11
Mateched Values: matched count. How many commands are matched
Non Matching Values: commands with differences. How many commands mismatch
Found Only in DCT_en: commands found just in file 1. DCT_en are the first 6 characters of input
file 1.
Found Only in ICC_en: commands found just in file 2. ICC_en are the first 6 characters of input
file 2.
./cc_html/ index.html have the same format as this text table, but titles are clickable to sort, ‘…’ is
clickable to expand and <command_name> is clickable for more details (list of mismatches).

DC Graphical: Some additional power
With the DC Graphical license, you also get MCMM

(Multi-Corner Multi-Mode)
Performs concurrent timing analysis for each scenario,
which is a mode or a corner or a combination of both,
made up of:
SDC constraints
Operating Condition
Functional Modes
– Mission
– Test
– Standby
– Etc
5- 12

Concurrent Multi-Corner Multi-mode (MCMM)
Corner Functional Modes

(Process, VDD, Temp) (Sleep, Test, Normal, etc.)
Corner N
Corner N
Parasitics
(TLU+)
Design
Compiler Graphical
Netlist optimized for all scenarios

Single Report for timing & power
MCMM in DC Graphical allows

Concurrent timing analysis tracked for each scenario
Intelligent multi-scenario synthesis, optimization and reporting
5- 13

Summary
Name matching: Post-compile floorplan objects to

pre-compile RTL objects
set_fuzzy_query_options
set fuzzy_matching_enabled
Viewing a Floorplan prior to compile_ultra
Available in 2009.06; for earlier versions,
use Solvnet script
Correlation with ICC
Solvnet checklist
Automatic Consistency Checking
Solvnet script
Additional power with MCMM
5- 14

Customer Support
© 2009 Synopsys, Inc. All Rights Reserved 20090112
Customer Support CS-1

© 2009
Synopsys Support Resources
1. Build Your Expertise:

Customer Education Services
www.synopsys.com/support
Workshop schedule and registration
Download materials
(SolvNet id required)
2. Empower Yourself:
solvnet.synopsys.com
Online technical information and
access to support resources
Documentation & Media
3. Access Synopsys Experts:

Support Center
CS- 2

© 2009
SolvNet Online Support Offers
Immediate access to
the latest technical
information
Product- and Release-
Specific Update Training
Thousands of expert-
authored articles, Q&As,
scripts and tool tips
Enter-a-call online
Support Center access
Release information
Online documentation
License keys
Electronic software
downloads
Synopsys announcements
(latest tool, event and
product information)
CS- 3

© 2009
SolvNet Registration is Easy
1. Go to solvnet.synopsys.com/
ProcessRegistration
2. Pick a username and password.
3. You will need your “Site ID” on
the following page.
4. Authorization typically takes
just a few minutes.
CS- 4

© 2009
Support Center: AE-based Support
Industry seasoned Application

Engineers:
50% of the support staff has
>5 years applied experience
Many tool specialist AEs with
>12 years industry experience
Access to internal support
resources
Great wealth of applied Contact us:
knowledge: Enter A Call
Service >2000 issues per
month
Remote access and debug via
ViewConnect www.synopsys.com/support
CS- 5

© 2009
Other Technical Sources
Application Consultants (ACs):

Tool and methodology pre-sales support
Contact your Sales Account Manager for more information
Synopsys Professional Services (SPS) Consultants:
Available for in-depth, on-site, dedicated, custom consulting
Contact your Sales Account Manager for more details
SNUG (Synopsys Users Group):
www.snug-universal.org
CS- 6

© 2009
Summary: Getting Support
Customer Education Services

SolvNet
Support Center
SNUG
CS- 7

© 2009
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CUSTOMER EDUCATION SERVICES

Synopsys Customer Education Services

Workshop Registration: 1-800-793-3448

Destination Control Statement

Registered Trademarks (®)

Service Marks (SM)

Document Order Number: 10-I-013-SSG-002

Synopsys Customer Education Services

Unit i : Introduction & Overview

Unit 1: DC-T Physical Elements

Synopsys 10-I-013-SLG-001 i Design Compiler Topographical/Graphical Workshop

Unit 2: Setting Up and Running

Unit 3: Typical Flows

Synopsys 10-I-013-SLG-001 ii Design Compiler Topographical/Graphical Workshop

DCT Automatic High Fanout Synthesis (AHFS) .......................................................... 3-25

Unit 4: Handling Congestion

Unit 5: Ensuring the Integrity of Results

Synopsys 10-I-013-SLG-001 iii Design Compiler Topographical/Graphical Workshop

Unit CS: Customer Support

Synopsys 10-I-013-SLG-001 iv Design Compiler Topographical/Graphical Workshop

Synopsys Customer Education Services

Introduction & Overview i -1

EDA = Electronic Design Automation

Introduction & Overview i -2

Building Hours Phones

Emergency EXIT Messages

Please turn off cell phones and pagers

Introduction & Overview i -3

Use Design Compiler Topographical/Graphical

Introduction & Overview i -4

Engineers familiar with Design Compiler

Introduction & Overview i -5

You should have experience in the following areas:

Introduction & Overview i -6

IC Compiler 1 IC Compiler 2: HDP

Design Compiler ere

DFT Compiler 1 TetraMAX 1 TetraMAX 2: DSM

Introduction & Overview i -7

2 Setting up and Running

5 Ensuring Integrity of Results

Synopsys 10-I-013-SIG-002 © 2009 Synopsys, Inc. All Rights Reserved i -8

Introduction & Overview i -8

Successfully load physical element files into DC-T

Introduction & Overview i -9

Lab Exercise ! Caution

For Further Reference Question

“Under the Hood”

Lab Exercise: A lab is associated with this unit, module, or concept.

Caution: Warnings of common mistakes, unexpected behavior, etc.

Introduction & Overview i -10

2 Setting up and Running

5 Ensuring Integrity of Results

Synopsys 10-I-013-SSG-002 © 2009 Synopsys, Inc. All Rights Reserved 1- 1

DC-T Physical Elements 1-1

After completing this unit, you should be able to:

DC-T Physical Elements 1-2

Need: Correlation & predictability

DC-T Physical Elements 1-3

Uses “virtual placement” to calculate net RC