applied

sciences
Article
Modified Design of Two-Switch Buck-Boost Converter to
Improve Power Efficiency Using Fewer Conduction
Components
Sunghwan Kim 1 , Haiyoung Jung 2, * and Seok-hyun Lee 1, *

1 Department of Electrical Engineering, Inha University, 100 Inha-ro, Michuhol-gu,

Incheon 22212, Republic of Korea
2 Department of Fire and Disaster Prevention, Semyung University, 65 Semyung-ro,
Jecheon-si 27136, Republic of Korea
* Correspondence: [email protected] (H.J.); [email protected] (S.-h.L.)

Abstract: In this study, a modified design of a two-switch buck-boost (TSBB) converter is proposed
to improve power efficiency using fewer conduction components, and the optimal power range
is measured. The proposed TSBB converter operates in three topologies: buck, boost, and buck-
boost, like the conventional TSBB converter. However, the proposed converter improves the power
efficiency in the buck and buck-boost topologies by decreasing conduction loss using the diode in the
switch-off section while maintaining the same number of semiconductors as that in the conventional
TSBB converter. The power efficiency of the buck topology improves for the power range 10–80 W in
the constant voltage (CV) and constant current (CC) modes; it increases on average by 0.75–1.36% and
0.83–2.27% in the CV and CC modes, respectively. The power efficiency of the buck-boost topology
step-down improves for the 10–80 W in all modes. This increases the average by 0.73–0.99% and
3.33–4.75% in the CV and CC modes, respectively. The power efficiency of the buck-boost topology
step-up increases on average by 1.65–2.00% for 10–80 W in the CV mode. In the CC mode, it increases
by 2.17–2.77% on average for 10–50 W.

Keywords: converter; buck-boost converter; TSBB converter; conduction loss; switching loss; metal-
Citation: Kim, S.; Jung, H.; Lee, S.-h.
oxide-semiconductor field effect transistor (MOSFET); switch; diode; voltage stress
Modified Design of Two-Switch
Buck-Boost Converter to Improve
Power Efficiency Using Fewer
Conduction Components. Appl. Sci.
1. Introduction
2023, 13, 343. https://doi.org/
10.3390/app13010343 The DC–DC converter is a power conversion device that converts the received DC
voltage to a DC voltage required by the system for transferring energy to the load [1].
Academic Editors: Kan Liu and
It is used in several electronic devices for stabilizing the operation of systems; this can
Wei Hu
range from high-power applications such as solar photovoltaics, electric vehicles, and
Received: 4 December 2022 energy storage systems to low-power applications such as laptops, mobile phones, and
Revised: 21 December 2022 portable batteries [2]. DC–DC converters are becoming miniaturized, and these parts are
Accepted: 22 December 2022 becoming denser because of the weight reduction and miniaturization of various application
Published: 27 December 2022 products [3]. DC–DC converters require high-power conversion efficiency for the reduction
of energy consumption and long life [4]. Such high power-conversion efficiency is an
important factor for a high-performance high-reliability DC–DC converter [5,6].
There are three topologies for non-isolated-type DC–DC converters: buck for step-
Copyright: © 2022 by the authors.
down, boost for step-up, and buck-boost for both step-down and step-up. Figure 1 shows
Licensee MDPI, Basel, Switzerland.
This article is an open access article
the circuit diagrams of each topology that consists of a switch, a diode, an inductor, and
distributed under the terms and
a capacitor. Step-down and step-up are determined by the duty ratio (d) and wiring of
conditions of the Creative Commons
the semiconductors. Table 1 summarizes the current path and gain (G) of each topology
Attribution (CC BY) license (https:// based on switch operation; these topologies of the single switch type should be selected
creativecommons.org/licenses/by/ based on the input and output voltage specifications of the system; it is difficult to switch
4.0/). between topologies owing to the fixed element connection. Buck-boost topology with both

Appl. Sci. 2023, 13, 343. https://doi.org/10.3390/app13010343 https://www.mdpi.com/journal/applsci

Appl. Sci. 2022, 12, x FOR PEER REVIEW 2 of 20

Appl. Sci. 2023, 13, 343 2 of 19

Appl. Sci. 2022, 12, x FOR PEER REVIEW 2 of 20
the same polarity as the input voltage because the polarity of the output voltage is oppo
site to that of the input voltage. Moreover, the power conversion efficiency decreases com
step-down
pared to that andofstep-up
othercannot be used
topologies in applications
because that require
the voltage stress of anthe
output voltage
switch andof the equals
diode
same polarity
the same as the
polarity as input voltage
the input because
voltage the polarity
because of the
the polarity ofoutput voltage
the output is opposite
voltage is oppo-to
the sum of the input voltage 𝑉𝑖 and output voltage 𝑉𝑜 . Therefore, the TSBB converter tha
that ofthat
site to the of
input voltage.
the input Moreover,
voltage. the power
Moreover, conversion
the power efficiency
conversion decreases
efficiency compared
decreases com-
can
to
pared
switch
that ofthat
to
to
other atopologies
different
of other
topology
because
topologies thebased
becausevoltage onstress
system
the voltage
requirements
of the
stress of switch andand
the switch
is diode
diodeused frequently
equals the
equals
[7–
10].
sum of the
the sum input
of the voltage
input voltage 𝑉 and
Vi and output voltage
output voltage 𝑉 . Therefore,
Vo . Therefore, the the
TSBB converter
TSBB converterthatthat
can
switch to +a different
can switch topology
to a different basedbased
topology on system requirements
on system is used
requirements
+ is frequently [7–10].[7
used frequently
L D D
S L S

Vi D Co Ro Vo Vi S Co Ro Vo Vi L Co Ro Vo

(a) (b) (c)

(a) Figure 1. Circuit diagram: (a)(b)
buck; (b) boost; (c) buck-boost. (c)
Figure 1.
1. Circuit diagram: (a) buck; (b) boost;
boost; (c)
(c) buck-boost.
Table 1. Circuit
Figure Current diagram: (a) gain
path and buck;in
(b)topologies. buck-boost.

Table 1.
Table 1. Current
Current path
path and
and gain
gain in
in topologies.
topologies.
Current path
Topology Gain (G)
Topology SwitchCurrentON Path
Current Path Switch OFF Gain
Topology Switch ON Switch Gain(G)
(G)
Buck Vi - SON
Switch - L - Co SwitchLOFF - Co - D
OFF d
Buck Vi - S - L - Co L - Co - D d
Boost
Buck Vi - L
Vi -S-L-C o - S L-CVoi -D
- L - D - Co d 1/(1-d)
Boost
Boost VV i - -L-S
L-S
iVi - S - L
Vi V
- iL-L-D-C
- D - oCo 1/(1-d)
1/(1 − d)
Buck-Boost L - Co - D d/(1-d)
Buck-Boost
Buck-Boost VV i -i -S-L
S-L L L-C
- Coo -D
-D d/(1 − d)
d/(1-d)
Figure 2 shows a circuit diagram of a conventional TSBB converter that comprises
two Figure
switches, twoadiodes,
Figure 22 shows
shows acircuit an
circuitdiagram inductor,
diagram ofof
and a capacitor.
a conventional
a conventional TSBBTSBB This TSBB
converter
converter
converter
thatthat comprises
comprises
operates in
two
the buck,
two switches,
switches, boost,
two two or
diodes, buck-boost
diodes, topology
an inductor,
an inductor, and and abased on
capacitor.
a capacitor. ThistheThisoperation
TSBB TSBB of the
converter
converter switch
operates
operates in [5–7].
in
the Table
2
the summarizes
buck, boost, the
or switching
buck-boost operations
topology based of the
on conventional
the operation
buck, boost, or buck-boost topology based on the operation of the switch [5–7]. Table 2 of TSBB
the converter;
switch [5–7]. it operates
Table in
2thesummarizes
summarizes thethe
buck topology switching
by the
switching operations
on/off
operations of of
thethe
switching conventional
of S 1 while
conventional TSBBTSBB
S2 is converter;
always
converter; off,
it it and
operates
operates in topol
ininboost
the
the
ogybuck
buck by topology
topology
the on/off by
by the the on/off
on/off
switching ofswitching
switching of Sof
S2 while S
1 S
while
1 1iswhile
S
always
2 Sis
2 is always
always
on. off,
off,
Further, and andin
the in boost
boost
TSBB topol-
topology
converter oper
ogy
by by
the the
on/offon/off switching
switching
ates in the buck-boost topology of S of
2 S
while
2 while
Sby S
is is always
always on. on. Further,
Further, thethe
TSBB TSBB converter
converter
1 the on/off switching of both S 1 and S2. It is easy to
1 oper-
operates
ates theinbuck-boost
the buck-boost topology by the on/off
in
change the topologytopology by the
despite the on/off
increase in switching
switching parts;of the
both ofSboth
1 andSvoltage
output S1 2and
. It isS2easy
. It is
has toeasy
thechange
same to polarity
change
the the topology
topology despitedespite the increase
the increase in parts;inthe
parts; the output
output voltagevoltage
has thehas samethe polarity
same polarity
as the
as the input in the buck-boost topology. Moreover, it is easy to select semiconductors be-
as the in
input input
the in the buck-boost
buck-boost topology.
topology. Moreover,
Moreover, it is easy
it is easy to select
to select semiconductors
semiconductors be-
because
cause
cause
the
the voltage
the voltage
voltage
stress
stressstress
of
of theofparts
the
the parts parts
doesdoes
does
not not
exceed
not
exceed exceed
the the
input
the
input input
voltage
voltage
voltage
Vi and𝑉 and 𝑉𝑖
output
output
and output
volt-
voltage
volt
age
age
V 𝑉𝑉𝑜 [9–13].
o [9–13].
[9–13].

S1 L D2

Vi D1 S2 Co Ro Vo

Figure 2. Circuit diagram of the conventional TSBB converter.

Figure2.2.Circuit
Figure Circuitdiagram
diagram of the
of the conventional
conventional TSBBTSBB converter.
converter.
Table 2. Switch operation of the conventional TSBB converter.
TableTable 3 presents
2. Switch the switching
operation and conduction
of the conventional TSBB semiconductors
converter. in each topology of a
single switch converter and a TSBB converter. The TSBB Component
converter uses more parts than
Topology Period
the single switch converter in each Stopology
1 owing Component
S2 to the composition
D1 and wiring
D2 of the
Topology thisPeriod
semiconductors; increases the power loss and lowers the power efficiency. The loss ofD2
Switch ON ON S1 S2 OFF D1
Buckconverter increases because of the Always
the TSBB amount OFF
of the conduction lossAlways
of one ON
diode
Switch OFF
Switch ON OFFON ON OFF
than the
Bucksingle switch type in the buck topology Always
and the amount
OFF of the conduction loss
Switch
Switch ONOFF OFF ON ON OFF Always ON
of one switch
Boost in the boost topology. Moreover,
Always ON the power efficiency
Always OFF in the buck-boost
topology decreasesSwitch OFFto the switching and conduction
owing OFF ON
Switch ON ON losses of one switch and one OFF
diodeBoost
[5,6,10]. Switch ON Always
ON ON ON OFFAlways OFF OFF
Buck-Boost Switch OFF OFF ON
Switch OFF OFF OFF ON ON
Switch ON ON ON OFF OFF
Buck-Boost
Switch OFF OFF OFF ON ON
Appl. Sci. 2023, 13, 343 3 of 19

Table 2. Switch operation of the conventional TSBB converter.

Component
Topology Period
S1 S2 D1 D2
Switch ON ON OFF
Buck Always OFF Always ON
Switch OFF OFF ON
Switch ON ON OFF
Boost Always ON Always OFF
Switch OFF OFF ON
Switch ON ON ON OFF OFF
Buck-Boost
Switch OFF OFF OFF ON ON

Table 3. Switching and conduction semiconductors of single switch converters and the conventional
TSBB converter.

Single Switch Type Conventional TSBB

Topology Switch ON Switch OFF Switch ON Switch OFF
Switching Conduction Switching Conduction Switching Conduction Switching Conduction
Buck S S D D S1 S1 , D2 D1 D1 , D2
Boost S S D D S2 S1 , S2 D2 S1 , D2
Buck-Boost S S D D S1 , S2 S1 , S2 D1 , D 2 D1 , D2

New circuits are suggested in [5,6] to prevent such a decrease in power efficiency. They
demonstrated that power efficiency can be increased compared to those of the conventional
TSBB converter by reducing the number of switching and conduction semiconductors in
the current path. However, there is a trade-off between the number of semiconductors in
the current path and the voltage stress. Therefore, in the new circuits of [5,6], the voltage
stress of the semiconductors in the boost and buck-boost topologies increases, and it will
lower power efficiency above a specific power range. The experimental results confirm
the efficiency based on changes in the output current; however, it is difficult to find the
optimal power range according to the changes in the input voltage and duty that influence
the voltage stress of the semiconductors. To solve this problem, this study proposed a new
type of TSBB converter for improving power efficiency and analyzing the optimal power
range that can improve power efficiency. The proposed TSBB converter can increase power
efficiency in buck and buck-boost topologies by reducing conduction loss caused by the
diode in the switch-off section while using the same number of semiconductors as that of
the conventional TSBB converter. Moreover, the optimal power range of each topology is
analyzed by evaluating the effect of an increase in the voltage stress of semiconductors.
The contributions of this study are as follows:
• We investigated related research about the TSBB converter and proposed a modified
design of the TSBB converter to improve power efficiency using fewer conduction
components in the current path.
• We presented the optimal power range according to the buck, boost, and buck-boost
topologies in CV and CC modes, and, in particular, divided into step-up/step-down
sections in the buck-boost topology.
• We analyzed the power dissipation of the three topologies and explained why the CC
mode of the buck-boost step-up is less efficient than conventional converters over a
certain power range through analytic and experimental diode stress analysis.
The remainder of this paper is organized as follows. Section 2 describes the operation
principle of the proposed TSBB converter. In Section 3, the power loss is compared between
the proposed TSBB converter and the conventional TSBB converter in each topology by
analyzing the switching and conduction losses. The experiment results are described in
Section 4, and, finally, the conclusions are presented in Section 5.
 principle of the proposed TSBB converter. In Section 3, the power loss is compa
tween the proposed TSBB converter and the conventional TSBB converter in eac
ogy by analyzing the switching and conduction losses. The experiment results
scribed in Section 4, and, finally, the conclusions are presented in Section 5.
Appl. Sci. 2023, 13, 343 4 of 19

2. Operation principle
FigurePrinciple
2. Operation 3 shows the circuit diagram of the proposed TSBB converter. Like the
tional TSBB
Figure converter,
3 shows thediagram
the circuit proposed of theTSBB converter
proposed is composed
TSBB converter. of two switch
Like the conven-
diodes,
tional anconverter,
TSBB inductor,theand a capacitor;
proposed further,isitcomposed
TSBB converter operatesofintwo
three topologies
switches, two based
diodes, an inductor, and a capacitor; further, it operates in three
switching of S1 and S2, and it operates in the buck topology by the on/off topologies based on theswitchi
switching of S1 and S2 , and it operates in the buck topology by the on/off switching of
in the boost topology by the switching of S2, and in the buck-boost topology by th
S1 , in the boost topology by the switching of S2 , and in the buck-boost topology by the
taneous on/off
simultaneous switching
on/off switchingof of S
S11 and
and SS2 .2.

S1 L

Vi D1 Co Ro Vo
S2

D2

Figure3. 3.
Figure Circuit
Circuit diagram
diagram of theof the proposed
proposed TSBB converter.
TSBB converter.

Table 4 summarizes the switching operations of the proposed TSBB converter. Table 4
Table 4 summarizes the switching operations of the proposed TSBB converte
indicates that the switching operations of S1 , S2 , and D1 are the same as those of the
4 indicatesTSBB
conventional thatconverter.
the switching operations
However, D2 performsof S 1, Sswitching
on/off 2, and D arebuck
in1 the thetopology
same as thos
conventional
and is always offTSBB converter.topology.
in the buck-boost However, D2 performs on/off switching in the buc
ogy and is always off in the buck-boost topology.
Table 4. Switch operation of the proposed TSBB converter.

Table 4. Switch operation of the proposed TSBB converter.

Component
Topology Period
S1 S2 D 1 D2
Component
Topology SwitchPeriod
ON ON Always OFF ON
Buck S1 S2 ON D 1 D
Switch OFF OFF OFF OFF
Switch
Switch ON ONAlways ON ON Always
Always OFF
OFF O
Boost
Buck Switch OFF ON OFF ON
Switch OFF OFF OFFOFF ON O
Switch ON ON ON OFF Always
Buck-Boost Switch
Switch OFF ON OFF Always OFF ON ON Always
OFF O
Boost
Switch OFF ON OFF OFF O
Figure 4 presents the operation
Switch ON principle ON of the proposed ONTSBB converter OFF in each Alw
Buck-Boost
topology. The switch-on/off sections are divided by the operation of the switch that
Switch OFF OFF OFF ON O
transfers the energy to the inductor. The semiconductors located in the current path in each
sectionFigure 4 presents
are conduction the operation
semiconductors; principle of that
the semiconductor the only
proposed
operatesTSBB
in oneconverter
of the in
pology. Thesections
switch-on/off switch-on/off sections
is the switching are dividedTable
semiconductor. by the operation
5 compares of the switch
the switching and that t
conduction semiconductors between the conventional and proposed
the energy to the inductor. The semiconductors located in the current path TSBB converters. In in each
comparison with the conventional TSBB converter, the proposed TSBB converter undergoes
are conduction semiconductors; the semiconductor that only operates in one of the
an increase in the switching loss of D2 in the switch-on section and a decrease in the
on/off sections
conduction loss of is
D2the switching
in the switch-offsemiconductor. Table 5topology,
section. In the buck-boost compares the switching a
the switching
duction
and semiconductors
conduction between
losses of D2 in the thesection
switch-off conventional and6 compares
decrease. Table proposed theTSBB
stress conver
between
comparisonthe conventional and proposed TSBB
with the conventional TSBB converters;
converter,theythehave the almost
proposed TSBBsameconverter
voltage stress in buck and boost topologies, but in the buck-boost topology, the stress of D1
goes an increase in the switching loss of D2 in the switch-on section and a decreas
increases to Vi + Vo .
conduction loss of D2 in the switch-off section. In the buck-boost topology, the sw
and conduction losses of D2 in the switch-off section decrease. Table 6 compares th
between the conventional and proposed TSBB converters; they have the almost sa
age stress in buck and boost topologies, but in the buck-boost topology, the stre
increases to 𝑉𝑖 + 𝑉𝑜 .
12, x FOR PEER REVIEW 5 of 20
Appl. Sci. 2023, 13, 343 5 of 19

S1 L S1 L

+ +

Vi D1 Co Ro Vo Vi D1 Co Ro Vo
S2 S2

D2 D2

Switch ON Switch OFF

(a)
S1 L S1 L

+ +

Vi D1 Co Ro Vo Vi D1 Co Ro Vo
S2 S2

D2 D2

Switch ON Switch OFF

(b)
S1 L S1 L

+ +

Vi D1 Co Ro Vo Vi D1 Co Ro Vo
S2 S2

D2 D2

Switch ON Switch OFF

(c)
Figure 4. OperationFigure
principle of the proposed
4. Operation principle TSBB
of the converter: (a) Buck;
proposed TSBB (b) Boost;
converter: (c) (b)
(a) Buck; Buck-boost.
Boost; (c) Buck-boost.

Table 5. Switching Table

and conduction
5. Switching semiconductors of the conventional
and conduction semiconductors and proposed
of the conventional TSBB con-
and proposed TSBB convert-
verters: (a) Switching semiconductors; (b) Conduction semiconductors.
ers: (a) Switching semiconductors; (b) Conduction semiconductors.

Conventional
Conventional Ref. [5][5]
Ref. Proposed
Proposed
Topology Gain
Topology Gain Switch
Switch
ON Switch
Switch OFF Switch
Switch ON Switch Switch
Switch OFF SwitchSwitch OFF
Switch ON
Buck d S1 ON OFF
D 1
ON
S1 , D2 OFF D1 ON S1 , D2 OFF D1
Boost 1/(1 − d) S2 S DD 2 S2
S1, D D1 D2 S1, D2 S2 D1 D2
Buck d
Buck-Boost d/(1 − d) S1 , S2 1 D1 , D12 S22
D1 S1 , S2 D1
Boost 1/(1-d) S2 D2 (a) S2 D2 S2 D2
Buck- Conventional Ref. [5] Proposed
Topology d/(1-d) S1, S2 D1, D2 S2 D 1 S1, S2 D 1
Boost Gain Switch ON Switch OFF Switch ON Switch OFF Switch ON Switch OFF
Buck d S1 , D2 D1 , D2 (a) S1 , D2 D1 S1 , D2 D1
Boost 1/(1 − d) S1 , S2Conventional
S1 , D2 S2Ref. [5] S1 , D2 S1 , S2
Proposed S1 , D2
Buck-Boost d/(1 − d) S1 , S2 D1 , D2 S2 D1 S1 , S2 D1
Topology Gain Switch Switch Switch Switch Switch Switch
(b)
ON OFF ON OFF ON OFF
Buck d S1, D2 D1, D2 S1, D2 D1 S1, D2 D1
Table 6. Comparison of stress in each TSBB converter: (a) Voltage stress; (b) Current stress.
Boost 1/(1-d) S1, S2 S1, D2 S2 S1, D2 S1, S2 S1, D2
Buck- Conventional
Topology d/(1-d) S S1, S2 D1, D2
S2
S2 D1
D1
S1, S2 D1
D2
Boost 1

Buck Vi -
(b) Vi -
Boost - Vo - Vo
Table 6. Comparison of stress
Buck-Boost Vi in each TSBB converter:
Vo (a) Voltage stress; V(b)
i Current stress. Vo

Conventional
Topology
S1 S2 D1 D2
Buck 𝑉𝑖 - 𝑉𝑖 -
Boost - 𝑉𝑜 - 𝑉𝑜
Appl. Sci. 2023, 13, 343 6 of 19

Table 6. Cont.

Ref. [5]
Topology
S1 S2 D1 D2
Coss,D2 Coss,S1
Buck Coss,S1 +Coss,D2 Vi
- Vi Coss,S1 +Coss,D2 Vi
Coss,S1
Boost - Vo - Coss,S1 +Coss,D2 Vo
Coss,D2 Coss,S1
Coss,S1 +Coss,D2 Vi Coss,S1 +Coss,D2 Vi
Buck-Boost or Vi + Vo Vi + Vo or
Coss,D2 Coss,S1
Coss,S1 +Coss,D2 Vo Coss,S1 +Coss,D2 Vo

Proposed
Topology
S1 S2 D1 D2
Coss,D2 ∼ Coss,S1 ∼
Buck Coss,S1 +Coss,D2 Vi ( = Vi ) - Vi Coss,S1 +Coss,D2 Vi ( = 0)
Boost - Vo - Vo
Coss,D2 ∼ Coss,D2 ∼
Buck-Boost Coss,S1 +Coss,D2 Vi ( = Vi ) Coss,S2 +Coss,D2 Vo ( = Vo ) Vi + Vo -

(a)
Conventional/Proposed
Topology
S1 S2 D1 D2
     
Buck 1 1− d - 1 1− d 1 1− d
Vo R1
+ 2L· f sw Vo R1
+ 2L· f sw Vo R1
+ 2L· f sw
   
Boost - Vi 1
+ d - Vi 1
+ d
(1− d )2 · R1 2L· f sw (1− d )2 · R1 2L· f sw
     
Buck-Boost Vi d
+ d
Vi d
+ d
Vi d
+ d -
(1− d )2 · R1 2L· f sw (1− d )2 · R1 2L· f sw (1− d )2 · R1 2L· f sw

(b)
1 Output resistance.

3. Analysis of Semiconductor Power Loss

The power loss of a TSBB converter includes the losses of the switch, diode, inductor,
and capacitor when various parasitic components in the circuit are ignored. The power
loss of the two converters is determined by the power loss of the semiconductors assuming
that the losses of the inductor and capacitor are the same between the conventional and
proposed TSBB converters. Therefore, the increase or decrease in power efficiency is
determined by the operation of the switch and diode.

3.1. Switch and Diode Current

Figure 5 presents the switch and diode current of the proposed TSBB converter in each
topology. In the buck topology, the inductor current flows through S1 and D2 during the
switch-on section and through D1 during the switch-off section. The inductor current IL is
V (1− d )
the output current Io and ∆IL = oL· f sw by the volt-sec balance law at switching frequency
f sw , the inductor current Imax , Imin flowing through switch S1 and diode D1 /D2 can be
expressed as:
∆I 1−d
 
1
Imax = Io + L = Vo + (1)
2 R 2L· f sw
∆I 1−d
 
1
Imin = Io − L = Vo − (2)
2 R 2L· f sw
The inductor current flows through S1 and D2 during the switch-on section and
through D1 during the switch-off section in the boost topology. Since the inductor current
 Appl. Sci. 2022, 12, x FOR PEER REVIEW 7 of 20

Appl. Sci. 2023, 13, 343 7 of 19

∆𝐼𝐿 1 1−𝑑
𝐼𝑚𝑎𝑥 = 𝐼𝑜 + = 𝑉𝑜 ( + ) (1)
Io d·Vi 2 𝑅 2𝐿 ∙ 𝑓𝑠𝑤
IL is 1−d and ∆IL = L· f sw , the inductor current Imax , Imin flowing through switch S1 /S2
and diode D2 can be expressed as: ∆𝐼𝐿 1 1−𝑑
𝐼𝑚𝑖𝑛 = 𝐼𝑜 − = 𝑉𝑜 ( − ) (2)
2 " 𝑅 2𝐿 ∙ 𝑓𝑠𝑤 #
∆IL 1 d
The inductor current
Imax = flows
Io +through
= VSi 1 and D2 2during+ the switch-on section and (3)
2 ( 1 − d ) · R 2L
through D1 during the switch-off section in the boost topology. Since · f sw the inductor current
𝐼𝑜 𝑑∙𝑉𝑖
𝐼𝐿 is and ∆𝐼𝐿 = , the inductor current" 𝐼𝑚𝑎𝑥 , 𝐼𝑚𝑖𝑛 flowing#through switch S1/S2
1−𝑑 𝐿∙𝑓𝑠𝑤
∆IL 1 d
and diode D2 can be expressed
Imin = Ioas: − = Vi − (4)
2 2 2L · f sw
(1 − d ) · R
∆𝐼𝐿 1 𝑑
In buck-boost topology, 𝐼𝑚𝑎𝑥 =the𝐼𝑜 + = 𝑉𝑖 current
inductor [ + through ] (3)
2 (1 − 𝑑)2flows
∙ 𝑅 2𝐿 ∙ 𝑓𝑠𝑤 S1 and D2 during the
switch-on section and through D1 during the switch-off section. Since the inductor current
Io d·Vi ∆𝐼𝐿 topology,1 the inductor 𝑑 current Imax , I
I L = 1− d and ∆IL = L· f sw 𝐼𝑚𝑖𝑛
same= 𝐼as
𝑜−
boost= 𝑉𝑖 [ − ] min flowing
(4)
2 be expressed 2
(1 − 𝑑) ∙ as:𝑅 2𝐿 ∙ 𝑓𝑠𝑤
through switch S /S and diode D can
1 2 2
In buck-boost topology, the inductor current
" flows through S#1 and D2 during the
∆IL the switch-off
switch-on section and through D1 during d
d section. Since the inductor current
𝐼 Imax
𝑑∙𝑉 = Io + = Vi 2 1
+ (5)
𝐼𝐿 = 𝑜 and ∆𝐼𝐿 = 𝑖 2
same as boost (1 − d ) · R
topology, the 2L
inductor · f
current
sw 𝐼𝑚𝑎𝑥 , 𝐼𝑚𝑖𝑛 flow-
1−𝑑 𝐿∙𝑓𝑠𝑤
ing through switch S1/S2 and diode D2 can be"expressed as: #
∆𝐼𝐿∆IL 𝑑 d 𝑑 d
𝐼𝑚𝑎𝑥 o − = 𝑉=
Imin==𝐼𝑜 I+ [V + 2𝐿+∙ 𝑓𝑠𝑤~] (5) (6)
22 2 𝑖 (1i − (𝑑)
1−
22 ∙ 𝑅112 2𝐿
𝑠𝑤 · f sw
d) · R1 ∙ 𝑓2L
∆𝐼𝐿 𝑑 𝑑
𝐼𝑚𝑖𝑛 = 𝐼𝑜 − = 𝑉𝑖 [ + ] (6)
VGS VGS VGS
d·Tsw d·Tsw d·Tsw

(1-d)·Tsw (1-d)·Tsw (1-d)·Tsw

t t t
1/fsw 1/fsw 1/fsw
VL VL VL
Vi - Vo Vi Vi

t t t
- Vo Vi - Vo - Vo

IL ΔIL IL ΔIL IL ΔIL

IS1, ID2 ID1 Io IS2 ID2 IS1, Is2 ID1

t t t

(a) (b) (c)

Figure5.
Figure 5. Switch
Switchand diode
and current
diode of theofproposed
current TSBB converter:
the proposed (a) Buck; (b)
TSBB converter: (a)Boost;
Buck;(c)(b)
Buck-
Boost;
boost.
(c) Buck-boost.
Thepower
The powerloss
loss of
of aa TSBB
TSBB converter
converterincludes
includesthe
thelosses
lossesof of
thethe
switch, diode,
switch, inductor,
diode, inductor,
andcapacitor
and capacitor when
when various
various parasitic
parasiticcomponents
componentsininthe thecircuit
circuitare ignored.
are ignored.TheThe
power
power
loss of the two converters is determined by the power loss of the semiconductors assum-
loss of the two converters is determined by the power loss of the semiconductors assuming
ing that the losses of the inductor and capacitor are the same between the conventional
that the losses of the inductor and capacitor are the same between the conventional and
and proposed TSBB converters. Therefore, the increase or decrease in the power efficiency
proposed TSBB converters. Therefore, the increase or decrease in the power efficiency is
is determined by the operation of the switch and diode.
determined by the operation of the switch and diode.
The losses of semiconductors are divided into switching and conduction losses. A
The losses of semiconductors are divided into switching and conduction losses. A
switching loss occurs during the transient time of the switching operation. Although the
switching loss occurs during the transient time of the switching operation. Although the
switching loss is 0 in the ideal condition, it is caused by the time delay attributed to the
switching loss is 0 in the ideal condition, it is caused by the time delay attributed to the
parasitic resistance and parasitic capacitance at the time of turn-on or turn-off [14,15]. The
parasitic resistance and parasitic
conduction loss is caused by the capacitance
current that at the time
flows by theofturn-on
turn-onoforthe
turn-off [14,15]. The
semiconductor
conduction loss is caused by the current that
and on the resistance of the semiconductor [16–18]. flows by the turn-on of the semiconductor
and on the resistance of the semiconductor [16–18].

3.2. Switching Loss

The switching loss of MOSFET, PS,SW is divided into switch turn-on loss, PS,SW,ON
switch turn-off loss PS,SW,OFF , and output capacitance loss PS,SW,Coss as [5,15,17]:
Appl. Sci. 2023, 13, 343 8 of 19

PS,SW = PS,SW,ON + PS,SW,OFF + PS,SW,Coss (7)

The switch turn-on and turn-off losses are difficult to calculate because of the nonlinear
characteristics of the drain-source voltage v DS and drain current i D . Therefore, they can be
determined by applying linear approximation in the rising and falling sections of v DS and
i D . The output capacitance loss of MOSFET can be determined by calculating the stored
energy of the capacitor because the energy is charged in the output capacitance when the
MOSFET turns off, and is discharged when the MOSFET turns on. The MOSFET switching
loss can be represented by using the turn-on time ton , turn-off time to f f , switching frequency
f sw , and output capacitance Coss of the MOSFET as [5,17,18]:

PS,SW = 21 ·v DS ·i D ·ton · f sw + 12 ·v DS ·i D ·to f f · f sw + 12 ·Coss ·v DS 2 · f sw

(8)
= 12 ·v DS ·i D ·(ton + to f f )· f sw + 12 ·Coss ·v DS 2 · f sw

The output capacitance of the MOSFET is several tens to hundreds of picofarads.

Therefore, it is negligible compared to the switch turn-on and turn-off losses and can be
represented as [5,6,17,18]:

1
PS,SW = ·v ·i D ·(ton + to f f )· f sw (9)
2 DS
The switching loss PD,SW of the diode can be divided into the switch turn-on loss
PD,SW,ON and the switch turn-off loss PD,SW,OFF it is represented as:

PD,SW = PD,SW,ON + PD,SW,OFF ∼

= PD,SW,OFF (10)

The switching loss of the diode can be approximated as the switch turn-off loss because
the loss of the diode caused by the reverse recovery in the turn-off section is considerably
larger than the turn-on loss [19,20].
Figure 6 shows the reverse recovery characteristic of the diode [6]. In an ideal diode,
the current flows when the voltage is applied in the forward direction, and no current flows
when the voltage is applied in the reverse direction. However, in an actual operation, the
reverse current flows for a certain time before it reaches zero when the diode is turned
off after a forward current flow. Here, the time during which the reverse current flows is
referred to as the reverse recovery time (trr ); the maximum value of the reverse current that
flows in the diode is referred to as the repetitive peak reverse current (IRRM ). The turn-off
loss PD,SW,OFF of the diode when the reverse voltage applied to the diode is VR and the
switching frequency is f sw can be expressed as [21,22]:

Appl. Sci. 2022, 12, x FOR PEER REVIEW 1 9 of 20

PD,SW = ·VR · IRRM ·trr · f sw (11)
2

ID
IF
trr
Practical Waveform

t
Approximate Waveform

IRRM

Figure 6.
Figure 6. Diode
Diode reverse
reverse recovery
recoverycharacteristics.
characteristics.

3.3. Conduction Loss

The instantaneous value of the conduction loss of the MOSFET, 𝑃𝑆,𝐶𝐷 (𝑡) can be ex-
pressed by 𝑣𝐷𝑆 (𝑡), 𝑖𝐷 (𝑡), and the drain-source resistance 𝑅𝐷𝑆(𝑂𝑁) in the complete switch
Appl. Sci. 2023, 13, 343 9 of 19

3.3. Conduction Loss

The instantaneous value of the conduction loss of the MOSFET, PS,CD (t) can be ex-
pressed by v DS (t), i D (t), and the drain-source resistance R DS(ON ) in the complete switch
turn-off section as [6,15,16,19]:

PS,CD (t) = v DS (t)·i D (t) = i D 2 (t)· R DS(ON ) (12)

The average value can be determined by integrating Equation (6) over the switching
period Tsw as:
Z Tsw
1
PS,CD (t) = i D 2 (t)· R DS(ON ) dt (13)
Tsw 0
PS,CD = ID(rms) 2 · R DS(ON ) (14)
The instantaneous value of the conduction loss of the diode PD,CD (t) can be expressed
by the forward voltage drop v F (t), forward current i F (t), and diode resistance R D as [5,6]:

PD,CD (t) = v F (t)·i F (t) + R D ·i F 2 (t) (15)

The average value can be determined by integrating Equation (8) over the switching
period Tsw as [5,12,15]:
Z T n
1 SW
o
PD,CD (t) = v F (t)·i F (t) + R D ·i F 2 (t) dt (16)
Tsw 0

PD,CD = VF · IF( AVG) + R D · IF( RMS) 2 (17)

4. Analysis of Power Loss in Topologies

Table 5 summarizes the switching and conduction semiconductors of the conventional
and proposed TSBB converters in each topology. Table 6 presents the voltage and current
stresses of the conventional and proposed TSBB converters in each topology. In each
topology, the switching loss that has reflected the voltage stress and conduction loss based
on the switch on/off time can be determined and compared.

4.1. Buck Topology

In Table 5, the switching semiconductors of the conventional TSBB converter are S1 /D1 ,
and the conducting semiconductors are S1 /D1 /D2 . Thus, the switching loss PCON,SW and
conduction loss PCON,CD can be expressed, respectively, as:

PCON,SW = PSW,S1 + PSW,D1 (18)

PCON,CD = PCD,S1,ON + PCD,D2,ON + PCD,D1,OFF + PCD,D2,OFF (19)

The switching semiconductors of the proposed TSBB converter are S1 /D1 /D2 , and
those of the conducting semiconductor are S1 /D1 /D2 . Therefore, the switching loss
PPRO,SW and conduction loss PPRO,CD can be expressed as:
   
Coss,D2 Coss,S1
PPRO,SW = PSW,S1 Vi + PSW,D1 (Vi ) + PSW,D2 Vi (20)
Coss,S1 + Coss,D2 Coss,S1 + Coss,D2
PPRO,CD = PCD,S1,ON + PCD,D2,ON + PCD,D1,OFF (21)
The switching loss varies by the voltage stress; however, the internal voltage of semi-
conductors is Vi for both the conventional and proposed TSBB converters. Consequently,
Appl. Sci. 2023, 13, 343 10 of 19

the switching losses of the semiconductors are the same. Therefore, the difference in power
loss between the two converters can be expressed as:
 
Coss,S1
PCON − PPRO = PCD,D2,OFF − PSW,D2 Vi (22)
Coss,S1 + Coss,D2

This difference can be determined by the conduction and switching losses in the
switch-off section of D2 . Since the switch-off section is (1 − d)· TSW , the lower the duty
ratio, the higher the efficiency of the proposed TSBB converter.

4.2. Boost Topology

In the boost topology, the switching semiconductors are S2 /D2 , and the conducting
semiconductors are S1 /S2 /D2 . Thus, the switching loss PCON,SW (= PPRO,SW ) and the
conduction loss PCON,CD (= PPRO,CD ) can be expressed as:

PCON,SW = PPRO,SW = PSW,S2 + PSW,D2 (23)

PCON,CD = PPRO,CD = PCD,S1,ON + PCD,S2,ON + PCD,S1,OFF + PCD,D2,OFF (24)

There is no difference in the efficiency between the conventional and proposed TSBB
converters because there is no change in the operation of semiconductors.

4.3. Buck-Boost Topology

In Table 5, both the switching and conducting semiconductors of the conventional
TSBB converter are S1 /S2 /D1 /D2 . Therefore, the switching loss PCON,SW and conduction
loss PCON,CD can be expressed as:

PCON,SW = PSW,S1 (Vi ) + PSW,S2 (Vo ) + PSW,D1 (Vi ) + PSW,D2 (Vo ) (25)

PCON,CD = PCD,S1,ON + PCD,S2,ON + PCD,D1,OFF + PCD,D2,OFF (26)

Both the switching and conducting semiconductors of the proposed TSBB converter
are S1 /S2 /D1 . Therefore, the switching loss PPRO,SW and conduction loss PPRO,CD can be,
respectively, expressed as:
   
C Coss,D2
PPRO,SW = PSW,S1 C oss,D2 Vi + P V
SW,S2 Coss,S2 +Coss,D2 o
oss,S1 +Coss,D2
(27)
+ PSW,D1 (Vi + Vo )

PPRO,CD = PCD,S1,ON + PCD,S2,ON + PCD,D1,OFF (28)

The voltage stress of each semiconductor is indicated in parentheses since the switch-
ing loss varies by the voltage stress. The loss difference between the conventional and
proposed TSBB converters is determined by the switching loss of D1 /D2 and the conduction
loss of D2 in the switch-off section, and it can be expressed as:

PCON − PPRO = PSW,D1 (Vi ) + PSW,D2 (Vo ) + PCD,D2,OFF − PSW,D1 (Vi + Vo ) (29)

There are no switching and conduction losses by D2 because the proposed TSBB
converter D2 does not operate. However, the voltage stress of D1 increases to Vi + Vo ,
the voltage stress and reverse current of the diode in a linear section are PSW,D1 (Vi ) +
PSW,D2 (Vo ) ∼
= PSW,D1 (Vi + Vo ). Therefore, the loss is determined by the conduction loss
of the switch-off section of D2 . The power efficiency of the proposed TSBB converter is
higher than that of the conventional TSBB converter. In contrast, the switching loss by D1 ,
PSW,D1 (Vi + Vo ), increases in the section where the reverse current of the diode increases
sharply owing to the voltage stress. Therefore, the power efficiency of the proposed TSBB
converter is lower than that of the conventional TSBB converter.
 𝑃𝑆𝑊,𝐷1 (𝑉𝑖 + 𝑉𝑜 ), increases in the section where the reverse current of the d
sharply owing to the voltage stress. Therefore, the power efficiency of the p
converter is lower than that of the conventional TSBB converter.
Appl. Sci. 2023, 13, 343 11 of 19
5. Experimental Results
Figure 7 shows a prototype of a 100 W TSBB converter fabricated to
5.proved
Experimental
power Results
efficiency. The Arduino controller generates a 5 V pulse wid
Figure 7 shows
(PWM) to control a prototype of a 100 W TSBB
the MOSFET converter
driver fabricated
IC input; to verify
upon the improved
receiving this signal
power efficiency. The Arduino controller generates a 5 V pulse width modulation (PWM)
driver
to controlICthe converts
MOSFET driverit to IC
aninput;
18 Vupon
drive signalthisand
receiving transfers
signal, the MOSFETit todriver
the gate of
The
IC specifications
converts it to an 18 V ofdrive
the components are 20%
signal and transfers or more
it to the gate of larger than the
the MOSFET. The calcula
specifications of the components are 20% or more larger than the calculated
stress considering the various input/output conditions of the experiment. T maximum stress
considering the various input/output conditions of the experiment. Table 7 summarizes
rizes
the the specifications
detailed detailed specifications of the
of the components; Tablecomponents; Table 8values
8 presents the maximum presents
of the the ma
of thestress
voltage voltage stress
measured measured
in the in the CV/CC modes.
CV/CC modes.

Figure
Figure7. 100 W TSBB
7. 100 prototype.
W TSBB prototype.
Table 7. Components specifications.
Table 7. Components specifications.
Component Part Name Specification
Component
PWM Generator
Part Name
Arduino Nano 5 V, 16 MHz
Specification
PWM Generator Arduino Nano 5 V, =167–16
Output Peak Current = 2.5 A, Input Current MHzmA
MOSFET Driver HCPL-J312 Supply Voltage = 15–30 V, Input Capacitance = 60 pF
Output
Rise TimePeak Current
= 0.1 us, Fall Time = 2.5usA, Input Current = 7
= 0.1
MOSFET Driver HCPL-J312 Supply Voltage
Drain-Source Voltage=VDSS
15 =- 250
30 VV, Input Capacitance
Gate-Source Voltage
Rise TimeVGSS==0.1±30us,
V Fall Time = 0.1 us
Drain Current ID = 51 A
MOSFET RCX510N25
Static Drain-Source Drain-Source
ON-State ResistanceVoltage
= 48 mΩ V
DSS = 250 V
Output Capacitance = 350 pF
Gate-Source
Rise Time = 300 Voltage
ns, Fall Time = 210 ns VGSS = ±30 V
Reverse voltage (DC) VR = 300 V
Drain Current ID = 51 A
MOSFET
Diode RCX510N25
RF2001T3D
Forward voltage VF = 1.3 V (at IF = 10 A)
Average Rectified
Static Forward CurrentON-State
Drain-Source IF = 20 A Resistance = 48
Reverse recovery time trr = 25 ns (at IF = 0.5 A, IR = 1 A, Irr = 0.25 × IR )
Output Capacitance = 350 pF
Cross Section = 0.654 cm2 , Path Length = 6.35 cm
Window Area =Rise 2 , Volume = 4.154 cm3
Inductor CH270125 Time
1.56 cm = 300 ns, Fall Time = 210 ns
AL Value = 157 nH/Turn2 , Permeability µ = 125
Reverse
Inductance = 250 uHvoltage (DC) VR = 300 V
RatedForward
Voltage (Vdcvoltage
) = 100 V V = 1.3 V (at I = 10 A)
F F
Rated ripple current = 2330 mA (at 100 kHz)
Diode RF2001T3D
100YXG820MEFC18 × 40 ◦
Electrolytic Capacitor Average
Leakage Current Rectified
= 3 µA, Impedance = 20Forward
C, 100 kHzCurrent I = 20
F
Dissipation Factor(MAX) tanδ = 0.08
Reverse recovery time= 820
Capacitance t =uF25 ns (at I = 0.5 A, I = 1 A,
rr F R

The experiments are conducted in the CV/CC modes of the three topologies. The
experiment for the buck-boost topology is conducted separately for the step-down and
step-up sections. In the CV mode, the power efficiency is measured for the output power
range of 10–80 W at the switching frequency f sw = 100 kHz of the output current. The
Appl. Sci. 2023, 13, 343 12 of 19

power efficiency was measured at three duty ratios to analyze the power efficiency based
on the change in the duty ratio. If the input/output voltage variation ratio Vvar is defined
as the ratio of the difference between the input and output voltages to the input voltage, it
can be expressed using the input voltage Vi and the output voltage Vo as:

|Vi − Vo |
Vvar (%) = × 100 (30)
Vi

In each topology, the power efficiency was measured at the duty ratios where Vvar
was 25%, 33%, and 50%. Table 9 shows the duty ratio based on Vvar in each topology.
Figure 8a–d shows PWM waveforms of the conventional and the proposed TSBB converter
in each topology implemented using Arduino Nano. Figure 8e–h presents waveforms of
the inductor current, the gate-source voltage, and the output voltage of the conventional
and proposed TSBB converters measured in CC mode at Vvar = 33% (Vo ∼ =40 V).

Table 8. Measured maximum voltage stresses on components in CV and CC modes.

CV CC
Conventional (Vmax ) Proposed (Vmax ) Conventional (Vmax ) Proposed (Vmax )
Vvar Device Buck-Boost Buck-Boost Buck-Boost Buck-Boost
Buck Boost Buck Boost Buck Boost Buck Boost
Step- Step- Step- Step- Step- Step- Step- Step-
Down Up Down Up Down Up Down Up
S1 53.3 - 53.3 32.0 53.3 - 53.3 32.0 80.0 - 80.0 80.0 80.0 - 80.0 80.0
S2 - 41.3 46.0 45.5 - 41.6 47.5 46.8 - 104.5 67.2 114.8 - 105.2 68.9 116.9
25% D1 53.3 - 53.3 32.0 53.3 - 100.8 78.8 80.0 - 80.0 80.0 80.0 - 148.9 196.9
D2 - 41.3 46.0 45.5 - 41.6 - - - 104.5 67.2 114.8 - 105.2 - -
S1 60.0 - 60.0 30.0 60.0 - 60.0 30.0 80.0 - 80.0 80.0 80.0 - 80.0 80.0
S2 - 41.3 45.9 44.9 - 41.7 47.5 46.3 - 111.9 59.0 121.0 - 112.0 60.5 123.0
33% D1 60.0 - 60.0 30.0 60.0 - 107.5 76.3 80.0 - 80.0 80.0 80.0 - 140.5 203.0
D2 - 41.3 45.9 44.9 - 41.7 - - - 111.9 59.0 121.0 - 112.0 - -
S1 80.0 - 80.0 26.7 80.0 - 80.0 26.7 80.0 - 80.0 80.0 80.0 - 80.0 80.0
S2 - 41.8 46.3 45.5 - 41.7 47.9 46.9 - 126.5 43.2 138.5 - 127.3 44.6 141.2
50% D1 80.0 - 80.0 26.7 80.0 - 127.9 73.6 80.0 - 80.0 80.0 80.0 - 124.6 221.2
D2 - 41.8 46.3 45.5 - 41.7 - - - 126.5 43.2 138.5 - 127.3 - -

Table 9. Duty ratio according to Vvar in each topology.

Buck-Boost
Vvar Buck Boost
Step-Down Step-Up
25% 0.750 0.200 0.430 0.556
33% 0.667 0.250 0.400 0.571
50% 0.500 0.330 0.330 0.600

5.1. Buck Topology

Figure 9 shows the power efficiency of the buck topology in the CV and CC modes. If
the power efficiency difference PDi f f is positive (+), it means efficiency improvement; if it
is negative (-), it indicates an efficiency decline. The power efficiency improves in every
condition from 10–80 W because of the removal of D2 in the switch-off section in the CV
and CC modes. PDi f f increases as the switch-off section becomes longer, i.e., when there
is an increase in the duty ratio. In the same duty ratio condition, PDi f f decreases with an
increase in the input voltage and output current. The improvement effect is large in the
low-power region. The proposed converter can achieve a greater efficiency improvement
effect in a region where the voltage conversion is large, and the output current is low.
Appl. Sci. 2023, 13, 343 13 of 19

0.750 0.333 0.429 0.600

0.667 0.250 0.400 0.571

0.500 0.200 0.333 0.556

Time = 5 us/div All = 5 V/div Time = 5 us/div All = 5 V/div Time = 5 us/div All = 5 V/div Time = 5 us/div All = 5 V/div
= 100 kHz = 100 kHz = 100 kHz = 100 kHz

(a) (b) (c) (d)

Conventional

Time = 5 us/div = 5 V/div Time = 5 us/div = 5 V/div Time = 5 us/div = 5 V/div Time = 5 us/div = 5 V/div
= 100 kHz = 20 V/div = 100 kHz = 20 V/div = 100 kHz = 20 V/div = 100 kHz = 20 V/div
= 1 A/div = 1 A/div = 1 A/div = 1 A/div

Proposed

Time = 5 us/div = 5 V/div Time = 5 us/div = 5 V/div Time = 5 us/div = 5 V/div Time = 5 us/div = 5 V/div
= 100 kHz = 20 V/div = 100 kHz = 20 V/div = 100 kHz = 20 V/div = 100 kHz = 20 V/div
= 1 A/div = 1 A/div = 1 A/div = 1 A/div

(e) (f) (g) (h)

Figure 8. Waveforms of PWM, inductor current 𝐼𝐿 , gate-source voltage 𝑉𝐺𝑆 ,
Figure 8. Waveforms of PWM,
and output voltage inductor
𝑉𝑜 : PWM ofcurrent IL , boost;
(a) buck; (b) gate-source voltage
(c) buck-boost VGS , and output voltage Vo :
step-down;
(d) buck-boost step-up; 𝐼 , 𝑉 , 𝑉 of (e) buck (at
PWM of (a) buck; (b) boost; (c) buck-boost step-down; (d) buck-boost step-up;
𝐿 𝐺𝑆 𝑜 d = 0.667, ; 𝐼𝐿 = 1.5 A); (f) boostI , V , V of (e) buck
L GS o
(at d = 0.250, 𝐼𝐿 = 0.75 A); (g) buck-boost step-down (at d = 0.400, 𝐼𝐿 = 1.5 A);
(at d
Appl. Sci. 2022, 12, x FOR PEER REVIEW
= 0.667; I L = 1.5 A); (f) boost (at d = 0.250, I L
and (h) buck-boost step-up (at d = 0.571, 𝐼𝐿 = 0.75 A).= 0.75 A); (g) buck-boost step-down (at d = 0.400,
14 of 20
IL = 1.5 A); and (h) buck-boost step-up (at d = 0.571, IL = 0.75 A).

Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop.

100 10 100 10 100 10

98 9 98 9 98 96.4 9
95.8 95.7 96.1 96.1 95.9 95.6 95.6 95.4 95.8 96.0 95.7 96.0 95.6 95.6 95.4
95.2 95.2 95.0 95.4 95.2 95.0 95.0 94.8
94.5 94.9

Efficiency Difference [%]

Efficiency Difference [%]

Efficiency Difference [%]

94.7
96 93.8 8 96 8 96 8
Power Efficiency [%]

Power Efficiency [%]

Power Efficiency [%]

93.1 93.1
94 95.5 95.5 95.3 95.2 95.0 7 94 95.3 95.1 95.1 95.0
7 94 7
94.9 94.8 94.6 95.1 95.0 95.1
94.6 94.9 94.7 94.5
94.2 94.1 94.1 94.0 93.9
92 6 92 6 92 90.8 94.0 6
93.0 93.4
92.5
90 5 90 91.6 5 90 5
88 4 88 4 88 4
86 3 86 3 86 2.29 3
1.38 1.23 1.45 1.50 1.49 1.40 1.33
84 2 84 1.10 0.97 2 84 1.03 0.93 0.92
2
0.82 0.77 0.71 0.78 0.82
0.61 0.56 0.54 0.55 0.53 0.43 0.45 0.53
82 0.34 0.53 0.51 0.32 1 82 1 82 1
80 0 80 0 80 0
10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100
Output Current [%] Output Current [%] Output Current [%]

(a)

Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop.

110 10 110 10 110 20

96.1 96.4 96.8 96.1 96.4 96.8
93.6 95.0 95.7 93.6 95.0 95.7 93.6 94.2 94.7
100 91.1 9 100 91.1 9 100 91.3 92.7 18
89.1
Efficiency Difference [%]
Efficiency Difference [%]

Efficiency Difference [%]

82.8 82.8 84.3

90 8 90 8 90 16
95.2 95.8 96.1 96.6 94.2 95.0 95.4 96.0
Power Efficiency [%]

Power Efficiency [%]

Power Efficiency [%]

93.0 94.4 91.3 93.3 92.6 93.3 93.9

80 89.7 7 80 7 80 89.9 91.5 14
87.5 69.7 86.9
70 80.0 6 70 6 70 81.0
12
1 75.1
62.4
60 5 60 4.12 5 60 10
7.30
50 4 50 4 50 8
2.77
40 3 40 3 40 6
1.42 1.58 3.29
30 2 30 1.13 2 30 2.21 4
0.67 0.54 0.50 0.64 0.82 0.43 1.46 1.20
1.03 0.85 0.79
20 0.29 0.28 0.18 1 20 0.41 0.33 1 20 2
10 0 10 0 10 0
10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80
Input Voltage [VDC] Input Voltage [VDC] Input Voltage [VDC]

(b)
Figure 9. Power efficiency comparison of the buck topology: (a) CV mode; (b) CC mode.
Figure 9. Power efficiency comparison of the buck topology: (a) CV mode; (b) CC mode.
5.2. Boost Topology
Figure 10 shows the power efficiency of the boost topology. The proposed converter
shows the same power efficiency in the measured error range because it has the same
number of semiconductors and the same stress as the conventional converter.
 10 0 10 0 10 0
10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80
Input Voltage [VDC] Input Voltage [VDC] Input Voltage [VDC]

(b)
Appl. Sci. 2023, 13, 343 14 of 19
Figure 9. Power efficiency comparison of the buck topology: (a) CV mode; (b) CC mode.

5.2.5.2.
Boost Topology
Boost Topology
Figure
Figure1010shows
showsthe
the power efficiencyofofthe
power efficiency the boost
boost topology.
topology. TheThe proposed
proposed converter
converter
shows the same power efficiency in the measured error range because it
shows the same power efficiency in the measured error range because it has the same has the same
number ofofsemiconductors
number semiconductors and thesame
and the samestress
stress asas
thethe conventional
conventional converter.
converter.

Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop.

100 8 100 8 100 8

98 96.0 96.0 95.7 7 98 7 98 7
95.5 95.2 95.5 95.9 95.5 95.4 95.3
94.9 94.7 95.0 94.7 94.8 94.8 94.6 94.8 95.1 95.0 95.0 94.8 94.7

Efficiency Difference [%]

Efficiency Difference [%]

Efficiency Difference [%]

96 94.5 6 96 94.3 93.9 6 96 94.1 93.8 6

Power Efficiency [%]

Power Efficiency [%]

Power Efficiency [%]

93.4
92.9
94 95.8 95.9 95.8 95.5 5 94 95.9 95.6 95.6 5 94 5
95.3 94.9 95.4 95.1 94.8 95.0 95.0 94.9
94.8 94.8 94.7 94.5 94.6 94.6 94.3 94.5 94.9 94.5
92 4 92 93.9 4 92 94.0 93.7 4
93.3
92.9
90 3 90 3 90 3
88 2 88 2 88 2
86 0.04 0.19 0.15 0.05
1 86 0.20 0.15 0.19 0.07 0.04 1 86 0.25 0.18 0.11 0.13 0.02 0.04 0.06 1
0.01 0.01
84 0 84 0 84 0
-0.14 -0.04 -0.10 -0.01 -0.01-0.08-0.14 -0.01-0.03 -0.01-0.07-0.13
82 -1 82 -1 82 -1
80 -2 80 -2 80 -2
10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100
Appl. Sci. 2022, 12, x FOR PEER
Output REVIEW
Current [%] Output Current [%] Output Current [%] 15 of 20

(a)

Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop.

105 8 105 8 105 8

96.3 96.2 95.8 95.2 95.8 96.2 95.8 95.4
100 94.9 95.9 94.5 7 100 94.7 94.1 93.7
7 100 94.9 95.5 95.6 95.2 94.8 94.5 94.5 7

Efficiency Difference [%]

Efficiency Difference [%]

Efficiency Difference [%]

95 90.6 6 95 90.7 6 95 91.6 6

Power Efficiency [%]

Power Efficiency [%]

Power Efficiency [%]

95.9 96.3 96.3 95.8 95.5 95.9 96.0 96.2 95.4 95.9 95.8 95.2 95.2 95.0 95.0
90 94.6 94.4 5 90 94.5 94.2 93.9 5 90 94.7 5
90.5 91.4
85 90.1 4 85 4 85 4
80 3 80 3 80 3
75 2 75 2 75 2
70 0.46 0.33 1 70 0.28 0.19 1 70 1
0.03 0.10 0.19 0.02 0.19 0.19 0.01
65 0 65 0 65 0
-0.01 -0.07 -0.10 -0.11 -0.05 -0.26
60 -0.23 -1 60 -0.37 -1 60 -0.37 -0.23 -0.39 -0.47 -0.51 -1
55 -2 55 -2 55 -2
10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80
Input Voltage [VDC] Input Voltage [VDC] Input Voltage [VDC]

(b)
Figure 10.10.
Figure Power
Powerefficiency
efficiency comparison
comparison ofofthe
theboost
boost topology:
topology: (a) (a)
CV CV mode;
mode; (b)mode.
(b) CC CC mode.

5.3.5.3. Buck-Boost
Buck-boost Topology
Topology
5.3.1. Step-Down
5.3.1. Step-Down
Figure 11 shows the power efficiency in the step-down section of the buck-boost
Figurein
topology 11the
shows theCC
CV and power efficiency
modes. The powerin the step-down
efficiency sectioninof
is improved the buck-boost
every condition to-
pology in the CV and CC modes. The power efficiency is improved
because of the removal of D2 in the switch-off section. In the CV mode, the efficiencyin every condition
because of the removal
improvement of D2 in
becomes larger theanswitch-off
with increase insection.
the outputIn current;
the CV Pmode, the efficiency
Di f f increases in the im-
high-power
provement region. In
becomes the CC
larger mode,
with the powerin
an increase efficiency improves
the output with𝑃a𝐷𝑖𝑓𝑓
current; decrease in thein the
increases
input voltage,
high-power region. PDithe
and In f f increases
CC mode, in the
the low-power region. improves
power efficiency In the same withduty condition,in the
a decrease
the voltage stress of the diode D1 increases with the input voltage; PDi f f decreases with an
input voltage, and 𝑃𝐷𝑖𝑓𝑓 increases in the low-power region. In the same duty condition,
increase in loss.
the voltage stress of the diode D1 increases with the input voltage; 𝑃𝐷𝑖𝑓𝑓 decreases with
an increase in loss.

Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop.
 because of the removal of D2 in the switch-off section. In the CV mode, the efficiency im-
provement becomes larger with an increase in the output current; 𝑃𝐷𝑖𝑓𝑓 increases in the
high-power region. In the CC mode, the power efficiency improves with a decrease in the
input voltage, and 𝑃𝐷𝑖𝑓𝑓 increases in the low-power region. In the same duty condition,
Appl. Sci. 2023, 13, 343 15 of 19
the voltage stress of the diode D1 increases with the input voltage; 𝑃𝐷𝑖𝑓𝑓 decreases with
an increase in loss.

Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop.

94 8 94 8 94 8
90.7 90.8 90.9 90.6 90.4290.6290.7690.5790.29 90.5 90.7 90.5 90.3 90.1
92 89.7 90.1 89.7 7 92 89.8789.48 7 92 89.7 90.1
7
89.57 89.5
89.1 89.10

Efficiency Difference [%]

Efficiency Difference [%]

Efficiency Difference [%]

90 88.6 6 90 6 90 88.6 6
Power Efficiency [%]

Power Efficiency [%]

Power Efficiency [%]

86.489.6190.2089.9789.70 86.38 89.8 89.9 89.7 89.4 89.9 89.8
88 89.30
5 88 89.4 89.0
5 88
85.6 89.3 89.8 89.3 89.1 5
88.6588.24 88.6 88.5 88.9
88.0 88.3
86 87.62 4 86 87.5 4 86 4
86.98
86.43 86.3
84 3 84 3 84 85.5 3
1.43 1.48 1.49 1.57 1.58
1.19 1.30 1.30 1.50
82 2 82 1.07 1.15 1.26 2 82
0.93 1.14
1.23 1.24 1.23 2
0.82 0.62 0.69
80 0.52
1 80 1 80 0.40 0.37 0.59 1
0.11 0.05 0.21 0.08 0.14
78 0 78 0 78 0
-0.05
76 -1 76 -1 76 -1
74 -2 74 -2 74 -2
10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100
Appl. Sci. 2022, 12, x FOR PEER
Output REVIEW
Current [%] Output Current [%] Output Current [%] 16 of 20

(a)

Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop.

105 40 105 40 105 40

89.9 90.6 90.9 91.1 88.0 89.2 90.0
90.4 90.7
88.2 89.0 89.5
95 86.9 88.8 36 95 85.6 36 95 85.1 87.0 36
82.5 80.4 81.6

Efficiency Difference [%]

Efficiency Difference [%]

Efficiency Difference [%]

85 32 85 32 85 74.3 32
Power Efficiency [%]

Power Efficiency [%]

Power Efficiency [%]

87.4 87.8 88.0 88.9 89.6 90.2 87.6 88.5
75 68.2 85.1 86.5 28 75 85.7 87.7 28 75 84.7 86.4 28
81.9 64.2 82.4 63.9 81.9
75.8 77.2
65 24 65 75.0 24 65 24
66.9
55 20 55 20 55 20
52.4 51.7
58.1
45 16 45 16 45 12.20 16
11.80
10.07
35 12 35 12 35 12
6.65 7.40
25 4.95 8 25 5.44 8 25 8
3.64 3.39 3.18 3.06 3.04 4.43
3.19 3.19
2.28 1.51 2.31 1.86
15 4 15 1.11 0.82 0.51 4 15 1.43 1.02 4
5 0 5 0 5 0
10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80
Input Voltage [VDC] Input Voltage [VDC] Input Voltage [VDC]

(b)
Figure 11.11.
Figure Power
Powerefficiency
efficiency comparison ofthe
comparison of thebuck-boost
buck-boost topology
topology (step-down):
(step-down): (a)mode;
(a) CV CV mode;
(b) (b)
CCCCmode.
mode.

5.3.2.
5.3.2. Step-Up
Step-Up
Figure 12 shows the power efficiency of the step-up buck-boost topology in the CV
Figure 12 shows the power efficiency of the step-up buck-boost topology in the CV
and CC modes. In the CV mode, the efficiency improves in general to 10–80 W and
and CC increases
PDi ff
modes. In inthe
the CV mode, the
high-power efficiency
region where improves
the output in general
current to 10–80
increases. InW CC 𝑃𝐷𝑖𝑓𝑓
theand
increases
mode, PDi f f decreases with an increase in Vvar and the input voltage. The power efficiencymode,
in the high-power region where the output current increases. In the CC
𝑃𝐷𝑖𝑓𝑓 decreases
decreases morewith
than the increase in 𝑉
an conventional 𝑣𝑎𝑟 and at
converter the input of
a power voltage.
50 W orThe power
higher. In theefficiency
step-up de-
section,
creases the output
more than thevoltage increases with
conventional the input
converter at avoltage,
power andof 50the
Wvoltage stressIn
or higher. ofthe
diode
step-up
D also
section,
1 increases. The efficiency decreases more than the conventional converter
the output voltage increases with the input voltage, and the voltage stress of diode because
D1 the
alsoresulting diode
increases. Theloss exceeds the
efficiency increasemore
decreases in thethan
efficiency obtained by the
the conventional removalbecause
converter of
D2 in the switch-off section. Therefore, the proposed converter is suitable for applications
the resulting diode loss exceeds the increase in the efficiency obtained by the removal of
below 50 W in the step-up section of the buck-boost topology.
D2 in the switch-off section. Therefore, the proposed converter is suitable for applications
below 50 W in the step-up section of the buck-boost topology.

Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop.

96 10 96 10 96 10
90.6 90.6 90.0 90.2 90.3 89.7 90.3 89.9
89.5 89.3 88.8 88.9 88.9 89.1
92 88.4 9 92 87.8 9 92 87.8 9
87.3 86.6 86.5
86.2 85.5
[%]
[%]

[%]

88 85.1 8 88 8 88 85.1 8
83.9 84.2 83.8
%]

%]

%]

90.1 89.4 89.7 89.1 83.0 82.2

88.9 88.5 88.6 88.8 89.0
 𝑃𝐷𝑖𝑓𝑓 decreases with an increase in 𝑉𝑣𝑎𝑟 and the input voltage. The power efficiency de-
creases more than the conventional converter at a power of 50 W or higher. In the step-up
section, the output voltage increases with the input voltage, and the voltage stress of diode
D1 also increases. The efficiency decreases more than the conventional converter because
the resulting diode loss exceeds the increase in the efficiency obtained by the removal of
Appl. Sci. 2023, 13, 343 16 of 19
D2 in the switch-off section. Therefore, the proposed converter is suitable for applications
below 50 W in the step-up section of the buck-boost topology.

Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop.

96 10 96 10 96 10
90.6 90.6 90.0 90.2 90.3 89.7 90.3 89.9
89.5 89.3 88.8 88.9 88.9 89.1
92 88.4 9 92 87.8 9 92 87.8 9
87.3 86.6 86.5
86.2 85.5

Efficiency Difference [%]

Efficiency Difference [%]

Efficiency Difference [%]

88 85.1 8 88 8 88 85.1 8
83.9 84.2 83.8
Power Efficiency [%]

Power Efficiency [%]

Power Efficiency [%]

90.1 89.4 89.7 89.1 83.0 82.2
88.9 88.5 88.6 88.2 88.8 89.0 88.3
84 87.7 7 84 87.2 7 84 87.2 80.9 7
86.4 85.9 85.8
85.2 84.4 84.4
80 84.1 6 80 6 80 6
82.8 83.2 82.7
81.5 81.7 81.1
76 5 76 80.3 5 76 79.5 5
77.7
72 4 72 4 72 3.18 4
2.74 2.62 2.77
68 2.34 2.46 3 68 2.16 2.32
2.44 3 68 2.41 3
1.94 2.15 2.10 1.94 2.01 2.11
1.49 1.67 1.51 1.69 1.87 1.56
64 1.21 2 64 1.23 2 64 1.35 2
0.60 0.59 0.50
60 1 60 0.19 1 60 0.04
1
56 0 56 0 56 0
10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100
Appl. Sci. 2022, 12, x FOR PEER
Output REVIEW
Current [%] Output Current [%] Output Current [%] 17 of 20

(a)

Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop. Efficiency Diff. Conv. Prop.

100 27.0 100.0 27 100 27

90.0 90.7 91.0 91.2 91.1 91.1 90.1 90.9 91.1 91.1 90.9 90.8 90.1 90.8 90.9 90.8 90.4 90.2
94 87.6 24.0 94.0 88.0 24 94 88.3 24

Efficiency Difference [%]

Efficiency Difference [%]

Efficiency Difference [%]

88 21.0 88.0 21 88 21
81.0
Power Efficiency [%]

Power Efficiency [%]

Power Efficiency [%]

89.7 90.5 90.8
91.1 91.3 79.9 90.6 91.1 91.1 91.1 90.1 90.5 90.8 90.8 90.7
88.4 89.7
79.2 88.6
82 88.1 18.0 82.0 18 82 18
84.7 85.6
84.1
76 15.0 76.0 15 76 15
70 12.0 70.0 12 70 75.3 12
72.3 73.5
64 6.94 9.0 64.0 6.40 9 64 9
5.63
58 3.52 6.0 58.0 3.27 6 58 6
2.66
1.84 1.69 1.20 1.47
52 0.99 0.55 0.38 3.0 52.0 0.54 3 52 0.70 0.40 3
46 0.0 46.0 0 46 0
-0.02-0.24 -0.01 -0.25 -0.35 -0.03 -0.45 -0.51
40 -3.0 40.0 -3 40 -3
10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80
Input Voltage [VDC] Input Voltage [VDC] Input Voltage [VDC]

(b)
Figure 12.
Figure 12. Power
Powerefficiency
efficiencycomparison
comparisonofofthe buck-boost
the topology
buck-boost (step-up):
topology (a) (a)
(step-up): CV CV
mode; (b) CC
mode; (b)
mode.
CC mode.

5.3.3. Diode Stress (Buck-Boost Step-Up, CC Mode)

Figure
Figure 13 13shows
showsthe theanalytic
analyticand andexperimental
experimental diode
diode powerpower loss in the
loss CCCC
in the mode modein the
in
step-up section of the buck-boost topology. A positive power
the step-up section of the buck-boost topology. A positive power loss difference loss difference L implies
Di f𝐿f 𝐷𝑖𝑓𝑓 im-
that
pliesthe
thatdiode loss of
the diode lossthe
ofproposed
the proposed TSBB converter
TSBB converter is large,
is large,whereas
whereas if itifisit negative,
is negative, it
implies a large
it implies a largediode
diode loss of of
loss thethe
conventional
conventional TSBBTSBB converter.
converter.
To
To calculate
calculate thethe diode
diode loss,
loss, information
information on on several
several parameters
parameters was was referenced
referenced from from
the
the datasheet and all data are typical values at 25 degrees. Parameters not provided in the
datasheet and all data are typical values at 25 degrees. Parameters not provided in the
datasheet
datasheet were
were used
used to to calculate
calculate thethe diode
diode loss
loss with
with some
some assumptions.
assumptions.
•• Forward voltage V𝑉F𝐹:: obtained
Forward voltage obtained fromfrom thethe V
VFF-I characteristic curve.
-IF characteristic curve.
•• Equivalent resistance R : obtained from the V -I characteristic
Equivalent resistance 𝑅D𝐷 : obtained from the VFF-IFF characteristic curve curve by by linear
linear ap-
ap-
proximation
proximation under under the the current
current conditions
conditions usedused in in the
the experiment.
experiment.
•• Reverse
Reverse recovery
recovery time time T rr and
𝑇𝑟𝑟 and peak
peak reverse
reverse recovery current I𝐼rrm
recovery current : estimated and
𝑟𝑟𝑚 : estimated and
calculated using value 16 nsec at the forward current
calculated using value 16 nsec at the forward current 𝐼𝐹 = 1.0 A and the I F = 1.0 A and the reverse
reverse current
cur-
Irent
R = 0.5 A.
𝐼𝑅 = 0.5 A.  
dIF dI𝑑𝐼F𝐹/ dIF
•• Peak reverse recovery
Peak reverse recovery voltage assumed𝑑𝐼dI
voltage 𝑉Vrrm: :assumed 𝐹 = 0.5 at VR 1𝑑𝐼+𝐹 ⁄dI
R= 0.5 at 𝑉𝑅 (1 + ) dIand and
cor-
𝑟𝑟𝑚 𝑑𝐼𝑅 𝑑𝐼𝑅 𝑑𝐼R𝑅 R
corrected coefficient by temperature with VR characteristic curve.
rected coefficient by temperature with VR characteristic curve.
• Ignored any other parasitic factors like internal inductance, capacitance, and so on.
• Ignored any other parasitic factors like internal inductance, capacitance, and so on.
Due
Due to to several
several assumptions
assumptions and and uncertain
uncertain parameter
parameter values, the two
values, the two results
results areare
slightly
slightly different. This is expected to be due to the reverse recovery characteristics that
different. This is expected to be due to the reverse recovery characteristics that
change exponentially with the increase in temperature and voltage stress, and also to be
affected by parasitic components on the PCB and errors in measurement equipment.
Despite these differences, both results show a similar trend in which diode losses
rapidly increase with voltage stress over a certain region, thereby diode power loss of the
Appl. Sci. 2023, 13, 343 17 of 19

Appl. Sci. 2022, 12, x FOR PEER REVIEW 18 of 20

change exponentially with the increase in temperature and voltage stress, and also to be
affected by parasitic components on the PCB and errors in measurement equipment.

Analytic (Calculated) Experimental (Measured)

Conv. D1 Conv. D2 Prop. D1 (Prop. - Conv.) Conv. D1 Conv. D2 Prop. D1 Difference (Prop. - Conv.)

16 2 16 2

Power Loss Difference [W]

Power Loss Difference [W]

0.52
14 0.15 1 14 0.07 0.24 1
Power Loss [W]

Power Loss [W]

12 0 12 0
10 -0.35 -0.13 -1 10 -1
-0.55 -0.60 -0.51
-0.84 -0.85 -0.77
-1.09 -1.16 -1.10 -0.99
8 -2 8 -2
6 -3 6 -3
4.33
3.72 3.85
4 2.94 -4 4 3.31 7.68 -4
7.01 2.79 6.59
2.34 5.34 2.26
1.53 1.88 1.75 5.10
2 1.18 1.36 4.05 -5 2 1.30 3.93 -5
3.07 1.00 3.11
0.72 1.77 1.40 2.33 1.54 1.85 2.25 2.77 2.03 1.57 2.84 1.91 2.30 2.68
0 0.69 0.86 1.12 1.46 1.26 -6 0 1.01 0.92 1.14 1.29 1.37
-6
Conv. (D1+D2)
Prop. (D1)
Conv. (D1+D2)
Prop. (D1)
Conv. (D1+D2)
Prop. (D1)
Conv. (D1+D2)
Prop. (D1)
Conv. (D1+D2)
Prop. (D1)
Conv. (D1+D2)
Prop. (D1)
Conv. (D1+D2)
Prop. (D1)
Conv. (D1+D2)
Prop. (D1)

Conv. (D1+D2)
Prop. (D1)
Conv. (D1+D2)
Prop. (D1)
Conv. (D1+D2)
Prop. (D1)
Conv. (D1+D2)
Prop. (D1)
Conv. (D1+D2)
Prop. (D1)
Conv. (D1+D2)
Prop. (D1)
Conv. (D1+D2)
Prop. (D1)
Conv. (D1+D2)
Prop. (D1)
10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80
Input Voltage [VDC] Input Voltage [VDC]

(a)
Conv. D1 Conv. D2 Prop. D1 (Prop. - Conv.) Conv. D1 Conv. D2 Prop. D1 Difference (Prop. - Conv.)

16 1.05 2 16 1.22 2
0.89
Power Loss Difference [W]

Power Loss Difference [W]

14 0.33 1 14 0.23 1
Power Loss [W]

Power Loss [W]

12 0 12 0
10 -0.14 -1 10 -0.25 -0.23 -0.17 -1
-0.51 -0.55 -0.43 -0.54
-0.79 -0.70 -0.83
8 -2 8 -2
6 -3 6 5.43 -3
4.24 4.68 9.78
3.31 8.25 4.10 8.28
4 -4 4 3.45 -4
2.59 6.02 2.53 6.73
2.04 1.63 5.30
2 1.31 1.62 4.37 -5 2 4.00 -5
1.13 3.18 2.96 0.95 1.20 2.84 2.71 3.14
0.68 1.78 1.31 2.38 1.58 1.92 2.38 1.81 1.46 1.69 2.02 2.40
0 0.64 0.81 1.05 1.39 1.18 -6 0 0.93 1.06 1.15
-6
Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)
Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)
10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80
Input Voltage [VDC] Input Voltage [VDC]

(b)
Conv. D1 Conv. D2 Prop. D1 (Prop. - Conv.) Conv. D1 Conv. D2 Prop. D1 Difference (Prop. - Conv.)

16 2 16 1.15 2
0.95 0.82
Power Loss Difference [W]

Power Loss Difference [W]

14 1 14 0.33 1
0.04
Power Loss [W]

Power Loss [W]

12 0 12 0
-0.17 -0.01
10 -0.44 -0.34 -1 10 -0.53 -0.31 -1
-0.71 -0.65 -0.61 -0.56 -0.61
8 -2 8 -2
5.16
6 -3 6 4.52 -3
4.95 3.90 10.87
3.81 8.99 3.24 9.36
4 -4 4 2.54 7.68 -4
2.92 6.29 6.09
2.25 4.54 1.90 4.57 4.55
2 1.35 1.73 -5 2 1.33 3.45 4.02 -5
1.07 3.26 2.44 3.08 0.92 3.22 2.86
0.62 1.77 1.28 2.41 1.57 1.95 1.99 1.64 2.20
0 0.56 0.74 0.95 1.30 1.07 -6 0 0.88 1.19 1.18
-6
Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)

Prop. (D1)
Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

Conv. (D1+D2)

10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80
Input Voltage [VDC] Input Voltage [VDC]

(c)
Figure 13.
Figure 13. Analytic
Analytic and
and experimental
experimental diode
diode power
power loss
loss of
of the
the buck-boost
buck-boost topology
topology step-up
step-up period
period
in the CC mode: (a) Duty = 0.556, I O = 0.8 A; (b) Duty = 0.571, IO = 0.75 A; and (c) Duty = 0.600, IO =
in the CC mode: (a) Duty = 0.556, IO = 0.8 A; (b) Duty = 0.571, IO = 0.75 A; and (c) Duty = 0.600,
0.667 A.
IO = 0.667 A.

6. Conclusions
Despite these differences, both results show a similar trend in which diode losses
This
rapidly study proposed
increase a modified
with voltage design
stress over of theregion,
a certain TSBB thereby
converter to improve
diode power
power loss ef-
of the
ficiency using fewer conduction components and measured the optimal output power
range. The proposed TSBB converter improved power efficiency in buck and buck-boost
topologies by reducing the conduction loss caused by the diode in the switch-off section
Appl. Sci. 2023, 13, 343 18 of 19

proposed TSBB converter is bigger than the conventional converter over a certain input
voltage. The increase in the D1 loss of the proposed TSBB converter becomes larger than
the power efficiency improvement by the removal of D2 . The power efficiency is reversed
at the point where the difference in diode loss changes from negative to positive (+). For
the proposed TSBB converter, the power efficiency increases at 60 W or lower at the duty
ratio of 0.556; the power efficiency increases at 50 W or lower at the duty ratios of 0.571
and 0.600.

6. Conclusions
This study proposed a modified design of the TSBB converter to improve power effi-
ciency using fewer conduction components and measured the optimal output power range.
The proposed TSBB converter improved power efficiency in buck and buck-boost topolo-
gies by reducing the conduction loss caused by the diode in the switch-off section power
efficiency. A 100 W prototype was designed and fabricated to verify the improvement.
Experiments were conducted in the CV/CC modes of three topologies, and the power
efficiency was measured for 10–80 W. In the buck topology, power efficiency improved in
the entire power range of 10–80 W; it increased on average by 0.75–1.36% and 0.83–2.27%
in the CV and CC modes, respectively. In the buck-boost topology step-down, the power
efficiency improved in the entire power range of 10–80 W; it improved on average by
0.73–0.99% and 3.33–4.75% in the CV and CC modes, respectively. In the buck-boost topol-
ogy step-up, the power efficiency increased on average by 1.65–2.00% in the entire power
range of 10–80 W in the CV mode, and by 2.17–2.77% in the power range of the 10–50 W in
the CC mode.
In future research, we will study how to reduce the conduction and switching losses
by reducing the voltage and current stress of semiconductors for efficiency improvement.
In addition, we will analyze the effect on output ripple under various conditions by using
inductance, capacitance, and switching frequency as design variables, and study how these
parameters affect converter efficiency.

Author Contributions: Conceptualization, S.K. and H.J.; methodology, S.K. and H.J.; software, S.K.
and H.J.; validation, S.K. and H.J.; formal analysis, S.K. and H.J.; investigation, S.K. and H.J.; data
curation, S.K. and H.J.; writing—original draft preparation, S.K. and H.J.; writing—review and
editing, S.K. and H.J.; supervision, H.J. and S.-h.L.; project administration, H.J. and S.-h.L.; funding
acquisition, H.J. All authors have read and agreed to the published version of the manuscript.
Funding: This work is supported by the Korea Agency for Infrastructure Technology Advance-
ment (KAIA) grant funded by the Ministry of Land, Infrastructure and Transport (Grant RS-2021-
KA164174).
Informed Consent Statement: Informed consent was obtained from all subjects involved in the study.
Data Availability Statement: Data sharing not applicable.
Conflicts of Interest: The authors declare no conflict of interest.

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