21311A04H9

EXPERIMENT : 1 LOGIC GATES

AIM :
 To design all logic gates.
 To write the Verilog HDL code for the realization of logic gates circuits.
 To write the test bench and simulate the design in Xilinx ISE environment for
verifying its functionality.
 To synthesize the design, implement it on Artix7 FPGA kit and verify its
functionality.
Apparatus :
 Computer System
 Xilinx ISE Design Suite 23.2 Tool (ISE Simulator, XST)
 Artix7 FPGA Boards
Logic Diagram :
AND GATE : TRUTH TABLE

OR GATE: TRUTH TABLE

NOT GATE : TRUTH TABLE

NAND GATE : TRUTH TABLE

NOR GATE: TRUTH TABLE

EXOR GATE: TRUTH TABLE

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EXNOR GATE: TRUTH TABLE

Experimental Procedure :
1. Write a Verilog program for the design of Logic Gate Functionalities
2. Write the test bench program for the given design.
3. Simulate the design using Xilinx ISim Simulator and verify its functionality.
4. Synthesize the design using Xilinx XST tool.
5. Obtain the RTL schematic and Technology schematic diagrams.
6. Assign pin packages using PlanAhead as per given in the evaluation board
(Artix7 FPGA).
7. Create Timing constraints for the design.
8. Implement the design with the user constraints specified in step 6 and 7.
9. Properly connect the FPGA evaluation board to the PC.
10. Generate the FPGA bitmap file and configure the device using iMPACT tool.
11. Verify the functionality of the design in the FPGA Board.
Verilog Source Code:
module logicgates (x,y,A,B,C,D,E,F,G); // Starting of module //
input x,y; // Input variables //
output A,B,C,D,E,F,G; // Output variables //
assign A= ~x;
assign B= x&y;
assign C= x|y;
assign D= ~(x&y);
assign E= ~(x|y);
assign F= x^y;
assign G= ~(x^y);
endmodule // End of module //

Verilog Testbench Code:

module logicgates_tb;
reg x;reg y;
wire A;wire B;wire C;wire D;wire E;wire F;wire G;
logicgates uut (.x(x), .y(y), .A(A), .B(B), .C(C), .D(D), .E(E), .F(F), .G(G));
initial begin
#100 x = 0; y = 0;
#100 x = 0; y = 1;
#100 x = 1; y = 0;
#100 x = 1; y = 1;
end
endmodule

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RTL Schematic :

Technology Schematic

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Simulated Waveforms:

Synthesis Reports :
Final Report

Device utilization summary:

Result :
The design of a Logic gates circuit is obtained and simulated using Verilog HDL in
Xilinx ISE environment. The design is then synthesized, implemented Artix7 FPGA
kit and its functionality is verified.

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Experiment 2 : ADDER’S

Aim:

 To design Half adder, Full adder and parallel adder.

 To write the Verilog HDL code for the realization of Half adder, Full adder
and parallel adder.
 To write the testbench and simulate the design in Xilinx ISE environment for
verifying its functionality.
 To synthesize the design, implement it on Artix7 FPGA kit and verify its
functionality.
Apparatus:
 PC
 Xilinx ISE Design Suite 23.2 Tool (ISE Simulator, XST)
 Artix7 FPGA Boards
Logic Diagram :
HALF ADDER TRUTH TABLE
A B SUM CARRY

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

FULL ADDER TRUTH TABLE

A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Parallel Adder

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Experimental Procedure :
1. Write the Verilog source code for the design.
2. Write the testbench program for the given design.
3. Simulate the design using Xilinx ISim Simulator and verify its
functionality.
4. Synthesize the design using Xilinx XST tool.
5. Obtain the RTL schematic and Technology schematic diagrams.
6. Assign pin packages using PlanAhead as per given in the evaluation board
(Artix7 FPGA).
7. Create Timing constraints for the design.
8. Implement the design with the user constraints specified in step 6 and 7.
9. Properly connect the FPGA evaluation board to the PC.
10. Generate the FPGA bitmap file and configure the device using iMPACT
tool.
11. Verify the functionality of the design in the FPGA Board.
Verilog Source Code :
module hadder(A,B,S,C); // Starting of module //
input A,B; // Declaring Input
Variables //
output S,C; // Declaring Output
Variables //
assign S=(A^B); // Assigning the vales of logical
operations //
assign C=(A&B);

endmodule
Verilog Testbench Code :
module hadder_tb;
// Inputs
reg A;
reg B;
// Outputs
wire S;
wire C;
// instantiate the unit under test (uut)
ha uut (.a(a), .b(b), .s(s), .c(c));
initial
begin
// initialize inputs
#100 A=0; B=0;
#100 A=0; B=1;
#100 A=1; B=0;
#100 A=1; B=1;
end
end module

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Simulated Waveform :

RTL Schematic :

Tecchnology Schematic :

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Synthesis Report :
Final Report

Device utilization summary

Full Adder

Verilog Source Code :

module fadder(A,B,C,S,C0);
input A,B,C;
output S,C0;
assign C0=(A&B)|(B&C)|(C&A);
assign S=(A^B^C);
endmodule

Verilog Testbench code :

module fadder_tb;
//Inputs
reg A;
reg B;
reg C;
//Outputs

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Wire S;
Wire C0;
//instantiate the unit under test
fa uut (.a(a), .b(b), .s(s), .c0(c0));
initial
begin
// initialize inputs
#100 A=0;B=0;C=0;
#100 A=0;B=0;C=1;
#100 A=0;B=1;C=0;
#100 A=0;B=1;C=1;
#100 A=1;B=0;C=0;
#100 A=1;B=0;C=1;
#100 A=1;B=1;C=0;
#100 A=1;B=1;C=1;
end
endmodule

RTL Schematic :

Technology Schematic :

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Simulated Waveform :

Synthesis Report :
Final Report

Device utilization summary

PARALLEL ADDER :

Verilog Source Code :

module pa(
input[3:0]a,
input[3:0]b,
input[3:0]c,
output s,
output c0
);

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wire c0,c1,c2;
FA f1(a[0],b[0],c,s[0],c0);
FA f2(a[1],b[1],c,s[1],c1);
FA f3(a[2],b[2],c,s[2],c2);
FA f4(a[3],b[3],c,s[3],c3);
endmodule

Verilog Testbench Code :

module pa_tb;
reg [3:0] a;
reg [3:0] b;
reg cin;
wire cout;
wire [3:0] s;
padder uut (.a(a), .b(b), .cin(cin), .cout(cout), .s(s));
initial
begin
a [3:0]=4’b0000;b [3:0] = 4’b0000;cin = 1’b0;
#100 a[3:0]=4'b1011;b[3:0]=4'b1000;cin=1'b0;
end
endmodule

RTL Schematic :

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 21311A04H9

Technology Schematic :

Simulated Waveform :

Synthesis Report :
Final Report

Device utilization summary

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Result :
The design of half adder, full adder and parallel adder is obtained and simulated using
Verilog HDL in Xilinx ISE environment. The design is then synthesized,
implemented in Spartan3E FPGA kit and its functionality is verified.

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EXPERIMENT 3 : ENCODER AND DECODER

Aim :
 To design a 8*3 encoder and 3*8 decoder circuit.
 To write the Verilog HDL code for the realization of 8*3 encoder and 3*8
decoder circuits.
 To write the testbench and simulate the design in Xilinx ISE environment for
verifying its functionality.
 To synthesize the design, implement it on Spartan3 FPGA kit and verify its
functionality.
Apparatus :
 PC
 Xilinx ISE Design Suite 23.2 Tool (ISE Simulator, XST)
 Artix 7E FPGA Boards
Logic Diagram :
Encoder

8 to3
encoder

Decoder

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 21311A04H9

Encoder Truth Table:

Decoder Truth Table :

Experimental Procedure :
1. Write the Verilog source code for the design.
2. Write the testbench program for the given design.
3. Simulate the design using Xilinx ISim Simulator and verify its
functionality.
4. Synthesize the design using Xilinx XST tool.
5. Obtain the RTL schematic and Technology schematic diagrams.
6. Assign pin packages using PlanAhead as per given in the evaluation
board (Artix 7 FPGA).
7. Create Timing constraints for the design.
8. Implement the design with the user constraints specified in step 6 and 7.
9. Properly connect the FPGA evaluation board to the PC.
10. Generate the FPGA bitmap file and configure the device using iMPACT
tool.
11. Verify the functionality of the design in the FPGA Board.

Verilog Source Code :

Encoder
module encoder(a,b,c,d,e,f,g,h,x,y,z);
input a,b,c,d,e,f,g,h;
output x,y,z;
assign x=(e|f|g|h);
assign y=(c|d|g|h);

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assign z=(b|d|f|h);

endmodule

Verilog Testbench Code :

Encoder
module encoder_tb;
reg a;reg b;reg c;reg d;reg e;reg f;reg g;reg h;
wire x;wire y;wire z;
encoder uut (.a(a), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g), .h(h), .x(x), .y(y), .z(z));
initial
begin
#100 a = 0;b = 0;c = 0;d = 0;e = 0;f = 0;g = 0;h = 0;
#100 a = 1;b = 0;c = 0;d = 0;e = 0;f = 0;g = 0;h = 0;
#100 a = 0;b = 1;c = 0;d = 0;e = 0;f = 0;g = 0;h = 0;
#100 a = 0;b = 0;c = 1;d = 0;e = 0;f = 0;g = 0;h = 0;
#100 a = 0;b = 0;c = 0;d = 1;e = 0;f = 0;g = 0;h = 0;
#100 a = 0;b = 0;c = 0;d = 0;e = 1;f = 0;g = 0;h = 0;
#100 a = 0;b = 0;c = 0;d = 0;e = 0;f = 1;g = 0;h = 0;
#100 a = 0;b = 0;c = 0;d = 0;e = 0;f = 0;g = 1;h = 0;
#100 a = 0;b = 0;c = 0;d = 0;e = 0;f = 0;g = 0;h = 1;
end
endmodule

RTL Schematic :
Encoder

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 21311A04H9

Technology Schematic :

Simulated Waveform :

Synthesis Reports :
Final Report

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 21311A04H9

Device utilization summary

Verilog Source Code :

Decoder
module decoder(a,b,c,d,e,f,g,h,x,y,z);
input x,y,z;
output a,b,c,d,e,f,g,h;
assign a=(~x)&(~y)&(~z);
assign b=(~x)&(~y)&(z);
assign c=(~x)&(y)&(~z);
assign d=(~x)&(y)&(z);
assign e=(x)&(~y)&(~z);
assign f=(x)&(~y)&(z);
assign g=(x)&(y)&(~z);
assign h=(x)&(y)&(z);

endmodule

Verilog Testbench Code :

module decoder_tb;
reg x; reg y; reg z;
wire a; wire b; wire c; wire d; wire e; wire f; wire g; wire h;
decoder uut (.a(a), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g), .h(h), .x(x), .y(y), .z(z));
initial begin
#100 x=0;y=0;z=0;
#100 x=0;y=0;z=1;
#100 x=0;y=1;z=0;
#100 x=0;y=1;z=1;
#100 x=1;y=0;z=0;
#100 x=1;y=0;z=1;

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#100 x=1;y=1;z=0;
#100 x=1;y=1;z=1;
end

endmodule

RTL Schematic :

Technology Schematic :

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 21311A04H9

Simulated Waveform:

Synthesis Report :

Final report

Device Utilization Summary

Result :
The design of a encoder and decoder circuit is obtained and simulated using Verilog
HDL in Xilinx ISE environment. The design is then synthesized, implemented in
Spartan3 FPGA kit and its functionality is verified.

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 21311A04H9

EXPERIMENT : 4 MULTIPLEXER AND DEMULTIPLEXER

Aim :
 To design a 8X1 multiplexer and 1X8 demultiplexer circuit.
 To write the Verilog HDL code for the realization of 8X1 multiplexer and 1X8
demultiplexer circuit .
 To write the test bench and simulate the design in Xilinx ISE environment for
verifying its functionality.
 To synthesize the design, implement it on Spartan3 FPGA kit and verify its
functionality.
Apparatus :
 PC
 Xilinx ISE Design Suite 23.2 Tool (ISE Simulator, XST)
 Artix 7E FPGA Boards

Logic Diagram and Truth Table :

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Experimental Procedure :

1.Write the Verilog source code for the design.

2.Write the test bench program for the given design.
3.Simulate the design using Xilinx ISim Simulator and verify its functionality.
4.Synthesize the design using Xilinx XST tool.
5.Obtain the RTL schematic and Technology schematic diagrams.
6.Assign pin packages using Plan Ahead as per given in the evaluation board
(Artix 7 FPGA).
7.Create Timing constraints for the design.
8.Implement the design with the user constraints specified in step 6 and 7.
9.Properly connect the FPGA evaluation board to the PC.
10.Generate the FPGA bitmap file and configure the device using iMPACT tool.
11.Verify the functionality of the design in the FPGA Board.

8x1 Multiplexer

Verilog source code :

module M8X1(input a, b, c, d, e, f, g, h, x, y,z,
output out );
assign
out=((~x)&(~y)&(~z)&a)|((~x)&(~y)&(z)&b)|((~x)&(y)&(~z)&c)|((~x)&(y)&(z)&d)
|((x)&(~y)&(~z)&e)|((~x)&(y)&(~z)&f)|((x)&(y)&(~z))&g|((x)&(y)&(z)&h);
endmodule

Verilog Testbench Code:

module demux18(
input i, x, y, z,
output a, b, c, d, e, f, g, h);
assign a=(~x)&(~y)&(~z)&i;

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assign b=(~x)&(~y)&(z)&i;
assign c=(~x)&(y)&(~z)&i;
assign d=(~x)&(y)&(z)&i;
assign e=(x)&(~y)&(~z)&i;
assign f=(x)&(~y)&(z)&i;
assign g=(x)&(y)&(~z)&i;
assign h=(x)&(y)&(z)&i;
endmodule
RTL Schematic :

Technology Schematic :

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 21311A04H9

Simulated Waveform :

Sythensis Report :

Final Report

Device utilization summary

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 21311A04H9

1x8 Demultiplexer :

Verilog Source Code :

module demux18(
input i, x, y, z,
output a, b, c, d, e, f, g, h);
assign a=(~x)&(~y)&(~z)&i;
assign b=(~x)&(~y)&(z)&i;
assign c=(~x)&(y)&(~z)&i;
assign d=(~x)&(y)&(z)&i;
assign e=(x)&(~y)&(~z)&i;
assign f=(x)&(~y)&(z)&i;
assign g=(x)&(y)&(~z)&i;
assign h=(x)&(y)&(z)&i;
endmodule

Verilog Testbench Code :

module demux18_tb;
reg i; reg x; reg y; reg z;
wire a; wire b; wire c; wire d; wire e; wire f; wire g; wire h;
demux18 uut (.i(i),.x(x),.y(y),.z(z),.a(a),.b(b),.c(c), .d(d),.e(e),.f(f),.g(g),.h(h));
initial begin
i = 1;
x = 0; y = 0; z = 0;
#100; x = 0; y = 0; z = 1;
#100; x = 0; y = 1; z = 0;
#100; x = 0; y = 1; z = 1;
#100; x = 1; y = 0; z = 0;
#100; x = 1; y = 0; z = 1;
#100; x = 1; y = 1; z = 0;
#100; x = 1; y = 1; z = 1;
end
endmodule
RTL Schematic :

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 21311A04H9

Technology Schematic :

Simulated Waveform :

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 21311A04H9

Synthesis Report
Final Report

Device utilization summary

Result :
 The design of a 8X1 multiplexer and 1X8 demultiplexer circuit is obtained and
simulated using Verilog HDL in Xilinx ISE environment. The design is then
synthesized, implemented in Spartan3 FPGA kit and its functionality is
verified.

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 21311A04H9

EXPERIMENT : 5a D FLIP FLOP

Aim :
 To design a D flip-flop circuit.
 To write the Verilog HDL code for the realization of D flip-flop circuit .
 To write the testbench and simulate the design in Xilinx ISE environment for
verifying its functionality.
 To synthesize the design, implement it on Atrix7 FPGA kit and verify its
functionality.
Apparatus :
 PC
 Xilinx ISE Design Suite 23.2 Tool (ISE Simulator, XST)
 Atrix 7 FPGA (Bayes) Boards
Logic Diagram :

Truth Table :
CLK D Q

0 X LAST STATE

1 0 0

1 1 1

Experimental Procedure :
1. Write the Verilog source code for the design.
2. Write the testbench program for the given design.
3. Simulate the design using Xilinx ISim Simulator and verify its functionality.
4. Synthesize the design using Xilinx XST tool.
5. Obtain the RTL schematic and Technology schematic diagrams.
6. Assign pin packages using PlanAhead as per given in the evaluation board (Artix 7
FPGA).
7. Create Timing constraints for the design.
8. Implement the design with the user constraints specified in step 6 and 7.
9. Properly connect the FPGA evaluation board to the PC.
10. Generate the FPGA bitmap file and configure the device using iMPACT tool.
11. Verify the functionality of the design in the FPGA Board.

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Verilog Source Code :

module dff(
input d,
input clk,
input rst,
output reg q
);
always @ (posedge clk)
if (~rst) begin
q<=1'b0;
end else begin
q<=d;
end
endmodule
Verilog Testbench Code :

module dff_tb;
reg d;
reg clk;
reg rst;
wire q;
dff_tb uut (.d(d), .clk(clk), .rst(rst), .q(q));
initial begin
d=0;clk=0;rst=0;
forever
#50 clk=~clk;
end
initial begin
#100 d = 0;rst = 0;
#100 d = 1;rst = 0;
#100 d = 0;rst = 1;
#100 d = 1;rst = 0;
end
endmodule

RTL Schematic :

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 21311A04H9

Technology Schematic :

Simulated Waveform :

Synthesis Report
Final Report

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 21311A04H9

Device utilization summary

Result:
The design of a D flip-flop circuit is obtained and simulated using Verilog HDL in
Xilinx ISE environment. The design is then synthesized, implemented in Atrix 7
FPGA kit and its functionality is verified.

EXPERIMENT : 5b T Flip Flop

Aim :
 To design a Tflip-flop circuit.
 To write the Verilog HDL code for the realization of T flip-flop circuit .
 To write the testbench and simulate the design in Xilinx ISE environment for
verifying its functionality.
 To synthesize the design, implement it on Atrix7 FPGA kit and verify its
functionality.
Apparatus :
 PC
 Xilinx ISE Design Suite 23.2 Tool (ISE Simulator, XST)
 Atrix 7 FPGA (Bayes) Boards
Logic Diagram :

Truth Table :

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 21311A04H9

Experimental Procedure :
1.Write the Verilog source code for the design.
2. Write the testbench program for the given design.
3. Simulate the design using Xilinx ISim Simulator and verify its functionality.
4.Synthesize the design using Xilinx XST tool.
5.Obtain the RTL schematic and Technology schematic diagrams.
6. Assign pin packages using PlanAhead as per given in the evaluation board (Artix 7
FPGA).
7.Create Timing constraints for the design.
8.Implement the design with the user constraints specified in step 6 and 7.
9.Properly connect the FPGA evaluation board to the PC.
10.Generate the FPGA bitmap file and configure the device using iMPACT tool.
11.Verify the functionality of the design in the FPGA Board.
Verilog Source Code :
module t_ff(
input t,
input clk,
input rst,
output reg q
);
always @ (posedge clk)
if (~rst) begin
q <= 1'b0;
end else if (t) begin
q <= !q;
ends
endmodule

Verilog Testbench Code :

module t_ff_tb;
reg t;
reg clk;
reg rst;
wire q;
t_ff uut (.t(t),.clk(clk),.rst(rst),.q(q));
initial begin
t = 0;clk = 0;rst = 0;
forever
#50 clk=~clk;
end
initial begin
t = 1;rst = 0;#100
t = 0;rst = 1;#100
t = 0;rst = 0;#100
t = 1;rst = 1;#100
#100;
end
endmodule

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RTL Schematic :

Technology Schematic :

Simulated Waveforms :

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Synthesis Reports :
Final report

Device utilization summary

Result :
The design of a T flip-flop circuit is obtained and simulated using Verilog in Xilinx
ISE environment. The design is then synthesized, implemented in Atrix7 FPGA kit
and its functionality is verified.

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EXPERIMENT : 5c JK Flip Flop

Aim :
 To design a JK flip-flop circuit.
 To write the Verilog HDL code for the realization of JKflip-flop circuit .
 To write the testbench and simulate the design in Xilinx ISE environment for
verifying its functionality.
 To synthesize the design, implement it on Atrix7 FPGA kit and verify its
functionality.
Apparatus :
 PC
 Xilinx ISE Design Suite 23.2 Tool (ISE Simulator, XST)
 Atrix 7 FPGA (Bayes) Boards
Logic Diagram :

Truth Table :

Experimental Procedure :

1. Write the Verilog source code for the design.

2. Write the testbench program for the given design.
3. Simulate the design using Xilinx ISim Simulator and verify its functionality.
4. Synthesize the design using Xilinx XST tool.
5. Obtain the RTL schematic and Technology schematic diagrams.
6.Assign pin packages using PlanAhead as per given in the evaluation board
(Artix 7 FPGA).
7.Create Timing constraints for the design.
8.Implement the design with the user constraints specified in step 6 and 7.
9.Properly connect the FPGA evaluation board to the PC.
10.Generate the FPGA bitmap file and configure the device using iMPACT tool.
12. Verify the functionality of the design in the FPGA Board.

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Verilog Source Code :

module jk_ff(
input [1:0] jk,
input clk,
input rst,
output reg q,qb
);
always @ ( posedge clk )
if (rst)
begin
q = 1'd1;
qb = ~q;
end
else
begin
case (jk)
2'd0 : q = q;
2'd1 : q = 1'd0;
2'd2 : q = 1'd1;
2'd3 : q = ~q;
endcase
qb = ~q;
end
endmodule

Verilog Testbench Code :

module jk_ff_tb;
reg [1:0] jk;
reg clk;
reg rst;
wire q;
wire qb;
jk_ff uut (.jk(jk),.clk(clk),.rst(rst),.q(q),.qb(qb));
initial begin
jk = 2'd0;clk = 0;rst = 1;
forever
#50 clk=~clk;
end
initial begin
#100 rst=0;jk = 2'd0;#100;
jk = 2'd1;#100;
jk = 2'd2;#100;
jk = 2'd3;#100;
end
endmodule

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RTL Schematic :

Technology Schematic :

Simulated Waveform :

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 21311A04H9

Synthesis Report :
Final Report

Device utilization summary

Result :
The design of a JK flip-flop circuit is obtained and simulated using Verilog HDL in
Xilinx ISE environment. The design is then synthesized, implemented in Spartan3
FPGA kit and its functionality is verified.

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EXPERIMENT : 5d SR Flip Flop

Aim :
 To design a SR flip-flop circuit.
 To write the Verilog HDL code for the realization of SR flip-flop circuit .
 To write the testbench and simulate the design in Xilinx ISE environment for
verifying its functionality.
 To synthesize the design, implement it on Atrix7 FPGA kit and verify its
functionality.
Apparatus :
 PC
 Xilinx ISE Design Suite 23.2 Tool (ISE Simulator, XST)
 Atrix 7 FPGA (Bayes) Boards
Logic Diagram :

Truth Table :

Experimental Procedure :
1. Write the Verilog source code for the design.
2. Write the testbench program for the given design.
3. Simulate the design using Xilinx ISim Simulator and verify its functionality.
4. Synthesize the design using Xilinx XST tool.
5. Obtain the RTL schematic and Technology schematic diagrams.
6. Assign pin packages using PlanAhead as per given in the evaluation board (Artix
7 FPGA).
7. Create Timing constraints for the design.
8. Implement the design with the user constraints specified in step 6 and 7.
9. Properly connect the FPGA evaluation board to the PC.
10. Generate the FPGA bitmap file and configure the device using iMPACT tool.
11.Verify the functionality of the design in the FPGA Board.

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Verilog Source Code :

module rs_ff(
input [1:0] rs,
input clk,rst,
output reg q,qb
);
always @ ( posedge clk)
if (rst)
begin
q = 1'b0;
qb = ~q;
end

Verilog Testbench Code :

module sr_ff_tb;
reg [1:0] rs;
reg clk;
reg rst;
wire q;
wire qb;
rs_ff uut (.rs(rs),.clk(clk),.rst(rst),.q(q),.qb(qb));
initial begin
rs = 2'd0;clk = 0;rst = 1;
#50 clk=~clk;
end
initial begin
#100 rst=0;rs = 2'd0;#100;
rs = 2'd1;#100;
rs = 2'd2;#100;
rs = 2'd3;#100;
end
endmodule
RTLSchematic :

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Technology Schematic :

Simulated Waveform :

Synthesis Report :
Final Report

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Device utilization summary

Result :
The design of a RS flip-flop circuit is obtained and simulated using Verilog HDL in
Xilinx ISE environment. The design is then synthesized, implemented in Artix
7FPGA kit and its functionality is verified.

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EXPERIMENT : 6a BINARY COUNTER

Aim :
 To design a binary counter circuit.
 To write the Verilog HDL code for the realization of Binary counter circuit .
 To write the testbench and simulate the design in Xilinx ISE environment for
verifying its functionality.
 To synthesize the design, implement it on Atrix7 FPGA kit and verify its
functionality.
Apparatus :
 PC
 Xilinx ISE Design Suite 23.2Tool (ISE Simulator, XST)
 Atrix 7 FPGA (Bayes) Boards
Logic Diagram :

Experimental Procedure :
1. Write the Verilog source code for the design.
2. Write the testbench program for the given design.
3. Simulate the design using Xilinx ISim Simulator and verify its functionality.
4. Synthesize the design using Xilinx XST tool.
5. Obtain the RTL schematic and Technology schematic diagrams.
6. Assign pin packages using PlanAhead as per given in the evaluation board
(Artix 7 FPGA).
7. Create Timing constraints for the design.
8. Implement the design with the user constraints specified in step 6 and 7.
9. Properly connect the FPGA evaluation board to the PC.
10. Generate the FPGA bitmap file and configure the device using iMPACT
tool.
11. Verify the functionality of the design in the FPGA Board.

Verilog Source Code :

module binarycounter(
input clk,rst,
output reg[7:0] bin_out
);

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always@ (posedge clk)

begin
if (rst)
bin_out<=8'b00000000;
else
bin_out<=bin_out+8'b00000001;
end
Endmodule

Verilog Testbench Code :

module binarycounter_tb;
// Inputs
reg clk;
reg rst;
// Outputs
wire [7:0] bin_out;
// Instantiate the Unit Under Test (UUT)
binarycounter uut (.clk(clk), .rst (rst), .bin_out (bin_out));
initial begin
clk=0;
// Initialize Inputs
forever begin #10 ;clk=~clk;
end
end
initial begin rst=1;
#100 rst=0;
end
endmodule

RTLSchematic :

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 21311A04H9

Technology Schematic :

Simulated Waveform :

Synthesis Report :
Final Report

45
 21311A04H9

Device utilization summary

Result :
The design of a RS flip-flop circuit is obtained and simulated using Verilog HDL in
Xilinx ISE environment. The design is then synthesized, implemented in Artix
7FPGA kit and its functionality is verified.

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EXPERIMENT : 6b UPDOWN COUNTER

Aim :
 To design a updown counter circuit.
 To write the Verilog HDL code for the realization of updown counter circuit .
 To write the testbench and simulate the design in Xilinx ISE environment for
verifying its functionality.
 To synthesize the design, implement it on Atrix7 FPGA kit and verify its
functionality.
Apparatus :
 PC
 Xilinx ISE Design Suite Tool (ISE Simulator, XST)
 Atrix 7 FPGA (Bayes) Boards
Logic Diagram :

Experimental Procedure :
12. Write the Verilog source code for the design.
13. Write the testbench program for the given design.
14. Simulate the design using Xilinx ISim Simulator and verify its
functionality.
15. Synthesize the design using Xilinx XST tool.
16. Obtain the RTL schematic and Technology schematic diagrams.
17. Assign pin packages using PlanAhead as per given in the evaluation board
(Artix 7 FPGA).
18. Create Timing constraints for the design.
19. Implement the design with the user constraints specified in step 6 and 7.
20. Properly connect the FPGA evaluation board to the PC.
21. Generate the FPGA bitmap file and configure the device using iMPACT
tool.
22. Verify the functionality of the design in the FPGA Board.

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Verilog Source Code :

module updowncounter(
input updown, clk, rst,
output reg [7:0] out
);
//-------------Code Starts Here----
always @ (posedge clk)
if (rst) begin // active high reset
out <= 8'b0;
end else if (updown) begin
out <= out + 1;
end else begin
out <= out-1;
end
endmodule

Verilog Testbench Code :

module updc_tb;
// Inputs
reg updown;
reg clk;
reg rst;
// Outputs
wire [7:0] out;
// Instantiate the Unit Under Test (UUT)
updowncounter uut (.updown(updown),.c1k(c1k) ,.rst(rst),.out(out));
initial begin
clk=0;
forever begin
#10;
clk=~clk;
end
end
initial begin
updown = 1;rst = 1;#100;
updown = 1;rst=0;#300;
updown = 0;rst=0;#500;
updown = 1;
end
endmodule

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RTLSchematic :

Technology Schematic :

Simulated Waveform :

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 21311A04H9

Synthesis Report :
Final Report

Device utilization summary

Result :
The design of a updown counter circuit is obtained and simulated using Verilog HDL
in Xilinx ISE environment. The design is then synthesized, implemented in Artix
7FPGA kit and its functionality is verified.

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