DIGITAL ELECTRONICS LAB MANUAL

FOR

III SEMESTER B.E (E & C)

(For private circulation only)

VISHVESHWARAIAH TECHNOLOGICAL UNIVERSITY

NAME……………………………………………

REG NO…………………………………………

BATCH…………………………………………..

DEPARTMENT OF ELECTRONICS & COMMUNICATION

SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY
MARLUR, TUMKUR-572105
 DIGITAL ELECTRONICS LAB
DO’S DON’ TS
1. Be regular to the lab.
1. Do not exceed the voltage Rating.
2. Follow proper Dress Code.
2. Do not inter change the IC’s while
3. Maintain Silence. doing the experiment.

4. Know the theory behind the experiment 3. Avoid loose connections and short
before coming to the lab. circuits.
5. Identify the different leads or terminals 4. Do not throw the connecting wires to
or pins of the IC before making floor.
connection.
5. Do not come late to the lab.
6. Know the Biasing Voltage required for
different families of IC’s and connect the 6. Do not operate p/IC trainer kits
power supply voltage and ground unnecessarily.
terminals to the respective pins of the
IC’s. 7. Do not panic if you don’t get the
output.
7. Know the Current and Voltage rating of
the IC’s before using them in the
experiment.

8. Avoid unnecessary talking while doing

the experiment.

9. Handle the IC Trainer Kit properly.

10. Mount the IC Properly on the IC Zif

Socket.

11. Handle the microprocessor kit properly.

12. While doing the Interfacing, connect

proper voltages to the interfacing kit.

13. Keep the Table clean.

14. Take a signature of the In charge before

taking the kit/components.

15. After the completion of the experiments

switch off the power supply and return
the apparatus.

16. Arrange the chairs/stools and equipment

properly before leaving the lab.
 CONTENTS

Experiment No Page. No

1. Verification of Gates 2

2. Half/Full Adder/Subtractor 6

3. Parallel Adder/Subtractor 10

4. Excess-3 to BCD & Vice Versa 12

5. Binary-Grey & Grey-Binary Converter 16

6. MUX/DEMUX 20

7. MUX/DEMUX using only NAND Gates 26

8. Comparators 28

9. Encoder/Decoder 32

10. Flip-Flops 36

11. Counters 38

12. Shift Registers 44

13. Johnson/Ring Counters 48

14. Sequence Generator 50

15. Multivibrators 52

16. Static RAM 56

17. Question Bank 57

Digital Electronics Lab SSIT

Inverter Gate (NOT Gate)  7404LS

Y1 Y2 Y3 Y4 Y5 Y6
A O/P
(V) (V) (V) (V) (V) (v)
0 1

1 0

2-Input AND Gate  7408LS

A B O/P Y1 Y2 Y3 Y4
(V) (V) (V) (V)
0 0 0
0 1 0
1 0 0
1 1 1

2-Input OR Gate  7432LS

Y1 Y2 Y3 Y4
A B O/P
(V) (V) (V) (V)
0 0 0
0 1 0
1 0 0
1 1 1

2-Input NAND Gate  7400LS

A B O/P Y1 Y2 Y3 Y4
(V) (V) (V) (V)
0 0 1
0 1 0
1 0 0
1 1 0

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Digital Electronics Lab SSIT

Experiment No: Date: / /

VERIFICATION OF GATES

Aim: - To study and verify the truth table of logic gates

Apparatus Required: -
All the basic gates mention in the fig.

Procedure: -

1. Place the IC on IC Trainer Kit.

2. Connect VCC and ground to respective pins of IC Trainer Kit.

3. Connect the inputs to the input swit ches provided in the IC Trainer

Kit.

4. Connect the outputs to the switches of O/P LEDs,

5. Apply various combinations of inputs according to the truth table and

observe condition of LEDs.

6. Disconnect output from the LEDs and note down the corresponding

multimeter voltage readings for various combinations of inputs.

2-Input NOR Gate  7402LS

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 Digital Electronics Lab SSIT

Y1 Y2 Y3 Y4
A B O/P
(V) (V) (V) (V)

0 0 1
0 1 0
1 0 0
1 1 0

2- Input EX-OR Gate  7486LS

Y1 Y2 Y3 Y4
A B O/P
(V) (V) (V) (V)
0 0 0
0 1 1
1 0 1
1 1 0

3- Input NAND Gate  7410LS

2-Input NAND Gate  CD4011

Y1 Y2 Y3
A B C O/P
(V) (V) (V)
Y1 Y2 Y3 Y4
A0 B0 O/P
0 1
0 0 1 1(V) (V) (V) (V)
00 01 01 1
00 11 11 1
11 00 01 1
1 0 1 1
1 1 0
1 1 0 1
1 1 1 0

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Digital Electronics Lab SSIT

2-Input NOR Gate  CD4001

Y1 Y2 Y3 Y4
A B O/P
(V) (V) (V) (V)
0 0 1
0 1 0
1 0 0
1 1 0

4-Input NAND Gate  7420LS

Y1 Y2 Y3
A B C D O/P
(V) (V) (V)
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

Conclusion:-

…………………………….
Signature of the staff

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Digital Electronics SSI

Half Adder using basic gates:-

S  AB  AB

SAB

C  AB
Full Adder using basic gates:-

Half Adder using NAND gates only:-

Full Adder using NAND gates only:-

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Digital Electronics SSI

Experiment No: Date: / /

HALF/FULL ADDER & HALF/FULL SUBTRACTOR

Aim: - To realize half/full adder and half/full subtractor.

i. Using X-OR and basic gates

ii. Using only nand gates.

Apparatus Required: -

IC 7486, IC 7432, IC 74 08, IC 7400, etc.

Procedure: -

1. Verify the gates.

2. Make the connections as per the circuit diagram.

3. Switch on VCC and apply various combinations of input according to the

truth table.

4. Note down the output readings fo r half/full adder and half/full

subtractor sum/difference and the carry/borrow bit for different
combinations of inputs.

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Digital Electronics SSI

Using X – OR and Basic Gates (a)Half Subtractor

Full Subtractor

(ii) Using only NAND gates (a) Half subtractor

(b) Full Subtractor

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Digital Electronics SSI

Half Adder Half Subtractor

A B S C S(V) C(V) A B D B D(V) B(V)
0 0 0 0 0 0 0
0 1 1 0 0 1 1 1
1 0 1 0 1 0 1 0
1 1 0 1 1 1 0 0
Full Adder Full Subtractor
A B Cn-1 S C S(V) C(V) A B Cn-1 D B D(v) B(v)
0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 1 1
0 1 0 1 0 0 1 0 1 1
0 1 1 0 1 0 1 1 0 1
1 0 0 1 0 1 0 0 1 0
1 0 1 0 1 1 0 1 0 0
1 1 0 0 1 1 1 0 0 0
1 1 1 1 1 1 1 1 1 1

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Digital Electronics SSI

Conclusion: -

…………………………………………..
Signature of the staff in charge

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Digital Electronics SSI

Pin Detail: -

7483

Adder : -

Truth Table: -

A3 A2 A1 A0 B3 B2 B1 B0 C4 (V) S3(V) S2(V) S1(V) S0(V)

0 0 0 1 0 0 1 0 0 0 0 1 1
0 1 0 1 1 0 1 1 1 1 0 0 0
1 0 1 0 1 0 1 0 1 0 1 0 0
1 1 1 1 1 1 1 1 1 1 1 1 0
0 1 1 1 0 0 1 1 0 1 0 1 0

Subtractor:-

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Digital Electronics SSI

Experiment No: Date: / /

PARALLEL ADDER AND SUBTRACTOR USING 7483

Aim: - To realize IC7483 as parallel adder / Subtractor.

Apparatus Required: -

IC 7483, IC 7404, etc.

Procedure: -

1. Apply the inputs to A0 to A3 and B0 to B3.

2. Connect C0 to the Ground.

3. Check the output sum on the S0 to S3 and also C4.

4. For subtraction connect C0 to Vcc, Apply the B input through NOT

gate, which gives the complement of B.

5. The truth table of adder and Subtractor are noted down.

Truth Table for Subtractor

A3 A2 A1 A0 B3 B2 B1 B0 C4(V) S3(V) S2(V) S1(V) S0(V)

0 0 1 0 0 0 0 1 1 0 0 0 1
0 1 0 1 0 0 1 1 1 0 0 1 0
0 0 1 1 0 1 0 1 0 1 1 1 0

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Digital Electronics SSI

1 0 1 0 0 1 1 0 1 0 1 0 0
1 0 0 0 1 1 1 1 0 1 0 0 1

Conclusion: -

…………………………….
Signature of the staff

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Digital Electronics SSI

BCD To Excess-3

Truth Table For Code Conversion: -

Inputs Outputs
B3 B2 B1 B0 E3 (v) E2 (v) E1 (v) E0 (v)
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

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Digital Electronics SSI

Experiment No: Date: / /

BCD to Excess 3 AND Excess 3 to BCD

Aim: - To verify BCD to excess –3 code conv ersion using NAND gates. To study

and verify the truth table of excess-3 to BCD code converter

Apparatus Required: -
IC 7400, IC 7404, etc.

Procedure: - (BCD Excess 3 and Vice Versa)

1. Make the connections as shown in the fig.
2. Pin [14] of all IC’S are connected to +5V and pin [7] to the ground.
3. The inputs are applied at E3, E2, E1, and E0 and the corresponding
outputs at B3, B2, B1, and B0 ar e taken for excess – 3 to BCD.
4. B3, B2, B1, and B0 are the inputs an d the corresponding outputs are E3,
E2, E1 and E0 for BCD to excess – 3.
5. Repeat the same procedure for other combinations of inputs.
6. Truth table is written.

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Digital Electronics SSI

Excess-3 To BCD :-

Truth Table For Code Conversion: -

Inputs Outputs
E3 E2 E1 E0 B3 (v) B2 (v) B1 (v) B0(v)
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

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Digital Electronics SSI

Exercise: -

1. Obtain the expression for E3, E2, E1 and E0

2. Obtain the expression for B3, B2, B1 and B0

Conclusion: -

……………………….………………….
Signature of the staff-in charge

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Digital Electronics SSI

Circuit Diagram: -

Binary To Gray Gray To Binary

Truth Table For Both: -

Inputs Outputs
B3 B2 B1 B0 G3 (V) G2 (V) G1 (V) G0 (V)
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

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Digital Electronics SSI

Experiment No: Date: / /

BINARY TO GRAY AND GRAY TO BINARY

CONVERSION
Aim: - To convert given binary numbers to gray codes.

Apparatus Required: -
IC 7486, etc

Procedure: -

1. The circuit connections are made as shown in fig.

2. Pin (14) is connected to +Vcc and Pin (7) to ground.

3. In the case of binary to gray conver sion, the inputs B0, B1, B2 and B3 are

given at respective pins and outputs G0, G1, G2, G3 are taken for all the

16 combinations of the input.

4. In the case of gray to binary conver sion, the inputs G0, G1, G2 and G3 are

given at respective pins and outputs B0, B1, B2, and B3 are taken for all

the 16 combinations of inputs.

5. The values of the outputs are tabulated.

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Using Nand Gates Only: -

Binary To Gray

Gray To Binary

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Truth Table For Both: -

Inputs Outputs
B3 B2 B1 B0 G3 (V) G2 (V) G1 (V) G0 (V)
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

Conclusion: -

…………………………………………..
Signature of the staff in charge

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Digital Electronics SSI

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Digital Electronics SSI

Pin Details: -

Truth Table: -

CHANNEL – A CHANNEL – B
INPUTS SELECT O/P INPUTS SELECT O/P
LINES LINES
Ēa Ioa I1a I2a I3a S1 S2 Za(v) Ēa Iob I1b I2b I3b S1 S2 Za(v)
1 X X X X X X 0 1 X X X X X X 0
0 0 X X X 0 0 0 0 0 X X X 0 0 0
0 1 X X X 0 0 1 0 1 X X X 0 0 1
0 X 0 X X 0 1 0 0 X 0 X X 0 1 0
0 X 1 X X 0 1 1 0 X 1 X X 0 1 1
0 X X 0 X 1 0 0 0 X X 0 X 1 0 0
0 X X 1 X 1 0 1 0 X X 1 X 1 0 1
0 X X X 0 1 1 0 0 X X X 0 1 1 0
0 X X X 1 1 1 1 0 X X X 1 1 1 1

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Digital Electronics SSI

Experiment No: Date: //

MUX/DEMUX USING 74153 & 74139

Aim: - To verify the truth table of multiplexer using 74153 & to verify a

demultiplexer using 74139. To study the arithmetic circuits half-adder half

Subtractor, full adder and full Subtractor using multiplexer.

Apparatus Required: -
IC 74153, IC 74139, IC 7404, etc.

Procedure: - (IC 74153)

1. The Pin [16] is connected to + Vcc.
2. Pin [8] is connected to ground.
3. The inputs are applied either to ‘A’ input or ‘B’ input.
4. If MUX ‘A’ has to be initialized, Ea is made low and if MUX ‘B’ has to be
initialized, Eb is made low.
5. Based on the selection lines one of the inputs will be selected at the output
and thus the truth table is verified.
6. In case of half adder using MUX, sum and carry is obtained by applying a
constant inputs at I0a, I1a, I 2a, I 3a and I 0b, I 1b, I 2b and I3b and the
corresponding values of select lines are changed as per table and the
output is taken at Z0a as sum and Z0b as carry.
7. In this case, the channels A and B are kept at constant inputs according to
the table and the inputs A and B are varied. Making Ea and Eb zero and
the output is taken at Za, and Zb.
8. In full adder using MUX, the input is applied at Cn-1, An and Bn.
According to the table corresponding outputs are taken at Cn and Dn.

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Digital Electronics SSI

Half Adder Using 74153 – Half Subtractor: -

Full Adder Using 74153: - Full Subtractor Using 74153: -

Truth Tables: - Same for both Subtractor and adder

Full Adder/subtractro
An Bn Cn-1 Sn/Dn (V) Cn/Bn (V)

Half adder/subtractor 0 0 0

A B Sn/Dn (V) Cn/Bn (V) 0 0 1

0 0 0 1 0

0 1 0 1 1

1 0 1 0 0

1 1 1 0 1
1 1 0
1 1 1

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Digital Electronics SSI

Pin Details: -

Truth Table For Demux: -

CHANNEL – A CHANNEL – B
Inputs Outputs Inputs Outputs
Procedure: - (IC 74139)
Ēa S1a S0a Y0a Y1a Y2a Y3a Ēb S1b S0b Y0b Y1b Y2b Y3b
1 1.X TheXinputs
1 are applied
1 1 to either
1 ‘a’1inputXor ‘b’Xinput1 1 1 1
0 2.0 The0demux
0 is activated
1 1 by making
1 0Ea low
0 and0 Eb low.
0 1 1 1
0 0 1 1 0 1 1 0 0 1 1 0 1 1
3. The truth table is verified.
0 1 0 1 1 0 1 0 1 0 1 1 0 1
0 1 1 1 1 1 0 0 1 1 1 1 1 0

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Digital Electronics SSI

Half adder

Half Adder
A B Sn (V) Cn (V)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Half subtractor:-

Half Subtractor
A B Dn (V) Bn (V)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Exercise:-
 Repeat the experiment to verify Channel B.

Full Adder using IC 74139:-

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Digital Electronics SSI

Full subtractor using IC 74139:-

Truth Tables:-

Conclusion:- Full Adder Full Subtractor

An Bn Cn-1 Sn (V) Cn (V) An Bn Cn-1 Dn (V) Bn (V)
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 0 1
1 1 0 1…………………………………………..
1 0
1 1 1 1 1Signature
1 of the staff in
charge

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Department of E & SSI

MUX USING NAND GATES ONLY: -

DEMUX USING NAND GATES ONLY: -

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 Department of E & SSI

Experiment No: DATE: //

MUX AND DEMUX USING NAND GATES

AIM: - To verify the truth table of MUX and DEMUX using NAND.

APPARATUS REQUIRED: -
IC 7400, IC 7410, IC 7420, etc.
PROCEDURE: -

1. Connections are made as shown in the Circuit diagram.

2. Change the values of the inputs as per the truth table and note down

the outputs readings using multimeter.

TRUTH TABLES: -

INPUT OUPUT INPUT OUPUT

A B I0 I1 I2 I3
Conclusion:- Y (V) Ē A B Y0 (V) Y1 (V) Y2 () Y3 (V)
0 0 0 X X X 0 1 X X 1 1 1 1
0 0 1 X X X 1 0 0 0 0 1 1 1
0 1 X 0 X X 0 0 0 1 1 0 1 1
0 1 X 1 X X 1 0 1 0 1 1 0 1
1 0 X X 0 X 0 0 1 1 1 1 1 0
1 0 X X 1 X 1 …………………………………………..
1 1 X X X 0 0
1 1 X X X 1 1

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Department of E & SSI

Signature of the staff in charge

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Digital Electronics SSI

One Bit Comparator: -

Y1 Y2 Y3
A B
(A>B) (A = B) (A < B)
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0

Two Bit Comparator: -

Two-Bit Comparator: -
A1 A0 B1 B0 Y1 (A > B) Y2 (A = B) Y3 (A < B)
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

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Digital Electronics SSI

Experiment No: Date: / /

COMPARATORS
Aim: - To verify the truth t able of one bit and two bit comparators using logic

gates.

Apparatus Required: -
IC 7486, IC 7404, IC 7408, et c.

Procedure: -

1. Verify the gates.

2. Make the connections as per the circuit diagram.

3. Switch on Vcc.

4. Applying i/p and Check for the outputs.

5. The voltameter readings of outputs are taken and tabulated in tabular

column.

6. The o/p are verified.

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Digital Electronics SSI

4- bit Comparator

Tabular Coloumn For 8-Bit Comparator: -

A3 B3 A2 B2 A1 B1 A0 B0 A>B A=B A<B A>B A=B A<B

A3>B3 X X X X X X
A3<B3 X X X X X X
A3=B3 A2>B2 X X X X X
A3=B3 A2<B2 X X X X X
A3=B3 A2=B2 A1>B1 X X X X
A3=B3 A2=B2 A1<B1 X X X X
A3=B3 A2=B2 A1=B1 A0>B0 X X X
A3=B3 A2=B2 A1=B1 A0<B0 X X X
A3=B3 A2=B2 A1=B1 A0=B0 1 0 0
A3=B3 A2=B2 A1=B1 A0=B0 0 1 0
A3=B3 A2=B2 A1=B1 A0=B0 0 0 1

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Digital Electronics SSI

8- Bit Comparator: -
LSB MSB

Exercise:-

 Write the truth table for 8-bit comparator and verify the same for the
above circuit.

Conclusion:-

…………………………………………..

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Digital Electronics SSI

Signature of the staff in charge

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Department of E & SSI

PIN DETAILS:-

TRUTH TABLE:-

En A B C D E F G H Q2(V) Q1(V) Q0(V) ES(V) EO(V)

1 X X X X X X X X 1 1 1 1 1
0 0 1 1 1 1 1 1 1 1 1 1 0 1
0 X 0 1 1 1 1 1 1 1 1 0 0 1
0 0 X 0 1 1 1 1 1 1 0 1 0 1
0 0 0 X 0 1 1 1 1 1 0 0 0 1
0 0 0 0 X 0 1 1 1 0 1 1 0 1
0 0 0 0 0 X 0 1 1 0 1 0 0 1
0 0 0 0 0 0 X 0 1 0 0 1 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 1 1 1 1 1 1 1 1 1 1 1 1 0

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 Department of E & SSI

Experiment No: DATE: / /

ENCODER & DECODER

AIM:-To convert a given octal input to th e binary output and to study the LED
display using 7447 7-segment decoder/ driver.

APPARATUS REQUIRED: -

IC 74148, IC 7447, 7-segment displa y, etc.

PROCEDURE: - (Encoder)

1. Connections are made as per circuit diagram.

2. The octal inputs are given at the corresponding pins.

3. The outputs are verified at the corresponding output pins.

PROCEDURE: - (Decoder)

1. Connections are made as per the circuit diagram.

2. Connect the pins of IC 7447 to the respec tive pins of the LED display board.

3. Give different combinations of the in puts and observe the decimal numbers
displayed on the board.

RESULT: -

The given octal numbers are converted into binary numbers.

The given data is displayed using &-segment LED decode r.

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Department of E & SSI

TABULAR COLUMN:-

Q4 Q3 Q2 Q1 O/P Display Glowing LEDs

0 0 0 0 0 a,b,c,d,e,f

0 0 0 1 1 b,c

0 0 1 0 2 a,b,d,e,g

0 0 1 1 3 a,b,c,d,g

0 1 0 0 4 b,c,f,g

0 1 0 1 5 a,c,d,f,g

0 1 1 0 6 a.c.d.e.f.g

0 1 1 1 7 a.b.c

1 0 0 0 8 a,b,c,d,e,f,g

1 0 0 1 9 a,b,c,d,f,g

1 0 1 0 10 d,e,g

1 0 1 1 11 c,d,g

1 1 0 0 12 c,d,e

1 1 0 1 13 a,g,d

1 1 1 0 14 d,e,f,g

1 1 1 1 15 blank

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Department of E & SSI

PIN DETAILS:-

DISPLAY:-

Conclusion:-

………………………………………….
Signature of the staff in charge

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Digital Electronics SSI

Circuit Diagram: - (Mas ter Slave JK Flip-Flop)

D Flip-Flop:-

T Flip-Flop:-

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Digital Electronics SSI

Experiment No: Date: / /

FLIP-FLOP
Aim:- Truth table verification of Flip-Flops : (i) JK Master Slave
(ii) D- Type
(iii) T- Type.
Apparatus Required: -
IC 7410, IC 7400, etc.

Procedure: -
1. Connections are made as per circuit diagram.
2. The truth table is verified for various combinations of inputs.

Truth Table:- (Master Slave JK Flip-Flop)

Preset Clear J K Clock Qn+1 Qn 1

0 1 X X X 1 0 Set
1 0 X X X 0 1 Reset
1 1 0 0 Qn Qn No Change
1 1 0 1 0 1 Reset
1 1 1 0 1 0 Set
1 1 1 1 Qn Qn Toggle

D Flip-Flop:-
Preset Clear D Clock Qn+1 Qn1
1 1 0 0 1
1 1 1 1 0

T Flip-Flop:-
Preset Clear T Clock Qn+1 Qn1
1 1 0 Qn Qn
1 1 1 Qn Qn

Exercise:-
 Write the timing diagrams for all the above Flip-Flops

……………………………………………
Signature of the staff in charge

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Digital Electronics SSI

Pin Details: - Truth Table:-

Clock QC QB QA
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

Timing Diagram:-

Circuit Diagram: - 3-Bit Asynchronous Up Counter

3-bit Asynchronous
up counter
Clock QC QB QA
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0

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9 0 0 1
Experiment No: Date: / /

COUNTERS

Realization of 3-bit counters as a se quential circuit and Mod-N counter

Aim:- design (7476, 7490, 74192, 74193).

Apparatus Required: -

IC 7408, IC 7476, IC 7 490, IC 74192, IC 74193, IC 7400, IC 7416, IC 7432

etc.

Procedure: -

1. Connections are made as per circuit diagram.

2. Clock pulses are applied one by on e at the clock I/P and the O/P is
observed at QA, QB & QC for IC 7476.

3. Truth table is verified.

Procedure (IC 741 92, IC 74193):-

1. Connections are made as per the ci rcuit diagram except the connection
from output of NAND gate to the load input.

2. The data (0011) = 3 is made available at the da ta i/ps A, B, C & D

respectively.

3. The load pin made low so that the data 0011 appe ars at QD, QC, QB & QA
respectively.

4. Now connect the output of the NAND gate to the load input.

5. Clock pulses are applied to “count up” pin and the truth table is verified.

6. Now apply (1100) = 12 for 12 to 5 count er and remaining is same as for 3

to 8 counter.

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7. The pin diagram of IC 7419 2 is same as that of 74193. 74192 can be

configured to count between 0 and 9 in either direction. The starting value
can be any number between 0 and 9.

Circuit Diagram: - 3-Bit Asynchronous Down Counter

3-bit Asynchronous
down counter
Clock QC QB QA
0 1 1 1
1 1 1 0
2 1 0 1
3 1 0 0
4 0 1 1
5 0 1 0
6 0 0 1
7 0 0 0
8 1 1 1
Mod 5 Asynchronous 0Counter:-
9 1 1

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Mod 5 Asynchronous
counter
Clock QC QB QA
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 0 0 0
Mod 3 Asynchronous Counter:-

Mod 3 Asynchronous
counter
Clock QC QB QA
0 0 0 0
1 0 0 1
2 0 1 0
3 0 0 0
4 0 0 1
5 0 1 0

3-bit Synchronous Counter:-

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IC 7490 (Decade Counter):-

Clock QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0

IC 7490 (MOD-8 Counter):-

Clock
QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 0 0 0 0
9 0 0 0 1

Circuit Diagram (IC 74193) To Count from 3 to 8:-

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Count in
Clock QD QC QB QA
Decimal
0 0 0 1 1 3
1 0 1 0 0 4
2 0 1 0 1 5
3 0 1 1 0 6
4 0 1 1 1 7
5 1 0 0 0 8
6 0 0 1 1 3
7 repeats 4

Circuit Diagram (IC 74193) To Count from 8 to 3:-

Count in
Clock QD QC QB QA
Decimal
0 0 1 0 1 5
1 0 1 1 0 6
2 0 1 1 1 7
3 1 0 0 0 8
4 1 0 0 1 9
5 1 0 1 0 10
6 1 0 1 1 11
7 1 1 0 0 12
8 0 1 0 1 5
Function Table for 7490:- 9 repeats 6

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Clock R1 R2 S1 S2 QD QC QB QA
X H H L X L L L L RESET
X H H X L L L L L RESET
SET
X X X H H H L L H
TO 9
X L X L COUNT
L X L X COUNT
L X X L COUNT
X L L X COUNT

4 I/P OR Gate can be realized as follows:-

Conclusion:-

…………………………………………..
Signature of the staff in charge

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Circuit Diagram: - Shift Left

Clock Serial i/p QA QB QC QD

1 1 X X X 1
2 0 X X 1 0
3 1 X 1 0 1
4 1 1 0 1 1

SIPO (Right Shift):-

Clock Serial i/p QA QB QC QD

1 0 0 X X X
2 1 1 0 X X
3 1 1 1 0 X
4 1 1 1 1 0

SISO:-

Clock Serial i/p QA QB QC QD

1 do=0 0 X X X
2 d1=1 1 0 X X
3 d2=1 1 1 0 X
4 d3=1 1 1 1 0=do
5 X X 1 1 1=d1
6 X X X 1 1=d2
7 X X X X 1=d3

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Experiment No: Date: / /

SHIFT REGISTERS
Realization of 3-bit counters as a se quential circuit and Mod-N counter
Aim:- design (7476, 7490, 74192, 74193).

Apparatus Required: -
IC 7495, etc.
Procedure: -
Serial In Parallel Out:-
1. Connections are made as per circuit diagram.
2. Apply the data at serial i/p
3. Apply one clock pulse at clock 1 (Right Shift) observe this data at QA.
4. Apply the next data at serial i/p.
5. Apply one clock pulse at clock 2, observ e that the data on QA will shift to
QB and the new data applied will appear at QA.
6. Repeat steps 2 and 3 till all the 4 bits data are entered on e by one into the
shift register.

Serial In Serial Out:-

1. Connections are made as per circuit diagram.
2. Load the shift register with 4 bits of data one by one serially.
3. At the end of 4th clock pulse the first data ‘d0’ appears at QD.
4. Apply another clock pulse; the second data ‘d1’ appears at QD.
5. Apply another clock pulse; the third data appears at QD.
6. Application of next clock pulse will enable the 4 th data ‘d3’ to appear at
QD. Thus the data applied serially at the input comes out serially at QD

PISO:-

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Mode Clock Parallel i/p Parallel o/p

A B C D QA QB QC QD
1 1 1 0 1 1 1 0 1 1
0 2 X X X X X 1 0 1
0 3 X X X X X X 1 0
0 4 X X X X X X X 1

PIPO:-

Clock Parallel i/p Parallel o/p

A B C D QA QB QC QD
1 1 0 1 1 1 0 1 1

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Parallel In Parallel Out:-

1. Connections are made as per circuit diagram.
2. Apply the 4 bit data at A, B, C and D.
3. Apply one clock pulse at Clock 2 (Note: Mode control M=1).
4. The 4 bit data at A, B, C and D appears at QA, QB, QC and QD
respectively.

Parallel In Serial Out:-

1. Connections are made as per circuit diagram.
2. Apply the desired 4 bit data at A, B, C and D.
3. Keeping the mode control M=1 apply one clock pulse. The data applied at
A, B, C and D will appear at QA, QB, QC and QD respectively.
4. Now mode control M=0. Apply clock pulses one by one and observe the
data coming out serially at QD.

Left Shift:-
1. Connections are made as per circuit diagram.
2. Apply the first data at D and apply on e clock pulse. This data appears at
QD.
3. Now the second data is made availabl e at D and one clock pulse applied.
The data appears at QD to QC an d the new data appears at QD.
4. Step 3 is repeated until all the 4 bits are entered one by one.
5. At the end 4th clock pulse the 4 bits are available at QA, QB, QC and QD.

Conclusion:-

…………………………………………..
Signature of the staff in charge

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Circuit Diagram: - Ring Counter

Mode Clock QA QB QC QD
1 1 1 0 0 0
0 2 0 1 0 0
0 3 0 0 1 0
0 4 0 0 0 1
0 5 1 0 0 0
0 6 repeats

Johnson Counter:-

Mode Clock QA QB QC QD
1 1 1 0 0 0
0 2 1 1 0 0
0 3 1 1 1 0
0 4 1 1 1 1
0 5 0 1 1 1
0 6 0 0 1 1
0 7 0 0 0 1
0 8 0 0 0 0
0 9 1 0 0 0
0 10 repeats

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Experiment No: Date: / /

JOHNSON COUNTERS / RING COUNTER

Aim:- Design and testing of Ring counter/ Johnson counter.

Apparatus Required: -

IC 7495, IC 7404, etc.

Procedure: -

1. Connections are made as per the circuit diagram.

2. Apply the data 1000 at A, B, C and D respectively.

3. Keeping the mode M = 1, apply one clock pulse.

4. Now the mode M is made 0 and clock pulses are applied one by one and
the truth table is verified.

5. Above procedure is repeated for Johnson counter also.

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Circuit Diagram: - Sequence Generator

Truth Table:-

Map
Clock QA QB QC QD o/p D
Value
15 1 1 1 1 1 0
7 2 0 1 1 1 0
3 3 0 0 1 1 0
1 4 0 0 0 1 1
8 5 1 0 0 0 0
4 6 0 1 0 0 0
2 7 0 0 1 0 1
9 8 1 0 0 1 1
12 9 1 1 0 0 0
6 10 0 1 1 0 1
11 11 1 0 1 1 0
5 12 0 1 0 1 1
10 13 1 0 1 0 1
13 14 1 1 0 1 1
14 15 1 1 1 0 1

Karnaugh Map for D:-

QA QB
QCQD 00 01 11 10
00 0 0 0 0
01 1 1 1 1
11 0 0 0 0
10 1 1 1 1

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Experiment No: Date: //

SEQUENCE GENERATOR
Aim:- Design of Sequence Generator.

Apparatus Required: -

IC 7495, IC 7486, etc.

Design:-

To generate a sequence of length S it is necessary to use at least N number of

Flip-Flops, which satisfies the condition S≤ 2N -1.

The given sequence length S = 15.

Therefore N = 4.

Note: - There is no guarantee that the given sequence can be generated by 4 f/fs.
If the sequence is not realizable by 4 f/fs then 5 f/fs must be used and so on.

Procedure: -

1. Connections are made as per the circuit diagram.

2. Clock pulses are applied one by one and truth table is verified.

Conclusion:-

………………………………………….
Signature of the staff in
charge

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Circuit Diagram: - Monostable Multivibrator

Waveform:-

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Experiment No: Date: //

MULTIVIBRATORS
Design and testing of Monostable and Astable multivibrators using 555
Ai timer.

Apparatus Required: -

IC 555 timer, resistor, capacitor, etc.

Design:- (Monostable)
Given pulse width required = 1ms
Pulse width T = 1.1RC
Therefore 1ms = 1.1RC
Let C = 0.1μf

Therefore 1103
R
1.1 0.1106

Procedure: -(Monostable)

1. Connections are made as per the circuit diagram.

2. Triggering pulses are applied at pin 2.

3. The pulse width of the waveform at pin3 is measured and verified with the
designed value.

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Astable Multivibrator:-

Wave form:-

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Design:-
Ton = 0.69(RA + RB)C, Toff = 0.69 RB C
Given; f = 10 KHz, duty cycle = 70%,
Therefore T = (1/f) = (1/10x103) = 0.1ms
D = (Ton/T) = 0.7
Ton = 0.7T = 0.7x0.1ms = 0.07ms
T = Ton + Toff
Therefore Toff = 0.03ms
Ton = 0.69 (RA + RB) C
Let C = 0.1μf
Therefore 0.07 x 10-3 = 0.69 (RA + RB) 0.1 x 10-6
Therefore RA + RB = 1014 ohms
Toff = 0.69 RB C
0.03 x 10-3 = 0.69 (RB) 0.1 x 10-6
Therefore RB = 434.7 ohms
Therefore RA = 579 ohms

Procedure: -
1. Connections are made as per circuit diagram
2. Switch on the 5V power supply
3. Observe the waveforms at pin 3 on CRO, measure Ton, Toff, T and its
amplitude.
4. Also observe capacitor voltage on CRO.

Conclusion:-

………………………………………….

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Example for Data Input:-
Address Inputs Data Inputs
A3 A2 A1 A0 I/O4 I/O3 I/O2 I/O1
0 0 0 0 0 0 1 0
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0

Example for Data Output:-

Address Inputs Data Outputs
A3 A2 A1 A0 I/O4 I/O3 I/O2 I/O1
0 0 0 0 0 0 1 0
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
Experiment No: Date: / /

STATIC RAM

Aim: - To conduct an experiment to store a set of data in a RAM using IC 2114

starting from location ------- to location-------- and retrieve the same data.

Apparatus Required: -
IC 2114, etc.
Procedure: -
1. circuits connections are made to the appropriate pins of IC 2114
2. First you have to write th e data and then read th e data, for writing data
make WE to low and CS input to low
3. for a 4-bit data select any address input from A0 to A9. for ex, select A3 to
A0 and connect the data inputs / outputs i.e., I/O4 – I/O1
4. write a 4-bit data of your choice in each of the re quired address inputs or
memory locations
5. by doing the above steps 2, 3 and 4 the data will be stored in the memory
location
6. for reading data

a. make WE to high and CS input to low

b. disconnect the data inpu ts I/O4 – I/O1 from input lines and connect
them to output lines to read the data
c. and then give the addr ess inputs of the data you have stored and
observe the outputs through I/O4 – I/O1.
Conclusion:-

………………………………………….
Signature of the staff in charge