UNIT-I

8085 Processor: PART-A

Hardware Architecture

The architecture of the 8085 processor is an 8-bit microprocessor that has a total of 40
pins. It has a data bus of 8 bits, an address bus of 16 bits, and a program counter of 16 bits.
The processor has six general-purpose registers, including the accumulator, and two special-
purpose registers, including the stack pointer and the program counter.

The Intel 8085 is an 8-bit microprocessor that was widely used in the early days of computing
and is known for its simplicity and versatility. Here's a brief overview of its architecture:

1. **Data Bus**: The 8085 has an 8-bit data bus, which means it can process data in 8-bit
chunks at a time.

2. **Address Bus**: It has a 16-bit address bus, allowing it to address up to 64 KB of memory.

This means it can access 2^16 (65536) different memory locations.

3. **Registers**: The 8085 has six general-purpose registers (B, C, D, E, H, and L), which
can be paired to form three 16-bit register pairs (BC, DE, and HL). It also has a 16-bit stack
pointer (SP) and a 16-bit program counter (PC).

4. **Accumulator**: The Accumulator (A) is the primary register for performing arithmetic
and logical operations. It's also used for storing results.
5. **Flags**: The 8085 has five flag bits in the flags register to indicate the results of
arithmetic and logic operations: Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P), and Carry
(CY).

6. **Control Unit**: The control unit is responsible for controlling the operation of the
microprocessor. It generates control signals to synchronize the execution of instructions.

7. **Arithmetic and Logic Unit (ALU)**: The ALU performs arithmetic and logical
operations on data stored in registers. It can perform operations like addition, subtraction,
AND, OR, XOR, etc.

8. **Instruction Set**: The 8085 has a relatively simple instruction set with a variety of data
manipulation, branching, and control instructions. Instructions are encoded as opcodes and
operands and are fetched from memory for execution.

9. **Memory Interfacing**: The 8085 can address a range of memory and I/O devices. It uses
the address bus to select memory locations and the data bus to transfer data between memory
and registers.

10. **Interrupts**: The 8085 supports five interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5, and
INTR. These interrupts can be used for handling external events and are serviced by specific
interrupt service routines.

11. **Clock and Timing**: The 8085 requires a clock signal to synchronize its operations. It
typically operates at a 3 MHz frequency.

12. **Serial I/O**: The 8085 has limited built-in support for serial data communication
through the serial input (SI) and serial output (SO) pins.

13. **Minimum Mode and Maximum Mode**: The 8085 can operate in different modes
depending on the system requirements. In the minimum mode, it uses 74xx series chips for
control signal generation, while in the maximum mode, it can generate control signals
internally.

Overall, the Intel 8085 microprocessor is a fundamental component in the history of

computing, playing a pivotal role in early microcomputer systems and paving the way for more
advanced processors.
8085 pinouts:

The Intel 8085 microprocessor, introduced in 1976, played a pivotal role in the early days of
computing. It was an 8-bit microprocessor, meaning it could process 8 bits of data at a time.
The 8085 had a 40-pin dual in-line package (DIP), and its pin diagram provides essential
information about its functionality and connectivity.

The 8085 pin diagram consists of various pins, each serving a specific purpose. Here's a brief
overview of some key pins:

1. Address Bus (A8-A15): These pins are used to specify memory locations or I/O ports
for reading or writing data.
2. Data Bus (D0-D7): These pins are bidirectional and carry data between the
microprocessor and memory or I/O devices.
3. Control Signals: These pins include signals like Read (RD), Write (WR), and Memory
Request (MR) to control the flow of data and memory access.
4. Interrupt Pins (INTR, RST 7.5, RST 6.5, RST 5.5): These pins are used to handle
external interrupts and allow the microprocessor to respond to events or requests from
external devices.
5. Power Supply Pins (Vcc, Vss): These pins provide the necessary power supply to the
microprocessor.

Understanding the 8085 pin diagram is crucial for designing and interfacing the
microprocessor with various peripherals and memory devices. It enables engineers and
hobbyists to establish proper connections and ensure the efficient functioning of the system.
Functional blocks of 8085 Microprocessor:

The main blocks of 8085 microprocessor are:

1. Accumulator

2. Temporary Register

3. Flag Register

4. Instruction Register

5. General Purpose Register

6. Stack Pointer

7. Program Counter

8. Timing and Control Unit

9. Buffer Unit

10. ALU

Timing and Control Unit: This is the section of CPU used to generate timing and control
signals which are required to synchronize the microprocessor operations with the system clock
and to provide communication between microprocessor and peripherals, this control entire
operation of microprocessor and peripherals connected to it. This also controls data flow
through the bus, this is provided with an oscillator and controlling sequencing generator.

Instruction Register: This is an 8-bit register that stores opcode of an instruction byte during
fetch cycle. After words, it is decoded by an internal decoder followed by this register.

Program Counter: It is a 16-bit register employed to provide a sequence for execution of

instructions. It always points to the memory address form which next byte is to be fetched that
is, when current instruction byte is fetched this program counter will be incremented by one
to point to the new memory location. It is not programmable.

Stack Pointer: It is a 16-bit register that holds the address of stack top which is the last
memory location.

General Purpose Register: These are 8-bit registers used for internal data operations of
microprocessors. These are programmable. Example 8085 contains 6 registers B, C, D, E, H
and L. These registers can be combined as BC, DE and HL register pairs.

ALU: This ALU performs arithmetic and logical operations by using address, registers, and
counters and so on. The contents of the accumulator and temporary register are inputted to
ALU and results of performed operation by ALU are stored in an accumulator. The functions
that will be performed are addition, subtraction, complementing, and incrementing and so on
Accumulator: This is an 8-bit register. This store one of the operands of arithmetic and logic
operations, after ALU, performs the required task, the results are stored in an accumulator.
This is identified as register A

Temporary register: This stores one of the inputs to ALU that is this provides one of the
operands which is to be used in the required task.

Flag register: This register has five useful flip-flops which act as flags to indicate reflected
data conditions. The five flags used in 8085 are discussed below. It contains 7 data blocks

Zero flags: This reflects the zero results of an operation. That is whenever the results of
arithmetic or a logical operation are zero, this becomes as 1.

Sign flag: If D2 is as1, this is set and id D7 is a 0 this will be reset.

Auxiliary carry flag: This will hold a binary 1, whenever a carry passes from D3 to D4.

Parity flag: This is a 1 when the result maintains even parity that is even number of 1.

Carry flag: This is set whenever the result of an arithmetic or a logical operation overflows.
This is also useful as a borrow flag during subtraction processes.

These flags will change only after arithmetic and logical operations but do not alter with other
operations.

The general purpose peripherals are the devices that perform a specific task but may be used
for interfacing any I/O devices to the microprocessor. Some of the general purposes peripheral
are:

1. Input /Output port.

2. Multipurpose programmable device.
3. Programmable interrupt controller (PIC)
4. Programmable DMA interface.
5. Programmable communication interface.
6. Programmable interval timer.
Memory organization
I/O Ports and Data Transfer Concepts
I/O Ports

There are two methods in which I/O devices can be connected to the Microprocessor.

Memory mapped I/O

I/O mapped I/O

Memory mapped I/O:

In this method I/O device is treated like the memory. Here there is no IO/M signal.

If the processor wants to read the data from a I/O device it will place the address of the

I/O device on the address bus. Then the I/O device will get selected. The memory which

is having the same address will also get selected.so we have to use separate address for

memory and separate address for I/O device.

I/O mapped I/O:

Here we have the IO/M signal. So we can select either the memory or I/O device

for read and write operation.

Data Transfer Concepts

Parallel data transfer

Serial data transfer

Parallel data transfer

Programmed I/O

Interrupt I/O

DMA

Programmed I/O:

Here the processor has to check whether the I/O device is ready or not through the

Ready signal of the I/O device. If the ready signal is high, then it will send the data to the

I/O device. Otherwise it will continuously check the Ready signal. The processor is busy

in checking the Ready signal. The drawback is wastage of time.

Interrupt I/O:
In this method the I/O device will interrupt the Processor through the INTR signal

to indicate to the processor that it is ready to accept the next data. Then the processor will
send the INTA signal. Then the processor stops its normal execution and start transferring

the data to the I/O device.

DMA:

Using DMA I/O device can directly transfer the data to the Memory using the

Address and Data buses of Processor.

Serial data Transfer

Some of the external I/0 devices receive only the serial data. Normally serial

communication is used in the MultiProcessor environment. 8051 has two pins for serial

communication.

• SID- Serial Input data.

• SOD-Serial Output data.

Serial data communication can be categorized on the basis of how data transmission

occurs. These are:

1. Simplex:

In simplex communication, the hardware is set such that the data exchange takes

place in only one direction. Example: Computer to Printer communication.

2. Half Duplex:

The half-duplex communication allows the data exchange in both directions, but

not at the same time. Example: Walkie talkie.

3. Full Duplex:

It permits the information transfer in both directions at the same time. Example:

Telephone lines.

Interrupts
The processor has the following interrupts:
 INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled

using STI/CLI instructions or using more complicated method of updating the FLAGS

register with the help of the POPF instruction.

When an interrupt occurs, the processor stores FLAGS register into stack, disables
further interrupts, fetches from the bus one byte representing interrupt type, and jumps to
interrupt processing routine address of which is stored in location 4 * <interrupt
type>.Interrupt processing routine should return with the IRET instruction.

NMI is a non-maskable interrupt. Interrupt is processed in the same way as the

INTR interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing

routine is stored in location 0008h. This interrupt has higher priority than the maskable

interrupt.

Software interrupts can be caused by:

• INT instruction - breakpoint interrupt. This is a type 3 interrupt.

• INT <interrupt number> instruction - any one interrupt from available 256
• interrupts.
• INTO instruction - interrupt on overflow
• Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt.

When the CPU processes this interrupt it clears TF flag before calling the interrupt

processing routine.

Synchronous Data Transfer

• The word ‘Synchronous ‘means ‘taking place at the same time.’

• Thus, to establish communication between our processor and the device, we need
• to set a common clock pulse. This common pulse synchronizes the peripheral
• device with the 8085 microprocessor.
• This method is used when the speed of the microprocessor, Intel 8085, in this case,
• and the external peripheral device match with each other.
• If the device is ready to send data, it can indicate via the READY pin of 8085.
• Once the speeds match, the data transfer immediately begins, once a signal is
• issued by the microprocessor to begin transferring. The microprocessor need not
• wait for an extended period because of the matching speeds.
• This technique of data transfer is seldom used to communicate with I/O devices
• though. Because I/O devices compatible with the microprocessor’s speed are
• usually not found.
 • Hence, this method of data transfer is most commonly employed for
• communicating with compatible memory devices.

Asynchronous Data Transfer

• When the speed of the I/O device is slower than that of the microprocessor, we
• prefer the Asynchronous Data Transfer Method. As the speeds of both the devices
• differ, the I/O device’s internal timing is entirely independent of the
• microprocessor.
• Thus, they are termed to be ‘asynchronous ‘from each other. The term
• asynchronous means ‘at irregular intervals.’
 8086 Architecture

Main Features:

The Intel 8086 microprocessor, released in 1980, is a 16-bit processor that was widely used in
personal computers during the 1980s. Some of its main features include a clock speed of 2.5
to 3.5 MHz, 16 KB of memory (expandable to 64 KB), two 8-bit data buses, and support for
graphics and sound. The 8086 also introduced several new instructions and features, such as
the x86 architecture and support for segmented memory.

• It is a 16-bit μp.

• 8086 has a 20 bit address bus can access up to 220 memory locations (1 MB).

• It can support up to 64K I/O ports.

• It provides 14, 16 -bit registers.

• Word size is 16 bits and double word size is 4 bytes.

• It has multiplexed address and data bus AD0- AD15 and A16 – A19.

• It requires single phase clock with 33% duty cycle to provide internal timing.3

• 8086 is designed to operate in two modes, Minimum and Maximum.

• It can prefetches up to 6 instruction bytes from memory and queues them in order to

speed up instruction execution.

• It requires +5V power supply.

• A 40 pin dual in line package.

• Address ranges from 00000H to FFFFFH

• Memory is byte addressable - Every byte has a separate address.

Pin Diagram and Description of 8086 Microprocessor

Pin Diagram 8086 Microprocessor

An 8086 microprocessor is also a 40 pin IC but has few separate pin configuration for
minimum and maximum mode which we will discuss in this article.

Here, from the below figure it is clear that from pin number 24 to 32, we have shown the
different configuration for minimum and maximum mode. However, excluding these 8 pins,
the rest 32 pins are the same for both minimum as well as maximum mode.
Pin description of 8086 Microprocessor

VCC – Pin number 40 – At this pin, the external power supply of + 5V is provided to
the processor.
VSS – Pin number 1 and 20 – These two pins acts as the ground. This pin directs the
extra current of the microprocessor to ground.
AD0 – AD15 – Pin number 2 to 16 and 39 – These are the multiplexed address and data
bus.
We know that the 8086 microprocessor has 20-bit address bus and 16-bit data bus. So,
the 16 lines of the address and data bus are multiplexed together so as to reduce the number
of lines inside the IC.

We are aware of the fact that at a time either address or data will be transmitted by the
bus. So, at a particular time only either the address or the data bus will be enabled from the
multiplexed buses.

A16/S3, A17/S4, A18/S5 and A19S6 – Pin number 35 to 38 – Out of 20 address bits, 4 are
present in the multiplexed form with the status signals. In the case of memory
operations, these pins act as an address bus and contain the memory address of any
particular instruction or data.
However, from I/O operations these pins are low that shows the status of the
processor.

Basically, the signal at S3 and S4 show that which segment is currently accessed by
the microprocessor among the four segments present in it.
The table below will show the encoding of S3 and S4:
Also, S5, when enabled, shows the presence of an interrupts in the microprocessor.
So, basically, it serves as an interrupt flag.
The signal at S6 shows the status of the bus master for the current operation. More
simply we can say, whether the 8086 is the bus master or any other proficient device
is acting as the bus master.
When 0 is present as the signal at this pin then it indicates the 8086 is holding the
access of the bus otherwise it is high i.e., 1.

BHE’ / S7 – Pin number 34 – BHE is an acronym for Bus High Enable. The
combination of the BHE signal and S7 status informs about the existence of the data
on the bus. Also, different combinations show whether the bus is containing overall
16 bit, upper byte or lower byte of the data.
The table below represents the status for the signal at this pin:

MN/MX’ – Pin number 33 –The status at this particular pin shows whether the
processor is operating in the minimum mode or maximum mode.
A signal 0 at this pin informs that the 8086 is operating in maximum mode i.e.,
multiple processors. While signal 1 shows the operation under minimum mode i.e.,
single processor.
RD’ – Pin number 32 – An active low signal at this pin shows that the microprocessor
is performing read operation with either memory or I/O devices.
CLK – Pin number 19 – A signal at this pin provides the timing to the internal
operations that are being executed inside the microprocessor.
NMI – Pin number 17 – NMI is Non-maskable interrupt. These are basically
uncontrollable interrupts generated inside the processor. When an NMI occurs, then
an interrupt service routine is generated by the interrupt vector table.
TEST – Pin number 23 – This pin basically shows the wait instruction. Whenever a
low signal at this pin occurs then the processing inside the processor continues. As
against, in case of the high signal, the processor has to wait for the disabling of this
pin.
INTR – Pin number 18 – INTR stands for an interrupt request. The processor after
each clock cycle samples the INTR and if the signal at this pin is found to be high
then the processor controls that interrupt internally.
READY – Pin number 22 – This signal is used by the peripherals and memory devices
in order to show the readiness for the next operation.
RESET – Pin number 21 – Whenever this pin is enabled then it resets the processor
and other devices connected to the system by immediately terminating the recent
task.
Pins in Minimum mode

INTA’ – Pin number 24 – It is an interrupt acknowledge pin. Whenever an INTR signal

is generated, then the microprocessor generates INTA signal, as a response to that
interrupt.
ALE – Pin number 25 – ALE is an abbreviation for address latch enable. Whenever an
address is present in the multiplexed address and data bus, then the microprocessor
enables this pin.
This is done to inform the peripherals and memory devices about fetching of the data
or instruction at that memory location.

DEN’ – Pin number 26 – DEN is used for data enable. This is an active low pin that
means whenever a 0 is present at this pin then the transceiver gets enabled and it
separates the data from the multiplexed address and data bus.
DT/R’ – Pin number 27 – This pin is used to show whether the data is getting
transmitted or is received. A high signal at this pin provides the information regarding
the transmission of data. While a low indicates reception of data.
M/IO’ – Pin number 28 – This pin indicates whether the processor is performing an
operation with memory or I/O devices. Whenever a high is present at this pin then it
shows the operation is carried out through the memory. While a low signal shows
operation through I/O devices.
WR’ – Pin number 29 – An active low signal at this pin indicates that the processor is
performing write operation from either memory or I/O devices.
HOLD – Pin number 31 – When an external device enables this pin then the
processor stops accessing the buses immediately after the recent task gets over.
HLDA – Pin number 30 – This pin is used as a response pin for the hold request.
Once request for accessing the buses is produced by an external entity. Then the
microprocessor acknowledges the device that its request will be considered once it
gets over by the current operation.
Pins in Maximum mode

S0‘, S1‘ and S2‘ – Pin number 26 to 28 – These are basically 3 status pins and are active
low. This means that if the status at all the 3 pins is 0 then it shows that multiple
interrupts are to be handled in maximum mode.
The table below is representing the status of the processor in different combinations:

QS0 and QS1 – Pin number 24 and 25 – These two pins indicate the status of the 6-
byte pre-fetch queue present in the architecture of 8086.

LOCK’ – Pin number 29 –This pin is involved in maximum mode operation. So,
basically, when a single processor is accessing the buses and peripherals then it locks
the resources being used by it. So, that no other entity can access it until the recent
processor frees it.
RQ’/ GT0‘ and RQ’/ GT1‘ – Pin number 30 and 31 – Due to the involvement of
multiple processors, these pins indicate the request and grant permission for
accessing the buses, memory and peripherals.
This is all about the pin diagram and description of the 8086 microprocessor.
8086 MP Family

The 8086 microprocessor family refers to a series of microprocessors developed by

Intel. The 8086 was introduced in 1978 and was a 16-bit microprocessor, which was a
significant advancement at the time. It was widely used in early personal computers and
embedded systems. The 8086 family also includes the 80186, 80286, 80386, 80486, and later
the Pentium processors, which were all based on the original 8086 architecture. These
processors played a crucial role in the development of modern computing and are considered
foundational in the history of microprocessors.

The 8086 microprocessor family refers to a series of microprocessors developed by

Intel. The 8086 microprocessor was introduced in 1978 and marked a significant
advancement in the field of microprocessing technology. It was the first 16-bit
microprocessor in the x86 architecture, which has since become one of the most widely used
instruction set architectures in the world.

The 8086 microprocessor family includes a range of processors such as the 8088,
80186, 80286, and others, each offering improvements and enhancements over its
predecessors. These processors have been widely used in various computing devices, from
early personal computers to embedded systems.

The 8086 microprocessor family played a crucial role in the development of modern
computing and has had a lasting impact on the technology industry. Its architecture and
instruction set have influenced subsequent generations of microprocessors and continue to be
relevant today.

8086 Internal Architecture

Interrupts and Interrupt responds ( https://www.scribd.com/document/483388071/7 )

An interrupt is a condition that halts the microprocessor temporarily to work on a different

task and then returns to its previous task. An interrupt is an event or signal that requests the
CPU’s attention. This halt allows peripheral devices to access the microprocessor. Whenever
an interrupt occurs, the processor completes the current instruction and starts the
implementation of an Interrupt Service Routine (ISR) or Interrupt Handler. ISR is a program
that tells the processor what to do when the interrupt occurs. After the ISR execution, control
returns to the main routine where it was interrupted. In the 8086 microprocessor following
tasks are performed when the microprocessor encounters an interrupt:
The value of the flag register is pushed into the stack. It means that first, the value of SP
(Stack Pointer) is decremented by two then the value of the flag register is pushed to the
memory address of the stack segment.

• The value of starting memory address of CS (Code Segment) is pushed into the stack.
• The value of IP (Instruction Pointer) is pushed into the stack.
• IP is loaded from word location (Interrupt type) * 04.
• CS is loaded from the following word location.
• Interrupt, and Trap flags are reset to 0.

The different types of interrupts present in the 8086 microprocessor are given by:

Hardware Interrupts – Hardware interrupts are those interrupts that are caused by any
peripheral device by sending a signal through a specified pin to the microprocessor. There
are two hardware interrupts in the 8086 microprocessor. They are:

NMI (Non-Maskable Interrupt): It is a single pin non-maskable hardware interrupt that

cannot be disabled. It is the highest priority interrupt in the 8086 microprocessor. After its
execution, this interrupt generates a TYPE 2 interrupt. IP is loaded from word location
00008 H, and CS is loaded from the word location 0000A H.

INTR (Interrupt Request): It provides a single interrupt request and is activated by the I/O
port. This interrupt can be masked or delayed. It is a level-triggered interrupt. It can receive
any interrupt type, so the value of IP and CS will change on the interrupt type received.

Software Interrupts – These are instructions inserted within the program to generate
interrupts. There are 256 software interrupts in the 8086 microprocessor. The instructions are
of the format INT type, where the type ranges from 00 to FF. The starting address ranges
from 00000 H to 003FF H. These are 2-byte instructions. IP is loaded from type * 04 H, and
CS is loaded from the following address given by (type * 04) + 02 H. Some important
software interrupts are:

• TYPE 0 corresponds to division by zero(0).

• TYPE 1 is used for single-step execution for debugging the program.
• TYPE 2 represents NMI and is used in power failure conditions.
• TYPE 3 represents a break-point interrupt.
• TYPE 4 is the overflow interrupt.
 System Timing

The 8086 system timing refers to the way the 8086 microprocessor manages and
synchronizes its operations. It involves the use of various timing components and signals to
ensure that the processor can execute instructions and communicate with external devices in
a coordinated manner.

The 8086 microprocessor has a built-in clock generator that provides a basic timing
reference. This clock generator produces a series of pulses at a specific frequency, which is
typically 4.77 MHz or 8 MHz. These pulses are used to synchronize the internal operations
of the processor, such as the fetch-decode-execute cycle.

In addition to the clock generator, the 8086 microprocessor also has several control signals
that are used to manage timing. These signals include the READY signal, which indicates
that the processor is ready to receive data from external devices, and the WAIT signal, which
indicates that the processor is waiting for external devices to complete their operations.

The 8086 microprocessor also uses a number of interrupt signals to handle asynchronous
events. These signals allow external devices to interrupt the processor's normal operation and
request its attention. The processor can then respond to the interrupt and perform the
necessary actions.

Overall, the 8086 system timing is a complex mechanism that ensures that the processor can
operate efficiently and reliably. It involves the use of various timing components and signals
to synchronize internal operations, manage external communication, and handle interrupts.

Minimum mode and Maximum mode configuration

The 8086 microprocessor, advanced by Intel, was one of the most influential and extensively used
microprocessors inside the early days of personal computing. It added a 16-bit architecture and
served as the foundation for the x86 family of processors that keep dominating the marketplace
these days. The 8086 microprocessor featured two working modes known as Maximum Mode and
Minimum Mode, which provided exclusive levels of system configuration and control.

Maximum Mode:
The Maximum Mode of the 8086 microprocessor is supposed for use in structures where the
processor is the significant element and has full control over the device bus. In this mode, the
microprocessor acts because of the bus controller and interacts without delay with other gadgets
together with memory, I/O ports, and co-processors. The Maximum Mode configuration calls for
extra help chips, including the 8288 bus controller, to manipulate bus arbitration and generate
control alerts.
Key features of the Maximum Mode consist of:

1. Bus Control: The 8086 microprocessor takes control of the machine bus, permitting it to initiate and
control all records transfers among diverse devices related to the gadget.
2. Multiple Processors: The Maximum Mode supports the usage of a couple of processors, making it
suitable for multiprocessor structures. Each processor is assigned specific obligations, and that they
talk through shared memory.
3. External Bus Controller: In Maximum Mode, an outside bus controller, such as the 8288, is required
to address bus arbitration and generate bus manage indicators. This controller facilitates efficient
statistics transfer and prevents conflicts amongst distinctive gadgets.
4. Expanded Address and Data Lines: The Maximum Mode lets in the usage of all 20 cope with lines
and sixteen records strains of the 8086 microprocessor, allowing admission to a larger memory space
and extra great I/O abilities.

Minimum Mode:
The Minimum Mode of the 8086 microprocessor is designed for systems wherein the processor
shares the gadget bus with different devices and does not act as the bus controller. This mode is
commonly utilized in single-processor systems or while the device calls for fewer assets and a much
less complex configuration.
Key features of the Minimum Mode encompass:

1. Bus Controller: In Minimum Mode, the microprocessor relies on an outside bus controller,
which includes the 8284 clock generator, to address bus control indicators and bus
arbitration. The bus controller coordinates the activities of various devices linked to the
machine bus.
2. Single Processor: The Minimum Mode is generally used in unmarried-processor structures
wherein the microprocessor is the number one processing unit and does not require the
complexities related to multiprocessor structures.
3. Limited Address and Data Lines: In Minimum Mode, most effective 16 address traces and
16 facts lines of the 8086 microprocessor are utilized, proscribing the reminiscence addressing
skills and I/O options compared to the Maximum Mode.
4. Reduced Complexity: The Minimum Mode configuration simplifies the machine design with
the aid of offloading bus manager obligations to an external bus controller, decreasing the
overall complexity and price of the gadget.

Choosing the correct mode relies upon the unique requirements of the system. The Maximum Mode
is appropriate for big-scale systems with a couple of processors, massive reminiscence and I/O
requirements, and the need for full control over the device bus. On the other hand, the Minimum
Mode is favored for easier structures with a single processor and restrained useful resource
requirements, where the microprocessor stocks the bus with different gadgets.

Difference between minimum mode and maximum mode in 8086 microprocessor

Minimum mode Maximum mode

There can be only one processor. There can be multiple processors.

 Minimum mode Maximum mode

Performance is slower. Performance is faster.

The circuit is simple. The circuit is complex.

Multiprocessing cannot be performed. Multiprocessing can be performed.

MN/MX is 1 to indicate the minimum

MN/MX is 0 to indicate the maximum mode
mode.

The 8086 generates INTA for interrupt The 8288 Bus Controller generates the interrupt
acknowledgment. acknowledgment signal (INTA).

The 8086 itself provides an ALE for the Because there are several processors, the 8288 bus
latch. controller provides ALE for the latch.

The system is more affordable. The system costs more money.

It is used for small systems. It is used for large systems.

The multiprocessor setup is not

The multiprocessor configuration is accepted.
supported.

----------------------------------------------------------------------------------------------------------------

Feature Minimum Mode Maximum Mode

Multiplexed bus
Bus width 8-bit

20-bit
Address bus width 20-bit
 Multiple bus control signals
Control signal Single bus control signal

Additional support chips

Fewer support chips
Additional support chips required
required

Supported
Coprocessor support Not supported

Maximum number of Up to 3
0
coprocessors

Required
Bus controller Not required

Required Required
Clock generator

Required
Data buffer Not required

External
Interrupt controller Built-in

Interrupt controller Not available Available

----------------------------------------------------------------------------------------------------------------

Feature Maximum Mode Minimum Mode

Bus Control 8086 acts as bus controller and 8086 does not act as a bus
manages the gadget bus. controller and relies on an external
bus controller.
Bus Requires an external bus controller Requires an external bus controller
Controller (e.G.8288) for bus arbitration and (e.G., 8284) for bus manage signal
manipulate sign generation. era and coordination.

Address Utilizes all 20 address traces for Utilizes handiest sixteen cope with
Lines extended reminiscence addressing. traces for limited reminiscence
addressing.

Data Lines Uses all 16 records strains for statistics Uses the handiest 16 data traces for
switch. facts switch.

Processor Supports a couple of processors for Designed for unmarried-processor

multiprocessor structures. systems.

System Full control over the device bus and Share management of the device
Control gadgets linked to it. bus with other gadgets.

System More complicated device design Simple gadget layout as bus

Complexity because of bus manipulation manager is treated by means of an
obligations and support chips. external bus controller.

Memory and Can get right of entry to a larger Limited reminiscence addressing
I/O memory space and accommodate extra and I/O options.
good sized I/O abilities.

System Cost Generally higher gadget value because Lower machine fee due to reduced
of extra support chips. complexity and less aid chips.

Typical Use Suitable for larger systems with Preferred for simpler systems with
more than one processor and sizable an unmarried processor and
memory/I/O requirements. restricted resource desires.