8259A PIC

PROGRAMMABLE INTERRUPT CONTROLLER

Y 8086, 8088 Compatible Y Single a 5V Supply (No Clocks)
Y MCS-80, MCS-85 Compatible Y Available in 28-Pin DIP and 28-Lead
Y Eight-Level Priority Controller PLCC Package
Y Expandable to 64 Levels
Y Programmable Interrupt Modes
Y Individual Request Mask Capability

a
The Intel 8259A Programmable Interrupt Controller handles up to eight
vectored priority interrupts for the CPU.It is cascadable for up to 64 vectored
priority interrupts without additional circuitry. It is packaged in a 28-pinDIP,
uses NMOS technology and requires a single 5V supply.
The 8259A is designed to minimize the software and real time overhead
in handling multi-level priority interrupts. It has several modes, permitting
optimization for a variety of system requirements.

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 82C59A Programmable Interrupt
Controller
„ Block diagram of the 82C59A

Block diagram and pin layout of the 82C59A

82C59A Programmable Interrupt

Controller
„ Internal architecture of the 82C59A

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„ Internal architecture of the 82C59A

™Eight functional parts of the 82C59A

• The data bus buffer
• The read/write logic
• The control logic
• The in-service register
• The interrupt-request register
• The priority resolver
• The interrupt-mask register
• The cascade buffer/comparator
8259A Pin Description
8-bit data bus:
The 8-bit data bus (𝐷7 − 𝐷0 ) allows the 8086-
* to send control words to the 8259A and read a status word from the 8259A.
* to send interrupt types to the 8086.
The eight data lines are always connected to the lower half of the 8086 data bus because the 8086
expects to receive interrupt types on lower 8-bit data lines.
𝑹𝑫, 𝑾𝑹 𝒂𝒏𝒅 𝑪𝑺:
The 𝑹𝑫 and 𝑾𝑹 inputs control data transfer when the device is selected by asserting its chip select
(𝑪𝑺) input low. Usually 𝑹𝑫 and 𝑾𝑹 pins are connected to the system 𝑹𝑫 and 𝑾𝑹 lines. 𝑪𝑺 may be
connected to address decoder’s output.
Address pin 𝑨𝟎 :
𝐴0 input of 8259A is used to select one of the two internal addresses in the device. This pin may be
connected to any of the system address lines.

7
Cascade lines (CAS2-CAS0):
The cascade lines (CAS2-CAS0) are used as outputs from the master to the slaves for cascading
multiple 8159As in a system. The master outputs a 3-bit slave identification number on these lines.
Each slave in a system is assigned a 3-bit ID as part of its initialization. Sending this 3-bit ID number
enables the slave.
Slave program/Enable buffer (𝐒𝐏/𝑬𝑵):
This pin is a dual function pin, when the 8259A is in buffered mode, this is an output that controls the
data bus transceivers in a large microprocessor based system. When the 8259A is not in the buffered
mode, this pin programs the device as a master (1) or a slave(0). When we use only one 8159A in our
system, the 𝐒𝐏/𝑬𝑵 pin is tied high (1).
INT Pin:
The interrupt output (INT) pin of 8259A is connected to the INTR pin on the microprocessor (8086)
when there is only one 8259A in the system. In a system with master and slaves, only master’s INT pin
is connected to 8086. The slave’s INT pins are connected to different IR pins of the master.
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Interrupt acknowledge (𝑰𝑵𝑻𝑨 ) pin:
This input pin of 8259A is connected to the 𝑰𝑵𝑻𝑨 output of the 8086.
Interrupt request inputs(𝐈𝐑𝟕 − 𝐈𝐑𝟎) :
The eight interrupt request inputs (IR7-IR0) are used to request an interrupt by the external devices in
case of single 8159A system. In case of multiple 8259A system these input pins (IR7-IR0) of the master
is connected to output INT pins of the slaves. Unused IR inputs should be tied to ground so that a noise
pulse can not accidentally cause an interrupt. An interrupt signal must remain high on an IR input until
after the falling edge of the first 𝑰𝑵𝑻𝑨 pulse.

9
Internal Block Diagram of 8259A
The Interrupt Request Register (IRR):
The IRR keeps track of which interrupt inputs are asking for service. If an interrupt input has an
interrupt signal on it, then the corresponding bit in the IRR will be set.

The In Service Register (ISR):

The ISR keeps track of which interrupt inputs are currently being serviced. For each input that is
currently being serviced, the corresponding bit will be set in the ISR.

The Priority Resolver:

The Priority Resolver acts as a “judge” that determines if and when an interrupt request on one of the
IR inputs gets serviced.

The interrupt Mask Register (IMR):

This register is used to disable (mask) or enable (unmask) individual interrupt inputs.
Each bit in this register corresponds to the interrupt input with the same number. We can
unmask an interrupt input by sending a command word with a 0 in the bit position that
corresponds to that input.

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 82C59A Programmable Interrupt
Controller (PIC)

„ Programming the 82C59A

™ Two types of command words are provided to program the

82C59A: the initialization command words (ICW) and the
operational command words (OCW).

™ ICW commands (ICW1, ICW2, ICW3, ICW4) are used to load

the internal control registers of the 82C59A to define the

basic configuration or mode in which it is used.

™ The OCW commands (OCW1, OCW2, OCW3) permit the

8088 or 8086 microprocessor to initiate variations in the

basic operating modes defined by the ICW commands.

™ The MPU issues commands to the 82C59A by initiating

output (I/O-mapped) or write (Memory-mapped) cycles.

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The initialization of the PIC is rather complicated because it has many possible operating
modes.
ThePIC’s operating mode is normally initialized by theBIOSwhen the system is booted.
We will only consider thestandard PIC operating used on the IBM PC and only asystem
with a single (master) PIC.

As we say before; 8259A accepts two types of command words generated

by the CPU:
Initialization Command Words (ICWs) and the Operation Command Words
(OCWs). The OCWs are the command words which command the 8259A to
operate in various interrupt modes.

These modes are:

a. Fully nested mode(FNM)
b. Special fully nested mode (SFNM)
c. Rotating priority mode
d. Special mask mode
e. Polled mode
The OCWs can be written into the 8259A anytime after initialization.
1- The initialization command words (ICWs):

82C59A Programmable Interrupt

Controller

ICW1

ICW2

NO (SNGL=1)
IN CASCADE
MODE ?
YES (SNGL=0)

ICW3

NO (IC4=0) IS ICW4
NEEDED ?
YES (IC4=1)

ICW4
Initialization sequence of
the ICWs in 82C59A
READY TO ACCEPT
INTERRUPT REQUESTS

Controller
„ Initialization command words
™ICW1

Bits ADI, A7, A6, A5 are don’t care for microprocessor operation and only
apply to the 8259A when used with an 8-bit 8085 microprocessor
 82C59A Programmable Interrupt
Controller
EXAMPLE
What value should be written into ICW1 in order to configure the
82C59A so that ICW4 is needed in the initialization sequence, the
system is going to use multiple 82C59As, and its inputs are to be
level sensitive? Assume that all unused bits are to be logic 0.
Solution:
Since ICW4 is to be initialized, D0 must be logic 1, D0 = 1
For cascaded mode of operation, D1 must be 0, D1 = 0
And for level-sensitive inputs, D3 must be 1, D3 = 1
Bits D2 and D5 through D7 are don’t-care states and are 0.
D2 = D5 = D6 = D7 = 0
Moreover, D4 must be fixed at the 1 logic level, D4 = 1
This gives the complete command word
D7D6D5D4D3D2D1D0 = 000110012 = 1916

82C59A Programmable Interrupt

Controller
„ Initialization command words
™ICW2 is used for type number determination

ICW2: Selects the vector number used with the interrupt request inputs. For example,
if we decide to program the 8259A so it functions at vector locations 08H0FH,
we place 08H in the command word

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 82C59A Programmable Interrupt
Controller
EXAMPLE
What should be programmed into register ICW2 if the type
numbers output on the bus by the device are to range from F016
through F716?

Solution:
To set the 82C59A up so that type numbers are in the range of F016
through F716, its device code bits must be
D7D6D5D4D3 = 111102
The lower three bits are don’t-care states and all can be 0s. This
gives the word
D7D6D5D4D3D2D1D0 = 111100002 = F016

82C59A Programmable Interrupt

Controller
Initialization command words
™ICW3 is required only for cascaded mode of
operation

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 82C59A Programmable Interrupt
Controller
EXAMPLE
Assume that a master PIC is to be configured so that its IR0
through IR3 inputs are to accept inputs directly from external devices,
but IR4 through IR7 are to be supplied by the INT outputs of slaves.
What code should be used for the initialization command word ICW3?
Solution:
For IR0 through IR3 to be configured to allow direct inputs from
external devices, bits D0 through D3 of ICW3 must be logic 0:
D3D2D1D0 = 00002
The other IR inputs of the master are to be supplied by INT outputs
of slaves. Therefore, their control bits must be all 1:
D7D6D5D4 = 11112
This gives the complete command word
D7D6D5D4D3D2D1D0 = 111100002 = F016

82C59A Programmable Interrupt

Controller
„ Initialization command words
™ ICW4 is used to configure device for use with the 8088 or
8086 and selects various features in its operation.

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 82C59A Programmable Interrupt
Controller
„ Operational command words
™OCW1 is used to access the contents of the
interrupt-mask register (IMR). Setting a bit to logic
1 masks out the associated interrupt input.

82C59A Programmable Interrupt

Controller
EXAMPLE
What should be the OCW1 code if interrupt inputs IR0 through
IR3 are to be masked and IR4 through IR7 are to be unmasked?
Solution:
For IR0 through IR3 to be masked, their corresponding bits in the
mask register must be make logic 1:
D3D2D1D0 = 11112
On the other hand, for IR4 through IR7 to be unmasked, D4 through
D7 must be logic 0:
D7D6D5D4 = 00002
This gives the complete command word
D7D6D5D4D3D2D1D0 = 000011112 = 0F16

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 82C59A Programmable Interrupt
Controller
„ Operational command words
™ OCW2 is used to select appropriate priority scheme and
assigns an IR level for the scheme.

L2 to L0 are used to describe

interrupt level on which action
need to be performed.

82C59A Programmable Interrupt

Controller
EXAMPLE
What OCW2 must be issued to the 82C59A if the priority
scheme rotate on nonspecific EOI command is to be selected?

Solution:
To enable the rotate on nonspecific EOI command priority scheme,
bits D7 through D5 must be set to 101. Since a specific level does
not have to be considered, the rest of the bits in the command word
can be 0. This gives OCW2 as

D7D6D5D4D3D2D1D0 = 101000002 = A016

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82C59A Programmable Interrupt
Controller
„ Operational command words
™ OCW3 permits reading of the contents of the ISR or IRR
registers through software.

82C59A Programmable Interrupt

Controller
EXAMPLE
Write a program that will initialize an 82C59A with the
initialization command words ICW1, ICW2, ICW3 derived in the
previous examples, and ICW4 is equal to 1F16. Assume that the
82C59A resides at address A00016 in the memory address space.
Solution:
Since the 82C59A resides in the memory address space, we can
use a series of move instructions to write the initialization command
words into its registers. Note that the memory address for an ICW is
A00016 if A0 = 0, and it is A00116 if A0 = 1. However, before doing
this, we must first disable interrupts. This is done with the instruction

CLI ; Disable interrupts

 82C59A Programmable Interrupt
Controller
Next we will create a data segment starting at address 0000016:
MOV AX, 0 ;Create a data segment at 00000H
MOV DS, AX
Now we are ready to write the command words to the 82C59A:
MOV AL, 19H ;Load ICW1
MOV [0A000H], AL ;Write ICW1 to 82C59A
MOV AL, 0F0H ;Load ICW2
MOV [0A001H], AL ;Write ICW2 to 82C59A
MOV AL, 0F0H ;Load ICW3
MOV [0A001H], AL ;Write ICW3 to 82C59A
MOV AL, 1FH ;Load ICW4
MOV [0A001H], AL ;Write ICW4 to 82C59A
Initialization is now complete and the interrupts can be enabled
STI ;Enable interrupts

Interrupt Interface Circuits Using the

82C59A

Minimum-mode interrupt interface for the 8088 microcomputer using the 82C59A

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 8259A Operating Modes:

1. Fully nested mode :

• It is the default mode of operation of 8259.

• Here, IR0 has the highest priority and IR 7 has the

lowest priority.
• It is suitable for a single 8259 configuration.

• This mode offers simple prioritization but can lead to

starvation for lower-priority interrupts, especially when

high-priority ones take a long time to service.

2. Special fully nested mode (SFNM) :

This mode only used by the master 8259 in a
cascaded configuration.
Shares the same fixed priority scheme as fully nested
mode (IRQ0 highest, IRQ7 lowest).
When a lower-priority interrupt from a slave arrives
while a higher-priority interrupt from the same slave is
already being serviced, it is not ignored.
Instead, the master acknowledges the new interrupt but
keeps it pending until the higher-priority one is finished.
After servicing the higher-priority interrupt, the master
serves the pending one, effectively nesting interrupts
from the same slave.
This mode guarantees that multiple interrupts from the
same source are served in their order of arrival, even if
they have the same priority level.
 3. Priority modes :
There are two rotating priority modes –
1. Automatic rotation mode
• In this mode, after a device is serviced, it gets the

lowest priority.
• All other priorities rotate according to it.

• Example: If IR4 has just been serviced, it will get

the lowest priority.

2. Specific Rotation Mode
• Here, the programmer can alter priorities by

programming the lowest priority and thus fixing

all other priorities.
• For example: If IR6 is programmed as the lowest

priority, then IR7 will have the highest priority.

4. Special mask mode (SMM) :

The Special Mask Mode (SMM) in the 8259 PIC is a
temporary interrupt handling mode used in cascaded
configurations. Its primary purpose is to prevent
starvation of lower-priority interrupts while a higher-
priority one is being serviced.

It works as follows:

SMM enables all interrupts except the one currently

being serviced (regardless of its priority).
This effectively "masks" the current interrupt level,
preventing additional requests from the same source.
However, other interrupt sources (even lower priority
ones) can still request service.
Once the current interrupt is finished, the masked level
becomes active again, allowing pending requests to be
processed in their order of arrival.

5. Poll mode :
Poll mode in the 8259 (Programmable Interrupt
Controller) is an alternative way for the
microprocessor (μP) to manage interrupts instead of
relying on their automatic delivery via interrupt lines.
Here's a brief explanation:
The μP actively queries the 8259 using a specific
command ("poll command") via OCW3 instead of
passively waiting for an interrupt signal.
In response, the 8259 sends a "poll word" back to the
μP, indicating the highest-priority pending interrupt (if
any).
The μP then identifies the source of the interrupt and
proceeds to service it.

➢ EOI – (End Of Interrupt) :

When the microprocessor acknowledges an
 interrupt request by sending the first INTA
signal, the 8259 sets the corresponding bit in
the In Service Register (ISR). This starts the
service of the interrupt.
When this bit in the ISR is cleared, then it is
known as the end of interrupt (EOI).
EOI Modes:
1. Normal EOI Mode –
a "normal EOI" (End Of Interrupt) is a command sent by
the microprocessor to signify the completion of an
interrupt service routine (ISR). Sending the EOI command
clears the corresponding bit in the 8259's In-Service
Register (ISR), indicating that the interrupt has been
handled and the PIC can move on.
Further EOI command is of two types :
• Non Specific EOI Command Here the

programmer doesn’t specify the bit number to be

reset in the ISR. 8259 itself resets the highest
priority bit from ISR.
• Specific EOI Command: Here the programmer

determines the bit number to be reset from ISR.

2. Automatic EOI mode (AEOI) –
In this mode, the EOI command is not required. Instead,
8259 will itself clear the corresponding bit from ISR at
the end of the 2nd INTA pulse.
➢ Buffered Mode :
Buffered Mode in the 8259 PIC (Programmable
Interrupt Controller) aims to improve
communication efficiency between the 8259 and
the microprocessor (μP) during data
transfer.
8259 sends a "buffer enabled" signal (SP'/EN' pin) to the
μP when data is placed on the data bus.
This will enables faster data transfer between the 8259
and the μP compared to Non-Buffered Mode.
Reduces wait states and improves overall system
performance.

How it works:

When the 8259A is used in a large system where bus

driving buffers are required on the data bus and the
cascading mode is used, there exists the problem of
enabling buffers. The buffered mode will structure the
8259A to send an enable signal on SP/EN to enable the
buffers. In this mode, whenever the 8259A's data bus
outputs are enabled, the SP/EN output becomes active.

However, this requires additional hardware connections

(SP'/EN' pin).
Only affects communication speed, not overall interrupt
priority handling.
Interrupt Interface Circuits Using the
82C59A

EXAMPLE
Analyze the circuit in the following figure and write an
appropriate main program and a service routine that counts as a
decimal number the positive edges of the clock signal applied to the
IR0 input of the 82C59A.

Interrupt Interface Circuits Using the

82C59A
Solution:
Lets first determine the I/O addresses of the 82C59A registers:
A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0
= 11111111000000002 for A1 = 0, M/IO = 0 and
= 11111111000000102 for A1 = 1, M/IO = 0
These two I/O addresses are FF00H and FF02H, respectively. The
address FF00H is for the ICW1 and FF02H is for the ICW2, ICW3,
ICW4, and OCW1 command words.
The command words are:
ICW1 = 000100112 = 13H
ICW2 = 010010002 = 48H
ICW3 = not needed
ICW4 = 000000112 = 03H
OCW1 = 111111102 = FEH

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Interrupt Interface Circuits Using the 82C59A

Software organization:
 Interrupt Interface Circuits Using the
82C59A
Flowcharts of the main program and service routine:
Main Program SRV72
Set up data segment,
Save processor
stack segment, and
status
stack pointer

Set up the Increment

interrupt vector the count

Initialize Restore processor

82C59A status

Enable interrupts Return

Wait for
interrupt

the 82C59A
Program:
;MAIN PROGRAM
CLI ;Start with interrupt disabled
START: MOV AX, 0 ;Extra segment at 00000H
MOV ES, AX
MOV AX, 1000H ;Data segment at 01000H
MOV DS, AX
Note:
Victore type=72 MOV AX, 0FF00H ;Stack segment at 0FF00H
72 x 4 = 288 = 120H MOV SS, AX
MOV SP, 100H ;Top of stack at 10000H

MOV AX, OFFSET SRV72 ;Get offset for SRV72

MOV [ES:120H], AX ;Set up the IP
MOV AX, SEG SRV72 ;Get CS for the service routine
MOV [ES:122H], AX ;Set up the CS

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 Interrupt Interface Circuits Using
the 82C59A
Program:

MOV DX, 0FF00H ;ICW1 address

MOV AL, 13H ;Edge trig input, single 8259A
OUT DX, AL
MOV DX, 0FF02H ;ICW2, ICW4, OCW1 address
MOV AL, 48H ;ICW2, type 72
OUT DX, AL
MOV AL, 03H ;ICW4, AEOI, nonbuf mode
OUT DX, AL
MOV AL, 0FEH ;OCW1, mask all but IR0
OUT DX, AL
STI ;Enable the interrupts

Interrupt Interface Circuits Using the

82C59A
Program:

SRV72: PUSH AX ;Save register to be used

MOV AL, [COUNT] ;Get the count
INC AL ;Increment the count
DAA ;Decimal adjust the count
MOV [COUNT], AL ;Save the new count
POP AX ;Restore the register used
IRET ;Return from interrupt
 Software Interrupts
„ The 8088 and 8086 microcomputer systems are
capable of implementing up to 256 software
interrupts.
„ The INT n instruction is used to initiate a software
interrupt. The software interrupt service routine
vectors are also located in the memory locations in
the vector table.
„ Software interrupts are of higher priority than the
external interrupts and are not masked out by IF.
„ The software interrupts are actually vectored
subroutine calls.

Nonmaskable Interrupt
„ The nonmaskable interrupt (NMI) is initiated from external
hardware.
„ Differences between NMI and other external interrupts:
™ NMI can not be masked out with the interrupt flag.
™ Request for NMI service are signaled to the 8088/8086
microprocessor by applying logic 1 at the NMI input, not the
INTR input.
™ NMI input is positive edge-triggered. Therefore, a request for
NMI is automatically latched internal to the MPU.
„ NMI automatically vectors from the type 2 vector location
in the pointer table (000816 ~000A16)
„ Typically, the NMI is assigned to hardware events that
must be responded to immediately, such power failure.

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Reset
„ The RESET input of the 8088 and 8086
microprocessors provides a hardware means for
initializing the microcomputer.

Reset interface and timing sequence of the 8088

Reset
„

8088 signal status 8086 signal status

Bus and control signal status of the 8088/8086 during system reset

30
Reset
„ When the MPU recognizes the RESET input, it
initiates its internal initialization routine. At completion
of initialization, the flags are all cleared, the registers
are set to the values in the following table.
CPU COMPONENT CONTENT
Flags Clear
Instruction pointer 0000H
CS Register FFFFH
DS Register 0000H
SS Register 0000H
ES Register 0000H
Queue Empty

Reset
„ The external hardware interrupts are disabled after
the initialization.
„ Program execution begins at address FFFF016 after
reset. This storage location contains an instruction
that will cause a jump to the startup (boot-strap)
program that is used to initialize the reset of the
microcomputer system’s resources, such as I/O ports,
the interrupt flag, and data memory.
„ After the system-level initialization is complete,
another jump can be performed to the starting point
of the microcomputer’s operating system or
application program.

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Internal Interrupt Functions
„ Four of the 256 interrupts of the 8088 and 8086 are
dedicated to internal interrupt functions.
„ Internal interrupts differ from external hardware
interrupts in that they occur due to the result of
executing an instruction, not an event that takes
place in external hardware.
„ Internal interrupts are not masked out with IF flag.
„ Internal interrupts of the 8088 and 8086 MPU:
™ Divide error (Type number 0)
™ Single step (Type number 1)
™ Breakpoint interrupt (Type number 3)
™ Overflow error (Type number 4)

Internal Interrupt Functions

„ Internal interrupt vector locations

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