Double Data Rate 3

DDR3

- Naveen Kumar
Double Data Rate (DDR)

• DDR define the High speed data transfer between memory controller
and memory Module.
• DDR protocol allow for data to be tarnsfered on both the rising &
falling edge of the signals.
• This dobles the data transfer rate over single data protocol.

- Naveen Kumar
Features
• VDD = VDDQ = 1.5V ±0.075V(VDD-Supply voltage for Digital circuit in chip)
• VDDQ 1.5V center-terminated push/pull I/O (VDDQ-voltage for I/O circuit)
• 8n-bit prefetch architecture(Redunce the Latency)
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• Multipurpose register

- Naveen Kumar
8n Prefetch
• DDR protocol support an 8n prefetch architecture.
• This is mean memory controller can prefetch 8 data words at a time, which reduce latancy of
memory access.

On-Die-Termination
• To improve signal integrity
• This is reduce the need for extranal termination register, which save space and power.

Fly-by-topology
• DDR protocol uses a FBT topology to reduce signal skew.
• Efficient transfer data between the memory controller and memory modules.

- Naveen Kumar
APPLICATIONS
• Higher Speed Data transfer rate (double clk freq, no. of data transfered per clk)
• Low Power Consumption(Reducing voltage from 1.8v to 1.5v)
• Improved signal Integrity(High Speed Data transfer)

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Industrial Temperature
• The industrial temperature (IT) device requires that the case
temperature not exceed –40°C or 95°C.
• JEDEC specifications require the refresh rate to double when TC
exceeds 85°C;
• Additionally, ODT resistance and the input/output impedance must be
derated when TC is < 0°C or >95°C.

- Naveen Kumar
• Row address is denoted as,
Example:
1Gb: n = 12 (x16); 1Gb: n = 13 (x4, x8);
2Gb: n = 13 (x16) and 2Gb: n = 14 (x4, x8);
4Gb: n = 14 (x16); and 4Gb: n = 15 (x4,x8).

- Naveen Kumar
Functional Description
• DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.
• The double data rate architecture is an 8n-prefetch architecture with an interface designed
to transfer two data words per clock cycle at the I/O pins.
• A single read or write operation for the DDR3 SDRAM effectively consists of a single
8n-bit-wide, four-clockcycle data transfer at the internal DRAM core and eight
corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins.

- Naveen Kumar
DQS, DQS#
• Data strobe is transmitted externally along with data for use in data capture at
DDR3 SDRAM input receiver.
• DQS is center-aligned with data for WRITEs.
• DQS is Edge-aligned with data for Read data.

CK and CK#
• CK - Positive edge of the clock (HIGH)
• CK#- Negative Edge of the clock(LOW)
• Control ,Command and address signal are regitered at every positive edge of CK.
• Input data is registered on the first rising edge of DQS after the WRITE preamble.
• Output data is referenced on the first rising edge of DQS after the READ
preamble.

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• Registered ACTIVATE command - then followed by WRITE or WRITE
command.
• Address bits are registered with the ACTIVATE command used to
select the bank and row to be accessed.
• Address bits are registered with READ or WRITE command are used to
select the bank and starting column location for burst Access.
• The device uses a READ and WRITE BL8 and BC4.
• Self-Refresh mode is provided, along with power saving and power-
down mode.

- Naveen Kumar
 CKE(clock Enable)
• CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and
clocks on the DRAM.
• Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all banks idle), or CKE HIGH power-down (row active in any bank).
• CKE is synchronous for power-down entry and exit and for self refresh entry.
• CKE is asynchronous for self refresh exit.
• Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
POWER-DOWN.
• Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH.

- Naveen Kumar
Input Output Capacitance
• 1. VDD = 1.5V ±0.075mV, VDDQ = VDD, VREF = VSS, f = 100 MHz, TC = 25°C. VOUT(DC) = 0.5 ×
• VDDQ, VOUT = 0.1V (peak-to-peak).
• 2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.
• 3. Includes TDQS, TDQS#. CDDQS is for DQS vs. DQS# and TDQS vs. TDQS# separately.
• 4. CDIO = CIO(DQ) - 0.5 × (CIO(DQS) + CIO(DQS#)).
• 5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR =
• A[n:0], BA[2:0].
• 6. CDI_CTRL = CI(CTRL) - 0.5 × (CCK(CK) + CCK(CK#)).
• 7. CDI_CMD_ADDR = CI(CMD_ADDR) - 0.5 × (CCK(CK) + CCK(CK#)).

- Naveen Kumar
Mode Register
• Mode registers (MR0–MR3) are used to define various modes of
programmable operations of the DDR3 SDRAM.
• A mode register is programmed via the mode register set(MRS) command
during initialization, and it retains the stored information (except for MR0[8],
which is self-clearing) until it is reprogrammed, RESET# goes LOW, the
device loses power.
• The MRS command can only be issued (or re-issued) when all banks are idle
and in the precharged state (tRP is satisfied and no data bursts are in progress).
• After an MRS command has been issued, two parameters must be satisfied:
tMRD and tMOD. The controller must wait tMRD before initiating any
subsequent MRS commands.
- Naveen Kumar
• 1. Prior to issuing the MRS command, all banks must be idle and
precharged, tRP (MIN) must be satisfied, and no data bursts can be in
progress.
• 2. tMRD specifies the MRS to MRS command minimum cycle time.
• 3. CKE must be registered HIGH from the MRS command until tMRSPDEN
(MIN) (see Power-Down Mode.
• 4. For a CAS latency change, tXPDLL timing must be met before any non-
MRS command.

- Naveen Kumar
• 1. Prior to issuing the MRS command, all banks must be idle (they must be
precharged, tRP must be satisfied, and no data bursts can be in progress).
• 2. Prior to Ta2 when tMOD (MIN) is being satisfied, no commands (except
NOP/DES) may by issued.
• 3. If RTT was previously enabled, ODT must be registered LOW at T0 so that
ODTL is satisfied prior to Ta1. ODT must also be registered LOW at each
rising CK edge from T0 until tMODmin is satisfied at Ta2.
• 4. CKE must be registered HIGH from the MRS command until tMRSPDEN
(MIN), at which time power-down may occur (see Power-Down Mode .

- Naveen Kumar
Mode Register 0(MR0)

• The base register, MR0, is used to define various DDR3 SDRAM modes of
operation.
• These definitions include the selection of a burst length, burst type, CAS
latency, operating mode, DLL RESET, write recovery, and precharge power-
down mode.

- Naveen Kumar
Burst Length

• Burst length is defined by MR0[1: 0].

• Read and write accesses to the DDR3 SDRAM are burst-oriented, with the burst length
being programmable to 4 (chop mode), 8 (fixed), or selectable using A12 during a
READ/WRITE command (on-the-fly).
• The burst length determines the maximum number of column locations that can be
accessed for a given READ or WRITE command.
• When MR0[1:0] is set to 01 during a READ/WRITE command, if A12 = 0, then BC4
(chop) mode is selected. If A12 = 1, then BL8 mode is selected.
• Specific timing diagrams, and turnaround between READ/WRITE, are shown in the
READ/WRITE sections of this document.
- Naveen Kumar
Burst Type

• Accesses within a given burst may be programmed to either a

sequential or an interleaved order.
• The burst type is selected via MR0[3] .
• The ordering of accesses within a burst is determined by the burst
length, the burst type, and the starting column address.
• DDR3 only supports 4-bit burst chop and 8-bit burst access modes.
• Full interleave address ordering is supported for READs, while
WRITEs are restricted to nibble (BC4) or word (BL8) boundaries.
- Naveen Kumar
 1. Internal READ and WRITE operations start at the same point in time for BC4 as they do
for BL8.
2. Z = Data and strobe output drivers are in tri-state.
3. V = A valid logic level (0 or 1), but the respective input buffer ignores level-on input
pins.
4. X = “Don’t Care.”
- Naveen Kumar
DLL Reset

• MR0[8] is self-clearing, meaning it returns to a value of 0 after the DLL

RESET function has been initiated.
• Anytime the DLL RESET function is initiated, CKE must be HIGH and the
clock held stable for 512 (tDLLK) clock cycles before a READ command can
be issued.
• Failing to wait for synchronization to occur may result in invalid output timing
specifications, such as tDQSCK timings.

- Naveen Kumar
Write Recovery
• WRITE recovery time is defined by MR0[11:9].
• Write recovery values of 5, 6, 7, 8, 10, or 12 may be used by
programming MR0[11:9].
• The user is required to program the correct value of write recovery
and is calculated by dividing tWR (ns) by tCK (ns) and rounding up a
noninteger value to the next integer:
WR (cycles) = roundup (tWR [ns]/tCK [ns]).
Precharge Power Down

• The precharge PD bit applies only when precharge power-down mode

is being used.
• When MR0[12] is set to 0, the DLL is off during precharge power-
down providing a lower standby current mode.
• MR0[12] is set to 1, the DLL continues to run during precharge
power-down mode to enable a faster exit of precharge power-down
mode.
CAS Latency(CL)

• The CL is defined by MR0[6:4].

• CAS latency is the delay, in clock cycles, between the internal READ
command and the availability of the first bit of output data.
• The CL can be set to 5, 6, 7, 8, 9, or 10.
• DDR3 SDRAM do not support half-clock latencies.
• Examples of CL = 6 and CL = 8 are shown below.
• If an internal READ command is registered at clock edge n, and the CAS
latency is m clocks, the data will be available nominally coincident with clock
edge n + m.
• See the Speed Bin Tables for the CLs supported at the various operating
frequencies.
Mode Register 1(MR1)

• The mode register 1 (MR1) controls additional functions and features not available in the
other mode registers:
• Q OFF (OUTPUT DISABLE).
• TDQS (for the x8 configurationonly).
• DLL ENABLE/DLL DISABLE.
• RTT.
• nom value (ODT).
• WRITE LEVELING.
• POSTED CAS ADDITIVE latency, and OUTPUT DRIVE STRENGTH.
- Naveen Kumar
• The function are controlled via bits.
• The MR1 register is programmed via Mode register set(MRS) command,
retains the stored information until it is reprogrammed, until RESET#
goes LOW, or until the device loses power.
• Reprogramming the MR1 register will not alter the contents of the
memory array, provided it is performed correctly.
• The MR1 register must be loaded when all banks are idle and no bursts
are in progress.
• The controller must satisfy the specified timing parameters tMRD and
tMOD before initiating a subsequent operation.
DLL Enable/Disable
• The DLL may be enabled or disabled by programming MR1[0] during the LOAD
MODE command.
• DLL enable - power-up initialization and upon returning to Normal operation.
• DLL Disable - DLL for the purpose of debugging or evaluation.
• Enabling the DLL should always be followed by resetting the DLL using the
appropriate LOAD MODE command.
• DLL Enable - Entering the self refresh mode.
• DLL Automatically Disable - Entering SELF REFRESH operation and is
automatically reenabled and reset upon exit of SELF REFRESH operation.
* ODT is not allowed to be used
* The output data is no longer edge-aligned to the clock
* CL and CWL can only be six clocks
Output Drive Strength(ODT)
• The drive strength mode register setting is defined by MR1[5, 1].
• RZQ/7 (34Ω [NOM]) is the primary output driver impedance setting for DDR3 SDRAM devices.
• RZQ/7 (34Ω [NOM]) is the primary output driver impedance setting for DDR3 SDRAM devices
• To calibrate the output driver impedance, an external precision resistor (RZQ) is connected between the
ZQ ball and VSSQ.
• The value of the resistor must be 240Ω ±1%.
• The output impedance is set during initialization.
• To meet the 34Ω specification, the output drive strength must be set to 34Ω during initialization.
• To obtain a calibrated output driver impedance after power-up, the DDR3 SDRAM needs a calibration
command that is part of the initialization and reset procedure.
OUTPUT Enable/Disable
• The OUTPUT ENABLE function is defined by MR1[12].
• When enabled (MR1[12] = 0) - all outputs (DQ, DQS, DQS#)
function when in the normal mode of operation.
• When disabled (MR1[12] = 1) - all DDR3 SDRAM outputs (DQ and
DQS, DQS#) are tri-stated(Three state).
• The output disable feature is intended to be used during IDD
characterization of the READ current and during tDQSS margining
(write leveling) only.
Termination Data Strobe(TDQS)
• Termination data strobe (TDQS) is a feature of the x8 DDR3 SDRAM
configuration that provides termination resistance (RTT) and may be useful in
some system configurations.
• TDQS is not supported in x4 or x16 configurations.
• When enabled via the mode register (MR1[11]), the RTT that is applied to
DQS and DQS# is also applied to TDQS and TDQS#.
• The OUTPUT DATA STROBE function of RDQS is not provided by TDQS;
thus, RON does not apply to TDQS and TDQS#.
• When the TDQS function is enabled via the mode register, the DM function is
not supported.
• When the TDQS function is disabled, the DM function is provided and and the
TDQS# ball is not used.
On-Die-Termination
• ODT resistance RTT,nom is defined by MR1[9, 6, 2].
• The RTT termination value applies to the DQ, DM, DQS, DQS#, and TDQS, TDQS#
balls.
• DDR3 supports multiple RTT termination values based on RZQ/n where n can be 2, 4, 6,
8, or 12 and RZQ is 240Ω.
• RTT,nom termination is allowed any time after the DRAM is initialized, calibrated, and
not performing read access, or when it is not in self refresh mode.
• Additionally, write accesses with dynamic ODT enabled (RTT(WR)) temporarily replaces
RTT,nom with RTT(WR).
• The ODT feature is designed to improve signal integrity of the memory channel by
enabling the DDR3 SDRAM controller to independently turn on/off ODT for any or all
devices.
• The ODT input control pin is used to determine when RTT is turned on (ODTL on) and
off (ODTL off), assuming ODT has been enabled via MR1[9, 6, 2].
Write leveling
• The WRITE LEVELING function is enabled by MR1[7].
• Write leveling is used (during initialization) to deskew the DQS strobe
to clock offset as a result of fly-by topology designs.
• DDR3 SDRAM memory modules adopted fly-by topology for the
commands, addresses, control signals, and clocks.
• fly-by topology benefits from a reduced number of stubs and their
lengths.
• fly-by topology induces flight time skews between the clock and DQS
strobe (and DQ) at each DRAM on the DIMM.
POSTED CAS ADDITIVE Latency
• POSTED CAS ADDITIVE latency (AL) is supported to make the command and data bus.
• MR1[4, 3] define the value of AL .
• MR1[4, 3] enable the user to program the DDR3 SDRAM with AL = 0, CL - 1, or CL - 2.
• DDR3 SDRAM enables a READ or WRITE command to be issued after the ACTIVATE
command for that bank prior to tRCD (MIN).
• The only restriction is ACTIVATE to READ or WRITE + AL ≥ tRCD (MIN) must be
satisfied.
• Assuming tRCD (MIN) = CL, a typical application using this feature sets AL = CL - 1tCK
= tRCD (MIN) - 1tCK.
• READ latency (RL) is controlled by the sum of the AL and CAS latency (CL), RL = AL +
CL.
• WRITE latency (WL) is the sum of CAS WRITE latency and AL, WL = AL + CWL.
Mode Register2(MR2)
• The mode register 2 (MR2) controls additional functions and features not available in the
other mode registers.
• Additional functions are CAS WRITE latency (CWL), AUTO SELF REFRESH (ASR),
SELF REFRESH TEMPERATURE (SRT), and DYNAMIC ODT (RTT(WR)).
• These functions are controlled via the bits.
• The MR1 register is programmed via the MRS command and retains the stored
information until it is reprogrammed, until RESET# goes LOW, or until the device loses
power.
• Reprogramming the MR1 register will not alter the contents of the memory array,
provided it is performed correctly.
• The MR1 register must be loaded when all banks are idle and no bursts are in progress.
• The controller must satisfy the specified timing parameters tMRD and tMOD before
initiating a subsequent operation. - Naveen Kumar
CAS Write Latency(CWL)

• CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing
of the internal write to the latching of the first data in.
• CWL must be correctly set to the corresponding operating clock frequency.
• The overall WRITE latency (WL) is equal to CWL + AL .
Auto Self Refresh(ASR)

• Mode register MR2[6] is used to disable/enable the ASR function.

• When ASR is disabled, the self refresh mode’s refresh rate is assumed
to be at the normal 85°C limit (sometimes referred to as 1x refresh
rate).
• Enabling ASR assumes the DRAM self refresh rate is changed
automatically from 1x to 2x when the case temperature exceeds 85°C.
• This enables the user to operate the DRAM beyond the standard 85°C
limit up to the optional extended temperature range of 95°C while in
self refresh mode.
Self Refresh Temperature(SRT)

• Mode register MR2[7] is used to disable/enable the SRT function.

• When SRT is disabled, the self refresh mode’s refresh rate is assumed to be at the
normal 85°C limit (sometimes referred to as 1x refresh rate).
• This enables the user to operate the DRAM beyond the standard 85°C limit up to
the optional extended temperature range of 95°C while in self refresh mode.
• The standard self refresh current test specifies test conditions to normal case
temperature (85°C) only, meaning if SRT is enabled, the standard self refresh
current specifications do not apply.
Dynamic ODT

• The dynamic ODT (RTT(WR)) feature is defined by MR2[10, 9].

• Dynamic ODT is enabled when a value is selected.
• This new DDR3 SDRAM feature enables the ODT termination value to change
without issuing an MRS command, essentially changing the ODT termination on-the-
fly.
• With dynamic ODT (RTT(WR)) enabled, the DRAM switches from normal ODT
(RTT,nom) to dynamic ODT (RTT(WR)) when beginning a WRITE burst and
subsequently switches back to ODT (RTT,nom) at the completion of the WRITE
burst.
• If RTT,nom is disabled, the RTT,nom value will be High-Z. Special timing parameters
must be adhered to when dynamic ODT (RTT(WR)) is enabled: ODTLcnw,
ODTLcnw4, ODTLcnw8, ODTH4, ODTH8, and tADC.
Mode Register3(MR3)

• The mode register 3 (MR3) controls additional functions and features not available in
the other mode registers.
• Currently defined is the MULTIPURPOSE REGISTER (MPR).
• This function is controlled via the bits.
• The MR3 is programmed via the LOAD MODE command and retains the stored
information until it is programmed again or until the device loses power.
• Reprogramming the MR3 register will not alter the contents of the memory array,
provided it is performed correctly.
• The MR3 register must be loaded when all banks are idle and no data bursts are in
progress, and the controller must wait the specified time tMRD and tMOD before
initiating a subsequent operation.
Multipurpose Regiter(MPR)

• The MULTIPURPOSE REGISTER function is used to output a predefined system timing

calibration bit sequence.
• Bit 2 is the master bit that enables or disables access to the MPR register, and bits 1 and 0
determine which mode the MPR is placed in.
• The basic concept of the multipurpose register.
• If MR3[2] is a 0, then the MPR access is disabled, and the DRAM operates in normal
mode.
• However, if MR3[2] is a 1, then the DRAM no longer outputs normal read data but
outputs MPR data as defined by MR3[0, 1].
• If MR3[0, 1] is equal to 00, then a predefined read pattern for system calibration is
selected.
• To enable the MPR, the MRS command is issued to MR3, and MR3[2] = 1.
• Prior to issuing the MRS command, all banks must be in the idle state (all banks are
precharged, and tRP is met).
• When the MPR is enabled, any subsequent READ or RDAP commands are
redirected to the multipurpose register.
• The resulting operation when either a READ or a RDAP command is issued, is
defined by MR3[1:0] when the MPR is enabled.
• When the MPR is enabled, only READ or RDAP commands are allowed until a
subsequent MRS command is issued with the MPR disabled (MR3[2] = 0).
• Power-down mode, self refresh, and any other nonREAD/RDAP commands are
not allowed during MPR enable mode.
• The RESET function is supported during MPR enable mode.
MPR Functional Description

• The MPR JEDEC definition enables either a prime DQ (DQ0 on a x4 and a x8; on
a x16, DQ0 = lower byte and DQ8 = upper byte) to output the MPR data with the
remaining DQs driven LOW, or for all DQs to output the MPR data.
• fixed READ burst and READ burst chop (MRS and OTF via A12/BC#) with
regular READ latencies and AC timings applicable, provided the DLL is locked as
required.
MPR addressing for a valid MPR read is as follows:
• A[1:0] must be set to 00 as the burst order is fixed per nibble
• A2 selects the burst order:
– BL8, A2 is set to 0, and the burst order is fixed to 0, 1, 2, 3, 4, 5, 6, 7
• For burst chop 4 cases, the burst order is switched on the nibble base along with the following:
– A2 = 0; burst order = 0, 1, 2, 3
– A2 = 1; burst order = 4, 5, 6, 7
Burst order bit 0 (the first bit) is assigned to LSB, and burst order bit 7 (the last bit) is
• assigned to MSB
• A[9:3] are a “Don’t Care”
• A10 is a “Don’t Care”
• A11 is a “Don’t Care”
• A12: Selects burst chop mode on-the-fly, if enabled within MR0
• A13 is a “Don’t Care”
• BA[2:0] are a “Don’t Care”
MPR Register Address Definitions and Bursting Order

• The MPR currently supports a single data format. This data format is a
predefined read pattern for system calibration. The predefined
pattern is always a repeating 0–1 bit pattern.
Note:(Fig 59)
• 1. READ with BL8 either by MRS or OTF.
• 2. Memory controller must drive 0 on A[2:0].