ECE2007-DIGITAL DESIGN

Dr. MANIKANDAN
Department of ECE, School of Engineering,
Presidency University, Bengaluru

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 MODULE – 1
Boolean function simplification

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 What is DIGITAL DESIGN (DD)?
Digital means - 0, 1
Logic means - Ideas
Design means – Process or Method or
Procedure
How to define DD now?
Digital Design is the process of combining
ideas using 0’s and 1’s for a particular
application.

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 Number Systems
Decimal System (10 values)
Values are 0,1,2,3,4,5,6,7,8,9
Binary System (2 values)
Values are 0,1
Octal System (8 values)
Values are 0,1,2,3,4,5,6,7
Hexadecimal System
Values are 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
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REPRESENTATION IN DIFFERENT NUMBER SYSTEMS

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 DECIMAL NUMBER
Eg:1. 7654
7X103 + 6X102 + 5X101 + 4X100
(7654)10

Eg:2. (.327)10
3X10-1 + 2X10-2 + 7X10-3

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 BINARY SYSTEM
BI – Two Values 0 and 1
Eg:1. (101)2
1X22 + 0X21 + 1X20
1X4 + 0X2 + 1X1 = 4+0+1 = (5)10
Eg:2. (.011)2
• 0X2-1 + 1X2-2 + 1X2-3
0X0.5 + 1X0.25 + 1X0.125
0+0.25+0.125 = 0.375 = (.375)10

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LINKS FOR NUMBER CONVERSIONS
Number System Conversions
https://www.youtube.com/watch?v=aW3qCcH6
Dao

https://www.youtube.com/watch?v=kAnBaQoJk
po

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 Boolean Algebra (BA)
• Invented by George Boole
• BA is a system for combining two-valued
decision states and arriving at a two-valued
outcome.
• Initially used in Electrical Switching which lead
to Telephone Networks and then in digital
circuits.
• For Binary System, BA was suitable.

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 Terminologies in LOGIC GATES
TRUE, FALSE
Gates
Logic Symbols
Boolean Expression
Truth Table
Logic Diagram
Complement
IC Numbers

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 Logic Gates

NOT Gate (or) INVERTER Gate

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 LOGIC GATES EXPLAINED

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 LOGIC GATES EXPLAINED

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BOOLEAN FUNCTIONS (OR) SWITCHING
FUNCTIONS

F1 = X + Y’Z
F2 = X’Y’Z + X’YZ + XY’

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DERIVING LOGIC DIAGRAM FROM BOOLEAN FUNCTIONS

 F1 = X + Y’Z

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 DERIVING LOGIC DIAGRAM FROM BOOLEAN FUNCTIONS

 F2 = X’Y’Z + X’YZ + XY’

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 DERIVING TRUTH TABLE FROM
BOOLEAN FUNCTIONS

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 PRACTISES

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 PRACTISES

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 BINARY CODES

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 GRAY CODE

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 FORMS IN BOOLEAN FUNCTIONS
TWO FORMS OF BOOLEAN FUNCTIONS
CANONICAL FORM
STANDARD FORM
LITERALS

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 CANONICAL FORM
 MIN TERMS  MAX TERMS
 AND GATE IS USED  OR GATE IS USED
 REPRESENTED BY “m”  REPRESENTED BY “M”
 SYMBOL IS “”  SYMBOL IS “π”
 ‘0’ AS PRIMED  ‘0’ AS UNPRIMED
(COMPLEMENT) (DIRECT)
 ‘1’ AS UNPRIMED  ‘1’ AS PRIMED
(DIRECT ) (COMPLEMENT )
 CONSIDER ‘1’ IN OUTPUT  CONSIDER ‘0’ IN OUTPUT
TO FORM SUM OF TO FORM PRODUCT OF
MINTERMS MAXTERMS

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 CANONICAL FORM FOR 3 VARIABLES

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 EXAMPLE REVISITED IN CANONICAL FORM

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 EXAMPLE REVISITED IN CANONICAL
FORM

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 STANDARD FORMS

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 BOOLEAN POSTULATES & THEOREMS

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 DEMORGAN’S THEOREM

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 K-MAP
What Is Karnaugh Map ?
Why We Need K-map?
What Is Minimization In Digital Circuits?
What Are The Benefits Of Minimization In
Digital Circuits?
How to start with K-Map?
https://www.youtube.com/watch?v=3vkMgTmieZI

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 TWO VARIABLE K-MAP

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 THREE VARIABLE K-MAP

https://www.youtube.com/watch?v=vEMxaiPcXss

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EXAMPLES FOR 3-VARIABLE K-MAP
• F(x,y,z) = (3,4,6,7)
• F(x,y,z) = (2,3,4,5)
• F(x,y,z) = (0,2,4,5,6)

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EXAMPLES FOR 3-VARIABLE K-MAP

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 MORE EXAMPLES-3-VARIABLE K-MAP

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 4-VARIABLE K-MAP

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EXAMPLES FOR 4-VARIABLE K-MAP
• F(w,x,y,z) = (0,1,2,4,5,6,8,9,12,13,14)
• F = A’B’C’ + B’CD’ + A’BCD’ + AB’C’

https://www.youtube.com/watch?v=9A7UP7vhs9Y

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EXAMPLES FOR 4-VARIABLE K-MAP

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EXAMPLES FOR 4-VARIABLE K-MAP

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 DON’T CARE CONDITIONS IN K-MAP
DON’T CARE is not bothered
In digital, Don’t Care can act as either 0 or 1 as
per designer’s requirement.
In K-Map, “X” used for don’t care conditions

Simplify the following function

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 5 –VARIABLE K-MAP

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 5 –VARIABLE K-MAP

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 EXAMPLES FOR 5 –VARIABLE K-MAP
F=(0,2,4,7,8,10,12,16,18,20,23,24,25,26,27,28)

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 PRIME IMPLICANTS & ESSENTIAL
PRIME IMPLICANTS
A prime implicant is a product term obtained
by combining the maximum possible number
of adjacent squares in the map.
The prime implicant is essential if it is the only
prime implicant that covers the minterm.

 Find all the prime implicants of the following

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 ODD FUNCTION AND EVEN FUNCTION
IN K-MAPS

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 NAND IMPLEMENTATION

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 NOR IMPLEMENTATION

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 MODULE – 2
Combinational Logic circuits

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 COMBINATIONAL CIRCUITS

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 DESIGN PROCEDURE FOR
COMBINATIONAL CIRCUITS
1. Read the design description properly and
understand precisely.
2. Identify the number of inputs, outputs and
resolution( number of bits in design).
3. Label the necessary inputs and outputs
4. Frame the truth table accordingly.
5. From the truth table, derive the Boolean
Function using the K-Map.
6. Realize the obtained Boolean Function as
“LOGIC DIAGRAM”
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 ADDERS AND SUBTRACTORS
Adders are classified as follows
Half Adder – Two Single Bit Addition
Full Adder – Three Single Bit Addition
4 Bit Adder – Two Four Bit Addition
BCD Adder – Decimal Addition
Half Subtractor – Two Single Bit Subtraction
Full Subtractor – Three Single Bit Subtraction
4 bit Subtractor –Two Four Bit Subtraction
Universal 4 Bit Adder & Subtractor
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 HALF ADDER
Truth Table Boolean Function

Logic Diagram

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 FULL ADDER

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 FULL ADDER

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FULL ADDER USING TWO HALF ADDERS

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 4 BIT ADDER

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 HALF SUBTRACTOR
Truth Table Boolean Function

Logic Diagram

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 FULL SUBTRACTOR

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 FULL SUBTRACTOR-LOGIC DIAGRAM

CAN YOU DRAW THE LOGIC DIAGRAM?

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 A majority gate in a digital circuit whose output is equal to 1 if the majority
of inputs are 1’s.the output is 0 otherwise. Using a truth table, find the
Boolean function implemented by a 3-input majority gate. Simplify the
function and implement with the gates.

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 4 BIT MAGNITUDE COMPARATOR
DESIGN
Equality Check

Conditions and Boolean Functions

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 Source: https://www.youtube.com/watch?v=WSJwKRBWax0
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 4 BIT MAGNITUDE COMPARATOR

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 8:1 MULTIPLEXER-Symbol & TT

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 8:1 MULTIPLEXER- Logic Diagram

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 DEMULTIPLEXER-SYMBOL

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 1:4 DeMUX

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 1:8 DEMULTIPLEXER-Logic Diagram

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 1:8 DEMULTIPLEXER-Logic Diagram

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 3 : 8 DECODER

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 3 : 8 DECODER – Logic Diagram

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 8:3 ENCODER-Symbol & TT

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 8:3 ENCODER-Logic Diagram

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 4:2 PRIORITY ENCODER

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 4:2 PRIORITY ENCODER

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