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    Dd&co-Bcs302-First Test Question Bank

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    Ronita Joe
    The document provides guidelines for preparing for the first internal test in the subject of Digital Design and Computer Organization. It lists 27 questions covering topics like Boolean algebra, logic gates, K-maps, and Verilog/VHDL coding. The questions focus on simplifying Boolean functions, drawing logic diagrams, implementing circuits using NAND/NOR gates, describing programming in Verilog and VHDL, and writing code for simple digital circuits. Students are expected to study these areas in order to perform well on the upcoming exam.

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    Dd&co-Bcs302-First Test Question Bank

    Uploaded by

    Ronita Joe
    148 views3 pages
    The document provides guidelines for preparing for the first internal test in the subject of Digital Design and Computer Organization. It lists 27 questions covering topics like Boolean algebra, logic gates, K-maps, and Verilog/VHDL coding. The questions focus on simplifying Boolean functions, drawing logic diagrams, implementing circuits using NAND/NOR gates, describing programming in Verilog and VHDL, and writing code for simple digital circuits. Students are expected to study these areas in order to perform well on the upcoming exam.

    Original Title

    DD&CO-BCS302-FIRST TEST QUESTION BANK

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    The document provides guidelines for preparing for the first internal test in the subject of Digital Design and Computer Organization. It lists 27 questions covering topics like Boolean algebra, logic gates, K-maps, and Verilog/VHDL coding. The questions focus on simplifying Boolean functions, drawing logic diagrams, implementing circuits using NAND/NOR gates, describing programming in Verilog and VHDL, and writing code for simple digital circuits. Students are expected to study these areas in order to perform well on the upcoming exam.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    148 views3 pages

    Dd&co-Bcs302-First Test Question Bank

    Uploaded by

    Ronita Joe
    The document provides guidelines for preparing for the first internal test in the subject of Digital Design and Computer Organization. It lists 27 questions covering topics like Boolean algebra, logic gates, K-maps, and Verilog/VHDL coding. The questions focus on simplifying Boolean functions, drawing logic diagrams, implementing circuits using NAND/NOR gates, describing programming in Verilog and VHDL, and writing code for simple digital circuits. Students are expected to study these areas in order to perform well on the upcoming exam.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 3

    USN

    CAMBRIDGE INSTITUTE OF TECHNOLOGY


    K.R. PURAM, BENGALURU-560036

    Department of CSE/ISE/AI&ML
    Question Bank/Guidelines to prepare for First Internal test

    Sub. Name: Digital Design and Computer Organization Sub. Code: BCS302 Semester: III

    1) State the duality principle of Boolean algebra with an example.

    2) Write the basic theorems and postulates of Boolean algebra and prove them.

    3) Simplify the following Boolean functions to a minimum number of literlas.


    F( x,y ) = x(x’+y), F(A,B) = --------

    4) Find the complement of the following functions:


    F1 = A’B+AC, F2 = ------- F3= ---------

    5) Draw the Graphic symbols and truth table for digital logic gates.

    6) Show that AND and OR functions are Commutative and Associative.

    7) Show that NAND and NOR functions are Commutative and but not Associative.

    8) a)Explain Positive and Negative logic with examples.

    b)Show the the following by means of truth tables:


    i) Positive logic ------ gate is a negative logic ------- gate

    9)Demonstrate the validity of the following identities/theorems by means of truth tables:

    10)Reduce the following Boolean expressions to indicated number of literals.

    11)Determine the complement of F(x,y,z) = ------------and show that


    F.F’ = 0 and F + F’ = 1.

    12)Determine the truth table for the Boolean function


    F= xy’z + x’y’z + ------ +-------- and represent it in ∑m form.

    Page 1 of 2
    13)Determine Boolean equations for the output of the following truth table. Simplify the Boolean
    expression for minimum literals and draw the Circuit using only NAND Gates.
    A B C Y
    0 0 0
    0 0 1
    0 1 0
    0 1 1
    1 0 0
    1 0 1
    1 1 0
    1 1 1

    14)What is K- map ? Explan two, three and four variable K-Maps with examples.

    15) Explain the don’t care condition in K Map with an example.

    16) Explain the NAND and NOR implementation of circuits with examples.

    17)Show Boolean function F (A,B,C) = ---------- with


    i) AND, OR and inverter gates iii) NAND Gates
    ii) NOR gates.

    18)Solve the following Boolean functions using K – Map and write the circuit for simplified
    circuit using NAND gates.
    i) F(A,B,C,D) = ∑ m( , , , , ) + d(, , , , ,)

    19)Solve the following Boolean functions using K – Map and write the circuit for simplified
    circuit using NAND gates.
    F(A,B,C,D) = A’BC +AB’ + ACD’+ ---- +-----+-------

    20)Solve the following Boolean functions using K – Map and write the circuit for simplified
    circuit using NOR gates.
    i) F(A,B,C,D) = ∑ m( , , , , ) + d(, , , , ,)

    21)Solve the following Boolean functions using K – Map and write the circuit for simplified
    circuit using NOR gates.
    F(A,B,C,D) = A’BC +AB’ + ACD’+ ---- +-----+-------

    22)Explain Verilog program description with an example./ Explain the design encapsulation of
    Verilog with an example.

    23)Explain VHDL program description with an example./ Explain the design encapsulation of
    VHDL with an example.

    Page 2 of 2
    24)Show the Verilog code using continuous assignment statements for a single circuit whose
    Boolean functions are ---------------

    25)Show the VHDL code signal assignment statements for the circuit whose Boolean function
    is ------------

    26)Write the Verilog code using structural or gate level for the following circuit.

    27)Draw the logic diagram for the digital circuit specified by the following Verilog code.

    Page 3 of 2

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