[AK4399]

AK4399
High Performance 123dB Premium 32-Bit DAC

GENERAL DESCRIPTION
AK4399 is a 32-bit DAC, which corresponds to DVD-Audio systems. An internal circuit includes newly
developed 32bit Digital Filter for better sound quality achieving low distortion characteristics and wide
dynamic range. The AK4399 has full differential SCF outputs, removing the need for AC coupling
capacitors and increasing performance for systems with excessive clock jitter. The AK4399 accepts
192kHz PCM data and 1-bit DSD data, ideal for a wide range of applications including DVD-Audio and
SACD.

FEATURES
• 128x Over sampling
• Sampling Rate: 30kHz ∼ 216kHz
• 32Bit 8x Digital Filter (Short delay option GD=7/fs)
- Ripple: ±0.005dB, Attenuation: 100dB
• High Tolerance to Clock Jitter
• Low Distortion Differential Output
• DSD data input
• Digital De-emphasis for 32, 44.1, 48kHz sampling
• Soft Mute
• Digital Attenuator (255 levels and 0.5dB step)
• Mono Mode
• External Digital Filter Mode
• THD+N: -105dB
• DR, S/N: 123dB
• I/F Format: 24/32bit MSB justified, 16/20/24/32bit LSB justified, I2S, DSD
• Master Clock:
30kHz ~ 32kHz: 1152fs
30kHz ~ 54kHz: 512fs or 768fs
30kHz ~ 108kHz: 256fs or 384fs
108kHz ~ 216kHz: 128fs or 192fs
• Power Supply: 4.75 ∼ 5.25V
• Digital Input Level: TTL
• Package: 44pin LQFP

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■ Block Diagram

DVDD VSS3 PDN AVDD VSS4

VSS2
VDDL
BICK/DCLK
PCM AOUTLP
8X SCF
LRCK/DSDR/WCK Data
Interpolator
Interface AOUTLN
SDATA/DSDL
VCML
VREFHL
DSD ΔΣ Bias VREFLL
DATT
Data Modulator Vref
Soft Mute VREFLR
Interface
VREFLL
VCMR

External AOUTRP
BCK
DF SCF
DINL Interface AOUTRN
DINR

CSN/SMUTE VDDR
Control Clock
CCLK/DEM0
Register Divider
CDTI/DEM1
VSS1

CAD0 CAD1/DIF0 PSN DZFL/DIF1 DIF2 MCLK DZFR

Block Diagram

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■ Ordering Guide
AK4399EQ −10 ∼ +70°C 44pin LQFP (0.8mm pitch)
AKD4399 Evaluation Board for AK4399

■ Pin Layout

AOUTRN
VREFHR
AOUTLN

VREFLR
VREFHL

VREFLL

VDDR
VDDL
VSS2

VSS1
NC
33

32

31

30

29
28

27

26

25

24

23
AOUTLP 34 22 AOUTRP
VCML 35 21 VCMR
NC 36 20 NC
NC 37 19 DINL
NC 38
AK4399 18 DINR
NC 39 17 NC
VSS3 40 16 BCK
Top View
AVDD 41 15 TST2/DZFR
MCLK 42 14 PSN
VSS4 43 13 NC
NC 44 12 DIF2
10

11
1

5
6

9
TST1/CAD0

DIF0/CAD1

DIF1/DZFL
SMUTE/CSN

DEM1/CDTI
LRCK/DSDR/WCK
SDATA/DSDL
DVDD

PDN

BICK/DCLK

DEM0/CCLK

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PIN/FUNCTION

No. Pin Name I/O Function

1 DVDD - Digital Power Supply Pin, 4.75 ∼ 5.25V
Power-Down Mode Pin
2 PDN I When at “L”, the AK4399 is in power-down mode and is held in reset.
The AK4399 should always be reset upon power-up.
BICK I Audio Serial Data Clock Pin in PCM Mode
3
DCLK I DSD Clock Pin in DSD Mode
SDATA I Audio Serial Data Input Pin in PCM Mode
4
DSDL I DSD Lch Data Input Pin in DSD Mode
LRCK I L/R Clock Pin in PCM Mode
5 DSDR I DSD Rch Data Input Pin in DSD Mode
WCK I Word Clock input pin
Soft Mute Pin in Parallel Control Mode
SMUTE I When this pin is changed to “H”, soft mute cycle is initiated.
6
When returning “L”, the output mute releases.
CSN I Chip Select Pin in Serial Control Mode
TST1 I Test Pin in Parallel Control Mode (Internal pull-down pin)
7
CAD0 I Chip Address 0 Pin in Serial Control Mode (Internal pull-down pin)
DEM0 I De-emphasis Enable 0 Pin in Parallel Control Mode
8
CCLK I Control Data Clock Pin in Serial Control Mode
DEM1 I De-emphasis Enable 1 Pin in Parallel Control Mode
9
CDTI I Control Data Input Pin in Serial Control Mode
DIF0 I Digital Input Format 0 Pin in PCM Mode
10
CAD1 I Chip Address 1 Pin in Serial Control Mode
DIF1 I Digital Input Format 1 Pin in PCM Mode
11
DZFL O Lch Zero Input Detect Pin in Serial Control Mode
12 DIF2 I Digital Input Format 2 Pin in PCM Mode
No internal bonding.
13 NC -
Connect to GND.

Note: All input pins except internal pull-up/down pins must not be left floating.

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Parallel or Serial Select Pin (Internal pull-up pin)

14 PSN I
“L”: Serial Control Mode, “H”: Parallel Control Mode
Test pin in Parallel Control Mode.
TST2 I
15 Connect to GND.
DZFR O Rch Zero Input Detect Pin in Serial Control Mode
16 BCK I Audio Serial Data Clock Pin (Internal pull-down pin)
No internal bonding.
17 NC -
Connect to GND.
18 DINR I Rch Audio Serial Data Input Pin (Internal pull-down pin)
19 DINL I Lch Audio Serial Data Input Pin (Internal pull-down pin)
No internal bonding.
20 NC -
Connect to GND.
Right channel Common Voltage Pin,
21 VCMR -
Normally connected to VSS with a 10uF electrolytic cap.
22 AOUTRP O Rch Positive Analog Output Pin
23 AOUTRN O Rch Negative Analog Output Pin
24 VSS1 - Ground Pin
25 VDDR - Rch Analog Power Supply Pin, 4.75 ∼ 5.25V
26 VREFHR I Rch High Level Voltage Reference Input Pin
27 VREFLR I Rch Low Level Voltage Reference Input Pin
No internal bonding.
28 NC -
Connect to GND.
29 VREFLL I Lch Low Level Voltage Reference Input Pin
30 VREFHL I Lch High Level Voltage Reference Input Pin
31 VDDL - Lch Analog Power Supply Pin, 4.75 ∼ 5.25V
32 VSS2 - Ground Pin
33 AOUTLN O Lch Negative Analog Output Pin
34 AOUTLP O Lch Positive Analog Output Pin
Left channel Common Voltage Pin,
35 VCML -
Normally connected to VSS with a 10uF electrolytic cap.
No internal bonding.
36 NC -
Connect to GND.
No internal bonding.
37 NC -
Connect to GND.
No internal bonding.
38 NC -
Connect to GND.
No internal bonding.
39 NC -
Connect to GND.
40 VSS3 - Ground Pin
41 AVDD - Analog Power Supply Pin, 4.75 ∼ 5.25V
42 MCLK I Master Clock Input Pin
43 VSS4 - Ground Pin
No internal bonding.
44 NC -
Connect to GND.

Note: All input pins except internal pull-up/down pins must not be left floating.

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■ Handling of Unused Pin

The unused I/O pins should be processed appropriately as below.

(1) Parallel Mode (PCM Mode only)

Classification Pin Name Setting

AOUTLP, AOUTLN These pins must be open.
Analog
AOUTRP, AOUTRN These pins must be open.
SMUTE This pin must be connected to VSS4.
Digital TST1 This pin must be open.
TST2 This pin must be connected to VSS4.

(2) Serial Mode

1. PCM Mode

Classification Pin Name Setting

AOUTLP, AOUTLN These pins must be open.
Analog
AOUTRP, AOUTRN These pins must be open.
DIF2 These pins must be connected to VSS4.
Digital
DZFL, DZFR These pins must be open.

2. DSD Mode

Classification Pin Name Setting

AOUTLP, AOUTLN These pins must be open.
Analog AOUTRP, AOUTRN These pins must be open.
DZFL, DZFR These pins must be open.

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ABSOLUTE MAXIMUM RATINGS

(VSS1-4 =0V; Note 1)
Parameter Symbol min max Units
Power Supplies: Analog AVDD −0.3 6.0 V
Analog VDDL/R −0.3 6.0 V
Digital DVDD −0.3 6.0 V
Input Current, Any Pin Except Supplies IIN - ±10 mA
Digital Input Voltage VIND −0.3 DVDD+0.3 V
Ambient Temperature (Power applied) Ta −10 70 °C
Storage Temperature Tstg −65 150 °C

Note 1. All voltages with respect to ground.

Note 2. VSS1-4 must be connected to the same analog ground plane.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

(VSS1-4 =0V; Note 1)
Parameter Symbol min typ max Units
Analog AVDD 4.75 5.0 5.25 V
Power Supplies
Analog VDDL/R 4.75 5.0 5.25 V
(Note 3)
Digital DVDD 4.75 5.0 5.25 V
Voltage “H” voltage reference VREFHL/R AVDD−0.5 - AVDD V
Reference “L” voltage reference VREFLL/R VSS - - V
(Note 4) VREFH − VREFL ΔVREF 3.0 - AVDD V

Note 1. All voltages with respect to ground.

Note 3. The power up sequence between AVDD, VDDL/R and DVDD is not critical.
Note 4. The analog output voltage scales with the voltage of (VREFH − VREFL).
AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFHL/R − VREFLL/R)/5.

* AKEMD assumes no responsibility for the usage beyond the conditions in this data sheet.

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ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=VDDL/R=DVDD=5.0V; VSS1-4 =0V; VREFHL/R=AVDD, VREFLL/R= VSS;
Input data = 24bit; RL ≥ 1kΩ; BICK=64fs; Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz;
Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure 20; unless otherwise specified.)
Parameter min typ max Units
Resolution - - 24 Bits
Dynamic Characteristics (Note 5)
THD+N fs=44.1kHz 0dBFS - -105 98 dB
BW=20kHz −60dBFS - -60 - dB
fs=96kHz 0dBFS - 102 - dB
BW=40kHz −60dBFS - -57 - dB
fs=192kHz 0dBFS 102 - dB
BW=40kHz −60dBFS -57 - dB
BW=80kHz −60dBFS -54 - dB
Dynamic Range (−60dBFS with A-weighted) (Note 6) 117 123 dB
S/N (A-weighted) (Note 7) 117 123 dB
Interchannel Isolation (1kHz) 110 120 dB
DC Accuracy
Interchannel Gain Mismatch - 0.15 0.3 dB
Gain Drift (Note 8) - 20 - ppm/°C
Output Voltage (Note 9) ±2.65 ±2.8 ±2.95 Vpp
Load Capacitance - - 25 pF
Load Resistance (Note 10) 1 - - kΩ
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”)
AVDD + VDDL/R - 60 90 mA
DVDD (fs ≤ 96kHz) - 43 - mA
DVDD (fs = 192kHz) - 46 70 mA
Power down (PDN pin = “L”) (Note 11)
AVDD+VDDL/R+DVDD - 10 100 μA

Note 5. Measured by Audio Precision, System Two. Averaging mode. Refer to the evaluation board manual.
Note 6. Figure 20 External LPF Circuit Example 2. 101dB for 16-bit data and 118dB for 20-bit data.
Note 7. Figure 20 External LPF Circuit Example 2. S/N does not depend on input data size.
Note 8. The voltage on (VREFH − VREFL) is held +5V externally.
Note 9. Full-scale voltage(0dB). Output voltage scales with the voltage of (VREFHL/R − VREFLL/R).
AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFHL/R − VREFLL/R)/5.
Note 10. Regarding Load Resistance, AC load is 1kΩ (min) with a DC cut capacitor (Figure 20). DC load is 1.5k ohm
(min) without a DC cut capacitor (Figure 19). The load resistance value is with respect to ground. Analog
characteristics are sensitive to capacitive load that is connected to the output pin. Therefore the capacitive load
must be minimized.
Note 11. In the power down mode. The P/S pin = DVDD, and all other digital input pins including clock pins
(MCLK, BICK and LRCK) are held VSS4.

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SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SD bit=“0”)
Parameter Symbol min typ max Units
Digital Filter
Passband (Note 12) ±0.01dB PB 0 20.0 kHz
−6.0dB - 22.05 - kHz
Stopband (Note 12) SB 24.1 kHz
Passband Ripple PR ±0.005 dB
Stopband Attenuation SA 100 dB
Group Delay (Note 13) GD - 36 - 1/fs
Digital Filter + SCF
Frequency Response: 0 ∼ 20.0kHz - ±0.2 - dB

SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode; DEM=OFF; SD bit=“0”)
Parameter Symbol min typ max Units
Digital Filter
Passband (Note 12) ±0.01dB PB 0 43.5 kHz
−6.0dB - 48.0 - kHz
Stopband (Note 12) SB 52.5 kHz
Passband Ripple PR ±0.005 dB
Stopband Attenuation SA 95 dB
Group Delay (Note 13) GD - 36 - 1/fs
Digital Filter + SCF
Frequency Response: 0 ∼ 40.0kHz - ±0.3 - dB

SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SD bit=“0”)
Parameter Symbol min typ max Units
Digital Filter
Passband (Note 12) ±0.01dB PB 0 87.0 kHz
−6.0dB - 96.0 - kHz
Stopband (Note 12) SB 105 kHz
Passband Ripple PR ±0.005 dB
Stopband Attenuation SA 90 dB
Group Delay (Note 13) GD - 36 - 1/fs
Digital Filter + SCF
Frequency Response: 0 ∼ 80.0kHz - +0/−1 - dB

Note 12. The passband and stopband frequencies scale with fs. For example, PB=0.4535×fs (@±0.01dB), SB=0.546×fs.
Note 13. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24bit data of
both channels to input register to the output of analog signal.

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SHORT DELAY FILTER CHARACTERISTICS (fs = 44.1kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SD bit=“1”)
Parameter Symbol min typ max Units
Digital Filter
Passband (Note 12) ±0.01dB PB 0 20.0 kHz
−6.0dB - 22.05 - kHz
Stopband (Note 12) SB 24.1 kHz
Passband Ripple PR ±0.005 dB
Stopband Attenuation SA 100 dB
Group Delay (Note 13) GD - 7 - 1/fs
Digital Filter + SCF
Frequency Response : 0 ∼ 20.0kHz - ±0.2 - dB

SHORT DELAY FILTER CHARACTERISTICS (fs = 96kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Double Speed Mode; DEM=OFF; SD bit=“1”)
Parameter Symbol min typ max Units
Digital Filter
Passband (Note 12) ±0.01dB PB 0 43.5 kHz
−6.0dB - 48.0 - kHz
Stopband (Note 12) SB 52.5 kHz
Passband Ripple PR ±0.005 dB
Stopband Attenuation SA 95 dB
Group Delay (Note 13) GD - 7 - 1/fs
Digital Filter + SCF
Frequency Response : 0 ∼ 40.0kHz - ±0.3 - dB

SHORT DELAY FILTER CHARACTERISTICS (fs = 192kHz)

(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SD bit=“1”)
Parameter Symbol min typ max Units
Digital Filter
Passband (Note 12) ±0.01dB PB 0 87.0 kHz
−6.0dB - 96.0 - kHz
Stopband (Note 12) SB 105 kHz
Passband Ripple PR ±0.005 dB
Stopband Attenuation SA 90 dB
Group Delay (Note 13) GD - 7 - 1/fs
Digital Filter + SCF
Frequency Response : 0 ∼ 80.0kHz - +0/−1 - dB

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DC CHARACTERISTICS
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V)
Parameter Symbol min typ max Units
High-Level Input Voltage VIH 2.4 - - V
Low-Level Input Voltage VIL - - 0.8 V
High-Level Output Voltage (Iout=−100μA) VOH DVDD−0.5 - - V
Low-Level Output Voltage (Iout=100μA) VOL - - 0.5 V
Input Leakage Current (Note 14) Iin - - ±10 μA

Note 14. The TST1/CAD0 and P/S pins have internal pull-up devices, nominally 100kΩ. Therefore The TST1/CAD0 and
P/S pins are not included.

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SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V)
Parameter Symbol min typ max Units
Master Clock Timing
Frequency fCLK 7.7 41.472 MHz
Duty Cycle dCLK 40 60 %
LRCK Frequency (Note 15)
1152fs, 512fs or 768fs fsn 30 54 kHz
256fs or 384fs fsd 54 108 kHz
128fs or 192fs fsq 108 216 kHz
Duty Cycle Duty 45 55 %
PCM Audio Interface Timing
BICK Period
1152fs, 512fs or 768fs tBCK 1/128fsn ns
256fs or 384fs tBCK 1/64fsd ns
128fs or 192fs tBCK 1/64fsq ns
BICK Pulse Width Low tBCKL 30 ns
BICK Pulse Width High tBCKH 30 ns
BICK “↑” to LRCK Edge (Note 16) tBLR 20 ns
LRCK Edge to BICK “↑” (Note 16) tLRB 20 ns
SDATA Hold Time tSDH 20 ns
SDATA Setup Time tSDS 20 ns
External Digital Filter Mode
tB tBL 27 ns
BICK Period
tBH 10 ns
BCK Pulse Width Low
tBW 10 ns
BCK Pulse Width High
tWB 5 ns
BCK “↑” to WCK Edge
tWCK 5 ns
WCK Edge to BCK “↑”
tWCH 54 ns
WCK Pulse Width Low
tDH 54 ns
WCK Pulse Width High
tDS 5 ns
DATA Hold Time
5 ns
DATA Setup Time
DSD Audio Interface Timing
DCLK Period tDCK 1/64fs ns
DCLK Pulse Width Low tDCKL 160 ns
DCLK Pulse Width High tDCKH 160 ns
DCLK Edge to DSDL/R (Note 17) tDDD −20 20 ns
Control Interface Timing
CCLK Period tCCK 200 ns
CCLK Pulse Width Low tCCKL 80 ns
Pulse Width High tCCKH 80 ns
CDTI Setup Time tCDS 50 ns
CDTI Hold Time tCDH 50 ns
CSN High Time tCSW 150 ns
CSN “↓” to CCLK “↑” tCSS 50 ns
CCLK “↑” to CSN “↑” tCSH 50 ns
Reset Timing
PDN Pulse Width (Note 18) tPD 150 ns

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Note 15. When the 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK4399 should be reset by the
PDN pin or RSTN bit.
Note 16. BICK rising edge must not occur at the same time as LRCK edge.
Note 17. DSD data transmitting device must meet this time.
Note 18. The AK4399 can be reset by bringing the PDN pin “L” to “H” upon power-up.

■ Timing Diagram
1/fCLK

VIH
MCLK
VIL
tCLKH tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK

1/fs

VIH
LRCK
VIL

tBCK

VIH
BICK
VIL
tBCKH tBCKL

1/fs

VIH
WCK
VIL

tB

VIH
BCK
VIL
tBH tBL

Clock Timing

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VIH
LRCK
VIL

tBLR tLRB

VIH
BICK
VIL

tSDS tSDH

VIH
SDATA
VIL
Audio Interface Timing (PCM Mode)

tDCK
tDCKL tDCKH

VIH
DCLK
VIL

tDDD

DSDL VIH
DSDR
VIL

Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = “0”)

tDCK
tDCKL tDCKH

VIH
DCLK
VIL

tDDD tDDD

DSDL VIH
DSDR
VIL

Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)

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VIH
CSN
VIL

tCSS tCCKL tCCKH

VIH
CCLK
VIL

tCDS tCDH

VIH
CDTI C1 C0 R/W A4
VIL

WRITE Command Input Timing

tCSW

VIH
CSN
VIL

tCSH

VIH
CCLK
VIL

VIH
CDTI D3 D2 D1 D0
VIL

WRITE Data Input Timing

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tPD
PDN
VIL

Power Down & Reset Timing

VIH
WCK
VIL

tBW tW B

VIH
BCK
VIL

tDS tDH

VIH
DATA
VIL

External Digital Filter I/F mode

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OPERATION OVERVIEW

■ D/A Conversion Mode

In serial mode, the AK4399 can perform D/A conversion for either PCM data or DSD data. The D/P bit controls
PCM/DSD mode. When DSD mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode,
PCM data can be input from BICK, LRCK and SDATA pins. When PCM/DSD mode is changed by D/P bit, the AK4399
should be reset by RSTN bit. It takes about 2/fs to 3/fs to change the mode. In parallel mode, the AK4399 performs for
only PCM data.

DP bit Interface
0 PCM
1 DSD
Table 1. PCM/DSD Mode Control

When DP bit= “0”, an internal digital filter or external digital filter can be selected. When using an external digital filter
(EX DF I/F mode), data is input to each MCLK, BCK, WCK, DINL and DINR pin. EXD bit controls the modes. When
switching internal and external digital filters, the AK4399 must be reset by RSTN bit. A Digital filter switching takes
2~3k/fs.

Ex DF bit Interface
0 PCM
1 EX DF I/F
Table 2. Digital Filter Control (DP bit = “0”)

■ System Clock
[1] PCM Mode

The external clocks, which are required to operate the AK4399, are MCLK, BICK and LRCK. MCLK should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. Sampling speed and MCLK frequency are detected automatically and then the initial master clock
is set to the appropriate frequency (Table 3). When external clocks are changed, the AK4399 should be reset by the PDN
pin or RSTN bit.

The AK4399 is automatically placed in reset state when MCLK and LRCK are stopped during a normal operation (PDN
pin =“H”), and the analog output becomes Hi-Z. When MCLK and LRCK are input again, the AK4399 exit reset state and
starts the operation. After exiting system reset (PDN pin =“L”→“H”) at power-up and other situations, the AK4399 is in
power-down mode until MCLK and LRCK are supplied.

The MCLK frequency corresponding to each sampling speed should be provided (Table 4).

MCLK Mode Sampling Rate

1152fs Normal 30kHz~32kHz
512fs 768fs Normal 30kHz~54kHz
256fs 384fs Double 30kHz~108kHz
128fs 192fs Quad 108kHz~216kHz
Table 3. Sampling Speed

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LRCK MCLK (MHz)

fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs
32.0kHz N/A N/A 8.1920 12.2880 16.3840 24.5760 36.8640
44.1kHz N/A N/A 11.2896 16.9344 22.5792 33.8688 N/A
48.0kHz N/A N/A 12.2880 18.4320 24.5760 36.8640 N/A
88.2kHz N/A N/A 22.5792 33.8688 N/A N/A N/A
96.0kHz N/A N/A 24.5760 36.8640 N/A N/A N/A
176.4kHz 22.5792 33.8688 N/A N/A N/A N/A N/A
192.0kHz 24.5760 36.8640 N/A N/A N/A N/A N/A
Table 4. System Clock Example (Parallel Control Mode) (N/A: Not available)

MCLK= 256fs/384fs supports sampling rate of 30kHz~108kHz (Table 5). But, when the sampling rate is 30kHz~54kHz,
DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs.

MCLK DR,S/N
256fs/384fs 120dB
512fs/768fs 123dB
Table 5. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)

[2] DSD Mode

The external clocks, which are required to operate the AK4399, are MCLK and DCLK. MCLK should be synchronized
with DCLK but the phase is not critical. The frequency of MCLK is set by DCKS bit.

The AK4399 is automatically placed in reset state when MCLK is stopped during a normal operation (PDN pin =“H”),
and the analog output becomes Hi-Z. After exiting system reset (PDN pin =“L”→“H”) at power-up and other situations,
the AK4399 is in power-down mode until MCLK is supplied.

DCKS bit MCLK Frequency DCLK Frequency

0 512fs 64fs (default)
1 768fs 64fs
Table 6. System Clock (DSD Mode)

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■ Audio Interface Format

[1] PCM Mode

Data is shifted in via the SDATA pin using BICK and LRCK inputs. Eight data formats are supported and selected by the
DIF2-0 pins (Parallel control mode) or DIF2-0 bits (Serial control mode) as shown in Table 7. In all formats the serial data
is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 20-bit and 16-bit
MSB justified formats by zeroing the unused LSBs. Settings should be made by DIF2-0 pins in parallel mode and DIF2-0
bits in serial mode.

Mode DIF2 DIF1 DIF0 Input Format BICK Figure

0 0 0 0 16bit LSB justified ≥ 32fs Figure 1
1 0 0 1 20bit LSB justified ≥ 48fs Figure 2
2 0 1 0 24bit MSB justified ≥ 48fs Figure 3 (default)
3 0 1 1 24bit I2S Compatible ≥ 48fs Figure 4
4 1 0 0 24bit LSB justified ≥ 48fs Figure 2
5 1 0 1 32bit LSB justified ≥ 64fs Figure 5
6 1 1 0 32bit MSB justified ≥64fs Figure 6
7 1 1 1 32bit I2S Compatible ≥ 64fs Figure 7
Table 7. Audio Interface Format

LRCK
0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1
BICK
(32fs)

SDATA 15 14 6 5 4 3 2 1 0 15 14 6 5 4 3 2 1 0 15 14
Mode 0
0 1 14 15 16 17 31 0 1 14 15 16 17 31 0 1
BICK
(64fs)

SDATA Don’t care 15 14 0 Don’t care 15 14 0

Mode 0
15:MSB, 0:LSB
Lch Data Rch Data
Figure 1. Mode 0 Timing

LRCK
0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 0 1
BICK
(64fs)

SDATA Don’t care 19 0 Don’t care 19 0

Mode 1
19:MSB, 0:LSB

SDATA Don’t care 23 22 21 20 19 0 Don’t care 23 22 21 20 19 0

Mode 4
23:MSB, 0:LSB
Lch Data Rch Data
Figure 2. Mode 1/4 Timing

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LRCK

0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1

BICK
(64fs)

SDATA 23 22 1 0 Don’t care 23 22 1 0 Don’t care 23 22

23:MSB, 0:LSB

Lch Data Rch Data

Figure 3. Mode 2 Timing

LRCK

0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1

BICK
(64fs)

SDATA 23 22 1 0 Don’t care 23 22 1 0 Don’t care 23

23:MSB, 0:LSB

Lch Data Rch Data

Figure 4. Mode 3 Timing

LRCK
0 1 2 20 21 22 32 33 63 0 1 2 20 21 22 32 33 63 0 1

BICK(128fs)

SDATA 31 1 0 31 1 0

0 1 2 12 13 14 23 24 31 0 1 2 12 13 14 23 24 31 0 1

BICK(64fs)

SDATA 31 30 20 19 18 9 8 1 0 31 30 20 19 18 9 8 1 0 31

Lch Data Rch Data

31: MSB, 0:LSB

Figure 5. Mode 5 Timing

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LRCK
0 1 2 20 21 22 32 33 63 0 1 2 20 21 22 32 33 63 0 1

BICK(128fs)

SDATA 31 30 12 11 10 0 31 30 12 11 10 0 31

0 1 2 12 13 14 23 24 31 0 1 2 12 13 14 23 24 31 0 1

BICK(64fs)

SDATA 31 30 20 19 18 9 8 1 0 31 30 20 19 18 9 8 1 0 31

Lch Data Rch Data

31: MSB, 0:LSB

Figure 6. Mode 6 Timing

LRCK
0 1 2 20 21 22 33 34 63 0 1 2 20 21 22 33 34 63 0 1

BICK(128fs)

SDATA 31 13 12 11 0 31 13 12 11 0

0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 1

BICK(64fs)

SDATA 0 31 21 20 19 9 8 2 1 0 31 21 20 19 9 8 2 1 0

Lch Data Rch Data

31: MSB, 0:LSB

Figure 7. Mode 7 Timing

[2] DSD Mode

In case of DSD mode, DIF2-0 pins and DIF2-0 bits are ignored. The frequency of DCLK is fixed to 64fs. DCKB bit can
invert the polarity of DCLK.

DCLK (64fs)
DCKB=1

DCLK (64fs)
DCKB=0

DSDL,DSDR D0 D1 D2 D3
Normal

DSDL,DSDR
Phase Modulation D0 D1 D1 D2 D2 D3

Figure 8. DSD Mode Timing

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[3] External Digital Filter Mode (EX DF I/F Mode)

DW indicates the number of BCK in one WCK cycle. The audio data is input by MCLK, BCK and WCK from the DINL
and DINR pins. Three formats are available (Table 9) by DIF2-0 bits setting. The data is latched on the rising edge of
BCK. The BCK and MCLK clocks must be the same frequency and must not burst. BCK and MCLK frequencies for each
sampling speed are shown in Table 8.

The AK4399 is automatically placed in reset state when MCLK and WCK are stopped during a normal operation (PDN
pin =“H”), and the analog output becomes Hi-Z. When MCLK and WCK are input again, the AK4399 exit reset state and
starts the operation. After exiting system reset (PDN pin =“L”→“H”) at power-up and other situations, the AK4399 is in
power-down mode until MCLK and WCK are supplied.

Sampling MCLK&BCK [MHz] WCK ECS

Speed[kHz] 128fs 192fs 256fs 384fs 512fs 768fs
N/A N/A N/A N/A 22.5792 33.8688 16fs
44.1(30~54) 0
32 48 DW
N/A N/A 11.2896 16.9344 N/A 33.8688 8fs
44.1(30~54) 1
32 48 96 DW
N/A N/A 24.576 36.864 N/A N/A 8fs
96(54~108) 0
32 48 DW
12.288 18.432 N/A 36.864 N/A N/A 4fs
96(54~108) 1
32 48 96 DW
24.576 36.864 N/A N/A N/A N/A 4fs
192(108~216) 0
32 48 DW
N/A 36.864 N/A N/A N/A N/A 2fs
192(108~216) 1
96 DW
Table 8 System Clock Example (EX DF I/F mode) (N/A: Not available)

Mode DIF2 DIF1 DIF0 Input Format

0 0 0 0 16bit LSB justified
1 0 0 1 N/A
2 0 1 0 N/A
3 0 1 1 N/A
4 1 0 0 24bit LSB justified
5 1 0 1 32bit LSB justified
6 1 1 0 N/A
7 1 1 1 N/A
Table 9 Audio Interface Format (EX DF I/F mode) (N/A: Not available)

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1/16fs or 1/8fs or 1/4fs or 1/2fs

WCK
0 1 8 9 10 11 16 17 26 27 28 29 30 31 0 1

BCK

DINL or 31 30 24 23 22 21 20 17 16 15 14 6 5 4 3 2 1 0
DINR
0 1 5 6 7 8 47 48 49 65 92 93 94 95 0 1

BCK

DINL or
Don’t care Don’t care Don’t care 31 3 2 1 0 on’t care
DINR
0 1 5 6 7 8 23 24 25 17 44 45 46 47 0 1

BCK

DINL or
Don’t care Don’t care Don’t care 31 3 2 1 0 Don’t care
DINR

Figure 9 EX DF I/F Mode Timing

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■ D/A Conversion Mode Switching Timing

RSTN bit
≥4/fs

D/A Mode PCM Mode DSD Mode

≥0

D/A Data PCM Data DSD Data

Figure 10. D/A Mode Switching Timing (PCM to DSD)

RSTN bit

D/A Mode DSD Mode PCM Mode

≥4/fs

D/A Data DSD Data PCM Data

Figure 11. D/A Mode Switching Timing (DSD to PCM)

Note. The signal range is identified as 25% ~ 75% duty ratios in DSD mode. DSD signal must not go beyond this duty
range at the SACD format book (Scarlet Book).

■ De-emphasis Filter
A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15µs) and is enabled or
disabled with DEM1-0 pins or DEM1-0 bits. In case of 256fs/384fs and 128fs/192fs, the digital de-emphasis filter is
always off. When DSD mode, DEM1-0 bits are ignored. The setting value is held even if PCM mode and DSD mode are
switched.

DEM1 DEM0 Mode

0 0 44.1kHz
0 1 OFF (default)
1 0 48kHz
1 1 32kHz
Table 10. De-emphasis Control

■ Output Volume
The AK4399 includes channel independent digital output volumes (ATT) with 255 levels at linear step including MUTE.
These volume control is in front of the DAC and it can attenuate the input data from 0dB to –127dB and mute. When
changing output levels, transitions are executed in soft change; thus no switching noise occurs during these transitions.

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■ Zero Detection (PCM mode, DSD mode)

The AK4399 has channel-independent zeros detect function. When the input data at each channel is continuously zeros
for 8192 LRCK cycles, the DZF pin of each channel goes to “H”. The DZF pin of each channel immediately return to “L”
if the input data of each channel is not zero after going to “H”. If the RSTN bit is “0”, the DZF pins of both channels go to
“H”. The DZF pins of both channels go to “L” at 4 ~ 5/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, the DZF
pins of both channels go to “H” only when the input data for both channels are continuously zeros for 8192 LRCK cycles.
The zero detect function can be disabled by setting the DZFE bit. In this case, DZF pins of both channels are always “L”.
The DZFB bit can invert the polarity of the DZF pin.

■ Mono Output
The AK4399 can select input/output for both output channels by setting the MONO bit and SELLR bit. This function is
available for any audio format.

MONO bit SELLR bit Lch Out Rch Out

0 0 Lch In Rch In
0 1 Rch In Lch In
1 0 Lch In Lch In
1 1 Rch In Rch In
Table 11 MONO Mode Output Select

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■ Soft Mute Operation

The soft mute operation is performed at digital domain. When the SMUTE pin goes to “H” or the SMUTE bit set to “1”,
the output signal is attenuated by −∞ during ATT_DATA × ATT transition time from the current ATT level. When the
SMUTE pin is returned to “L” or the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation
gradually changes to the ATT level during ATT_DATA × ATT transition time. If the soft mute is cancelled before
attenuating −∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle.
The soft mute is effective for changing the signal source without stopping the signal transmission.

S M U T E pin or
S M U T E b it
(1 ) (1 )
AT T _ L e ve l
(3 )
A tte nu atio n

-∞
GD GD
(2 ) (2 )

AO U T

(4 )
81 92 /fs
D Z F pin

Notes:
(1) ATT_DATA × ATT transition time. For example, this time is 1020LRCK cycles (1020/fs) at ATT_DATA=255 in
Normal Speed Mode.
(2) The analog output corresponding to the digital input has group delay (GD).
(3) If the soft mute is cancelled before attenuating −∞ after starting the operation, the attenuation is discontinued
and returned to ATT level by the same cycle.
(4) When the input data for each channel is continuously zeros for 8192 LRCK cycles, the DZF pin for each channel
goes to “H”. The DZF pin immediately returns to “L” if input data are not zero.

Figure 12. Soft Mute Function

■ System Reset
The AK4399 should be reset once by bringing the PDN pin = “L” upon power-up. It initializes register settings of the
device. The AK4399 exits this system reset (power-down mode) by MCLK and LRCK after the PDN pin = “H”, and the
analog block exits power-down mode. The digital block exits power-down mode after the internal counter counts MCLK
for 4/fs.

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■ Power ON/OFF timing

The AK4399 is placed in the power-down mode by bringing the PDN pin “L” and the registers are initialized. the analog
outputs are floating (Hi-Z). As some click noise occurs at the edge of the PDN pin signal, the analog output should be
muted externally if the click noise influences system application.

The DAC can be reset by setting RSTN bit to “0”. In this case, the registers are not initialized and the corresponding
analog outputs go to VCML/R. As some click noise occurs at the edge of RSTN signal, the analog output should be muted
externally if click noise aversely affect system performance.

Power

PDN pin (1)

Internal
State Normal Operation Reset

“0”data “0”data
(Digital)
(2)
GD GD

DAC Out (3) (4) (4) (3)

(Analog)

(5)
Clock In Don’t care
MCLK,LRCK,BICK
Don’t care

DZFL/DZFR (7)

External
(6) Mute ON Mute ON
Mute

Notes:
(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.
(2) The analog output corresponding to digital input has group delay (GD).
(3) Analog outputs are floating (Hi-Z) in power-down mode.
(4) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(5) MCLK, BICK and LRCK clocks can be stopped in power-down mode (PDN pin= “L”).
(6) Mute the analog output externally if click noise (3) adversely affect system performance
The timing example is shown in this figure.
(7) DZFL/R pins are “L” in the power-down mode (PDN pin = “L”).

Figure 13. Power-down/up Sequence Example

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■ Reset Function
(1) RESET by RSTN bit = “0”

When the RSTN bit = “0”, the AK4399’s digital block is powered down, but the internal register values are not initialized.
In this time, the analog outputs go to VCML/R voltage and DZFL/DZFR pins are “H”. Figure 14 shows an example of
reset by RSTN bit.

RSTN bit
3~4/fs (5) 2 ~3 /fs (5)
In ternal
RSTN bit

In ternal Normal Operation D igital Block Normal O peration

Stat e P

D/ A In “0 ” data
(Dig ital)
(1) GD GD (1)
D/ A Out (3) (2) (3)
(Ana log )

2/ fs(4 )
DZF (6)

Notes:
(1) The analog output corresponding to digital input has group delay (GD).
(2) Analog outputs settle to VCOM voltage.
(3) Small pop noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0”
data is input.
(4) The DZF pins change to “H” when the RSTN bit becomes “0”, and return to “L” at 2/fs after RSTN bit becomes
“1”.
(5) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the
internal RSTN bit “1”.
(6) Mute the analog output externally if click noise (3) and Hi-Z (2) adversely affect system performance

Figure 14. Reset Sequence Example 1

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(2) RESET by MCLK or LRCK/WCK Stop

The AK4399 is automatically placed in reset state when MCLK or LRCK is stopped during PDM mode (RSTN pin
=“H”), and the analog outputs are floating (Hi-Z). When MCLK and LRCK are input again, the AK4399 exits reset state
and starts the operation. Zero detect function is disable when MCLK or LRCK is stopped. In DSD mode the AK4399 is in
reset state when MCLK is stopped, and it is in reset state when MCLK and WCK are stopped in external digital filter
mode.

AVDD pin
DVDD pin

RSTB pin (1)

In ternal
Power-down Normal O peration Digital Circuit P ower-down Normal Operation
Stat e

D/ A In (3)
Power-down
(Dig ital)
GD (2) GD (2)

D/A Out Hi-Z (4) (5) (4 )

(Analog) (4)
(5)
Cl ock In MCLK, BICK, LRC K Stop
MCLK , BICK, LRCK

Externa l
(6) (6) (6)
MUTE

Notes:
(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.
(2) The analog output corresponding to digital input has group delay (GD).
(3) The digital data can be stopped. Click noise after MCLK, BICK and LRCK are input again can be reduced by
inputting “0” data during this period.
(4) Click noise occurs within 3 ~ 4LRCK cycles from the riding edge (“↑”) of the PDN pin or MCLK inputs. This
noise occurs even when “0” data is input.
(5) Clocks (MCLK, BICK, LRCK) can be stopped in the reset state (MCLK or LRCK is stopped).
(6) Mute the analog output externally if click noise (4) influences system applications. The timing example is shown
in this figure.

Figure 15. Reset Sequence Example 2

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■ Register Control Interface

Pins (parallel control mode) or registers (serial control mode) can control the functions of the AK4399. In parallel control
mode, the register setting is ignored, and in serial control mode the pin settings are ignored. When the state of the PSN pin
is changed, the AK4399 should be reset by the PDN pin. The serial control interface is enabled by the PSN pin = “L”. In
this mode, pin settings must be all “L”. Internal registers may be written to through3-wire µP interface pins: CSN, CCLK
and CDTI. The data on this interface consists of Chip address (2-bits, C1/0), Read/Write (1-bit; fixed to “1”), Register
address (MSB first, 5-bits) and Control data (MSB first, 8-bits). The AK4399 latches the data on the rising edge of CCLK,
so data should be clocked in on the falling edge. The writing of data is valid when CSN “↑”. The clock speed of CCLK is
5MHz (max).

Function Parallel Control Mode Serial Control Mode

Audio Format Y Y
De-emphasis Y Y
SMUTE Y Y
DSD Mode - Y
EX DF I/F - Y
Short delay Filter - Y
Digital Attenuator - Y
Table 12. Function List1 (Y: Available, -: Not available)

Setting the PDN pin to “L” resets the registers to their default values. In serial control mode, the internal timing circuit is
reset by the RSTN bit, but the registers are not initialized.

CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK

CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

C1-C0: Chip Address (C1 bit =CAD1 pin, C0 bit =CAD0 pin)
R/W: READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 16. Control I/F Timing

* The AK4399 does not support the read command.

* When the AK4399 is in power down mode (PDN pin = “L”) or the MCLK is not provided, a writing into the control
registers is prohibited.
* The control data can not be written when the CCLK rising edge is 15 times or less or 17 times or more during CSN is
“L”.

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Function List

Function Default Address Bit PCM DSD Ex DF I/F

Attenuation Level 0dB 03H ATT7-0
Y Y Y
04H
External Digital Filter I/F Mode Disable 00H EXDF Y - Y
Ex DF I/F mode clock setting 16fs(fs=44.1kHz) 00H ESC - - Y
Audio Data Interface Modes 24bit MSB justified 00H DIF2-0 Y - -
Data Zero Detect Enable Disable 01H DZFE Y Y -
Data Zero Detect Mode Separated 01H DZFM Y Y
Short delay Filter Enable Sharp roll-off filter 01H SD Y - -
De-emphasis Response OFF 01H DEM1-0 Y - -
Soft Mute Enable Normal Operation 01H SMUTE Y Y Y
DSD/PCM Mode Select PCM mode 02H DP Y Y -
Master Clock Frequency Select at 512fs 02H DCKS
- Y -
DSD mode
MONO mode Stereo mode select Stereo 02H MONO Y Y Y
Inverting Enable of DZF “H” active 02H DZFB Y Y -
The data selection of L channel and R channel 02H SELLR
Y Y Y
R channel
Table 13. Function List2 (Y: Available, -: Not available)

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■ Register Map
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 0 EXDF ECS 0 DIF2 DIF1 DIF0 RSTN
01H Control 2 DZFE DZFM SD 0 0 DEM1 DEM0 SMUTE
02H Control 3 DP 0 DCKS DCKB MONO DZFB SELLR 0
03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

Notes:
Data must not be written into addresses from 05H to 1FH.
When the PDN pin goes to “L”, the registers are initialized to their default values.
When RSTN bit is set to “0”, only the internal timing is reset, and the registers are not initialized to their default
values.
When the state of the PSN pin is changed, the AK4399 should be reset by the PDN pin.

■ Register Definitions
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 0 EXDF ECS 0 DIF2 DIF1 DIF0 RSTN
Default 1 0 0 0 0 1 0 1

RSTN: Internal Timing Reset

0: Reset. All registers are not initialized.
1: Normal Operation (default)
When internal clocks are changed, the AK4399 should be reset by the PDN pin or RSTN bit.

DIF2-0: Audio Data Interface Modes (Table 7)

Initial value is “010” (Mode 2: 24-bit MSB justified).

ECS: Ex DF I/F mode clock setting (Table 8)

0: Disable: Internal Digital Filter mode (default)
1: Enable: External Digital Filter mode

EXDF: External Digital Filter I/F Mode (Serial mode only)

0: Disable: Internal Digital Filter mode (default)
1: Enable: External Digital Filter mode

DIF2-0: Audio Data Interface Modes (Table 7)

Initial value is “010” (Mode2: 24bit MSB justified)

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

01H Control 2 DZFE DZFM SD 0 0 DEM1 DEM0 SMUTE
Default 0 0 0 0 0 0 1 0

SMUTE: Soft Mute Enable

0: Normal Operation (default)
1: DAC outputs soft-muted.

DEM1-0: De-emphasis Response (Table 10)

Initial value is “01” (OFF).

SD: Short delay Filter Enable

0: Sharp roll-off filter (default)
1: Short delay filter

DZFM: Data Zero Detect Mode

0: Channel Separated Mode (default)
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both
channels are continuously zeros for 8192 LRCK cycles.

DZFE: Data Zero Detect Enable

0: Disable (default)
1: Enable
Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are
always “L”.

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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

02H Control 3 DP 0 DCKS DCKB MONO DZFB SELLR 0
Default 0 0 0 0 0 0 0 0

SELLR: The data selection of L channel and R channel, when MONO mode
0: All channel output R channel data, when MONO mode. (default)
1: All channel output L channel data, when MONO mode.
It is enabled when MONO bit is “1”, and outputs Rch date to both channels when “0”,outputs Lch data to
both channels when “1”.

DZFB: Inverting Enable of DZF

0: DZF pin goes “H” at Zero Detection (default)
1: DZF pin goes “L” at Zero Detection

MONO: MONO mode Stereo mode select

0: Stereo mode (default)
1: MONO mode
When MONO bit is “1”, MONO mode is enabled.

DCKB: Polarity of DCLK (DSD Only)

0: DSD data is output from DCLK falling edge. (default)
1: DSD data is output from DCLK rising edge.

DCKS: Master Clock Frequency Select at DSD mode (DSD only)

0: 512fs (default)
1: 768fs

DP: DSD/PCM Mode Select

0: PCM Mode (default)
1: DSD Mode
When D/P bit is changed, the AK4399 should be reset by RSTN bit.

Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0

03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
Default 1 1 1 1 1 1 1 1

ATT7-0: Attenuation Level

256 levels, 0.5dB step

Data Attenuation
FFH 0dB
FEH -0.5dB
FDH -1.0dB
: :
: :
02H -126.5dB
01H -127.0dB
00H MUTE (-∞)

The transition between set values is soft transition of 7425 levels. It takes 7424/fs (168ms@fs=44.1kHz) from
FFH (0dB) to 00H (MUTE). If the PDN pin goes to “L”, the ATTs are initialized to FFH. The ATTs are FFH
when RSTN bit= “0”. When RSTN return to “1”, the ATTs fade to their current value. This digital attenuator is
independent of soft mute function.

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SYSTEM DESIGN

Figure 17 shows the system connection diagram. Figure 19, Figure 20 and Figure 21 show the analog output circuit
examples. The evaluation board (AKD4399) demonstrates the optimum layout, power supply arrangements and
measurement results.

Analog5.0V

Master clock
10u +
Digital 5.0V 10u
+ +
0.1u Lch Out
Lch Lch
LPF Mute
NC 44

VSS4 43

MCLK 42

AVDD 41

VSS3 40

NC 39

NC 38

NC 37

NC 36

VCML 35
34AOUTLP
0.1u
10u
1 DVDD AOUTLN 33
+
Reset & PD 2 PDN VSS2 32
0.1u 10u
64fs 3 BICK VDDL 31 +
Audio Data 4 SDATA VREFHL 30 +

fs 5 LRCK AK4399EQ VREFLL 29

0.1u 10u

6 CSN NC 28

Micro- 7 CAD0 VREFLR 27

0.1u 10u
Controller 8 CCLK Top View VREFHR 26 +
+
9 CDTI VDDR 25
0.1u 10u
10 CAD1 VSS1 24
11 DZFL AOUTRN 23
22 AOUTRP
21 VCMR
15 DZFR

18 DINR

19 DINL
12 DIF2

14 PSN

16 BCK
13 NC

17 NC

20 NC

Rch Rch
+ LPF Mute
Rch Out
10u

Digital Analog
+ Electrolytic Capacitor

Ceramic Capacitor

Notes:
- Chip Address = “00”. BICK = 64fs, LRCK = fs
- Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc.
- VSS1-4 must be connected to the same analog ground plane.
- When AOUT drives a capacitive load, some resistance should be connected in series between AOUT and the
capacitive load.
- All input pins except pull-down/pull-up pins should not be allowed to float.

Figure 17. Typical Connection Diagram (AVDD=VDDL/R=5V, DVDD=5V, Serial control mode)

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Digital Ground Analog Ground

NC 44

NC 39
NC 38

NC 37
NC 36
VSS4 43
MCLK 42
AVDD 41
VS S3 40

VCML 35
AOUTL P 34
1 DVDD AOUTLN 33

2 PDN VSS2 32
System
3 BICK/DCLK VDDL 31

AK4399EQ
4 SDATA/DSDL VREFHL 30
Controller
5 LRCK/DSDR/W CK VREFLL 29
6 SMUTE/CSN NC 28
7 DFS0 /CAD0 VREFLR 27
8 DEM0/CCLK VREFHR 26
9 DEM1/CDTI VDDR 25
10 DIF0/CAD1 VSS1 24

15 A CKS/DZFR
11 DIF1/ DZFL AOUTRN 23

22 AOUTRP
21 VCMR
18 DINR
12 DIF2

19 DINL
16 BCK
14 PSN
13 NC

17 NC

20 NC
Figure 18. Ground Layout

1. Grounding and Power Supply Decoupling

To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, VDDL/R and DVDD
respectively. AVDD and VDDL/R are supplied from analog supply in system and DVDD is supplied from digital supply in
system. Power lines of AVDD, VDDL/R and DVDD should be distributed separately from the point with low impedance of
regulator etc. The power up sequence between AVDD, VDDL/R and DVDD is not critical. VSS1-4 must be
connected to the same analog ground plane. Decoupling capacitors for high frequency should be placed as near as
possible to the supply pin.

2. Voltage Reference

The differential voltage between VREFHL/R and VREFLL/R sets the analog output range. The VREFHL/R pin is
normally connected to AVDD, and the VREFLL/R pin is normally connected to VSS1/2/3. VREFHL/R and VREFLL/R
should be connected with a 0.1µF ceramic capacitor as near as possible to the pin to eliminate the effects of high frequency
noise. No load current may be drawn from VCML/R pin. All signals, especially clocks, should be kept away from the
VREFHL/R and VREFLL/R pins in order to avoid unwanted noise coupling into the AK4399.

3. Analog Outputs

The analog outputs are full differential outputs and 2.8Vpp (typ, VREFHL/R − VREFLL/R = 5V) centered around
AVDD/2. The differential outputs are summed externally, VAOUT = (AOUT+) − (AOUT−) between AOUT+ and AOUT−. If
the summing gain is 1, the output range is 5.6Vpp (typ, VREFHL/R − VREFLL/R = 5V). The bias voltage of the external
summing circuit is supplied externally. The input data format is 2's complement. The output voltage (VAOUT) is a positive
full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for
000000H(@24bit).

The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the audio
passband. Figure 19 shows an example of external LPF circuit summing the differential outputs by an op-amp.
Figure 20 shows an example of differential outputs and LPF circuit example by three op-amps.

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AK43 99

2.4k 2.4k
AOUT-
150 680p
+ Vop
3.3n
2.4k 150 Analog
AOU T+ Out

2.4k 680p -Vop

Figure 19. External LPF Circuit Example 1 for PCM (fc = 125kHz, Q=0.692)

Frequency Response Gain

20kHz −0.012dB
40kHz −0.083dB
80kHz −0.799dB
Table 14. Frequency Response of External LPF Circuit Example 1 for PCM

+15
3.3n
-15
+
10u
100u 180 0.1u
3 7
AOUTL- + 6
2 +
330 3.9n -
4
0.1u +10u
10k

NJM5534D +
10u 560
0.1u
680 1.0n
1.2k

100
620 2 - 4
6
+ Lch
3 7
620 1.0n NJM5534D
3.3n
560

+
10u
100u 180 0.1u
+ 3 7
AOUTL+ + 6
2 - +
330 3.9n 4 0.1u 10u
10k

NJM5534D +
10u
0.1u
680
1.2k

Figure 20. External LPF Circuit Example 2 for PCM

1st Stage 2nd Stage Total

Cut-off Frequency 182kHz 284kHz -
Q 0.637 - -
Gain +3.9dB -0.88dB +3.02dB
20kHz -0.025 -0.021 -0.046dB
Frequency
40kHz -0.106 -0.085 -0.191dB
Response
80kHz -0.517 -0.331 -0.848dB
Table 15. Frequency Response of External LPF Circuit Example 2 for PCM

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It is recommended for SACD format book (Scarlet Book) that the filter response at SACD playback is an analog low pass
filter with a cut-off frequency of maximum 50kHz and a slope of minimum 30dB/Oct. The AK4399 can achieve this filter
response by combination of the internal filter (Table 16) and an external filter (Figure 21).

Frequency Gain
20kHz −0.4dB
50kHz −2.8dB
100kHz −15.5dB
Table 16. Internal Filter Response at DSD Mode

2.0k 1.8k 4.3k

AOUT-
1.0k 270p
2.8Vpp
2200p +Vop
3300p
-
2.0k 1.8k 1.0k Analog
AOUT+ + Out 6.34Vpp

4.3k 270p -Vop

2.8V pp

Figure 21. External 3rd Order LPF Circuit Example for DSD

Frequency Gain
20kHz −0.05dB
50kHz −0.51dB
100kHz −16.8dB
DC gain = 1.07dB
Table 17. 3rd Order LPF (Figure 21) Response

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PACKAGE

■ Material & Lead finish

Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate

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 [AK4399]

MARKING

AK4399EQ
XXXXXXX
AKM
1

1) Pin #1 indication
2) AKM Logo
3) Date Code: XXXXXXX(7 digits)
4) Marking Code: AK4399
5) Audio 4 pro Logo

REVISION HISTORY

Date (YY/MM/DD) Revision Reason Page Contents

08/10/20 00 First Edition

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 [AK4399]

IMPORTANT NOTICE

z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or
strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or
distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all
claims arising from the use of said product in the absence of such notification.

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