FEDL9842-02 FEDL9842-02

This version: MSM9842

Jul. 2000
¡ Semiconductor
¡ Semiconductor
Previous version: May 1998

MSM9842
Playback LSI with Built-in FIFO

This document contains minimum specifications. For full specifications, please contact your
nearest Oki office or representative.

GENERAL DESCRIPTION

The MSM9842 is a mono/stereo playback LSI with a built-in 1K bit FIFO for easy interface with
external systems or non-semiconductor memory. It utilizes multiple playback modes, including
the new ADPCM2 algorithm, which allows for even higher quality sound reproduction. The
playback function of the MSM9842 is controlled by an MCU via 8/16-bit bus interface.

FEATURES

• 16/8-bit bus interface support

• FIFO capacity: User-definable (256/512/1024 bits)
(buffering time of 32 ms when using 8 kHz sampling frequency, 4-bit ADPCM2/ADPCM, and
in monaural playback)
• Supports four compression algorithms for playback:
4, 5, 6, 7, 8-bit ADPCM2; 4-bit ADPCM; 8; 16-bit PCM; and 8-bit Nonlinear PCM
• Sampling frequency: 4.0 kHz, 6.4 kHz, 8.0 kHz, 12.8 kHz, 16.0 kHz, 32.0 kHz (fosc=4.096 MHz)
• Sampling frequency: 22.05 kHz, 44.1 kHz (fosc=5.6448 MHz)
• DMA interface support
• Volume control (8 steps: 0 dB to –21 dB)
• Built-in 14-bit D/A converter
• Built-in low pass filter (LPF)
• Power supply voltage: 2.7 V to 5.5 V
• Package:
56-pin plastic QFP (QFP56-P-910-0.65-2K) (Product name: MSM9842GA)

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BLOCK DIAGRAM

AOUTL AOUTR

AVDD
LPF DAC DAC LPF AGND
DVDD
DGND

Volume Controller
EMP FIFO
MID
FUL/DREQR
DASD

External
CH/DACKR

DAC I/F
ADPCM2/ADPCM/PCM/Non-linear PCM
SOCK
Synthesizer

D15 to D0 MCU
I/F TEST0
WR TEST1
RD DMA I/F Timing Controller
CS TEST2
D/C TEST3
BUSY
TEST4

DREQL DACKL IOW VCK XT XT RESET

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PIN CONFIGURATION (TOP VIEW)

51 DREQL
50 DACKL
53 TEST3

48 TEST1
47 TEST0

45 TEST2
49 DGND

44 DASD
43 SOCK
52 IOW

46 VCK
56 NC
55 XT
54 XT
D0 1 42 BUSY
D1 2 41 D/C
D2 3 40 CS
D3 4 39 RD
NC 5 38 WR
D4 6 37 FUL/DREQR
D5 7 36 MID
D6 8 35 EMP
D7 9 34 CH/DACKR
NC 10 33 RESET
D8 11 32 NC
D9 12 31 DVDD
D10 13 30 AVDD
D11 14 29 AOUTR
NC 15
D12 16
D13 17
D14 18
D15 19
NC 20
DGND 21
AGND 22
NC 23
NC 24
NC 25
NC 26
TEST4 27
AOUTL 28

NC : No Connection

56-pin plastic QFP

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PIN DESCRIPTIONS

Symbol Type Description

For 8-bit bus interface, the command allows these pins to be configured to be inputs to input
data to and from an external memory. Otherwise, these pins are configured to be inputs only.
D15-D8 I/O
For 16-bit interface, these pins are a bidirectional data bus to input data to and from an external
microcontroller and memory.
Birirectional data bus to input data and output status to and from an external microcontroller
D7-D0 I/O
and memory.
WR I Write pulse input pin. This pin pulses "L" when command or voice data is input to D15-D0 pins.
RD I Read pulse input pin. This pin pulses "L" when status is output to D7-D0 pins.
Accepts write pulse and read pulse when this pin is "L". Does not accept write pulse and read
CS I
pulse when this pin is "H".
Voice data is input to D15-D0 pins when this pin is "H". Command is input to and status is
D/C I
output from D7-D0 pins when this pin is "L".
BUSY O This pin outputs a "L" level during, PLAYBACK or PAUSE.
"H" level indicates that there is no data in FIFO memory. Active "H" can be changed to active "L"
EMP O
by command input.
"H" level indicates that more than half of the FIFO memory space is filled with data.
Voice synthesis starts when MID changes to "H" level. Active "H" can be changed to active "L"
MID O
by command input. This pin outputs a synchro signal for voice data input when non-use of FIFO
is selected.
"H" level indicates that FIFO memory is full of data. This pin is "H" and data cannot be written in
FIFO memory. Active "H" can be changed to active "L" by command input.
FUL/DREQR O
When DMA transfer is selected, "H" level DREQR outputs a signal to request a DMA transfer.
Active "H" can be changed to active "L" by command input.
When stereo playback is selected and CH is "H", voice data is written in right FIFO memory, and
the EMP, MID or FUL pin outputs the status of right FIFO memory.
When CH is "L", data is written in right FIFO memory, and the EMP, MID or FUL pin outputs the
CH/DACKR I status of left FIFO memory. Set this pin to "L" during monophonic playback.
When DMA transfer and stereo playback are selected, DACKR is selected. In this case, DACKR
outputs a DMA transfer acknowledge signal. When DACKR is "L", the IOW signal is accepted.
Active "L" can be changed to active "H" by command input.
When DMA transfer is selected, "H" level DREQL outputs a signal to request a DMA transfer.
DREQL O
Active "H" can be changed to active "L" by command input.
DACKL inputs a signal when DMA transfer is permitted by the DMA controller. When DACKL
is "L", IOW signal is accepted. When stereo playback is selected, DACKL is a DMA transfer
DACKL I
acknowledge signal for left FIFO memory. Active "L" can be changed to active "H" by command
input. If DMA transfer is not used, set this pin to "H" level.

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PIN DESCRIPTIONS

Symbol Type Description

Signal to write external memory data to MSM9842 during DMA transfer.
IOW I
If DMA transfer is not used, set this pin to "H" level.
DASD O 16-bit serial data output pin when external DAC is used.
SOCK O Synchronizing clock for 16-bit serial data input when external DAC is used.
XT I Oscillator connection pins. When external clock is used, input clock into XT pin and leave XT
XT O pin open.
Outputs sampling frequency selected at playback. This sampling frequency is used as a
VCK O
synchronizing signal when external DAC is used.
RESET I When this pin is "L", the LSI is initialized.
TEST0
TEST1 I Pins for testing. Set the pins to "L".
TEST2
TEST3 I Pin for testing. Set the pin to "H".
TEST4 O Pin for testing. Set the pin to "OPEN".
Left side output pin for built-in LPF. This is the output pin of playback wavefroms, and is
AOUTL O
connected to the amplifier for driving speakers.
Right side output pin for built-in LPF. This is the output pin of playback wavefroms, and is
AOUTR O
connected to the amplifier for driving speakers.
Digital power supply pin. Insert a minimum 0.1 mF bypass capacitor between this pin and
DVDD —
DGND pin.
DGND — Digital GND pin.
Analog power supply pin. Insert a minimum 0.1 mF bypass capacitor between this pin and
AVDD —
AGND pin.
AGND — Analog GND pin.

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ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Rating Unit

Power Supply Voltage VDD Ta=25°C –0.3 to + 7.0 V
Input Voltage VIN Ta=25°C –0.3 to VDD+ 0.3 V
Storage Temperature TSTG — –55 to + 155 °C

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Condition Range Unit

Power Supply Voltage VDD DGND=AGND=0V 2.7 to 5.5 V
Operating Temperature TOP — –40 to +85 °C
Master Clock Frequency fOSC — 4.0 to 6.0 MHz

ELECTRICAL CHARACTERISTICS

DC Characteristics

DVDD=AVDD=2.7 to 5.5V, DGND=AGND=0V, Ta=–40 to +85°C

Parameter Symbol Condition Min. Typ. Max. Unit
High-level Input Voltage VIH — VDD¥0.85 — — V
Low-level Input Voltage VIL — — — VDD¥0.2 V
High-level output Voltage VOH IOH=–40 mA VDD–0.3 — — V
Low-level output Voltage VOL IOL=2 mA — — 0.45 V
High-level Input Current (*1) IIH1 VIH=VDD — — 10 mA
High-level Input Current (*2) IIH2 VIH=VDD — — 20 mA
DVDD=AVDD=4.5 to 5.5 V, VIH=VDD 30 150 300 mA
High-level Input Current (*3) IIH3
DVDD=AVDD=2.7 to 3.6 V, VIH=VDD 10 50 100 mA
Low-level Input Current (*1) IIL1 VIL=DGND –10 — — mA
Low-level Input Current (*2) IIL2 VIL=DGND –20 — — mA
DVDD=AVDD=4.5 to 5.5 V,
— 15 30 mA
fosc=4.096 MHz, whithout load
Operating Current consumption IDD
DVDD=AVDD=2.7 to 3.6 V,
— 10 20 mA
fosc=4.096 MHz, whithout load
At power down, without load
— — 10 mA
Ta=–40 to +70°C
Stanby Current consumption IDDS
At power down, without load
— — 50 mA
Ta=–40 to +85°C

*1 Applicable to input excluding XT pin.

*2 Applicable to XT pin.
*3 Applicable to TEST0, TEST1.

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CPU INTERFACE EXAMPLES

1) Interface when DMA controler is used (16-bit bus)

Memory

M9842

DMA D15 to 0
Controller
DREQL
DACKL
IOW
DREQR
DACKR

MCU

RD
WR
CS
D/C

Data bus

2) MCU & external memory interface (16-bit bus)

Memory
M9842

D15 to 0
DREQL
DACKL
IOW

MCU

RD
WR
CS
D/C
CH
EMP
MID
FUL

Data bus

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PACKAGE DIMENSIONS
(Unit : mm)

QFP56-P-910-0.65-2K

Mirror finish

Package material Epoxy resin

Lead frame material 42 alloy
Pin treatment Solder plating (≥5 mm)
Oki Electric Industry Co., Ltd. Package weight (g) 0.43 TYP.
Rev. No./Last Revised 4/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

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NOTICE
1. The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.

2. The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.

3. When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.

4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or

unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.

5. Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.

6. The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.

7. Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.

8. No part of the contents contained herein may be reprinted or reproduced without our prior
permission.

9. MS-DOS is a registered trademark of Microsoft Corporation.

Copyright 2000 Oki Electric Industry Co., Ltd.

Printed in Japan

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