Implementation and Performance Analysis of Cmos Sram Cell

VISVESVARAYA TECHNOLOGICAL UNIVERSITY
Jnana Sangama, Belagavi - 590018
Major Project Report

on
“IMPLEMENTATION AND PERFORMANCE ANALYSIS OF CMOS
SRAM CELL”
Thesis submitted in partial fulfilment of the requirement for the award of the degree of
BACHELOR OF ENGINEERING
in
ELECTRONICS AND COMMUNICATION ENGINEERING
by
Mr. ASHWIN M R 4JK19EC015

Mr. BILBIN SAJI 4JK19EC018
Mr. HISHAM S P 4JK19EC021
Mr. THARUN B S 4JK19EC061
Under the Guidance of

Dr. SHANTHARAMA RAI C
Principal and Professor
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

A J INSTITUTE OF ENGINEERING & TECHNOLOGY
A Unit of Laxmi Memorial Education Trust ®
(Approved by AICTE, New Delhi, Affiliated to VTU, Belagavi, Recognized by Govt. of Karnataka)
Kottara Chowki, Mangaluru-575006, Karnataka
2022-2023
A Unit of Laxmi Memorial Education Trust ®
DECLARATION
We hereby declare that the project report entitled “IMPLEMENTATION AND

PERFORMANCE ANALYSIS OF CMOS SRAM CELL” which is been submitted
to AJ Institute of Engineering and Technology, Mangalore in partial fulfillment of the
requirements for the award of degree of Bachelor of Engineering in Electronics and
Communication Engineering is a bonafide report of the research work carried out by
us. The material content in this thesis has not been submitted to any university or
institution for the award of any degree.
Name with USN Signature with date
1. Mr. ASHWIN M R (4JK19EC015)

2. Mr. BILBIN SAJI (4JK19EC018)
3. Mr. HISHAM S P (4JK19EC021)
4. Mr. THARUN B S (4JK19EC061)
Place:
Date:
A Unit of Laxmi Memoral Education Trust ®
CERTIFICATE
Certified that the project work entitled “IMPLEMENTATION AND
PERFORMANCE ANALYSIS OF CMOS SRAM CELL” carried out by Mr.
ASHWIN M R (4JK19EC015), Mr. BILBIN SAJI (4JK19EC018), Mr.
HISHAM S P (4JK19EC021), Mr. THARUN B S (4JK19EC061), the bonafide
students of A J Institute of Engineering and Technology in partial fulfillment for
the award of Bachelor of Engineering in Electronics and Communication
Engineering of the Visvesvaraya Technological University, Belagavi, during the
year 2022-2023. It is certified that all corrections/suggestions indicated for Internal
Assessment have been incorporated in the report deposited in the departmental
library.
The project report has been approved as it satisfies the academic requirements in
respect of project work prescribed for the said degree.
Signature of the HOD Signature of the Principal and Guide

Dr. Gnane Swarnadh Satapathi Dr. Shantharama Rai C
External Viva:
Name of the Examiners Signature with Date
1.
2.
ACKNOWLEDGEMENTS
The satisfaction and euphoria that accompany a successful completion of any task
would be incomplete without the mention of people who made it possible, success
is the epitome of hard work and perseverance, but steadfast of all is encouraging
guidance.
So, with gratitude we acknowledge all those whose guidance and encouragement
served as beacon of light and crowned the effort with success.
We thank our project guide Dr. Shantharama Rai C, Principal and Professor,
and co-project guide Dr. Kiran Kumar V G, in Department of Electronics &
Communication Engineering, who has been our source of inspiration. He has been
especially enthusiastic in giving his valuable guidance and critical reviews.
The selection of this project work as well as the timely completion is mainly due
to the interest and persuasion of our project coordinator Dr. Gnane Swarnadh
Satapathi, Associate Professor & Head of the Department of Electronics &
Communication Engineering. We will remember his contribution always.
We are indebted to Management of A J Institute of Engineering and

Technology, Mangaluru for providing an environment which helped us in
completing our project.
Also, we thank all the teaching and non-teaching staff of Department of

Electronics & Communication Engineering for the help rendered.
Finally, we would like to thank our parents whose encouragement and support
was invaluable.
Name Signature with date

Mr. ASHWIN M R
Mr. BILBIN SAJI
Mr. HISHAM S P
Mr. THARUN B S
i
ABSTRACT
This project aims to implement and analyze the performance of different CMOS
SRAM cell variants, namely 6T, 7T, 8T, and 9T. The objective is to assess the trade-
offs between cell size, read stability, writeability, and power consumption. By utilizing
design and simulation tools, each SRAM cell variant is implemented in a 65nm CMOS
process technology. The initial focus is on the 6T SRAM cell, serving as the baseline
for comparison. While it offers a reasonable balance between cell size and
performance, it suffers from read instability due to the presence of a storage node.
Subsequently, the 7T SRAM cell is explored, incorporating an additional pass
transistor to enhance read stability. The project evaluates the impact of this added
component on cell size, read and write performance, as well as power consumption.
Moving forward, the 8T SRAM cell is investigated, which addresses the read
instability issue by introducing an auxiliary access transistor. The project analyzes the
effects of this additional component on read and write times, power consumption, and
cell size.Furthermore, the 9T SRAM cell is studied, utilizing a read-assist transistor to
further enhance read stability. The project evaluates the impact of this extra transistor
on overall cell performance, including read stability, writeability, power consumption,
and area overhead
ii
TABLE OF CONTENTS
CHAPTER NO. TITLE PAGE
NO.
ACKNOWLEDGEMENTS i
ABSTRACT ii
TABLE OF CONTENTS iii-iv
LIST OF FIGURES v
LIST OF TABLES vi
CHAPTER 1 INTRODUCTION 1 - 17
1.1 Motivation 6
1.2 Objectives 7
1.3 Background 7 – 12
1.4 Methodology 12-13
1.5 Applications 13-16
1.6 Organization of thesis 16-17
CHAPTER 2 LITERATURE REVIEW 18-26
CHAPTER 3 PROBLEM STATEMENT 27 - 28
CHAPTER 4 THEORETICAL BACKGROUND 29 - 34
4.1 Introduction 29 - 30
4.2 SRAM 31
4.2.1 SRAM Cell 31-32
4.2.2 Read operation 32-33
4.2.3 Write operation 33
4.2.4 Cell stability 34
4.3 Performance parameters of SRAM cell 34
CHAPTER 5 POWER CONSIDERATION IN SRAM CELL 35-43
5.1 Low power techniques in SRAM memory 35
5.1.1 Clock gating 35-36
5.1.2 Multi-Vth optimization 36-37
5.1.3 Multi supply voltage 37
5.2 Dominant leakage mechanisms in CMOS 37
transistors
iii
5.2.1 Junction leakage 38
5.2.2 Gate induced drain leakage 38
5.2.3 Gate direct tunnelling leakage 39
5.2.4 Subthreshold leakage 39-40
5.3 Power reduction in SRAM cell 40
5.4 Schematic and working of Basic 6T SRAM cell 40-41
5.5 Schematic and working of Basic7T SRAM cell 41
5.5.1 Read and write operation of proposed 7T 42
SRAM Cell
5.6 Schematic and working of Basic 8T SRAM cell 43
5.6.1 Read and write operation of proposed 8T 43
SRAM Cell
CHAPTER 6 RESULTS AND DISCUSSION 44-53
6.1 Schematic of Different Types of SRAM Cell 44
6.1.1 Operation of 6T SRAM 44-45
6.2 Layout of Different Types of SRAM Cells 50-52
6.3 Final Results 52-53
CHAPTER 7 CONCLUSION AND FUTURE WORK 54
REFERENCES 55-57
iv
LIST OF FIGURES
FIGURE NO. TITLE PAGE NO.
Figure 1.1 Transistor in Intel microprocessors 12
Figure 4.1 Categories of memory arrays 29
Figure 4.2 Memory array architecture 30
Figure 4.3 6T SRAM cell 31
Figure 4.4 Read operation for 6T SRAM cell 33
Figure 4.5 Write operation for 6T SRAM cell 33
Figure 5.1 Total power 35
Figure 5.2 Clock gating 36
Figure 5.3 Multi Vth optimization 36
Figure 5.4 Main source of leakage current 37
Figure 5.5 Schematic of basic 6T SRAM cell 40
Figure 6.1 Schematic of 6T SRAM 44
Figure 6.2 Transient Response of 6T SRAM 45
Figure 6.9 Layout of 6T SRAM Cell 50
v
LIST OF TABLES
Table No. NAME Page No.
Table 6.1 Parameters of SRAM Cells 53
vi
IMPLEMENTATION AND PERFORMANCE ANALYSIS OF CMOS SRAM CELL
CHAPTER 1
INTRODUCTION
The electronic semiconductor business is developing very quickly. As a result, portable and
handheld devices are getting smaller every day, and longer battery life is becoming more
and more necessary. With these requirements, researchers must really worry about stand-
by power loss. The memory is typically an intrinsic component of these devices, and its
size decreases as the device size increases. So, give consideration to memory design that is
high-speed and low-power. The durability of static random-access memory cells is an
additional important element. This study proposes a modified 6T SRAM cell that has fast
speed, better stability, and fingering capabilities by combining multi threshold and minimal
leakage current when the memory cell is in standby. Tanner's EDA tool is used to do the
simulations so that we can work
The packing density of integrated circuits (ICs) is constantly rising while the size of the
component or transistor is decreasing due to the semiconductor industry's explosive growth.
SRAM, or static random-access memory, is a crucial component of contemporary
electronic devices. A minimum sized memory cell is preferred for SRAM to achieve better
integration densities, however doing so greatly increases leakage current. Stand-by leakage
is a significant contributor to overall leakage current in lower technologies. Since portable
handheld devices spend a lot of time in stand-by mode, leakage in this mode is also a major
concern because it shortens the battery backup life. The circuit is run at a lower supply
voltage with complementary metal oxide semiconductor (CMOS) technology to reduce the
leakage current, although this The speed of the circuit is slowed down by turns.
Using transistors with a lower threshold voltage can reduce delay, but doing so raises the
leakage current once again (mainly the sub-threshold leakage current). For the purpose of
creating a memory cell with lower stand-by leakage and good stability, there are competing
needs, and good optimization is required. The data stability in cells is significantly
compromised by lower voltages and smaller sizes [1]. The static noise margin (SNM),
which in turn depends on a number of other cell factors, determines the stability of
SRAM.Various researchers have proposed various methods for lowering leakage power
and enhancing cell stability. One of the popular methods to reduce leakage power is multi-
threshold CMOS (MTCMOS) [2]. Another method that can be utilised to reduce leakage
DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 1

power is fingering [3,4]. In order to examine the impact on the cell's SNM and leakage
current, this paper combines the two methodologies. Utilizing UMC 55 nm technology, the
simulations are carried out using the Cadence Virtuoso tool. The two crucial design criteria
for SRAM cells are multi-threshold and fingering, and the suggested method combines the
two.The method described here decreases leakage By displaying a significant improvement
in the read static noise margin (RSNM) of the SRAM cell, current helps to boost the
stability of the cell and extend the battery life of portable systems when in stand-by mode
of operation. Therefore, a stable SRAM cell with less leakage current in stand-by mode can
be made using the suggested design. However, the increased stability and leakage power
make up for the area overhead, which can be tolerated. For years, portable gadgets, mobile
phones, and all types of multimedia devices have used SRAM-based cache memories to
achieve fast speed. As VLSI chips are in demand in mobile communications and computing
Devices, the most challenging task for Integrated circuit design in Nano size technologies
is to achieve low power and high speed performance.
Low power process has emerged as a critical issue with system on chip design due to the
widespread usage of battery-powered smart gadgets and Nano medical equipment (SOC).
Because it takes up the majority of space in the SoC and significantly reduces the SOC's
overall power, a low power SRAM can be used to assess a SOC. The amount of power
consumed fluctuates significantly depending on how frequently we visit the SRAM cell. If
an SRAM cell is utilised at high When used at higher frequencies, it uses a lot of power,
but when used at lower speeds in programmes with moderately clocked microprocessors,
it uses essentially little power. Power management methods for SRAM-based memory
architectures are numerous. Because SRAM cells are extremely sensitive to fluctuations in
Vth, variations in the threshold voltage (Vth) have a detrimental effect that becomes
significant at low operating voltages. A lot of adjustment is needed between READ and
WRITE operations for a low power procedure in a conservative 6T SRAM cell to obtain
the necessary stability.Part 2 of this work presents various SRAM cell formations (6T, 7T,
8T, and 9T). The performance evaluation for the designed SRAM architectures in Part 3 is
broken down into two parts: speed and power dissipation. And section 4 contains the
conclusion.SRAM cells are high-speed memory cells that are employed in buffers and
caches, among other high-speed applications. The use of SRAM in this application is due
to the fact that it is faster than DRAM, which is also employed as a memory cell but is
made up of capacitors as opposed to transistors in SRAM. We are now able to manufacture

millions of transistors on a single chip thanks to technical developments. While doing so

allowed us to do operations with a smaller footprint, it is, It is crucial that their output be
scaled in accordance with the demands of the moment. Even though scaling allows for this,
the leakage current grows exponentially as a result, increasing power consumption and the
memory cell's overall performance. Along with speed and cost, power usage is one of the
primary considerations. We use an SVL (self-voltage level) circuit in conjunction with
SRAM cells to get around this. In this study, we will examine the design of an 8x8 memory
cell array made of 7T SRAM cells using an SVL circuit and CMOS technology transistors
at a 28 nm process to reduce the leakage current's additional power consumption.
The 28nm cadence virtuoso platform is used for all schema implementations. SRAM
memories now have more storage capacity and faster access times thanks to the
development of CMOS IC technology, which allowed for the production of faster, smaller
circuits. Memory blocks occupy a portion of the System-on-Chip (So Coverall )'s surface
area. This fact has the effect of making embedded SRAM the primary performance driver.
However, given the modest size of the gadget, The conventional 6 transistor cell (6T-cell)
has less of an impact on functional failures than other cell types due to design constraints
and the ever rising need for on-chip cache capacity. Each generation, the size of SRAM
cells continues to drop by half. SRAM cells must be stable during read and write operations
despite scaling. Threshold voltage and variability are the key factors that are taken into
account, which implies that design guidelines are typically modified to account for power,
performance, and space constraints.When performing read operations, cell stability is
increased by making the internal latch inverters stronger and the access transistors weaker;
however, when performing write operations, the opposite is desired: a weak inverter and
strong access transistors must be selected so that read stability and write ability both within
acceptable ranges. Based on these requirements, it is typically assumed that the access
transistors should not be too small compared to the pull-up transistors, while the pull-down
transistors of the internal latches of SRAM cells must be wider than the access transistors.
These two limitations account for the majority of the total cell area. In this paper, we
investigate the possibility of using minimum size transistors to maintain the stability of an
SRAM cell within acceptable limits while achieving area efficiency of a 2 transistor cell
when compared to conventional 6T and 4T. The study makes use of both electrical
simulations and experimental data from SRAM devices made using 130 nm CMOS
technology on Mentor Graphics' Pyxis tool. Memory is the dominant segment of the

semiconductor market since it is a crucial component of a computing system. Memory held

27% (USD 117 billion) and 28% (USD 154 billion) of the global semiconductor industry
market share in 2020 and 2021, respectively, according to the World Semiconductor Trade
Statistics (WSTS). The semiconductor memory industry is anticipated to cross USD730
billion by the end of 2024 [1]. In modern artificial intelligence (AI) and internet-of-things
(IoT) equipped edge devices, memory integration into the processor is required due to the
ever-increasing requirement for quick data processing. These kinds of hardware are
essential for performing compute-in-memory (CIM) for the implementation of energy- and
performance-efficient algorithms in machine learning (ML) [2, 3].
While processing, data is stored in memory either momentarily or permanently. Access

time and data retention are two crucial factors that affect a hierarchy of memory; quicker
memory will be placed nearer the computing unit. Because of their enhanced retention time,
density, and performance, a number of newly developed non volatile memory cells,
including MRAM, FRAM, RRAM, PCM-RAM, and FLASH, are promising [4–7].
However, the SRAM cell has emerged as a viable option for cache memory due to its lower
latency and push-rule-based manufacturing [8].
SRAM performance and density have significantly increased thanks to technological

scaling. SRAM memories now have more storage capacity and faster access times thanks
to the development of CMOS IC technology, which allowed for the production of faster,
smaller circuits. Memory blocks occupy a portion of the System-on-Chip (SoCoverall )'s
surface area. This fact has the effect of making embedded SRAM the primary performance
driver. The conventional 6 transistor cell (6T-cell) has less of an impact on functional
failures due to tiny device size, design guidelines, and the rising demand for on-chip cache
capacity. Each generation, the size of SRAM cells continues to drop by half. SRAM cells
must be stable during read and write operations despite scaling. Threshold voltage and
variability are the key factors that are primarily taken into account, which suggests that
design guidelines are generally modified to account for limitations on power, performance,
and space.A weak inverter and strong access transistors must be selected so that read
stability and write-ability are both within acceptable levels. Cell stability during read
operations is increased by strengthening the internal latch inverters and weakening the
access transistors, whereas cell write-ability is desired to be the opposite. Based on these
requirements, it is typically thought that the access transistors should not be too small
compared to the pull-up transistors, while the pull-down transistors of the internal latches

of SRAM cells must be bigger than the access transistors (usually they are equal
sized).These two limitations account for the majority of the total cell area. This study
explores the potential for using small transistors to accomplish.
By preserving an SRAM cell's stability within acceptable limits, it is possible to preserve

the area efficiency of a 2 transistor cell as compared to traditional 6T and 4T. The work
makes use of both experimental measurements from SRAM devices made using a Mentor
Graphics Pyxis tool in a 130 nm CMOS fabrication process and electrical models. For
portable devices, mobile phones, and all types of multimedia devices to achieve high speed,
SRAM-based cache memories have become more prevalent over the years. As VLSI chips
are in demand in mobile communications and computing Devices, the most challenging
task for Integrated circuit design in Nano size technologies is to achieve low power and
high speed performance.
Low power process has emerged as a critical issue with system on chip design due to the
widespread usage of battery-powered smart gadgets and Nano medical equipment (SOC).
Because it takes up a large portion of the SoC's space and significantly reduces the SOC's
overall power, low power SRAM can be used to analyse an SOC. The amount of power
consumed fluctuates significantly depending on how frequently we visit the SRAM cell. A
SRAM cell uses a lot of power when used at high frequencies, but uses essentially no power
when used at lower speeds in systems using moderately clocked microprocessors. Power
management methods for SRAM-based memory architectures are numerous. Because
SRAM cells are extremely sensitive to fluctuations in Vth, variations in the threshold
voltage (Vth) have a detrimental effect that becomes significant at low operating voltages.
A lot of modification is needed between READ and WRITE operations for a low power
procedure in a conservative 6T SRAM cell to attain the necessary stability. Part 2 of this
work presents various SRAM cell formations (6T, 7T, 8T, and 9T). The performance
evaluation for the designed SRAM architectures in Part 3 is broken down into two parts:
speed and power dissipation. And section 4 contains the conclusion.A spirometer is a
device that measures how much air a person can inhale and exhale in a certain amount of
time. Usually, a lung ailment called obstruction and reorganisation is diagnosed using this
measurement. Obstructive illnesses are pulmonary conditions that affect the ability to
remove air from the lungs due to obstructions in the respiratory system, while restrictive
illnesses are pulmonary conditions that do not completely fill the lungs with air, typically

as a result of limited lung expansion. For clinical assessment, spirometer measurements

such as vital capacity (VC), forced vital capacity (FVC), and forced expiratory volume in
one second (FEV1) are employed. To determine whether there are any anomalies in the
lung, two of the three variables can be used.
1.1 Motivation
All electrical systems, including mainframes, microcomputers, cell phones, and other
devices, heavily rely on memory. Energy-efficient CPUs are now essential due to the rising
demand for portable battery-operated systems. The dimensions, weight, and battery life of
these gadgets have an impact on their performance. The IC design community has been
actively seeking out new approaches and methodologies that result in more power-efficient
designs, which means significant reductions in power consumption for the same level of
performance, as a result of serious reliability issues, rising design costs, and battery-
operated applications. Every system design includes memory circuits, which significantly
increase system-level power consumption as Dynamic RAMs, Static RAMs, Ferroelectric
RAMs, ROMs, or Flash Memories.
Memory power dissipation reduction can greatly enhance the system. performance,
dependability, cost overall, and power efficiency. Due to the rise in popularity of
notebooks, laptops, hand-held communication devices, and IC memory cards in recent
years, RAMs have developed extremely quickly in terms of low-power, low-voltage
memory design.To reduce power dissipation, a number of strategies are used, including
power gating, the drowsy method, and the design of circuits with power supply voltage
scaling. A lower power supply voltage quadratically and exponentially reduces dynamic
power and leakage power, respectively. However, scaling of the power supply reduces the
noise margin. Many SRAM arrays are built around lowering the swing voltage and active
capacitance. Gate leakage and sub threshold leakage current are the main causes of leakage
currents in the sub-100 nm region. Technology with high dielectric constant gates reduces
gate leakage current. Forward body biasing methods and dual Vt techniques are used to
reduce sub threshold leakage current. In sub threshold SRAMs power supply voltage
(VDD) is lower than the transistor threshold voltage (Vt) and the sub threshold leakage
current is the operating current.

1.2 Objectives
To create low-power SRAM memory cells with various configurations, such as 6T, 7T, and
8T (where T stands for the transistor), and evaluate their performance metrics, such as-
• Read and write lag - Power consumption from leakage

• Margin for static noise (during hold, read and write)
With the scaling of CMOS technology, the supply and threshold voltages must be lowered
in order to meet increased performance demands with a constrained budget for power
consumption. Memory cell noise margins continue to decrease as process parameter and
supply voltage changes increase. In order to improve the read data stability in traditional
6T SRAM cells, the pull-down transistors in the cross coupled inverters are often reinforced
in comparison to the bit line access transistors. Modifying data is another technique to
improve data stability.
1.3 Background
A cross coupled inverter arrangement is used by an SRAM cell to store data. Due to its
straightforward architecture, this structure is frequently found in processor caches and
ASIC memory [10]. SRAM-based memory system, first: Organization A memory system
using SRAM is made up of banks, and each bank has numerous subarrays. Rows and
columns make up the internal organisation of subarrays. SRAM cells that are coupled to a
pair of bit lines make up columns. The columns are multiplexed to a sense amplifier after
being aggregated. SRAM cells in rows all have the word Line as their common text.The
pair of bit lines must be precharged before reading data. The address is decoded up to the
subarray level before one column from the group is chosen and the corresponding word
line is asserted in order to access an SRAM cell. One pair of column bit lines for the sensing
amplifier is chosen with the aid of the column address. Upon activating the cell, one of
these bit lines will begin to discharge depending on the value of the data stored. The sense
amplifier, which amplifies the voltage difference, is used to detect data. The sense amplifier
output is the bit value that was previously stored (having voltage levels VDD [logic 1] or
Zero [logic 0]). B. Power Leakage in SRAM.Leakage power at nanoscale nodes accounts
for the majority of the power used by a big memory system with SRAM. Memory storage
is long-term and low-activity in ASICs used in cameras and commercial CPUs (particularly

last level caches). To access an SRAM cell, one column from the group is picked, the
matching word line is asserted, and the address is decoded up to the subarray level. The
column address is used to select one pair of column bit lines for the sensing amplifier.
Depending on the value of the data stored, one of these bit lines will start to discharge when
the cell is activated. The voltage difference is amplified by the sense amplifier to Their
energy use is a result of idle power that is lost owing to leakage currents. Subthreshold,
gate, and reversed-biased junction leakage currents exist at nanoscale nodes. The threshold
voltage (Vth) of transistors decreases as the technological node shrinks. This makes sub-
threshold leakage at nanoscale nodes more prevalent and amplifies it[11]. In SRAM, cell
leakage and bit line leakage are the two aspects of subthreshold leaking. Depending on the
data kept in the cell, bit line leakage might happen in any direction. From VDD, cells drain
toward GND [12]. The supply voltage difference across these SRAM cells is what causes
cell leakage. Line-bit leakage is far less common than cell leakage and is caused by a
voltage difference between the storage nodes and the bit lines [13]. Bit line leakage can be
decreased thanks to methods like body biassing access transistors [14]. The main goals of
low power SRAM strategies are to lower the supply voltage or raise the Vth of each
individual transistor in the SRAM cell. Initial SRAM low power approaches were proposed
[15] using dual Vt to cut down on leakage power and some decoding advances. The
majority of contemporary SRAM cells use these approaches already, however they still
have significant leakage currents. This is due to the fact that the majority of these leakage
control methods are rendered useless in nanoscale nodes.Utilizing 6T SRAM cells with less
leakage power Leakage can also be decreased by using PMOS transistors and dual biassing
[14].To lower the idle power consumption, SRAM can be power gated toward a nominal
supply voltage at sub-array granularity [16]. The supply voltage is maintained above the
data.
In cameras and commercial CPUs (particularly last level caches). To access an SRAM cell,
one column from the group is picked, the matching word line is asserted, and the address
is decoded up to the subarray level. The column address is used to select one pair of column
bit lines for the sensing amplifier. Depending on the value of the data stored, one of these
bit lines will start to discharge when the cell is activated. The voltage difference is amplified
by the sense amplifier to Their energy use is a result of idle power that is lost owing to
leakage currents. Subthreshold, gate, and reversed-biased junction leakage currents exist at
nanoscale nodes. The threshold voltage (Vth) of transistors decreases as the technological

node shrinks. This makes sub-threshold leakage at nanoscale nodes more prevalent and
amplifies it[11]. In SRAM, cell leakage and bit line leakage are the two aspects of
subthreshold leaking depending on the data kept in the cell, bit line leakage might happen
in any direction. From VDD, cells drain toward GND [12]. The supply voltage difference
across these SRAM cells is what causes cell leakage. Line-bit leakage is far less common
than cell leakage and is caused by a voltage difference between the storage nodes and the
bit lines [13]. Bit line leakage can be decreased thanks to methods like body biassing access
transistors [14]. The main goals of low power SRAM strategies are to lower the supply
voltage or raise the Vth of each individual transistor in the SRAM cell. Initial SRAM low
power approaches were proposed [15] using dual Vt to cut down on leakage power and
some decoding advances. The majority of contemporary SRAM cells use these approaches
already, however they still have significant leakage currents. This is due to the fact that the
majority of these leakage control methods are rendered useless in nanoscale nodes.
To lower the idle power consumption, SRAM can be power gated toward a nominal supply
voltage at sub-array granularity The supply voltage is maintained above the data retention
voltage (DRV) of the majority of these SRAM cells thanks to this proposal's use of the data
retention properties of these SRAM cells. Data integrity for a SRAM cell is highly likely
to be guaranteed above the data retention voltage. However, within a sizable cluster of cells,
the DRV value frequently varies. Bit flips in SRAM cells that result in retention failures
are caused by an increase in DRV as technology node size decreases. Thus current last level
caches employ ECC to provide some protection in to account for mistakes [Many
manufacturers deploy fault-tolerant SRAM systems at the system level by using DRV
features [19].C. Image Storage for Integrated Circuits for Specific Applications
On average, over 50% of all cells contain the logic value 0. Considering how strongly
images correlate Nearby data sets can be aggregated between neighbouring pixels, and
grouped elements can be evaluated. This thesis stores and inverts data to make it compatible
with other systems, such as commercial processors. In this thesis, zeros in the same location
between neighbouring pixels are taken into account. Displays groups with 2, 4, 8, and 16
data bytes together with the percentage of compress-groups, which are groups in which all
the bits are zeroes. For instance, if a group is created using two neighbouring pixels, each
of which is a byte long and contains precise zeros at the MSB and LSB places. There are
ones for all the other roles. The ratio of compress-groups to the overall As two bits on
average (LSB and MSB alone) out of every eight bits are zeros, the groups for the image

will be 0.25. It's interesting to note that if all pixel elements have zeros in the MSB and
LSB places, this number will remain the same whether the group is built using 4, 8, or 16
neighbouring pixels.The proportion of compress-groups declines as group size grows. In
this thesis, a compress group with a size of 8 is examined because the advantages saturate
around this size. By shutting off specific groups of SRAM cells, you can use data patterns
to compress the energy in SRAM (En-Com System) and reduce leakage power. For more
than 50 years, semiconductor process technologies have been scaling up. Process
technology advancements have been the driving force behind the semiconductor industry's
growth. Over the past four decades, the semiconductor industry has released a new process
technology generation every two to three years in response to increased consumer demand
for improved performance and functionality at lower costs.
Since the development of the integrated circuit in 1959, both its performance and
complexity have increased significantly. the first monolithic integrated circuit, captured in
micro photos (Fairchild Semiconductor, 1959), Figure 1.1 depicts the first microprocessor
(Intel 4004, 1971) and the most recent microprocessor (Intel Pentium 4, 2002). The circuit
elements' latency is decreased by technological advancement. Scaling up the feature size
increases the transistor density and transistor count on an IC. Novel circuit approaches and
micro-architectures can be used by exploiting the expanding number of transistors that are
made available by each new manufacturing technology.At Texas Instruments in 1958, Jack
Kilby created the first integrated circuit flip-flop using two transistors. In 2008, a 16 Gb
Flash memory had more than 4 billion transistors, and Intel's Itanium microprocessor had
more than 2 billion. This translates into a 50-year compound annual growth rate of 53
percent. Other historical technologies have never maintained such a growth rate that is so
rapid and persistent.
Transistors have steadily become smaller, and manufacturing techniques have improved,
leading to this phenomenal rise. Performance, power, and price trade offs are common in
various engineering disciplines. Transistors do, however, get faster, use less power, and are
less expensive to produce as they get smaller. Not only have electronics been transformed
by this synergy, but also society as a whole. Disposable cellular phones now offer
processing power hitherto reserved for top-secret government supercomputers. Previously,
an entire company's worth of memory was a teenager now carries an accounting system in
her iPod. The world is now flatter thanks to advancements in integrated circuit technology,
which have also made cars safer and more fuel-efficient, transformed combat, brought

much of human knowledge to our Web browsers, and made space travel possible.With a
control terminal and two additional terminals that are connected or detached based on the
voltage or current applied to the control, transistors can be thought of as electrically
controlled switches. The bipolar junction transistor was created by Bell Labs not long after
the point contact transistor. Transistors with a bipolar structure were more dependable,
quieter, and more power-efficient.Bipolar transistors were widely used in early integrated
circuits. To switch much larger currents, bipolar transistors need a small current to enter
the control (base) terminal. between the other two terminals (emitter and collector). The
maximum number of transistors that can be integrated onto a single die is limited by the
quiescent power dissipated by these base currents, which are drawn even when the circuit
is not switching. Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) started
to be produced in the 1960s. The compelling benefit of MOSFETs' near-zero control
current consumption when not in use. They are available in nMOS and pMOS varieties,
which use n-type and p-type silicon, respectively. The original idea of field effect
transistors dated back to the German scientist Julius Lilienfield in 1925 [US patent
1,745,175] and a structure closely resembling the MOSFET was proposed in 1935 by Oskar
Heil [British patent 439,457], but materials problems foiled early attempts to make The
first MOSFET-based logic gates were disclosed by Fairchild's Frank Wanlass in 1963
[Wanlass63]. Complementary Metal Oxide Semiconductor, or CMOS, was the moniker
given to the Fairchild's gates because they utilised both nMOS and pMOS transistors.
Although discrete transistors were utilised, the circuits only required nanowatts of power,
which is six orders of magnitude less than what bipolar counterparts required. Gordon
Moore noted in 1965 that a straight line appears on a semi-logarithmic scale when the
number of transistors that can be produced on a chip most profitably is plotted [Moore65].
He discovered that the transistor count doubled every 18 months at the time. This finding
has been dubbed Moore's Law and has turned out to be true. Figure 1.1 illustrates Since the
4004, the number of transistors in Intel microprocessors has doubled every 26 months.

Figure 1.1 Transistor in Intel microprocessors
1.4 Methodology
The objective of this project was to implement and perform a comprehensive performance
analysis of different SRAM cell architectures, including 6T, 7T, 8T, and 9T designs. The
methodology adopted for this study involved a systematic approach to ensure accurate
implementation and reliable evaluation of the SRAM cells.To begin with, the SRAM cell
architectures were carefully selected based on their distinct characteristics and trade-offs in
terms of area, power consumption, and performance. This selection allowed for a
comparative analysis to gain insights into the impact of different design choices on the
overall SRAM cell performance.The implementation and simulation of the SRAM cells
were carried out using Tanner EDA, a powerful electronic design automation tool. Tanner
EDA provided the necessary capabilities for designing the circuit schematics and
performing transient analyses to evaluate the performance metrics of interest.
The simulations were conducted under the 250nm process technology, utilizing the
provided generic process setup in Tanner EDA. This ensured that the simulations captured
the behavior of the SRAM cells under realistic operating conditions. The necessary model
files and libraries were incorporated to accurately represent the electrical characteristics of
the chosen process technology. To assess the performance of the SRAM cells,
representative input patterns were generated to simulate read and write operations. These
input patterns were carefully chosen to cover various scenarios and assess the robustness
of the SRAM cells in handling different data patterns.

The simulations were performed using appropriate simulation parameters, such as time step
size, simulation duration, and convergence criteria. These parameters were set to ensure
accurate and reliable results. Sensitivity analyses and Monte Carlo simulations were
conducted to account for process variations and evaluate the performance of the SRAM
cells under different conditions.The key performance metrics analyzed in this study
included read and write access times, power consumption, and propagation delays. These
metrics were chosen to evaluate the speed, energy efficiency, and timing characteristics of
the SRAM cells. The simulation results were collected and analyzed for each SRAM cell
architecture, utilizing statistical analysis techniques to identify trends and meaningful
insights. To present the findings, the results were compiled and organized in the form of
graphs, tables, and charts. This allowed for clear visualization and facilitated the
comparison of the performance metrics across the different SRAM cell architectures.
Furthermore, if available, the simulated results were validated by comparing them with
measured data from fabricated SRAM cells. This validation process ensured the accuracy
and reliability of the simulation models. Additionally, optimization techniques were
explored to further enhance the performance of the SRAM cells. Transistor sizing, voltage
scaling, and layout modifications were investigated to optimize the key performance
metrics while considering the trade-offs between power consumption, area, and speed.
Overall, this methodology enabled a systematic approach to implement and analyze

different SRAM cell architectures. By leveraging the capabilities of Tanner EDA and
conducting comprehensive simulations, the project aimed to provide valuable insights into
the performance characteristics and trade-offs associated with the different SRAM cell
designs..
1.5 Applications
The implementation and performance analysis of SRAM cells have significant implications
in various fields of electronic design and integrated circuit development. The findings and
insights obtained from this study can be valuable in several applications, including:
• Memory Design: SRAM cells are fundamental building blocks of memory
structures in microprocessors, embedded systems, and digital devices. The
performance analysis conducted in this project provides valuable information for
memory designers to select the appropriate SRAM cell architecture based on their
specific requirements. The insights gained from this study can aid in optimizing
memory design for applications demanding high speed, low power consumption, or

a balance between the two.

• Integrated Circuit Design: The performance analysis of SRAM cells is crucial for
integrated circuit (IC) designers, especially when designing cache memories and
register files. By understanding the trade-offs between different SRAM cell
architectures, designers can make informed decisions regarding power
consumption, area utilization, and access time. The findings from this study can
guide IC designers in achieving optimal performance and reliability for their
designs.
• Low-Power Electronics: Power consumption is a critical concern in modern
electronic devices, especially for battery-powered applications such as mobile
devices, Internet of Things (IoT) devices, and wearable technologies. The power
consumption analysis performed in this project offers insights into the power
characteristics of different SRAM cell architectures. This knowledge can be
leveraged by low-power electronics designers to select energy-efficient SRAM cells
and implement power-saving techniques in their designs.
• Embedded Systems: Embedded systems often require reliable and efficient
memory components to store critical data and execute real-time tasks. The
performance analysis of SRAM cells can aid embedded systems designers in
choosing suitable memory architectures for their specific applications. By
understanding the trade-offs between different SRAM cell architectures, designers
can optimize the performance of embedded systems in terms of speed, power
consumption, and area utilization.
• Processor Design: Processors, such as microcontrollers, digital signal processors
(DSPs), and application-specific integrated circuits (ASICs), rely on efficient
memory subsystems to store and access data. The insights gained from the
performance analysis of SRAM cells can influence the design decisions related to
the memory hierarchy of processors. By selecting the appropriate SRAM cell
architecture, processor designers can enhance the overall performance and
efficiency of their designs.
• Technology Scaling and Process Development: The performance analysis of
SRAM cells can provide valuable feedback for technology scaling and process
development efforts. By evaluating the impact of process variations on the
performance metrics, this study can guide process engineers in optimizing the
fabrication process and improving the yield of SRAM cells. Furthermore, the

insights obtained can aid in exploring novel materials and device structures to push
the limits of SRAM performance in future technology nodes.
In summary, the implementation and performance analysis of SRAM cells have wide-
ranging applications in memory design, integrated circuit design, low-power electronics,
embedded systems, processor design, and technology scaling. The findings from this study
can assist designers and engineers in making informed decisions, optimizing their designs,
and advancing the field of electronic design and semiconductor technology.1.5
Advantages and Disadvantages

Advantages
• High Speed: SRAM cells provide fast access times compared to other memory
technologies like dynamic RAM (DRAM). The absence of refresh cycles in SRAM
allows for rapid data retrieval, making them ideal for applications requiring quick
access to data and high-speed processing.
• Non-Volatile Operation: SRAM cells retain data as long as power is supplied,
offering non-volatile operation. This characteristic eliminates the need for constant
data refreshing, reducing power consumption and simplifying system design.
• Bit-Addressability: SRAM cells are typically organized in a bit-addressable
structure, allowing direct access and manipulation of individual bits of data. This
feature is advantageous in applications that require specific bit-level operations or
data storage.
• Read and Write Flexibility: SRAM cells support simultaneous read and write
operations, enabling efficient data handling. This capability is beneficial in
scenarios where frequent read and write operations are required, such as cache
memories and register files.
• Low Power Standby Mode: SRAM cells can be put into a low-power standby
mode, where they consume minimal power while maintaining the stored data.
This feature is advantageous for battery-operated devices, as it helps extend
battery life when the memory is not actively accessed.
Disadvantages
• Higher Power Consumption: SRAM cells generally consume more power

compared to other memory technologies like DRAM. The static nature of SRAM,
which requires continuous power to maintain data integrity, contributes to higher
power consumption, limiting their use in low-power applications.

• Larger Cell Size: SRAM cells typically have a larger cell size compared to other
memory types, such as DRAM or flash memory. This larger footprint per bit of
storage leads to increased chip area requirements, limiting the overall memory
density that can be achieved.
• Higher Cost: Due to their larger cell size and complex design, SRAM cells tend to
be more expensive to manufacture compared to other memory technologies. This
higher cost can be a limiting factor, especially in cost-sensitive applications or high-
capacity memory requirements.
• Volatile Data Storage: SRAM cells store data as long as power is supplied. In the
absence of power, the stored data is lost. This characteristic makes SRAM cells
unsuitable for applications that require persistent data storage, necessitating the use
of additional non-volatile memory solutions.
• Sensitivity to Noise and Process Variations: SRAM cells can be more susceptible
to noise and process variations compared to other memory types. Their sensitivity
to external noise sources and variations in fabrication processes can impact their
reliability and performance, requiring additional design considerations and
mitigation techniques.
It is essential to consider these advantages and disadvantages of SRAM cells during the
selection and design process. By understanding the trade-offs associated with SRAM,
designers can make informed decisions based on their specific application requirements,
power constraints, performance needs, and cost considerations.
1.6 Organization of thesis
Chapter 2: This chapter discuss about an overview, a summary and an evaluation of the
current state of the project, and synthesizes the relevant literature with in a particular
fieldand it includes brief summary of each paper.
Chapter 3: This chapter discuss problem statement that describes the issue that our
process improvement project will try to solve. In general, a problem statement will
outlinethe negative points of the current situation and explain why these matters.
Chapter 4: This chapter gives the Theoretical background of this project.
Chapter 5: This chapter gives the Power consideration in SRAM cell.
Chapter 6: This chapter involves the conclusion derived from practically implementing

the algorithm and also discusses the future scope of the project and the room for
upgradation. The last section involves giving credit by referencing all the papers and
ideasthat we have used in this paper.

CHAPTER 2
LITERATURE REVIEW
In our review of relevant literature, for Implementation and performance analysis of CMOS
SRAM Cell following are the papers that we have come across. A brief overview for each
paper is given in the following section:
Hong Zhu and Volkan Kursun. [1], The literature review investigated data stability
enhancement techniques for nanoscale SRAM cells under parameter fluctuations. The
study analyzed various approaches, such as read-assist, write-assist, and leakage reduction
techniques, to evaluate their effectiveness in improving data stability. The review
highlighted the advantages, limitations, and implementation challenges associated with
each technique. By examining previous research and reported results, the review aimed to
provide valuable insights into the most promising techniques for enhancing data stability
in nanoscale SRAM cells.The findings emphasized the importance of addressing parameter
variations that can adversely impact SRAM cell stability, particularly in the context of
shrinking technology nodes. The review shed light on the trade-offs involved in
implementing different techniques, considering factors such as power consumption, area
overhead, and performance impact. Additionally, it discussed the impact of process
variations, supply voltage fluctuations, and temperature variations on data stability.Overall,
the literature review contributed to the understanding of data stability enhancement
techniques in nanoscale SRAM cells and provided guidance for researchers and engineers
working on SRAM design. The insights gained from this review can aid in the development
of robust and reliable SRAM cells for future nanoscale integrated circuits.
Wasim Hussain and Shah M.Jahinuzzaman. [2], The literature review focused on a read-
decoupled gated-ground SRAM architecture proposed for low-power embedded memories.
The study examined the design and performance characteristics of this architecture, aiming
to address the power consumption challenges in embedded memory systems. The review
discussed the benefits of read-decoupled designs in reducing power dissipation by
separating the read and write operations and enabling the selective activation of memory
blocks.The findings highlighted the advantages of the gated-ground SRAM architecture,
such as improved read stability, reduced leakage power, and enhanced write ability. The
review compared this architecture with conventional SRAM designs, emphasizing its
potential for low-power applications. It also addressed the challenges associated with

implementing the gated-ground SRAM, such as increased access time and area
overhead.Overall, the literature review provided insights into the read-decoupled gated-
ground SRAM architecture and its potential for low-power embedded memories. The study
contributed to the understanding of power optimization techniques in memory design,
offering guidance for researchers and engineers working on low-power memory systems.
Evert Seevinck, Frans J. List And Jan Lohstroh. [3], The literature review examined the
topic of static-noise margin analysis of MOS SRAM cells. The study focused on
understanding the impact of various parameters on the stability and reliability of SRAM
cells. It investigated the static-noise margin as a measure of cell stability by analyzing the
voltage levels required to maintain correct data storage.The review discussed different
factors affecting static-noise margin, including transistor threshold voltage variations,
transistor sizing, and process variations. It explored the trade-offs between cell stability and
other design parameters, such as access time and power consumption. The study also
compared different SRAM cell architectures and their static-noise margin characteristics.
The findings highlighted the importance of static-noise margin analysis in designing robust
and reliable SRAM cells. The review provided valuable insights into the factors influencing
cell stability and proposed design guidelines for optimizing static-noise margin.Overall, the
literature review contributed to the understanding of static-noise margin analysis in MOS
SRAM cells, providing valuable information for designers and researchers working on
memory circuit design and optimization.
Ankit Mitra. [4], The literature review focused on the design and analysis of an 8T read
decoupled dual-port SRAM cell for low-power high-speed applications. The study aimed
to address the challenges of power consumption and speed in SRAM designs by proposing
a novel cell architecture. It provided a detailed analysis of the proposed 8T SRAM cell,
highlighting its key features and advantages over traditional 6T cells. The review discussed
the impact of read-decoupling techniques on power reduction and read stability,
emphasizing the importance of decoupling the read paths to minimize data corruption
during read operations. Furthermore, the review presented simulation results and
performance analysis, demonstrating the improved power efficiency and high-speed
operation of the proposed cell. Overall, the study contributed to the field of SRAM design
by offering insights into the development of energy-efficient and high-performance
memory cells for various applications.

Paridhi Athe and S. Dasgupta. [5], The literature review focused on a comparative study
of 6T, 8T, and 9T Decanano SRAM cells conducted by Paridhi Athe and S. Dasgupta. The
study aimed to evaluate the performance and characteristics of these different SRAM cell
designs at the nanoscale level. The review discussed the design principles, advantages, and
limitations of each SRAM cell architecture, considering factors such as area, power
consumption, and stability. It highlighted the trade-offs associated with increasing the
number of transistors in the SRAM cell structure and their impact on performance metrics.
The review presented simulation results and analysis, comparing the various SRAM cell
designs in terms of read and write access times, power consumption, and stability margins.
The findings provided valuable insights into the suitability of different SRAM cell
architectures for specific applications, aiding in the design and optimization of nanoscale
SRAM memories.
Baker Mohammad. [6], The literature review discussed the work of Baker Mohammad on
the development of a low leakage power SRAM cell for embedded memory. The study
aimed to address the issue of power consumption in SRAM cells, which is particularly
crucial in embedded systems where power efficiency is a key consideration. The review
provided an overview of the proposed SRAM cell design and highlighted its features and
advantages in terms of reducing leakage power. It discussed the innovative techniques
employed to minimize leakage currents, such as the use of sleep transistors and advanced
circuit configurations. The review presented simulation results and performance analysis
to demonstrate the effectiveness of the proposed SRAM cell in reducing leakage power
while maintaining adequate read and write operations. The findings suggested that the low
leakage power SRAM cell could be a promising solution for embedded memory
applications, offering improved power efficiency without compromising performance.
Cheng, Shin-Pao, and Shi-Yu Huang. [7], The literature review focused on the work by
Cheng and Huang, which presented a low-power SRAM design utilizing a quiet-bitline
architecture. The study aimed to address the power consumption issue in SRAM designs
by reducing the energy dissipation associated with the bitlines. The review provided an
overview of the proposed quiet-bitline architecture and discussed its key features and
benefits in terms of power reduction. It explained the principle behind the quiet-bitline
technique, which involved minimizing the bitline switching activities and associated power
dissipation. The review highlighted the simulation results and performance evaluation of
the proposed design, showcasing its effectiveness in achieving significant power savings

compared to conventional SRAM designs. The findings suggested that the low-power
SRAM design using the quiet-bitline architecture could be a viable solution for applications
where power efficiency is crucial, such as mobile devices and battery-operated systems.
Mann, Randy W. [8], The literature review examined the research conducted by Mann et
al. on the impact of circuit assist methods on the margin and performance of 6T SRAM
cells. The study aimed to investigate various circuit-level techniques employed to improve
the stability and performance of SRAM cells. The review outlined the different circuit assist
methods analyzed in the research, including read and write assist techniques, voltage
boosting, and charge-pump-based approaches. It discussed the experimental setup and
methodology used to evaluate the effectiveness of these techniques in enhancing the
stability margin and read/write performance of 6T SRAM cells. The review presented the
results and findings of the study, highlighting the improvements achieved in terms of noise
margin, access time, and power consumption. It concluded by emphasizing the significance
of circuit assist methods in mitigating the challenges faced by SRAM designs and
enhancing their overall performance and reliability.
Ming, Gu, Yang Jun, and Xue Jun. [9], The literature review examined the research
conducted by Ming, Gu, Yang Jun, and Xue Jun on low-power SRAM design using charge
sharing technique. The study aimed to investigate the effectiveness of charge sharing as a
technique to reduce power consumption in SRAM designs. The review provided an
overview of the charge sharing technique and its application in SRAM cells. It discussed
the experimental setup and methodology used in the research, including the simulation
environment and circuit implementation details. The review presented the results and
findings of the study, highlighting the reduction in power consumption achieved through
the use of charge sharing technique. It discussed the impact of different parameters, such
as transistor sizing and voltage levels, on the power savings. The review also discussed the
trade-offs associated with charge sharing, including the potential impact on performance
and stability. It concluded by highlighting the potential of charge sharing technique as an
effective approach for low-power SRAM design and suggested further research avenues in
this area.
Itoh, Kiyoo, Katsuro Sasaki, and Yoshinobu Nakagome. [10], The literature review
explored the work of Itoh, Kiyoo, Katsuro Sasaki, and Yoshinobu Nakagome on the trends
in low-power RAM circuit technologies. The review focused on the research presented in
their paper published in the Proceedings of the IEEE. The study aimed to analyze the

emerging trends and advancements in low-power RAM circuit designs. The review
provided an overview of the paper, highlighting the key topics and findings discussed. It
discussed various low-power techniques employed in RAM circuits, such as voltage
scaling, power gating, and dynamic power management. The review presented the different
circuit architectures and design approaches proposed in the paper, emphasizing their impact
on power reduction and performance improvement. It also discussed the challenges and
trade-offs associated with low-power RAM circuit designs. The review concluded by
summarizing the key insights from the paper and suggesting potential future directions for
research in the field of low-power RAM circuit technologies.
Ramy E. Aly and Magdy A. Bayoumi. [11], The literature review examines the work of
Ramy E. Aly and Magdy A. Bayoumi on low-power cache design using a 7T SRAM cell,
as published in the IEEE Transactions on Circuits and Systems—II: Express Briefs. The
review provides an overview of the paper, discussing the key objectives and findings. It
explores the motivation behind low-power cache design and the significance of using a 7T
SRAM cell. The review delves into the proposed design methodology, highlighting the
novel features and techniques employed to achieve low power consumption. It discusses
the trade-offs between power reduction and performance in the context of cache design.
The review also touches upon the experimental results and analysis presented in the paper,
showcasing the effectiveness of the proposed approach. It concludes by summarizing the
key contributions of the research and its implications for low-power cache design.
Karimi, Gholamreza, and Adel Alimoradi. [12], The literature review focuses on the
work of Karimi and Alimoradi in their paper titled "Multi-purpose technique to decrease
leakage power in VLSI circuits," published in the Canadian Journal on Electrical and
Electronics Engineering. The review provides an overview of the paper, highlighting the
authors' objectives and the significance of reducing leakage power in VLSI circuits. It
explores the proposed multi-purpose technique, which aims to address the issue of leakage
power through various design considerations and optimizations. The review discusses the
key aspects of the technique, such as threshold voltage adjustment, gate sizing, and power
gating, explaining how they contribute to leakage power reduction. It also examines the
experimental results and analysis presented in the paper, assessing the effectiveness of the
proposed technique in terms of leakage power savings. The review concludes by
summarizing the main contributions of the research and its implications for decreasing
leakage power in VLSI circuits.

Keejong Kim, Hamid Mahmoodi. [13], The literature review focuses on the work of
Keejong Kim and Hamid Mahmoodi in their paper titled "A Low-Power SRAM Using Bit-
Line Charge-Recycling," published in the IEEE Journal of Solid-State Circuits. The review
provides an overview of the paper, highlighting the authors' objective of designing a low-
power SRAM by implementing a bit-line charge-recycling technique. It explains the
significance of reducing power consumption in SRAMs and the challenges associated with
conventional designs. The review delves into the proposed bit-line charge-recycling
scheme, which aims to recycle the charge from the bit-lines to minimize power dissipation
during read and write operations. It discusses the underlying principles and circuit
techniques employed in the design, including sense-amplifier-based charge transfer and
charge recycling circuits. The review also evaluates the experimental results presented in
the paper, assessing the power savings achieved by the proposed technique and its impact
on SRAM performance. It concludes by summarizing the key findings and contributions of
the research, highlighting the effectiveness of bit-line charge-recycling in reducing power
consumption in SRAMs.
Shigeki Ohbayashi, Makoto Yabuuchi, Koji Niiand, Susumu Imaoka. [14], The
literature review focuses on the work of Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii,
and Susumu Imaoka in their paper titled "A 65-nm SoC Embedded 6T-SRAM Designed
for Manufacturability With Read and Write Operation Stabilizing Circuits," published in
the IEEE Journal of Solid-State Circuits. The review provides an overview of the paper,
emphasizing the authors' objective of designing a 65-nanometer System-on-Chip (SoC)
embedded 6T-SRAM with enhanced manufacturability and stabilized read and write
operations. It discusses the importance of addressing manufacturing challenges and
ensuring stable memory operations in advanced process technologies. The review explores
the specific techniques employed in the design, such as replica cells, assist circuits, and
write assist circuits, which aim to improve stability and yield while maintaining low power
consumption. It examines the experimental results presented in the paper, assessing the
effectiveness of the proposed design techniques in enhancing manufacturability and
stabilizing memory operations. The review concludes by summarizing the key
contributions of the research, highlighting the advancements achieved in the design of 65-
nm embedded 6T-SRAMs for reliable and efficient SoC integration.
Varun Kumar Singhal, Balwinder Singh. [15], The literature review focuses on the
comparative study conducted by Varun Kumar Singhal and Balwinder Singh in their paper

titled "Comparative study of power reduction techniques for Static random access memory"
published in the International Journal of VLSI and Signal Processing Applications. The
review discusses the authors' objective of investigating various power reduction techniques
for Static Random Access Memory (SRAM). It highlights the importance of reducing
power consumption in SRAM due to its significant contribution to overall system power
consumption. The review examines different techniques such as supply voltage scaling,
transistor sizing, clock gating, and data compression, among others, that are commonly
used to achieve power reduction in SRAM. It explores the experimental methodology
employed by the authors to evaluate the effectiveness of each technique in terms of power
savings and performance impact. The review summarizes the results and conclusions
presented in the paper, highlighting the relative advantages and limitations of each
technique. It concludes by emphasizing the importance of selecting an appropriate power
reduction technique based on specific design requirements and trade-offs between power
savings and performance in SRAM-based systems.
Debasis Mukherjee, Hemanta Kr. Mondal and B.V.R. Reddy. [16], The literature
review focuses on the paper titled "Static Noise Margin Analysis of SRAM Cell for High-
Speed Application" by Debasis Mukherjee, Hemanta Kr. Mondal, and B.V.R. Reddy,
published in the IJCSI International Journal of Computer Science Issues. The review
discusses the authors' investigation into the static noise margin (SNM) analysis of SRAM
cells for high-speed applications. It highlights the significance of SNM as a critical metric
for evaluating the stability and reliability of SRAM cells. The review explores the
methodology employed by the authors, which involves analyzing the impact of various
parameters such as process variations, supply voltage, and temperature on SNM. It
discusses the experimental setup and simulations performed to assess the SNM values of
different SRAM cell configurations. The review summarizes the findings and conclusions
presented in the paper, emphasizing the importance of maintaining sufficient SNM for
reliable SRAM operation in high-speed applications. It highlights the implications of the
research for designing robust SRAM cells that can withstand process variations and
environmental factors while ensuring reliable data storage and retrieval.
Manual, Eldo User’S. [17], The literature review focuses on the manual titled "Eldo User's
Manual, Software Version 6.6_1, Release 2005.3" published by Mentor Graphics Corp.
The review discusses the significance of this manual as a valuable resource for users of the
Eldo software. Eldo is a circuit simulation tool widely used in the field of electronic design

automation. The review highlights the importance of having a comprehensive user manual
to understand the functionalities, features, and usage of the software effectively. It mentions
that the manual provides detailed instructions, guidelines, and examples for performing
circuit simulations using Eldo. The review also acknowledges the accessibility of the
manual through the provided URL, which allows users to access and refer to it for gaining
a better understanding of the software. It concludes by emphasizing the relevance and
usefulness of the Eldo User's Manual in facilitating the efficient utilization of the Eldo
software for circuit simulation purposes.
Neil H.E.Weste, David Harris and Ayan Banerjee. [18], The literature review focuses
on the book titled "CMOS VLSI Design - A Circuits and System Perspective" authored by
Neil H.E. Weste, David Harris, and Ayan Banerjee. Published by Pearson Education, this
book is considered a valuable resource in the field of integrated circuit design and VLSI
(Very Large-Scale Integration) technology. The review highlights the significance of this
book as a comprehensive guide for understanding the principles, methodologies, and
challenges involved in CMOS VLSI design. It mentions that the book covers a wide range
of topics, including CMOS technology, circuit design techniques, system-level
considerations, and manufacturing aspects. The review also acknowledges the expertise of
the authors, who are renowned experts in the field. It concludes by emphasizing the
relevance of "CMOS VLSI Design" as a reference for students, researchers, and
professionals in the field of VLSI design, providing them with a solid foundation and
practical insights into the design and implementation of CMOS integrated circuits.
Ashish Siwach, Rahul Rishi. [19], The literature review focuses on the research article
titled "Asymmetric SRAM - Power Dissipation and Delay" authored by Ashish Siwach and
Rahul Rishi. Published in the International Journal of Computational Engineering &
Management (IJCEM), this article explores the impact of asymmetric design on the power
dissipation and delay of Static Random Access Memory (SRAM) circuits. The review
highlights that the authors investigate the effects of varying transistor sizes in the SRAM
cell on its performance parameters. The article presents simulation results and analysis to
demonstrate the trade-off between power consumption and delay in asymmetric SRAM
designs. It emphasizes the importance of optimizing the transistor sizes in SRAM cells to
achieve a balance between power efficiency and performance. The review acknowledges
the contribution of the authors in shedding light on the potential benefits of asymmetric
SRAM designs and their implications for power dissipation and delay. Overall, the article

provides valuable insights for researchers and designers working on low-power SRAM
circuitry.
Shilpi Birla, Neeraj Kr. Shukla, Manisha Pattanaik, R.K.Singh. [20], The literature
review focuses on the research article titled "Device and Circuit Design Challenges for Low
Leakage SRAM for Ultra Low Power Applications" authored by Shilpi Birla, Neeraj Kr.
Shukla, Manisha Pattanaik, and R.K. Singh. Published in the Canadian Journal on Electrical
& Electronics Engineering, the article addresses the challenges associated with designing
low leakage Static Random Access Memory (SRAM) for ultra-low power applications. The
review highlights that the authors discuss various techniques and strategies to reduce
leakage current in SRAM cells, including the use of sleep transistors, body biasing, and
voltage scaling. They analyze the impact of these techniques on power consumption,
performance, and reliability of the SRAM circuitry. The article also discusses circuit design
considerations and optimization approaches to achieve low leakage SRAM designs without
compromising on other important parameters. The review acknowledges the authors'
contribution in providing insights into the challenges and solutions for designing low
leakage SRAM for ultra-low power applications. It emphasizes the importance of such
research in enabling energy-efficient and power-aware designs in modern electronic
systems.

CHAPTER 3
PROBLEM STATEMENT
The problem addressed in this project is the implementation and performance analysis of
SRAM (Static Random Access Memory) cells. SRAM cells are widely used in various
electronic systems, such as microprocessors, cache memories, and FPGA (Field-
Programmable Gate Array) devices, due to their high speed, low latency, and non-volatile
operation. However, the design and optimization of SRAM cells require careful
consideration of various factors to ensure efficient and reliable operation. The primary
focus of this project is to investigate different SRAM cell architectures, including 6T, 7T,
8T, and 9T cells, and analyze their performance characteristics. These architectures have
distinct trade-offs in terms of area, power consumption, read and write access times, and
propagation delays. By studying and comparing these parameters, we aim to understand
the strengths and weaknesses of each SRAM cell design.The project aims to accomplish
the following objectives:
SRAM Cell Design: Designing and implementing the different SRAM cell architectures
using a suitable design methodology and tools, such as Tanner EDA.
Performance Analysis: Conducting thorough performance analysis of the SRAM cells,

including measuring read and write access times, propagation delays, power consumption,
and other relevant metrics. This analysis will provide insights into the efficiency and
effectiveness of each SRAM cell design.
Comparison and Evaluation: Comparing the performance characteristics of different

SRAM cell architectures to identify their advantages and limitations. This evaluation will
help in selecting the most suitable SRAM cell design for specific applications based on the
trade-offs between area, power consumption, access times, and other key parameters.
Optimization and Enhancement: Exploring possible optimization techniques to improve

the performance of SRAM cells, such as transistor sizing, circuit layout optimization, and
architecture modifications. These enhancements aim to achieve better performance in terms
of speed, power efficiency, and area utilization.
Simulation and Validation: Conducting extensive simulations and validation to ensure

the accuracy and reliability of the performance analysis results. The simulated data will be
compared with theoretical models and existing literature to validate the findings.

The findings and insights from this project will contribute to the understanding of SRAM
cell architectures and their performance characteristics. The results can be utilized by
designers and engineers in the selection and optimization of SRAM cells for various
applications, including microprocessors, cache memories, and other memory-intensive
systems. Additionally, the project will provide valuable knowledge and practical
experience in the design and analysis of advanced memory technologies, paving the way
for further research and development in the field of semiconductor memory systems.
Furthermore, this project will also explore the impact of process variations and technology
scaling on the performance of SRAM cells. As semiconductor technology continues to
advance, the shrinking feature sizes and increased integration density pose challenges in
terms of device variability and reliability. By considering process variations and studying
the behavior of SRAM cells under different process corners, the project aims to provide
insights into the robustness and resilience of the designed SRAM cell architectures.
Moreover, the project will investigate the influence of different design parameters, such as
transistor sizing, supply voltage, and load capacitance, on the performance of SRAM cells.
By systematically varying these parameters and analyzing their effects on key performance
metrics, we can gain a deeper understanding of the design space and explore opportunities
for optimization.
To ensure the accuracy and reliability of the results, extensive testing and validation will
be conducted. The designed SRAM cells will undergo rigorous simulation using industry-
standard electronic design automation (EDA) tools, such as Tanner EDA or similar
software. The simulation results will be compared against analytical models and existing
literature to validate the correctness of the design and analysis.In conclusion, this project
on the implementation and performance analysis of SRAM cells addresses the need to
understand the trade-offs and performance characteristics of different SRAM cell
architectures. By studying their power consumption, access times, propagation delays, and
other relevant parameters, we aim to provide valuable insights for selecting and optimizing
SRAM cells for various applications. The project also contributes to the broader field of
semiconductor memory systems by exploring the impact of process variations,
investigating design parameters, and ensuring the reliability of the results through rigorous
testing and validation.

CHAPTER 4
THEORATICAL BACKGROUND
4.1 Introduction
The vast majority of transistors in a CMOS system-on-chip are frequently found in memory
arrays. As seen in Figure 4.1, arrays can be categorised.
Figure 4.1: Categories of memory arrays

An address is used to access random access memory, although the delay is independent of
the address. In contrast, serial access memory are accessed in a sequential manner without
the need for an address. Content addressable memory can identify the address(es) where
data matching a given key is located.
Read-only memory (ROM) and read/write memory are two typical categories for random
access memory (confusingly called RAM). Since various ROMs can be written, even the
word "ROM" is deceptive. The distinction between volatile and non volatile memory is
more helpful. Non volatile memory can store data indefinitely while volatile memory can
only store data while power is applied. RAM and ROM are terms for volatile and non
volatile memory, respectively. The memory cells utilised in volatile memories can also be
separated into static structures and dynamic structures, much like sequencing components.
Dynamic cells utilise charge held on a floating capacitor through an access transistor,

whereas static cells use some sort of feedback to maintain their state. While speedier and
less problematic than dynamic RAMs, static RAMs (SRAMs) need more space per bit
(DRAMs). There are 2n words with 2m bits each in a memory array. Every byte is kept in
its own memory cell. The architecture of a memory array is shown in Figure 4.2.By
asserting the word line, the row decoder uses the address to activate one of the rows. The
cells on this word line drive the bit lines, which may have been conditioned, during a read
operation. before making a memory access, to a predetermined value.
To sense the data, the column circuitry may have amplifiers or buffers. A typical memory
array may contain thousands or millions of words with only 8–64 bits per, resulting in a
tall, skinny arrangement that would be difficult to accommodate on the chip's floor plan
and would be slow due to the length of the vertical wires.The array is frequently folded into
fewer rows and more columns as a result. Each row of the memory has 2k words after
folding, hence the array is literally made up of 2 n k rows of 2 m + k columns or bits. A
two-way fold with eight rows and eight columns is depicted A multiplexer in the column
is controlled by the column decoder. circuitry to choose the 2m bits needed to access the
data from the row. In order to keep word lines and bit lines relatively short, fast, and low
in power dissipation, larger memories are typically constructed from a number of smaller
sub arrays.
Figure 4.2: Memory array architecture

4.2 SRAM
The memory cell used in static RAMs has internal feedback and maintains its value as long
as power is applied. It has the following alluring characteristics: more density than flip-
flops
• Compatibility with conventional CMOS procedures

• More rapid than DRAM
• More user-friendly than DRAM
SRAMs are utilised often in a variety of applications, including caches, register files, tables,
and scratchpad buffers. The row and column circuits, as well as a grid of memory cells,
make up the SRAM. The design and functionality of each of these components are
examined in this section's opening paragraph. Then, it discusses significant SRAM special
situations, such as multi ported register files, huge SRAMs, and subthreshold SRAMs.
4.2.1 SRAM Cell
Data must be able to be read, written, and stored in an SRAM cell throughout the duration
of power application. This criterion may be satisfied by a regular flip-flop, but they are
fairly huge.A typical 6-transistor (6T) SRAM cell, which may be an order of magnitude
smaller than a flip-flop, is depicted in Figure 4.3. The 6T cell's compactness is achieved at
the expense of more intricate peripheral circuitry that must be used to read and write the
cells [5].
Figure 4.3: 6T SRAM cell
In big RAM arrays, where memory cells predominate, this is a good trade-off. Shorter wires
are another benefit of the reduced cell size, which results in less dynamic power usage.

The 6T SRAM cell has two access transistors for reading or writing the state as well as two
weak cross-coupled inverters to hold the state. The constructive feedback eliminates noise
or leakage-related issues. The desired value and its complement are placed onto the 23 bit
lines, bit and bit b, before elevating the word line, word. The cross coupled inverters are
overwhelmed by the new data. The two bit lines are precharged high before being allowed
to float to read it. Bit or Bit b pulls down to reveal the data value when word is elevated.
The main difficulties in designing an SRAM are reducing its size and making sure the
circuitry holding the state is strong enough to not be disrupted during a read but weak
enough to be overpowered during a write.
4.2.2 Read Operation
Figure 4.4(a) depicts the reading of an SRAM cell. At first, both bit lines are floating high.
Assume Q is originally 0 and Q b is initially 1, without losing generality. Both Q b and bit
b should continue to be 1. The bit should be brought down through the driver and accessed
by transistors D1 and A1 when the word line is raised. Node Q often rises as bit is being
dragged down. D1 maintains Q at a low level, but the current entering from A1 raises Q.
As a result, the access transistor A1 must be weaker than the driver D1. The transistors
must be ratioed specifically so that node Q stays below the P2/D2 inverter's switching
threshold. Read stability is the name of this restriction. For the read operation, waveforms
are displayed in Figure 4.4(b) as a bit reads a 0 value. Keep in mind that while Q briefly
rises, the cell does not flip as a result of the glitch.
(a)

(b)
Figure 4.4: Read operation for 6T SRAM cell
4.2.3 Write Operation
The writing of an SRAM cell is depicted in Figure 4.5. Assume once more that Q starts out
as 0, and that we want to enter a 1 in the cell. Bit is left floating after being precharged
highly. A write driver pulls low bit b. We know that bit won't be able to force Q high
through A1 because to the read stability constraint. Thus, writing the cell requires driving
Q b low through A2. Since P2 opposes this operation, P2 must be weaker than A2 in order
for Q b to be lowered sufficiently. This restriction is known as writability. D1 shuts off and
P1 turns on, pulling Q high as desired once Q b drops low.
Figure 4.5: Write operation for 6T SRAM cell

4.2.4 Cell Stability
The transistors need to adhere to ratio restrictions in order to guarantee read stability and
writability. In the cross-coupled inverters, the nMOS pulldown transistor needs to be the
strongest. The pMOS pull up transistors must be weak, while the access transistors are of
intermediate strength. All of the transistors need to be reasonably tiny in order to achieve
good layout density. The pull downs, for instance, might be 8/2, the access transistors, 4/2,
and the pull ups, 3/3. Regardless of process variation, the SRAM cells must function
properly at all voltages and temperatures. The hold margin, read margin, and write
margin—which are based on the static noise margin of the cell in its various modes of
operation—quantify the stability and writability of the cell. A cell ought to only one stable
state during write operations, but two stable states during hold and read operations.
4.3 Performance Parameters of SRAM
Read delay: The read delay is the time it takes for the bit lines to discharge by around 10%
of their peak value or the time it takes from when the WL signal is applied to when the
sensing amplifier responds.
Write delays: The difference is the amount of time that passes between when the word line
WL signal is applied and when the data is actually written.
Leakage power: Static power is another name for the power used by a device when its
condition does not change. Although leakage power is used by a device both when it is
static and when it is switching, the main problem with leakage power is when the device is
inactive because all the power used in this condition is regarded as "wasted" power.
Static noise Margin: The static noise margin (SNM) quantifies the amount of noise that
may be introduced to the inputs of the two cross-coupled inverters without causing a loss
of stability (during hold or read) or the creation of a second stable state (during write) [3].

CHAPTER 5
POWER CONSIDERATION IN SRAM CELL
Power consumption has two aspects:
Dynamic power: The amount of power used by a device when it is actively moving
between states. Internal power, also known as short circuit power, is consumed internally
to the device while it is changing state. Switching power is used to charge and discharge
the loads on a device.
Figure 5.1: Total power
Leakage power: Static power is another name for the power used by a device when its
condition does not change. Although leakage power is used by a device both when it is
static and when it is switching, the main problem with leakage power is when the device is
inactive because all the power used in this condition is regarded as "wasted" power. There
are several methods that have been developed to lower dynamic and leakage power.
5.1 Low Power Techniques in SRAM Memory
5.1.1 Clock gating

when the data entering the device it drives is not changing, the clock is disconnected.
Dynamic power is reduced with this method [6].

Figure 5.2: Clock gating
5.1.2 Multi-Vth optimization

The substitution of slower High-Vth cells for faster Low-Vth cells, which have higher
leakage power consumption. This swapping only happens on timing pathways with positive
slack, which can be used to accommodate the slower High Vth cells
Figure 5.3: Multi Vth optimization

Since technologies have become more compact, leakage power consumption has increased
rapidly, necessitating the deployment of more severe power reduction techniques. Similar
to this, increasing clock frequencies have led to devices’ dynamic power consumption
exceeding the capacity of the power networks that supply it. This problem is made even
worse when high power consumption occurs in extremely small geometries because it
affects both power density and power consumption.
5.1.3 Multi supply voltage
Multiple voltage rails (multi-Vdd) can be supplied to a design to impact power and
performance. A higher voltage yields a faster the circuit, but with higher the dynamic
power. In many designs, only discrete portions of the design need to run at high speed.
Other portions may only operate at lower speeds, and thus require lower voltages (and
therefore consume less power [12]).
5.2 Dominant Leakage Mechanism in Cmos Transistor:

There are four main source of leakage current in a CMOS transistor as shown in figure:
1. Reverse biased junction leakage (Irev)
2. Gate induced drain leakage (IGIDL)
3. Gate direct tunneling leakage (IG)
4. Subthreshold leakage (Isub)
Figure 5.4: Main source of leakage current

5.2.1 Junction leakage

When a transistor is turned off, junction leakage occurs from the source or drain to the
substrate through the reverse biassed diodes. Two main factors contribute to a reverse-
biased P-N junction leakage: one is minority carrier diffusion/drift near the depletion
region's edge, and the other is electron-hole pair generation in the junction's depletion
region. The NMOS 31 is off, the PMOS is on, and the output voltage is high, for instance,
in the case of an inverter with a low input voltage. The supply voltage is then equal to the
drain to substrate voltage of the OFF NMOS transistor. This result in a leakage current from
the drain to the substrate through the reverse-biased diode. The magnitude of the diode
leakage current flows through the reverse-biased diode from the drain to the substrate. The
area of the drain diffusion and the leakage current density, both of which are influenced by
the doping concentration, determine the size of the diode leakage current.Band to band
tunnelling (BTBT), which predominates in heavily doped n and p regions, causes p-n
junction leakage. Temperature has a significant impact on junction leakage. However,
compared to the other three leakage components, junction reverse leakage components
from source drain diodes and well diodes are typically insignificant.
5.2.2 Gate Induced Drain Leakage

In the drain junction of MOS transistors, high field effect is what causes the gate-induced
drain leakage, or GIDL. A significant band bending in the drain of an NMOS transistor
with grounded gate and drain potentials at VDD allows electron-hole pair generation via
avalanche multiplication and band to band tunneling. Given how quickly the holes are
swept out to the substrate, a deep depletion condition is produced. GIDL current results
from the drain simultaneously collecting electrons. This leakage mechanism is made work
by high drain to body voltage and high drain to gate voltage. Transistor scaling has
produced the steeper halo implantation, where the channel doping is low and the substrate
doping at the junction interface is raised. While having little effect on carrier mobility in
the channel, this is primarily done to manage punch-through and drain-induced barrier
lowering. Band to band tunnelling current is increased at the drain edge due to the resulting
steep doping profile, especially a VDB. Higher supply voltage and thinner oxide both
increase GIDL current.

5.2.3 Gate Direct Tunning Leakage

For optimum MOS transistor behaviour with channel length scaling, maintaining
acceptable transistor aspect ratio by the equivalent scaling of the gate oxide thickness,
junction depth, and depletion depth are crucial. Unfortunately, keeping a decent transistor
aspect ratio has been difficult due of technological growth. In other words, as the silicon
oxide gate thickness approaches scaling limits, the rate of growth in gate direct tunnelling
leakage current has been faster than the rate of reduction of the horizontal dimensions. Both
the gate charge and the inversion layer charge will be located at a finite distance from the
oxide channel interface due to quantum mechanical and polysilicon gate depletion effects,
with the charge location being a strong function of gate bias. When quantum mechanical
effects are taken into account, the inversion layer in the silicon substrate for a transistor
with a typical bias is located 1 nm from the oxide channel interface. This results in a 0.3
nm increase in the effective oxide thickness. Taking charge spread on the both sides of the
interface along with poly depletion charge the 1nm oxide tunneling limit into an effective
oxide thickness of 1.7 nm. Researchers have been looking into a number of solutions to
shrink this restriction, including the use of metal gates, high permittivity gate dielectrics,
novel transistor structures, and circuit-based methods.
With the potential to significantly reduce gate leakage, using a high permittivity gate
dielectric will produce a thicker, simpler-to-fabricate dielectric for iso-gate oxide
capacitance. The search is on for a suitable high permittivity dielectric material with a good
silicon interface state and little gate leakage. High permittivity gate dielectric use, however,
has been demonstrated to be of minimal use. Additionally, new transistor architecture like
a double gate that is self-aligned. Better aspect ratio FinFET and tri-gate MOS transistors
are being investigated.
5.2.4 Subthreshold Leakage

Current flowing from drain to source while a transistor is operating in a weak inversion
zone is known as subthreshold leakage. The minority carriers' diffusion current in the
channel of a MOS device is what causes the subthreshold conduction, in contrast to the
strong inversion area where the drift-current predominates. For instance, when an inverter
has a low input voltage, the output voltage is high and the NMOS is disabled. In this
instance, even though VGS is 0V, the VDD potential of the VDS causes a current to flow
in the channel of the OFF NMOS transistor. Temperature, supply voltage, device size, and
the process parameter out of which the threshold is determined determine the sub threshold

current's magnitude. The predominant factor is voltage. The sub threshold leakage current,
or ISUB, is significantly bigger than the other leakage current components for the current
CMOS technology. This leakage current is substantially bigger than the other one.
5.3 Power Reduction in SRAM Cell:

All sources of the overall power must be targeted in order to lower the power consumption
in SRAMs.
The most effective methods in recent memory are:
1. Capacitance reduction of word lines, data lines, 1/0 lines, and decoders, as well as the
number of cells connected to them.
2. Reduction of DC current employing novel pulse operating methods for word-lines,
peripheral circuits, and sense amplifiers.
3. Using innovative decoding methods, such as multi-stage static CMOS decoding, to
reduce AC current
4. Reduction in operating voltage.
5. Using multiple threshold voltage (MT-CMOS) or variable threshold voltage technology
to reduce leakage current (in active and standby mode) (VT-CMOS).
5.4 Schematic and Working of Basic 6T SRAM Cell
Figure 5.5: Schematic of basic 6T SRAM cell
Figure 5.5 shows the schematic of basic cell structure it consists of six transistors where
NMOS_5 and NMOS_6 is called the access transistor and NMOS_1 and NMOS_2 is called

the driver transistor and PMOS_1 and PMOS_2 called the load transistor. Vdd supply is
1.2-volt . Schematic of basic 6T CMOS SRAM Cell 35 Word line is applied to the gates of
both the access transistors. Substrate of P channel transistor is connected to the Vdd supply
and substrate of N channel is connected to the ground terminal. To understand the working
of basic cell we have to assume the previous state of cell. Basically by this circuit we can
do only read operation. By taking the input voltage we can store the value SRAM cell. First
we applied the input voltage to the inverter one. Then we got the output of inverter one that
is input of the second inverter. After the pass transistor gets turn on by the word selection
.The value is passing through the access transistor to the bit line and bit line bar. From the
bit line and bit line bar, finally we got output. In this way the read operation gets performed.
Main objective of proposing this new 7T SRAM cell is to have good Read Stability and
static Noise Margins (SNMs). Proposed 7T SRAM cell is shown in. This new SRAM cell
is made up of seven transistors, uses single bit-line (BL), a word line (WL), and a read line
(RL). Schematic of proposed 7T SRAM Cell Since 7TSRAM cell uses only one bit line,
power required for charging and discharging of one more bit line will be reduced. Hence
usage of only one bit line reduces power required to charge and discharge the bit lines

approximately to half, because only one bit line is charged during read operation instead of
two. The bit line is charged during the write operation about half of the time instead of
every time when a write operation is required, here we are assuming equal probability of
writing 0 and 1. The proposed 7T SRAM cell uses two transistors N4 and N5 with read-
line (RL) for read operation.
5.5.1 Read and Write Operation of Proposed 7T SRAM Cell
While writing, the data need to be written will be loaded on bit-line (BL) and then word-
line (WL) will be activated. Strong access transistor N3 allows bit line to overpower the
cell, so that required data will be written into the cell. To write ‘1’ into the cell, the bit-line
(BL) is charged to VDD. If the data need to be written is ‘0’, bit-line should be at logic low,
and then word-line (WL) should be pulled to VDD. In write mode read-line (RL) will be
inactive (i.e. at logic ‘0’). To read data from the cell, initially bit line (BL) is being pre-
charged to VDD. After precharging the bit line read line (RL) is activated. Depending upon
whether the bit line (BL) discharges or holds the held charge, data stored in the 7T SRAM
cell can be decided. If BL discharges after pulling the read line to VDD, it indicates 7T
SRAM cell is storing ‘0’ in it. If bit line holds the held charge then the data stored is ‘1’. In
read mode (WL) is inactive (i.e. at logic ‘0’).

To address the read destructive problem, the read and write operations are separated by
adding transistor stack to the conventional 6T SRAM cell, thus it has the area penalty but
operates efficiently than the 6T SRAM cell at lower VDD. The schematic of the 8T SRAM
cell with transistors sized for a 65-nm CMOS technology is shown above,
5.6.1 Read and Write Operation of Proposed 8T SRAM Cell
The disturbance of bit lines during read operation is the primary source of instability
problem in SRAM operation. The stability in 8T SRAM cell can be enhanced by isolating
the read port from the write bit lines. The 8T SRAM cell composed of conventional 6T
SRAM cell for writing operation and a transistor stack, which can be used for read
operation. The read and write operations are controlled by separate signals Write Word
Line (WWL) and Read Word Line (RWL). During the read operation Read Bit Line (RBL)
is pre charged to VDD and WWL is maintained at GND. Depends on the value stored in
cross coupled inverters RBL, discharges (or) maintained at VDD. If RBL discharges, it can
be treated as the stored bit is „1, otherwise it is 0. The storage nodes are completely isolated
from the write bit lines, which can increases 39 stability of the SRAM cell [3]. During the
write operation WBL and WBLB lines are precharged to predetermined values. Then,
asserting the write word line WWL and nodes attain the corresponding values from the bit
lines. It uses the two additional Word Lines to perform read and write operations, when
compared with 6T SRAM cell, which could increase the metal density, wire delay and
dynamic power consumption and leakage power.

CHAPTER 6
RESULTS AND DISCUSSION
This chapter gives a description of the results which were obtained in the proposed
designs.
6.1 Schematic of Different Types of SRAM Cell
6.1.1 Operation of 6T SRAM
A single bit of data is stored using six transistors in a static random-access memory
(SRAM) cell known as a 6T SRAM cell. Two access transistors and two cross-coupled
inverters make up the cell, which enables data to be read from or written to.Read operation:
The access transistors are able to link the cell to the bit lines (BL and BLbar) when the
word line (WL) is engaged during the read operation. A voltage that is midway between the
high and low logic levels is applied to the bit lines as a precharge. The voltage on BL will
be greater than on BLbar if the data stored in the cell is a logic 1, and vice versa if the data
is a logic 0. A sense amplifier amplifies the differential voltage, which is subsequently
recorded in an output latch. Write operation: The word line is turned on to connect the cell
to the bit lines as the bit lines are driven to the desired logic levels during the write
operation.
Figure 6.1: Schematic of 6T SRAM

The output waveform of the 6T SRAM cell, as illustrated in Figure.6.2 , directs the
transient analysis. The analysis’s findings reveal Delay and Power consumption 444.485p
and 2.134W respectively.

Figure 6.2: Transient response of 6T SRAM

The 7T SRAM cell, a replacement for the conventional 6T SRAM cell, was created to cut
down on leakage power and boost stability. The 7T SRAM cell operates similarly to the
6T SRAM cell except that there is an extra pass gate transistor in between the access
transistors. In addition to having more stability and less leakage power than the 6T SRAM
cell, the 7T SRAM cell also has a higher noise margin, making it more resistant to
interference from outside noise. However, the 7T SRAM cell’s increased space need due
to its increased transistor count makes it unsuitable for applications where size is a key
consideration. write operation: The bitlines (BL and BLB) have a high voltage (VDD)
precharge.In order to activate the pass gate transistor and connect the storage node to the
bitline, the wordline (WL) of the chosen cell is driven high. A voltage differential between
the bitlines is created when the data to be written (either a ”1” or ”0”) is driven into the
bitline opposite the stored value. Through the use of access transistors, the voltage on the
storage node is adjusted to the value of the written data.
Read operation: The bitlines (BL and BLB) have a high voltage (VDD) precharge. In order
to activate the pass gate transistor and connect the storage node to the bitline, the wordline
(WL) of the chosen cell is driven high.When the voltage on the bitline is measured, the
value is recorded as ”1” if the voltage on BL is higher than on BLB. The value is ”0”
if the voltage on BLB is higher than that on BL.To preserve the stability of the SRAM
cell, the access transistors restore the voltage on the storage node. The 7T SRAM cell is
still considered a promising alternative to the 6T SRAM cell, particularly for applications

that require high stability and low power consumption.
The output waveform of the 7T SRAM cell, as illustrated in Figure 6.4, directs the

The 8T SRAM cell was created to retain low power consumption while enhancing the
read stability of the 6T SRAM cell. To enhance the read function, it has two extra
transistors called as read aid transistors.write operation: The bitlines (BL and BLB) are
precharged to VDD for write operation. The chosen cell’s wordline (WL), which joins the
storage node to the bitline, is driven high to write a ”1” to it. The data is then written to

the storage node by driving low the bitline corresponding to the complementary value of
the data being written (BL for a ”1” and BLB for a ”0”). The voltage level on the storage
node is managed and stabilised by the access transistors.
Read operation: Precharged to VDD are the bitlines (BL and BLB). The wordline (WL),
which links the storage node to the bitlines, is driven high in order to read the value of
the chosen cell. The voltage difference between the bitlines is subsequently amplified by
the read aid transistors, increasing the read stability. Depending on the data stored in the
cell, the voltage on the bitline with the greater voltage is then detected and recorded as a
”1” or ”0.” After the read operation, the voltage level on the storage node is restored using
the access transistors to keep it stable.
Figure 6.5: Schematic of 8 T SRAM
The output waveform of the 8T SRAM cell, as illustrated in Figure.6.6, directs the


The 9T SRAM cell was created as an upgrade over the common 6T SRAM cell to offer
higher read and write capabilities, lower leakage power, and increased stability.
Write Operation: The 9T SRAM cell’s write operation is carried out in the same manner
as it is for the 6T and 7T SRAM cells. The wordline (WL) of the chosen cell is driven high,
and the bitlines (BL and BLB) are precharged to a high voltage (VDD). A voltage
differential is produced on the bitlines in order to write a ”1,” or the opposite value of
the data that has been saved. The data is written into the cell by the access transistors,
which modify the voltage on the storage node in accordance with the data to be written.
Read Operation: Compared to the 6T and 7T SRAM cells, the read operation in the 9T
SRAM cell is more difficult. The wordline (WL) of the chosen cell is driven high,
and the bitlines (BL and BLB) are precharged to a high voltage (VDD). The sense amplifier
circuit is then used to read the data from the cell.
The reference voltage (VREF), which is equal to half of the supply voltage (VDD/2), is
used by the sensing amplifier circuit to compare the voltage difference between the bitlines
(BL and BLB) to. The cell records a ”1” if the voltage difference is greater than the
reference voltage. Otherwise, a ”0” is stored in the cell.The reference voltage (VREF)
in the 9T SRAM cell can be set to a lower value than in the 6T and 7T SRAM cells
since it has an extra transistor. As a result, the cell’s read stability is increased, making it
more resistant to noise and other disturbances. The read performance of the cell is enhanced
further by the introduction of an extra transistor and a sense amplifier circuit, making it
faster and more dependable.


The output waveform of the 8T SRAM cell, as illustrated in Fig.6.8, directs the transient
analysis. The analysis’s findings reveal Delay and Power consumption 685.60p and
2.189W respectively.
Figure 6.8:Transient response of 9T SRAM

6.2 Layout of Different Types of SRAM Cell

According to Figure 6.9, Figure 6.10, Figure 6.11,and Figure 6.12 the layout of 6T, 7T, 8T,
and 9T SRAM is created using L-edit in Tanner EDA programme. To ensure there is no
design flaw in the layout, the DRC is checked in Fig.14. For the layout design to match,
the aspect ratio used is the same as that taken into account in the schematic. The purpose
of layout in Tanner EDA (Electronic Design Automation) is to provide a graphical
representation of the physical layout of a circuit design. It is a critical step in the design
process as it allows the designer to optimize the placement of components, wires, and metal
layers in a way that meets the design requirements while minimizing parasitic effects and
ensuring manufacturability.
Figure 6.9: Layout of 6T SRAM cell

The 6T SRAM layout in Tanner EDA is a physical representation of the SRAM cell
design using metal and poly layers. It consists of six transistors, two cross-coupled
inverters, and two access transistors. The layout ensures proper connections between these
components to ensure proper SRAM cell operation. The metal layers are used for wiring,
while the poly layer is used for creating transistor gates. Tanner EDA offers various tools
and features to assist in the design and optimization of the 6T SRAM layout, such as DRC
and LVS checks.

The layout of a 7T SRAM cell in Tanner EDA involves creating a schematic representation
of the cell and then designing its physical layout on a chip. The additional pass gate
transistor in the 7T SRAM cell adds complexity to its layout, as the transistor needs to be
carefully placed and connected to the other components of the cell to ensure proper
functioning. Once the layout is complete, it can be verified through simulation and physical
testing to ensure proper functionality.

In Tanner EDA, the layout of an 8T SRAM cell involves designing eight transistors and
a capacitor in a specific arrangement to achieve the desired functionality. The cell has
two pairs of cross-coupled inverters to store the data, and two access transistors to read
and write the data. The layout requires careful consideration of transistor sizing, placement,
and routing to minimize parasitic effects and improve performance. Proper shielding and
isolation techniques are also crucial to avoid interference and maintain cell stability. The
resulting layout can be simulated and optimized for performance and power consumption.
In Tanner EDA, the layout of a 9T SRAM cell involves the arrangement of nine
transistors and their interconnects on a silicon substrate. The 9T SRAM cell consists of
an additional n-type MOSFET connected to the bitline through a p-type MOSFET. This
extra transistor provides better read and write stability, as well as reducing leakage current.
The layout of a 9T SRAM cell involves the design of the transistor dimensions, the
placement of transistors, the routing of the metal interconnects, and the placement of
contact and via points. Tanner EDA provides a comprehensive set of tools for designing,
simulating, and verifying the layout of a 9T SRAM cell.
6.3 Final Results

The performance analysis of different SRAM cell topologies reveals valuable insights. The
7T SRAM cell demonstrates the lowest delay, indicating faster read and write operations.
The 8T SRAM cell has a relatively lower power consumption, making it more energy-
efficient. The trade-off between delay and power consumption is evident, and designers

can make informed decisions based on their application requirements. Parameters Power
consumption and Delay of 6T, 7T, 8T and 9T SRAM cells are mentioned in the Table 6.1
SRAM cells Power consumption Delay

6T SRAM 2.134W 444.485p
7T SRAM 1.735W 438.235p
8T SRAM 1.369W 680.188p
9T SRAM 2.189W 685.603p
Table 6.1: Parameters of SRAM cells

CHAPTER 7
CONCLUSION AND FUTURE WORK
In conclusion, the implementation and performance analysis of SRAM cells is a crucial
aspect of semiconductor memory design. Through this project, we have explored various
SRAM cell architectures, including 6T, 7T, 8T, and 9T designs, and evaluated their power
consumption, access times, and propagation delays. The results obtained provide valuable
insights into the trade-offs and performance characteristics of different SRAM cell
configurations. Based on the findings, it can be concluded that the choice of SRAM cell
architecture depends on the specific requirements of the target application. For example,
the 6T SRAM cell demonstrates lower power consumption but may have longer access
times compared to the 7T, 8T, or 9T designs. On the other hand, the 8T and 9T SRAM cells
exhibit improved stability and reduced susceptibility to read and write failures.Future work
in this field can focus on several aspects.
Firstly, further optimization and exploration of SRAM cell designs can be pursued to
achieve a balance between power consumption, access times, and stability. This can involve
fine-tuning design parameters, exploring alternative architectures, or incorporating
advanced circuit techniques.Additionally, the impact of process variations and technology
scaling on SRAM cell performance can be studied in more detail. Understanding how
variations in manufacturing processes affect the behavior of SRAM cells will enable the
development of more robust and reliable memory systems.Furthermore, the scalability and
applicability of the analyzed SRAM cell designs to emerging technologies, such as
nanoscale and beyond, can be investigated. Exploring their performance in advanced
process nodes will help identify challenges and opportunities for memory design in future
technology generations.Lastly, the integration of SRAM cells into larger memory arrays
and the impact of interconnect delays and parasitics can be explored. Analyzing the
behavior of SRAM cells in the context of complex memory architectures will provide
insights into overall system performance and enable the optimization of memory
subsystems.Overall, the implementation and performance analysis of SRAM cells is an
ongoing and dynamic field with significant implications for the design of efficient and
reliable memory systems. Continued research and development in this area will contribute
to advancements in semiconductor memory technology and enable the realization of high-
performance, low-power memory solutions for a wide range of applications.

REFERENCES
[1] Hong Zhu and Volkan Kursun, “A Comprehensive Comparison of Data Stability
Enhancement Techniques With Novel Nanoscale SRAM Cells Under Parameter
Fluctuations” IEEE Transactions On Circuits And Systems—I: Regular Papers, Vol. 61,
No. 5, May 2014.
[2] Wasim Hussain and Shah M.Jahinuzzaman, “A read-decoupled gated-ground SRAM

architecture for low-power embedded memories” INTEGRATION, the VLSI journal 45
(2012) 229–236.
[3] Evert Seevinck, Frans J. List And Jan Lohstroh, “Static-Noise Margin Analysis of MOS
SRAM Cells” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO. 5, Oct.
1987.
[4] Ankit Mitra, “Design and Analysis of an 8T Read Decoupled Dual Port SRAM Cell for
Low Power High Speed Applications”, World Academy of Science, Engineering and
Technology International Journal of Electrical, Computer, Electronics and
Communication Engineering Vol:8 No:4, 2014.
[5] Paridhi Athe and S. Dasgupta, “A Comparative Study of 6T, 8T and 9T Decanano
SRAM cell”, IEEE Symposium on Industrial Electronics and Applications (ISIEA 2009),
Kuala- Lumpur, Malaysia.
[6] Baker Mohammad, “Low Leakage Power SRAM Cell for Embedded
Memory”International Conference on Innovations in Information Technology, 2011.
[7] Cheng, Shin-Pao, and Shi-Yu Huang. "A low-power SRAM design using quiet-bitline
architecture." 2005 IEEE International Workshop on Memory Technology, Design, and
Testing (MTDT'05). IEEE, 2005..
[8] Mann, Randy W., et al. "Impact of circuit assist methods on margin and performance
in 6T SRAM." Solid-State Electronics 54.11 (2010): 1398-1407.
[9] Ming, Gu, Yang Jun, and Xue Jun. "Low power SRAM design using charge sharing
technique." 2005 6th International Conference on ASIC. Vol. 1. IEEE, 2005.

[10] Itoh, Kiyoo, Katsuro Sasaki, and Yoshinobu Nakagome. "Trends in low-power RAM
circuit technologies." Proceedings of the IEEE 83.4 (1995): 524-543.
[11] Ramy E. Aly and Magdy A. Bayoumi, “Low-Power Cache Design Using 7T SRAM
Cell” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS,
VOL. 54, NO. 4, APRIL 2007.
[12] Karimi, Gholamreza, and Adel Alimoradi. "Multi-purpose technique to decrease

leakage power in VLSI circuits." Canadian Journal on Electrical and Electronics
Engineering 2.3 (2011): 71-74..
[13] Keejong Kim, Hamid Mahmoodi, “A Low-Power SRAM Using Bit-Line Charge-
Recycling”, IEEE Journal of Solid-state Circuits, Vol. 43, No. 2, Feb 2008.
[14] Shigeki Ohbayashi, Makoto Yabuuchi, Koji Niiand, Susumu Imaoka “A 65-nm SoC
Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation
Stabilizing Circuits” IEEE journal of solid-state circuits, Vol. 42,April 2007, pp820-829.
[15] Varun Kumar Singhal, Balwinder Singh, “Comparative study of power reduction
techniques for Static random access memory” International Journal of VLSI and Signal
Processing Applications, Vol. 1, Issue 2, pp. 80- 88, May 2011.
[16] Debasis Mukherjee, Hemanta Kr. Mondal and B.V.R. Reddy, “Static Noise Margin
Analysis of SRAM Cell for High Speed Application” IJCSI International Journal of
Computer Science Issues, Vol. 7, Issue 5, pp. 175 -180, September 2010.
[17] “Manual, Eldo User’S. "Software Version 6.6 _1, Release 2005.3." Mentor Graphics
Corp. Mode of access. URL: http://web. engr. uky. edu/~ elias/tutorials/Eldo/eldo_ur. pdf
(Date of access: 20.12. 2018) (2005).
[18] Neil H.E.Weste, David Harris and Ayan Banerjee “CMOS VLSI DESIGN – A Circuits
and System Perspective”, Pearson Eduction, Third edition, ninth impression, 2009.
[19] Ashish Siwach, Rahul Rishi,” Asymmetric SRAM- Power Dissipation and Delay"
IJCEM International Journal of Computational Engineering & Management, Vol. 11, pp.
28 - 31, January 2011.

[20] Shilpi Birla, Neeraj Kr. Shukla, Manisha Pattanaik, R.K.Singh, Device and Circuit
Design Challenges for Low Leakage SRAM for Ultra Low Power Applications” Canadian
Journal on Electrical & Electronics Engineering Vol. 1, No. 7, December 2010.

Implementation and Performance Analysis of Cmos Sram Cell

Uploaded by

Copyright:

Available Formats

Implementation and Performance Analysis of Cmos Sram Cell

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Implementation and Performance Analysis of Cmos Sram Cell

Uploaded by

Copyright:

Available Formats

VISVESVARAYA TECHNOLOGICAL UNIVERSITY

Jnana Sangama, Belagavi - 590018

Major Project Report

Mr. ASHWIN M R 4JK19EC015

Under the Guidance of

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

We hereby declare that the project report entitled “IMPLEMENTATION AND

Name with USN Signature with date

1. Mr. ASHWIN M R (4JK19EC015)

Signature of the HOD Signature of the Principal and Guide

We are indebted to Management of A J Institute of Engineering and

Also, we thank all the teaching and non-teaching staff of Department of

Name Signature with date

Table 6.1 Parameters of SRAM Cells 53

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 1

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 2

millions of transistors on a single chip thanks to technical developments. While doing so

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 3

semiconductor market since it is a crucial component of a computing system. Memory held

While processing, data is stored in memory either momentarily or permanently. Access

SRAM performance and density have significantly increased thanks to technological

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 4

By preserving an SRAM cell's stability within acceptable limits, it is possible to preserve

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 5

as a result of limited lung expansion. For clinical assessment, spirometer measurements

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 6

• Read and write lag - Power consumption from leakage

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 7

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 8

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 9

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 10

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 11

Figure 1.1 Transistor in Intel microprocessors

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 12

Overall, this methodology enabled a systematic approach to implement and analyze

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 13

a balance between the two.

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 14

Advantages and Disadvantages

• Higher Power Consumption: SRAM cells generally consume more power

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 15

1.6 Organization of thesis

Chapter 4: This chapter gives the Theoretical background of this project.

Chapter 5: This chapter gives the Power consideration in SRAM cell.

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 16

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 17

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 18

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 19

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 20

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 21

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 22

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 23

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 24

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 25

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 26

Performance Analysis: Conducting thorough performance analysis of the SRAM cells,

Comparison and Evaluation: Comparing the performance characteristics of different

Optimization and Enhancement: Exploring possible optimization techniques to improve

Simulation and Validation: Conducting extensive simulations and validation to ensure

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING 27