Features

Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) Low Voltage and Standard Voltage Operation
5.0 (VCC = 4.5V to 5.5V) 2.7 (VCC = 2.7V to 5.5V) 1.8 (VCC = 1.8V to 3.6V) 2.1 MHz Clock Rate 32-Byte Page Mode Block Write Protection Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection Self-Timed Write Cycle (5 ms Typical) High Reliability Endurance: 1 Million Write Cycles Data Retention: 100 Years ESD Protection: >4000V Automotive Grade and Extended Temperature Devices Available 8-Pin PDIP, JEDEC SOIC, and 14-Pin and 20-Pin TSSOP Packages

SPI Serial EEPROMs

8K (1024 x 8) 16K (2048 x 8) 32K (4096 x 8) 64K (8192 x 8)

Description
The AT25080/160/320/640 provides 8192/16384/32768/65536 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 1024/2048/4096/8192 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation

(continued)

AT25080 AT25160 AT25320 AT25640

Pin Configuration
Pin Name CS SCK SI SO GND VCC WP HOLD NC DC Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Write Protect Suspends Serial Input No Connect Dont Connect 14-Lead TSSOP
CS SO NC NC NC WP GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC HOLD NC NC NC SCK SI

8-Pin PDIP
CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI CS SO WP GND

8-Pin SOIC
1 2 3 4 8 7 6 5 VCC HOLD SCK SI

20-Lead TSSOP*
NC CS SO SO NC NC WP GND DC NC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 NC VCC HOLD HOLD NC NC SCK SI DC NC

Rev. 0675C08/98

*Pins 3, 4 and 17, 18 are internally connected for 14-lead TSSOP socket compatibility. 1

are essential. The AT25080/160/320/640 is available in space saving 8-pin PDIP, JEDEC SOIC, and 14-pin and 20-pin TSSOP packages. The AT25080/160/320/640 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate ERASE cycle is required before WRITE.

BLOCK WRITE protection is enabled by programming the status register with one of four blocks of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.

Absolute Maximum Ratings*

Operating Temperature .................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage........................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Block Diagram

AT25080/160/320/640

AT25080/160/320/640
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Test Conditions COUT CIN Note: Output Capacitance (SO) Input Capacitance(CS, SCK, SI, WP HOLD) , 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VOUT = 0V VIN = 0V

DC Characteristics
Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +1.8V to +5.5V, TAC = 0C to +70C, VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol Parameter Supply Voltage Supply Voltage Supply Voltage Supply Current Supply Current Standby Current Standby Current Standby Current Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Test Condition Min 1.8 2.7 4.5 Typ Max 3.6 5.5 5.5 3.0 5.0 0.1 0.2 0.5 -3.0 -3.0 -0.6 0.5 2.0 3.0 3.0 Units V V V mA mA A A A A A V V V V 0.2 VCC - 0.2 V V

VCC1 VCC2 VCC3 ICC1 ICC2 ISB1 ISB2 ISB3 IIL IOL V
(1) IL

VCC = 5.0V at 1 MHz, SO = Open VCC = 5.0V at 2 MHz, SO = Open VCC = 1.8V, CS = VCC VCC = 2.7V, CS = VCC VCC = 5.0V, CS = VCC VIN = 0V to VCC VIN = 0V to VCC, TAC = 0C to 70C

VCC x 0.3 VCC + 0.5

0.4

VIH(1) VOL1 VOH1 VOL2

VOH2 Note:

VCC x 0.7 4.5V VCC 5.5V 1.8V VCC 3.6V IOL = 3.0 mA IOH = -1.6 mA IOL = 0.15 mA
IOH = -100 A

VCC - 0.8

1. VIL min and VIH max are reference only and are not tested.

AC Characteristics
Applicable over recommended operating range from TA = -40C to +85C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol Parameter SCK Clock Frequency Voltage 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 200 200 800 200 200 800 250 250 1000 250 250 1000 250 250 1000 50 50 100 50 50 100 100 100 400 200 200 400 0 0 0 0 0 0 200 200 800 ns Min 0 0 0 Max 2.1 2.1 0.5 2 2 2 2 2 2 Units MHz

fSCK

tRI

Input Rise Time

tFI

Input Fall Time

tWH

SCK High Time

ns

tWL

SCK Low Time

ns

tCS

CS High Time

ns

tCSS

CS Setup Time

ns

tCSH

CS Hold Time

ns

tSU

Data In Setup Time

ns

tH

Data In Hold Time

ns

tHD

Hold Setup Time

tCD

Hold Hold Time

tV

Output Valid

ns

tHO

Output Hold Time

ns

AT25080/160/320/640

AT25080/160/320/640
AC Characteristics (Continued)
Applicable over recommended operating range from TA = -40C to +85C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol Parameter Hold to Output Low Z Voltage 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 1M Min 0 0 0 Max 100 100 100 100 100 100 250 250 1000 5 10 20 Units ns

tLZ

tHZ

Hold to Output High Z

ns

tDIS

Output Disable Time

ns

tWC Endurance(1) Note:

Write Cycle Time 5.0V, 25C, Page Mode

ms Write Cycles

1. This parameter is characterized and is not 100% tested.

Serial Interface Description

MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25080/160/320/640 always operates as a slave. TRANSMITTER/RECEIVER: The AT25080/160/320/640 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25080/160/320/640, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25080/160/320/640 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25080/160/320/640. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is 1, all write opera-

tions to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is "0". This will allow the user to install the AT25080/160/320/640 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to 1.

SPI Serial Interface

AT25080/160/320/640

AT25080/160/320/640
Functional Description
The AT25080/160/320/640 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers. The AT25080/160/320/640 utilizes an 8 bit instruction register. The list of instructions and their operation codes are contained in Table 1. All instructions, addresses, and data are transferred with the MSB first and start with a high-tolow CS transition. Table 1. Instruction Set for the AT25080/160/320/640
Instruction Name WREN WRDI RDSR WRSR READ WRITE Instruction Format 0000 X110 0000 X100 0000 X101 0000 X001 0000 X011 0000 X010 Operation Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Memory Array Write Data to Memory Array

Table 3. Read Status Register Bit Definition

Bit Bit 0 (RDY) Definition Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the write cycle is in progress. Bit 1= 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the device is WRITE ENABLED. See Table 3. See Table 3.

Bit 1 (WEN) Bit 2 (BP0) Bit 3 (BP1)

Bits 4-6 are 0s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 4.

Bits 0-7 are 1s during an internal write cycle.

WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 2. Status Register Format
Bit 7 WPEN Bit 6 X Bit 5 X Bit 4 X Bit 3 BP1 Bit 2 BP0 Bit 1 WEN Bit 0 RDY

WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25080/160/320/640 is divided into four array segments. One quarter (1/4), one half (1/2), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be READ only. The block write protection levels and corresponding status register control bits are shown in Table 4. The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. WREN, tWC, RDSR). Table 4. Block Write Protect Bits
Status Register Bits Level 0 1(1/4) 2(1/2) 3(All) BP1 0 0 1 1 BP0 0 1 0 1

Array Addresses Protected AT25080 None 0300 -03FF 0200 -03FF 0000 -03FF AT25160 None 0600 -07FF 0400 -07FF 0000 -07FF AT25320 None 0C00 -0FFF 0800 -0FFF 0000 -0FFF AT25640 None 1800 -1FFF 1000 -1FFF 0000 -1FFF

The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is 1. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is 0. When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the block-protected sections in the memory array are disabled.

Writes are only allowed to sections of the memory which are not block-protected. NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to 0, as long as the WP pin is held low. Table 5. WPEN Operation
WPEN 0 0 1 1 X X WP X X Low Low High High WEN 0 1 0 1 0 1 Protected Blocks Protected Protected Protected Protected Protected Protected Unprotected Blocks Protected Writable Protected Writable Protected Writable Status Register Protected Writable Protected Protected Protected Writable

READ SEQUENCE (READ): Reading the AT25080/160/320/640 via the SO (Serial Output) pin requires the following sequence. After the CS line is pulled low to select a device, the READ op-code is transmitted via the SI line followed by the byte address to be read (A15-A0, Refer to Table 6). Upon completion, any data on the SI line will be ignored. The data (D7-D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The READ sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous READ cycle. WRITE SEQUENCE (WRITE): In order to program the AT25080/160/320/640, two separate instructions must be executed. First, the device must be write enabled via the Write Enable (WREN) Instruction. Then a Write (WRITE) Instruction may be executed. Also, the address of the

memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection Level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A Write Instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE op-code is transmitted via the SI line followed by the byte address (A15-A0) and the data (D7-D0) to be programmed (Refer to Table 6). Programming will start after the CS pin is brought high. (The LOW to High transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. The READY/BUSY status of the device can be determined by initiating a READ STATUS REGISTER (RDSR) Instruction. If Bit 0 = 1, the WRITE cycle is still in progress. If Bit 0 = 0, the WRITE cycle has ended. Only the READ STATUS REGISTER instruction is enabled during the WRITE programming cycle. The AT25080/160/320/640 is capable of a 32-byte PAGE WRITE operation. After each byte of data is received, the five low order address bits are internally incremented by one; the high order bits of the address will remain constant. If more than 32-bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. The AT25080/160/320/640 is automatically returned to the write disable state at the completion of a WRITE cycle. NOTE: If the device is not Write enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication. Table 6. Address Key
Address AN Don't Care Bits AT25080 A9 - A0 A15 - A10 AT25160 A10 - A0 A15 - A11 AT25320 A11 - A0 A15 - A12 AT25640 A12 - A0 A15 - A13

AT25080/160/320/640

AT25080/160/320/
Timing Diagrams
Synchronous Data Timing (for Mode 0)
VIH CS VIL t CSS VIH SCK VIL t SU VIH SI VIL tV VOH SO VOL HI-Z t HO t DIS HI-Z VALID IN tH t WH t WL t CSH t CS

WREN Timing

WRDI Timing

RDST Timing
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

SCK

SI

INSTRUCTION

SO

HIGH IMPEDANCE

DATA OUT
7 6 5 4 3 2 1 0

MSB

WRSR Timing
CS

0 SCK

10

11

12

13

14

15

SI

INSTRUCTION

DATA IN 4 3 2

SO

HIGH IMPEDANCE

READ Timing
CS

0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 SCK

SI

INSTRUCTION

BYTE ADDRESS 15 14 13 ... 3 2 1 0

SO

HIGH IMPEDANCE

DATA OUT 7 6 5 4 3 2 1 0 MSB

10

AT25080/160/320/

AT25080/160/320/640
WRITE Timing

CS

0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31 SCK

SI

INSTRUCTION

BYTE ADDRESS 15 14 13 ... 3 2 1 0

DATA IN 7 6 5 4 3 2 1 0

SO
HOLD Timing
CS

HIGH IMPEDANCE

tCD

tCD

SCK
t HD

HO LD
t HZ

t HD

SO
t LZ

11

AT25080 Ordering Information

tWC (max) (ms)
5

ICC (max) (A)

5000

ISB (max) (A)

2.0

fMAX (kHz)
2100

Ordering Code AT25080-10PC AT25080N-10SC AT25080T1-10TC AT25080-10PC-2.7 AT25080N-10SC-2.7 AT25080T1-10TC-2.7 AT25080-10PC-1.8 AT25080N-10SC-1.8 AT25080T1-10TC-1.8 AT25080-10PI AT25080N-10SI AT25080T1-10TI AT25080-10PI-2.7 AT25080N-10SI-2.7 AT25080T1-10TI-2.7 AT25080-10PI-1.8 AT25080N-10SI-1.8 AT25080T1-10TI-1.8

Package 8P3 8S1 14T 8P3 8S1 14T 8P3 8S1 14T 8P3 8S1 14T 8P3 8S1 14T 8P3 8S1 14T

Operation Range Commercial (0C to 70C) Commercial (0C to 70C) Commercial (0C to 70C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C)

10

3000

0.5

2100

20

3000

0.2

500

5000

2.0

2100

10

3000

0.5

2100

20

3000

0.2

500

Package Type 8P3 8S1 14T 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 14-Lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options Blank -2.7 -1.8 Standard Device (4.5V to 5.5V) Low Voltage (2.7V to 5.5V) Low Voltage (1.8V to 3.6V)

12

AT25080/160/320/640

AT25080/160/320/640
AT25160 Ordering Information
tWC (max) (ms)
5

ICC (max) (A)

5000

ISB (max) (A)

2.0

fMAX (kHz)
2100

Ordering Code AT25160-10PC AT25160N-10SC AT25160T1-10TC AT25160-10PC-2.7 AT25160N-10SC-2.7 AT25160T1-10TC-2.7 AT25160-10PC-1.8 AT25160N-10SC-1.8 AT25160T1-10TC-1.8 AT25160-10PI AT25160N-10SI AT25160T1-10TI AT25160-10PI-2.7 AT25160N-10SI-2.7 AT25160T1-10TI-2.7 AT25160-10PI-1.8 AT25160N-10SI-1.8 AT25160T1-10TI-1.8

Package 8P3 8S1 14T 8P3 8S1 14T 8P3 8S1 14T 8P3 8S1 14T 8P3 8S1 14T 8P3 8S1 14T

Operation Range Commercial (0C to 70C) Commercial (0C to 70C) Commercial (0C to 70C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C)

10

3000

0.5

2100

20

3000

0.2

500

5000

2.0

2100

10

3000

0.5

2100

20

3000

0.2

500

Package Type 8P3 8S1 14T 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 14-Lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options Blank -2.7 -1.8 Standard Device (4.5V to 5.5V) Low Voltage (2.7V to 5.5V) Low Voltage (1.8V to 3.6V)

13

AT25320 Ordering Information

tWC (max) (ms)
5 ICC (max) (A) 5000 ISB (max) (A) 2.0 fMAX (kHz) 2100 Ordering Code AT25320-10PC AT25320N-10SC AT25320T1-10TC AT25320T2-10TC AT25320-10PC-2.7 AT25320N-10SC-2.7 AT25320T1-10TC-2.7 AT25320T2-10TC-2.7 AT25320-10PC-1.8 AT25320N-10SC-1.8 AT25320T1-10TC-1.8 AT25320T2-10TC-1.8 AT25320-10PI AT25320N-10SI AT25320T1-10TI AT25320T2-10TI AT25320-10PI-2.7 AT25320N-10SI-2.7 AT25320T1-10TI-2.7 AT25320T2-10TI-2.7 AT25320-10PI-1.8 AT25320N-10SI-1.8 AT25320T1-10TI-1.8 AT25320T2-10TI-1.8 Package 8P3 8S1 14T 20T 8P3 8S1 14T 20T 8P3 8S1 14T 20T 8P3 8S1 14T 20T 8P3 8S 14T 20T 8P3 8S1 14T 20T Operation Range Commercial (0C to 70C)

10

3000

0.5

2100

Commercial (0C to 70C)

20

3000

0.2

500

Commercial (0C to 70C)

5000

2.0

2100

Industrial (-40C to 85C)

10

3000

0.5

2100

Industrial (-40C to 85C)

20

3000

0.2

500

Industrial (-40C to 85C)

Package Type 8P3 8S1 14T 20T 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 14-Lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 20-Lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options Blank -2.7 -1.8 Standard Device (4.5V to 5.5V) Low Voltage (2.7V to 5.5V) Low Voltage (1.8V to 3.6V)

14

AT25080/160/320/640

AT25080/160/320/640
AT25640 Ordering Information
tWC (max) (ms)
5

ICC (max) (A)

5000

ISB (max) (A)

2.0

fMAX (kHz)
2100

Ordering Code AT25640-10PC AT25640N-10SC AT25640T1-10TC AT25640T2-10TC AT25640-10PC-2.7 AT25640N-10SC-2.7 AT25640T1-10TC-2.7 AT25640T2-10TC-2.7 AT25640-10PC-1.8 AT25640N-10SC-1.8 AT25640T1-10TC-1.8 AT25640T2-10TC-1.8 AT25640-10PI AT25640N-10SI AT25640T1-10TI AT25640T2-10TI AT25640-10PI-2.7 AT25640N-10SI-2.7 AT25640T1-10TI-2.7 AT25640T2-10TI-2.7 AT25640-10PI-1.8 AT25640N-10SI-1.8 AT25640T1-10TI-1.8 AT25640T2-10TI-1.8

Package 8P3 8S1 14T 20T 8P3 8S1 14T 20T 8P3 8S1 14T 20T 8P3 8S1 14T 20T 8P3 8S1 14T 20T 8P3 8S1 14T 20T

Operation Range Commercial (0C to 70C)

10

3000

0.5

2100

Commercial (0C to 70C)

20

3000

0.2

500

Commercial (0C to 70C)

5000

2.0

2100

Industrial (-40C to 85C)

10

3000

0.5

2100

Industrial (-40C to 85C)

20

3000

0.2

500

Industrial (-40C to 85C)

Package Type 8P3 8S1 14T 20T 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 14-Lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 20-Lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options Blank -2.7 -1.8 Standard Device (4.5V to 5.5V) Low Voltage (2.7V to 5.5V) Low Voltage (1.8V to 3.6V)

15

Packaging Information
8P3, 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 BA
.400 (10.16) .355 (9.02) PIN 1 .280 (7.11) .240 (6.10) .037 (.940) .027 (.690)

8S1, 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Dimensions in Inches and (Millimeters)

.020 (.508) .013 (.330)

PIN 1

.157 (3.99) .150 (3.81)

.244 (6.20) .228 (5.79)

.300 (7.62) REF

.050 (1.27) BSC

.210 (5.33) MAX SEATING PLANE .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .015 (.380) MIN .022 (.559) .014 (.356) .100 (2.54) BSC

.196 (4.98) .189 (4.80) .068 (1.73) .053 (1.35)

.010 (.254) .004 (.102)

.325 (8.26) .300 (7.62)

.012 (.305) .008 (.203)

0 REF 15 .430 (10.9) MAX

0 REF 8 .050 (1.27) .016 (.406)

.010 (.254) .007 (.203)

14T, 14-Lead, 0.170" Wide, Thin Super Small Outline Package (TSSOP) Dimensions in Inches and (Millimeters)

20T, 20-Lead, 0.170" Wide, Thin Super Small Outline Package (TSSOP) Dimensions in Inches and (Millimeters)

INDEX MARK
PIN 1

INDEX MARK
PIN 1

4.50 (.177) 4.30 (.169)

6.50 (.256) 6.25 (.246)

4.50 (.177) 4.30 (.169)

6.50 (.256) 6.25 (.246)

5.10 (.201) 4.90 (.193)

1.20 (.047) MAX

6.60 (.260) 6.40 (.252)

1.20 (.047) MAX

.650 (.026) BSC 0.30 (.012) 0.19 (.007)

0.15 (.006) 0.05 (.002)

SEATING PLANE

.650 (.026) BSC 0.30 (.012) 0.19 (.007)

0.15 (.006) 0.05 (.002)

SEATING PLANE

0 REF 8

0.20 (.008) 0.09 (.004)

0 REF 8

0.20 (.008) 0.09 (.004)

0.75 (.030) 0.45 (.018)

0.75 (.030) 0.45 (.018)

16

AT25080/160/320/640