300 IEEE ELECTRON DEVICE LETTERS, VOL. 43, NO.

2, FEBRUARY 2022

Graphene FET on Diamond for

High-Frequency Electronics
M. Asad , Student Member, IEEE, S. Majdi , A. Vorobiev , Senior Member, IEEE,
K. Jeppson , Life Senior Member, IEEE, J. Isberg , and J. Stake , Senior Member, IEEE

Abstract — Transistors operating at high frequencies are frequency of oscillation that lagged considerably due to non-
the basic building blocks of millimeter-wave communication negligible gate resistances.
and sensor systems. The high charge-carrier mobility and In GFETs, the maximum frequency of oscillation is in part
saturation velocity in graphene can open way for ultra- limited by poor drain current saturation which results in a non-
fast field-effect transistors with a performance even better
than what can be achieved with III-V-based semiconductors. negligible drain output conductance [4]. In 2016, an extrinsic
However, the progress of high-speed graphene transistors transit frequency ( f T ) of 50 GHz and a maximum oscillation
has been hampered by fabrication issues, influence of frequency ( f max ) of 40 GHz was achieved for a gate length
adjacent materials, and self-heating effects. Here, we report of 200 nm using quasi-freestanding bilayer epitaxial graphene
on the improved performance of graphene field-effect tran- grown on a SiC (0001) substrate [5]. Recently, using an
sistors (GFETs) obtained by using a diamond substrate. improved fabrication process for CVD GFETs, Bonmann et al.
An extrinsic maximum frequency of oscillation fmax of up
to 54 GHz was obtained for a gate length of 500 nm. Fur-
demonstrated an extrinsic f T of 34 GHz and a matching
thermore, the high thermal conductivity of diamond pro- f max of 37 GHz for 500-nm GFETs with promising scaling
vides an efficient heat-sink, and the relatively high optical behaviour [6]. In order to minimise the output conductance
phonon energy of diamond contributes to an increased it is essential to minimize the number of charge carriers not
charge-carrier saturation velocity in the graphene channel. induced by the field such as carriers due to contaminants
Moreover, we show that GFETs on diamond exhibit excellent and traps in the adjacent materials, or carriers induced by
scaling behavior for different gate lengths. These results self-heating.
promise that the GFET-on-diamond technology has the
potential of reaching sub-terahertz frequency performance. Another performance-limiting factor is the influence on
the charge-carrier velocity due to optical-phonon scattering
Index Terms — Diamond, field-effect transistors, with the materials surrounding the graphene channel. Hence,
graphene, maximum frequency of oscillation, MOGFETs, surrounding materials with high optical-phonon energies are
optical phonons, saturation velocity, transit frequency.
preferred since there is a direct correlation between the
charge-carrier velocity and the transit frequency as confirmed
I. I NTRODUCTION by ref [7].
G RAPHENE is a 2D material with unique electrical
properties such as extremely high charge-carrier velocity
useful for transit types of devices [1]. There has been extensive
In this work, we utilize both the high surface optical phonon
energy and the high thermal conductivity of diamond as a
substrate to increase the GFET performance. A record high
research and progress on high-frequency graphene electronics extrinsic f max of 54 GHz was achieved for a top-gated GFET
since the first top-gated graphene field-effect transistor (GFET) on a single-crystal diamond substrate. We estimate the charge-
was demonstrated in 2007 [2]. In 2012, excellent GFET carrier saturation velocity being as high as 3.2 · 107 cm/s.
performance with intrinsic transit frequencies above 400 GHz Finally, we show that the high-frequency performance scales
was achieved for a 67-nm gate length GFET [3]. However, with the gate length, which indicates that GFETs on diamond
this excellent performance was not matched by the maximum have the potential of reaching sub-terahertz frequencies.
Manuscript received November 27, 2021; accepted December 27,
2021. Date of publication December 28, 2021; date of current version II. M ETHODS
January 27, 2022. This work was supported in part by the European Top-gated dual-channel RF GFETs were fabricated on a
Union’s Horizon 2020 Research and Innovation Programme under Grant high-quality free-standing single-crystal diamond substrate.
881603, in part by the Swedish Research Council under Grant 2017-
04504, and in part the Swedish Energy Agency under Grant 48591-1. The commercially available diamond substrate was homoepi-
The review of this letter was arranged by Editor G. Han. (Corresponding taxially grown in the (100) direction using chemical vapor
author: M. Asad.) deposition (CVD) by Element Six Ltd [8]. Fig. 1(a) shows
M. Asad, A. Vorobiev, K. Jeppson, and J. Stake are with an optical micrograph of a set of GFETs with gate lengths
the Department of Microtechnology and Nanoscience, Chalmers
University of Technology, 41296 Gothenburg, Sweden (e-mail: (L g ) varying from 0.5 μm to 2 μm and a total gate width
[email protected]). of 30 μm. Fig. 1(b) shows a SEM image of a 0.5 μm
S. Majdi and J. Isberg are with the Division for Electricity, Department two-finger GFET. For illustration, Fig. 1(c) shows a three-
of Electrical Engineering, Uppsala University, 75103 Uppsala, Sweden.
Color versions of one or more figures in this letter are available at dimensional view of the GFET layout. As a first step of the
https://doi.org/10.1109/LED.2021.3139139. fabrication process, monolayer CVD graphene was transferred
Digital Object Identifier 10.1109/LED.2021.3139139 on to the diamond substrate, followed by deposition of a
0741-3106 © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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 ASAD et al.: GRAPHENE FET ON DIAMOND FOR HIGH-FREQUENCY ELECTRONICS 301

Fig. 2. GFET transfer characteristics (a) and output characteristics.

(b) GFET geometry Lg = 0.5 μm, W = 30 μm.

Fig. 1. Views of top-gate, dual-channel, high-frequency GFET on single

crystal diamond substrate: (a) Photograph of the test chip, (b) SEM
image, (c) schematic cross-sectional view, (d) small-signal equivalent
circuit and dashed region indicates the intrinsic transistor elements.

5-nm thick TiO2 /Ti protection layer for avoiding contact

between the electron-beam resist defining the source/drain
areas and the graphene. After wet-etch removal of the pro-
tection layer in the source/drain resist openings, Ti/Pd/Au
(1 nm/15 nm/285 nm) was deposited and source/drain contacts
were fabricated using lift-off. The use of a protection layer
is important for obtaining a clean metal/graphene interface
and a low contact resistance. Next, the graphene mesa was
defined. After removal of the remaining protection layer from
the channel area, the gate dielectric stack was formed by a
5-nm thick thermally oxidized Al2 O3 seed layer and an 18-nm
thick Al2 O3 top layer deposited by atomic layer deposition.
The gate fingers, the gate pad, and the source/drain pads were
formed by deposition of a Ti/Au (100 nm/300 nm) layer. All
patterns were defined using electron-beam lithography.
For GFET characterization, transfer and output character-
istics were obtained using a Keithley 2612B dual-channel
source meter. High-frequency S-parameters were measured
up to 40 GHz using an Agilent N5230A network analyzer.
Two-port open-short-load-through calibration was performed
using a standard calibration chip prior to the S-parameter
measurements. De-embedding and extraction of the small-
signal equivalent-circuit elements was performed based on the
method described by Dambrine et al. [9]. Special test struc-
tures were included to find the pad capacitances and induc-
tances from the S-parameter measurements. For analysing the
GFET high-frequency performance, the small-signal equiva-
lent circuit shown in Fig. 1(d) was used.
Fig. 3. Graphs showing (a) small-signal current gain h21 , maximum
stable gain/maximum available gain (MSG/MAG), and Mason’s unilateral
III. R ESULTS AND D ISCUSSIONS gain U versus frequency obtained at VGS = 1 V and VDS = −1.5 V.
Extrapolated extrinsic transit and maximum oscillation frequencies of
Fig. 2 shows the GFET transfer and output characteristics 44 and 54 GHz, respectively, are obtained. Solid lines are obtained
indicating typical GFET behavior. The JD vs. VDS curve from the S-parameters simulated using small-signal equivalent circuit
obtained for VGS = 1 V shows the conditions under which the analysis. (b) Intrinsic transit and maximum-oscillation frequencies versus
high-frequency performance was measured. Fig. 3 summarizes drain current density, (c) normalized small-signal conductances gm and
gds versus drain voltage.
the measurement results obtained for the same GFET biased
for maximum gain. First, the frequency-dependent current
gain (h 21 ), the Mason’s unilateral power gain (U ), and the our knowledge, this is the highest reported extrinsic perfor-
maximum stable gain/maximum available gain (MSG/MAG) mance of top-gated CVD GFETs so far [6], [7], [10]–[13].
obtained from the S-parameters are shown in Fig. 3(a). Fig. 3(b) shows an almost linear relationship between the
An extrinsic f T as high as 44 GHz and an extrinsic f max intrinsic transit frequency f T−int and the drain current density
as high as 54 GHz are indicated by the figure. To the best of JD , indicating a practically constant charge-carrier density n

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 302 IEEE ELECTRON DEVICE LETTERS, VOL. 43, NO. 2, FEBRUARY 2022

throughout the whole drain bias range (0 to 1.5 V). This

conclusion is based on the simple first-order assumption of
an intrinsic transit frequency f T−int = v d /(2π L g ) and a drain
current density JD = qnv d , where v d is the drift velocity, and
q is the elementary charge. Based on these assumptions an
effective charge carrier concentration n = 1.8 · 1012 cm−2 was
obtained. Furthermore, the assumption of a constant charge-
carrier density leads to the conclusion that the charge-carrier
drift velocity profile can be obtained not only from the fT−int
vs. VDS (as in previous work [7]) but also directly from the
output characteristic JD vs. VDS . Finally, we can conclude that
the effect of self-heating, typically resulting in an increasing
charge-carrier density, is sufficiently low due to the high
thermal conductivity of the diamond substrate. Fig. 4. Charge-carrier velocity (left axis) versus intrinsic electric
field along the channel derived from the drain current density JD vs.
From the broadband S-parameter measurements, the bias- Eint (right axis) by assuming a constant charge-carrier concentration
dependent small-signal equivalent circuit parameters gm , gds, n = 1.8 · 1012 cm−2 obtained from the slope of the fT-int vs JD graph
Cgs , and Cgd were extracted and normalized by the gate shown in Fig. 3b. The Caughey-Thomas model [14] (solid line) with
width. The values of Cgs and Cgd are 500 ± 50 fF/mm, γ = 3 was used to estimate the saturation velocity (dashed line).
450 ± 50 fF/mm, respectively, and are almost constant across
the drain bias range. Figs. 3(c) shows conductances gm and gds
versus the extrinsic drain voltage VDS . The observed increase
in transconductance gm and decrease in drain conductance
gds with VDS are the two main factors for the enhanced
high-frequency performance of these devices. Other extrinsic
circuit elements such as the pad inductance (L G = 13.8 pH,
L S = 1.6 pH, L D = 5 pH), source/drain resistance (RS /RD =
23 ), gate resistance, (RG = 8 ), parasitic pad capacitances
(CPG = 15 fF, CPD = 4 fF), and parasitic pad resistances
(Rpad = 21 k) are assumed to be bias-independent. Typically,
due to zero-bandgap in monolayer graphene, GFETs reveal
a linear output characteristic without drain current saturation
resulting in a relatively high gds which has an adverse impact
on the power gain i.e., limiting the fmax . In this work,
Fig. 5. Maximum frequency of oscillation (fmax ) versus gate length (Lg ).
high current density due to high charge carrier velocity and Solid red circles represent data from this work and the solid line showing a
significant drain current saturation due to velocity saturation 1/Lg dependence demonstrates the device scaling behavior. Also shown,
are observed and verified by the drain current modeling. The for comparison, is data from GFETs on CVD, exfoliated and epitaxial
drain current saturation results in low gds and, thus enhanced graphene on silicon and SiC substrates [3], [6], [7], [10], [13], [15], from
carbon nanotube FETs [16], [17] and from MOSFETs of similar gate
f max . Most promising way of increasing the high-frequency lengths [18]–[20].
performance of GFET is by increasing the gm , which is
proportional to the v d . The transconductance gm shown in
Fig. 3(d) increases with the VDS and shows signs of saturation are mainly attributed to a higher carrier velocity, improved
at higher field. current saturation, and reduced effects of self-heating.
Fig. 4 shows the charge-carrier velocity found from the
dependence of the drain current on the intrinsic drain field.
The saturation velocity v sat was derived by using the Caughey- IV. C ONCLUSION
Thomas velocity model [14] assuming a constant effective In summary, the potential of top-gated graphene field-effect
charge-carrier density – as previously concluded from the transistors on diamond substrate has been demonstrated. Sub-
almost linear relationship between fT versus JD across the stantial improvements in scaling behaviour and in maximum
drain voltage range shown in Fig. 3(b). The v sat in the diamond frequency of oscillation have been achieved due to the unique
GFET is estimated being as high as 3.2 · 107 cm/s. For properties of diamond such as high surface-optical-phonon
comparison, the v sat in an hBN-encapsulated graphene Hall- energy and high thermal conductivity when being used as
bar test structure was reported to 5 · 107 cm/s [21]. a substrate. To reach the full potential of GFETs on dia-
To demonstrate the future prospects of the diamond GFET mond, both material quality and fabrication processes must
technology, the extrinsic performance of GFETs for different be improved to achieve higher charge-carrier mobilities and
gate lengths is compared with published results in Fig. 5. saturation velocities.
In this work, the performance follows the solid trendline
1/L g0.9 , typical for Si-MOSFET and HEMT technologies [4],
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