TSB711, TSB711A

TSB712, TSB712A
Datasheet

Precision rail-to-rail input / output 36 V, 6 MHz op amps

Features
TSB712 and TSB712A

• Rail-to-rail input and output

• Low offset voltage: 300 µV maximum
• Wide supply voltage range: 2.7 V to 36 V
• Gain bandwidth product: 6 MHz
MiniSO8 SO8 • Slew rate : 3 V/µs
• Low noise : 12 nV/√Hz
TSB711 and TSB711A • Integrated EMI filter
• 2 kV HBM ESD tolerance
• Extended temperature range : -40 °C to +125 °C
• Automotive-grade available

SOT23-5
Applications
• High-side and low-side current sensing
• Hall effect sensors
• Data acquisition and instrumentation
• Test and measurement equipments
• Motor control
Maturity status link
• Industrial process control
TSB711, TSB711A, TSB712, TSB712A
• Strain gauge

Related products Description

Low-power, 2.5 MHz, rail-to-
TSB571, The TSB711, TSB711A, TSB712 and TSB712A 6 MHz bandwidth amplifiers feature
rail inputs and outputs, 36 V
TSB572
op amps rail-to-rail input and output, which is guaranteed to operate from +2.7 V to +36 V
single supply as well as from ±1.35 V to ±18 V dual supplies.
TSB511, Rail-to-rail inputs and
TSB512, outputs, 36 V, 6 MHz op These amplifiers have the advantage of offering a large span of supply voltage and
TSB514 amps an excellent input offset voltage of 300 µV maximum at 25 °C.
The combination of wide bandwidth, slew rate, low noise, rail-to-rail capability and
precision makes the TSB711, TSB711A, TSB712 and TSB712A useful in a wide
variety of applications such as: filters, power supply and motor control, actuator
driving, hall effect sensors and resistive transducers.

DS12487 - Rev 7 - October 2023 www.st.com

For further information contact your local STMicroelectronics sales office.
 TSB711, TSB711A, TSB712, TSB712A
Pin description

1 Pin description

Figure 1. TSB711 pin connections (top view)

OUT VCC+

VCC-

IN+ IN-

SOT23-5

Table 1. TSB711 pin description (SOT23-5)

Pin n° Pin name Description

1 OUT Output channel

2 VCC- Negative supply voltage

3 IN1+ Non-inverting input channel

4 IN- Inverting input channel

5 VCC+ Positive supply voltage

Figure 2. TSB712 pin connections (top view)

OUT1 VCC+

IN1- OUT2

IN1+ IN2-

VCC- IN2+

MiniSO8/SO8

Table 2. TSB712 pin description (miniSO8/SO8)

Pin n° Pin name Description

1 OUT1 Output channel 1

2 IN1- Inverting input channel 1
3 IN1+ Non-inverting input channel 1

4 VCC- Negative supply voltage

5 IN2+ Non-inverting input channel 2

6 IN2- Inverting input channel 2
7 OUT2 Output channel 2

8 VCC+ Positive supply voltage

DS12487 - Rev 7 page 2/32

 TSB711, TSB711A, TSB712, TSB712A
Absolute maximum ratings and operating conditions

2 Absolute maximum ratings and operating conditions

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

VCC Supply voltage (1) +40 or ±20 V

Vid Input voltage differential (2) ±2 V

Vin Input voltage (VCC-) - 0.2 to (VCC+) + 0.2 V

Iin Input current (3) ±10 mA

Storage temperature -65 to +150 °C

Thermal resistance junction-to-ambient (4) (5)

MiniSO-8 190
Rth-ja °C / W
SO8 125
SOT23-5 250
Tj Maximum junction temperature 150 °C

HBM: human body model (6) 2 kV

ESD CDM: charged device model (7) 1 kV

Latch-up immunity 100 mA

1. All voltage values, except the differential voltage are with respect to the network ground terminal.
2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. The maximum input
voltage differential value may be extended to the condition that the input current is limited to ±10 mA. See Section 5.2 Input
pin voltage range.
3. Input current must be limited by a resistor in series with the inputs when the input voltage is beyond the rails (see
Section 5.2 Input pin voltage range).
4. Short-circuits can cause excessive heating and destructive dissipation.
5. Rth are typical values.
6. Human body according to JEDEC standard JESD22-A114F.
7. According to ANSI/ESD STM5.3.1.

Table 4. Operating conditions

Symbol Parameter Value

VCC Supply voltage 2.7 V to 36 V

Vicm Common mode input voltage range (VCC-) to (VCC+) + 0.1 V

Toper Operating free air temperature range -40 °C to +125 °C

DS12487 - Rev 7 page 3/32

 TSB711, TSB711A, TSB712, TSB712A
Electrical characteristics

3 Electrical characteristics

Table 5. Electrical characteristics at VCC = 36 V, VICM = VOUT = VCC / 2, Tamb = 25 °C and RL connected to VCC / 2 (unless
otherwise specified)

Symbol Parameter Conditions Min. Typ. Max. Unit

DC performance
TSB711A, TSB712A, T = 25 °C,
±300
VCC- ≤ VICM ≤ VCC+ - 1.5 V

TSB711A, TSB712A, T = 25 °C, VCC- ≤ VICM ≤ VCC+ ±650

TSB711A, TSB712A, -40 °C < T < 125 °C,

±580
VCC- ≤ VICM ≤ VCC+ - 1.5 V

TSB711A, TSB712A, -40 °C < T < 125 °C,

±930
VCC- ≤ VICM ≤ VCC+
Vio Input offset voltage µV
TSB711, TSB712, T = 25 °C,
±800
VCC- ≤ VICM ≤ VCC+ -1.5 V

TSB711, TSB712, T = 25 °C, VCC- ≤ VICM ≤ VCC+ ±1200

TSB711, TSB712, -40 °C < T < 125 °C,

±1100
VCC- ≤ VICM ≤ VCC+ - 1.5 V

TSB711, TSB712, -40 °C < T < 125 °C,

±1400
VCC- ≤ VICM ≤ VCC+

ΔVio / ΔT Input offset voltage drift -40°C < T < 125 °C (1) 2.8 µV/°C

Long-term input offset voltage

ΔVio T = 25 °C (2) 0.57 µV/√mo
drift
VICM = VCC+, T = 25 °C 0 300

VICM = VCC+, -40 °C < T < 125 °C 0 900

IIB Input bias current (3)
VICM = VCC-, T = 25 °C -100 0
nA
VICM = VCC-,-40 °C < T < 125 °C -200 0

VICM = VCC+ 10
IIO Input offset current (4)
VICM = VCC- 10

RL ≥ 10 kΩ, (VCC-) + 0.5 V ≤ VOUT ≤ (VCC+) - 0.5 V,

110 125
T = 25 °C
AVD Open loop gain
RL ≥ 10 kΩ, (VCC-) + 0.5 V ≤ VOUT ≤ (VCC+) - 0.5 V,
105
-40 °C < T < 125 °C
(VCC-) ≤ VICM ≤ ( VCC+) - 1.5 V, T = 25 °C 115 130

(VCC-) ≤ VICM ≤ (VCC+) - 1.5 V, -40 °C < T < 125 °C 110

TSB711A, TSB712A (VCC-) ≤ VICM ≤ (VCC+), dB

100 120
T = 25 °C
Common-mode rejection ratio
CMR TSB711A, TSB712A (VCC-) ≤ VICM ≤ (VCC+),
20 log (∆VINCM / ∆VIO) 95
-40 °C < T < 125 °C
TSB711, TSB712 (VCC-) ≤ VICM ≤ (VCC+), T = 25 °C 90 120

TSB711 , TSB712 (VCC-) ≤ VICM ≤ (VCC+),

85
-40 °C < T < 125 °C

DS12487 - Rev 7 page 4/32

 TSB711, TSB711A, TSB712, TSB712A
Electrical characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

Power supply rejection ratio 5 V < (VCC+) - (VCC-) < 36 V, VICM = VCC / 2
SVR 100 125 dB
20 log (∆VCC / ∆VIO) -40 °C < T < 125 °C
No load, -40 °C < T < 125 °C 120
High level output voltage
VOH ISOURCE = 2 mA, -40 °C < T < 125 °C 200
(drop voltage from VCC+)
ISOURCE = 15 mA, -40 °C < T < 125 °C 1000
mV
No load , -40 °C < T < 125 °C 120

VOL Low level output voltage ISINK = 2 mA, -40 °C < T < 125 °C 200

ISINK = 15 mA , -40 °C < T < 125 °C 1000

VOUT = VCC, T = 25 °C 25 50
ISINK
VOUT = VCC, -40 °C < T < 125 °C 20
IOUT mA
VOUT = 0 V, T = 25 °C 25 50
ISOURCE
VOUT = 0 V, -40 °C < T < 125 °C 20

No load, T = 25 °C 1.8
ICC Supply current by op-amp mA
No load, -40 °C < T < 125 °C 3
AC performance

GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 4.5 6 MHz

9 V step, RL = 10 kΩ, CL = 100 pF, AV = 1 V/V,

SR Slew rate 2.2 3 V / µs
10% to 90%
VIN = 1 Vrms , RL = 10 kΩ, AV = +1, f = 1 kHz,
0.0003
Total harmonic distorsion + BW = 22 kHz
THD+N %
noise VIN = 1 Vrms , RL = 1 kΩ, AV = +1, f = 1 kHz,
0.00034
BW = 22 kHz
VOUT = 5 Vpp, f = 1 kHz, AV = +11, RL = 10 kΩ 125
CR Crosstalk dB
VOUT = 5Vpp, f = 10 kHz, AV = +11, RL = 10 kΩ 100

Φm Phase margin At unity gain, 25 °C, 10 kΩ, 100 pF 45 ᵒ

CLOAD Capacitive load drive 100 (5) pF

f = 10 Hz 20
en Input voltage noise density f = 100 Hz 13 nV/√Hz
f = 10 kHz 12
en p-p Input noise voltage 0.1 Hz ≤ f ≤ 10 Hz 0.5 µVPP

in Input current noise density f = 1 kHz 0.15 pA/√Hz

1. See Section 5.4 Input offset voltage drift over the temperature in application information.
2. Typical value is based on the VIO drift observed after 1000 h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an
activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration. See Section 5.5 Long term input offset voltage
drift.
3. Current is positive when it is sinked into the op-amp.
4. Iio is defined as |Iibp – Iibn|
5. For higher capacitive values see Figure 25. Phase margin vs. output current at VCC = 36 V, Figure 26. Phase margin vs. capacitive load and
Figure 27. Overshoot vs. capacitive load at VCC = 36 V
6. Theoretical value of the input current noise density based on the measurement of the input transistor base current: in = 2. q.ib

DS12487 - Rev 7 page 5/32

 TSB711, TSB711A, TSB712, TSB712A
Electrical characteristics

Table 6. Electrical characteristics at VCC = 5 V, VICM = VOUT = VCC / 2, Tamb = 25 °C and RL connected to VCC / 2 (unless
otherwise specified)

Symbol Parameter Conditions Min. Typ. Max. Unit

DC performance
TSB711A, TSB712A, T = 25 °C,
± 350
VCC- ≤ VICM ≤ VCC+ - 1.5 V

TSB711A,TSB712A, T = 25 °C, VCC- ≤ VICM ≤ VCC+ ± 650

TSB711A,TSB712A, -40 °C < T < 125 °C,

± 750
VCC- ≤ VICM ≤ VCC+ - 1.5 V

TSB711A, TSB712A, -40 °C < T < 125 °C,

± 1050
VCC- ≤ VICM ≤ VCC+
Vio Input offset voltage µV
TSB711, TSB712, T = 25 °C, VCC- ≤ VICM ≤ VCC+ -
± 800
1.5 V
TSB711, TSB712, T = 25 °C, VCC- ≤ VICM ≤ VCC+ ± 1200

TSB711, TSB712, -40 °C < T < 125 °C,

± 1100
VCC- ≤ VICM ≤ VCC+ - 1.5 V

TSB711, TSB712, -40 °C < T < 125 °C,

± 1400
VCC- ≤ VICM ≤ VCC+

ΔVio / ΔT Input offset voltage drift -40°C < T < 125 °C (1) 4 µV/°C

VICM = VCC+, T = 25 °C 0 300

VICM = VCC+, -40 °C < T < 125 °C 0 900

IIB Input bias current (2)
VICM = VCC-, T = 25 °C -100 0
nA
VICM = VCC-, -40 °C < T < 125 °C -200 0

VICM = VCC+ 10
IIO Input offset current (3)
VICM = VCC- 10

RL ≥ 10 kΩ, (VCC-) + 0.5 V ≤ VOUT ≤ (VCC+) - 0.5 V,

105 120
T = 25 °C
AVD Open loop gain dB
RL ≥ 10 kΩ, (VCC-) + 0.5 V ≤ VOUT ≤ (VCC+) - 0.5 V,
100
-40 °C < T < 125 °C
(VCC-) ≤ VICM ≤ ( VCC+) - 1.5 V, T = 25 °C 95 125

(VCC-) ≤ VICM ≤ (VCC+) - 1.5 V, -40 °C < T < 125 °C 90

TSB711A, TSB712A (VCC-) ≤ VICM ≤ (VCC+),

80 105
T = 25 °C
Common-mode rejection ratio
CMR TSB711A, TSB712A (VCC-) ≤ VICM ≤ (VCC+), dB
20 log ( ∆VINCM / ∆VIO ) 75
-40 °C < T < 125 °C
TSB711, TSB712 (VCC-) ≤ VICM ≤ (VCC+), T = 25 °C 75 105

TSB711, TSB712 (VCC-) ≤ VICM ≤ (VCC+),

70
-40 °C < T < 125 °C

High level output voltage No load, -40 °C < T < 125 °C 90

VOH
(drop voltage from VCC+) ISOURCE = 2 mA, -40 °C < T < 125 °C 200
mV
No load, -40 °C < T < 125 °C 90
VOL Low level output voltage
ISINK = 2 mA, -40 °C < T < 125 °C 200

DS12487 - Rev 7 page 6/32

 TSB711, TSB711A, TSB712, TSB712A
Electrical characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

VOUT = VCC, T = 25 °C 20 50
ISINK
VOUT = VCC, -40 °C < T < 125 °C 15
IOUT mA
VOUT = 0 V, T = 25 °C 20 50
ISOURCE
VOUT = 0 V, -40 °C < T < 125 °C 15

No load, T = 25 °C 1.4
ICC Supply current by op-amp mA
No load, -40 °C < T < 125 °C 2.3
AC performance

GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 4.5 6 MHz

3 V step, RL = 10 kΩ, CL = 100 pF,

SR Slew rate 2 2.7 V/µs
AV = 1 V/V, 10% to 90%

VIN = 1 Vrms , RL = 10 kΩ, AV = +1, f = 1 kHz,

0.00032
Total harmonic distorsion + BW = 22 kHz
THD+N %
noise VIN = 1 Vrms , RL = 1 kΩ, AV = +1, f = 1 kHz,
0.0004
BW = 22 kHz
Φm Phase margin At unity gain, 25 °C, 10 kΩ, 100 pF 34 ᵒ
CLOAD Capacitive load drive 100 (4) pF

f = 10 Hz 20
en Input voltage noise density f = 100 Hz 13 nV/√Hz
f = 10 kHz 12
en p-p Input noise voltage 0.1 Hz ≤ f ≤ 10 Hz 0.8 µVPP

in Input current noise density f = 1 kHz 0.15 (5) pA/√Hz

1. See Section 5.4 Input offset voltage drift over the temperature in application information.
2. Current is positive when it is sinked into the op-amp.
3. Iio is defined as |Iibp – Iibn|.
4. For higher capacitive values see Figure 24. Phase margin vs. output current at VCC = 5 V, Figure 26. Phase margin vs. capacitive load
5. Theoretical value of the input current noise density based on the measurement of the input transistor base current: in = 2. q.ib

DS12487 - Rev 7 page 7/32

 TSB711, TSB711A, TSB712, TSB712A
Typical performance characteristics

4 Typical performance characteristics

RL connected to VCC / 2 (unless otherwise specified).

Figure 4. Input offset voltage distribution at VCC = 5 V

Figure 3. Supply current vs. supply voltage
TSB711A, TSB712A

Figure 5. Input offset voltage distribution at VCC = 36 V

Figure 6. Input offset voltage vs. temperature at VCC = 5 V
TSB711A, TSB712A

DS12487 - Rev 7 page 8/32

 TSB711, TSB711A, TSB712, TSB712A
Typical performance characteristics

Figure 7. Input offset voltage vs. temperature at Figure 8. Input offset voltage thermal coefficient
VCC = 36 V distribution at VCC = 5 V

Figure 9. Channel separation vs. frequency at VCC = 36 V Figure 10. Input offset voltage vs. supply voltage

Figure 11. Input offset voltage vs. common mode voltage Figure 12. Input offset voltage vs. common mode voltage
at VCC = 5 V TSB711A, TSB712A at VCC = 36 V TSB711A, TSB712A

DS12487 - Rev 7 page 9/32

 TSB711, TSB711A, TSB712, TSB712A
Typical performance characteristics

Figure 13. Input bias current vs. temperature at Figure 14. Output current vs. output voltage at
VICM = VCC / 2 VCC = 5 V

Figure 15. Input bias current vs. common mode voltage at Figure 16. Input bias current vs. common mode voltage at
VCC = 5 V VCC = 36 V

Figure 17. Output current vs. output voltage at VCC = 36 V Figure 18. Output voltage (VOH) vs. supply voltage

DS12487 - Rev 7 page 10/32

 TSB711, TSB711A, TSB712, TSB712A
Typical performance characteristics

Figure 19. Output voltage (VOL) vs. supply voltage Figure 20. Positive slew rate at VCC = 36 V

Figure 21. Negative slew rate at VCC = 36 V Figure 22. Bode diagram at VCC = 5 V

Figure 23. Bode diagram at VCC = 36 V Figure 24. Phase margin vs. output current at VCC = 5 V

DS12487 - Rev 7 page 11/32

 TSB711, TSB711A, TSB712, TSB712A
Typical performance characteristics

Figure 25. Phase margin vs. output current at VCC = 36 V Figure 26. Phase margin vs. capacitive load

Figure 27. Overshoot vs. capacitive load at VCC = 36 V Figure 28. Small step response vs. time at VCC = 5 V

Figure 29. Desaturation time at low rail at VCC = 5 V Figure 30. Desaturation time at high rail at VCC = 5 V

DS12487 - Rev 7 page 12/32

 TSB711, TSB711A, TSB712, TSB712A
Typical performance characteristics

Figure 32. Amplifier behavior close to the low rail at

Figure 31. Small step response vs. time at VCC = 36 V
VCC = 36 V

Figure 33. Amplifier behavior close to the high rail at

Figure 34. Noise vs. frequency at VCC = 5 V
VCC = 36 V

Figure 35. Noise vs. frequency at VCC = 36 V Figure 36. Noise vs. time at VCC = 36 V

DS12487 - Rev 7 page 13/32

 TSB711, TSB711A, TSB712, TSB712A
Typical performance characteristics

Figure 37. THD+N vs. frequency Figure 38. THD+N vs. output voltage

Figure 39. PSRR vs. frequency at VCC = 10 V Figure 40. CMRR vs. frequency at VCC = 10 V

DS12487 - Rev 7 page 14/32

 TSB711, TSB711A, TSB712, TSB712A
Application information

5 Application information

5.1 Operating voltages

The TSB711, TSB711A, TSB712, TSB712A devices can operate from 2.7 to 36 V. The parameters are fully
specified at 5 V and 36 V power supplies. However, the parameters are very stable over the full VCC range and
several characterization curves show the TSB711, TSB711A, TSB712, TSB712A device characteristics over the
full operating range. Additionally, the main specifications are guaranteed in extended temperature range from -40
to 125 °C.

5.2 Input pin voltage range

The TSB711, TSB711A,TSB712 and TSB712A devices have an internal ESD diode protection on the inputs.
These diodes are connected between the inputs and each supply rail to protect the input stage from electrical
discharge, as shown in the figure below.

Figure 41. Input current limitation

Vcc+

100Ω
In - - VCC +

D1 D2 Out Out
100Ω VCC -
In+ +

Vcc-

When the input pin voltage exceeds the power supply, the ESD diodes become conductive and, depending on
this voltage, excessive current can flow through them. Without limitation this overcurrent can damage the device.
In this case, the current has to be limited to 10 mA by adding a resistance in series with the input pin.
Similarly, in order to avoid excessive current in the protection diodes between the positive and negative inputs,
the differential voltage should be limited to ± 2 V, or the current limited to 10 mA. Such a high differential voltage
can be reached when the output is in saturation mode, or slew rate limited. In particular, it can happen when the
device is used in comparator mode.
The TSB711, TSB711A, TSB712, TSB712A do not show any phase reversal for any input common mode voltage
inside the absolute maximum ratings (AMR) voltage window, (VCC-) - 200 mV < VICM < (VCC+) + 200 mV.

DS12487 - Rev 7 page 15/32

 TSB711, TSB711A, TSB712, TSB712A
Rail-to-rail input stage

5.3 Rail-to-rail input stage

The TSB711, TSB711A, TSB712, TSB712A devices are built with two complementary NPN and PNP input
differential pairs, as shown in the figure below.

Figure 42. Rail-to-rail input stage

V CC

Ip

VIP

Pn Pp
VIN
[…] […]

[…] […]

Nn Np

In

GND

The devices have rail-to-rail inputs, and the input common mode range is extended from VCC- to (VCC+) + 0.1 V.
However, the performance of these devices is optimized for the P-channel differential pair (which means from
VCC- to (VCC+) - 1.5 V). Around (VCC+) – 1 V, and with slight variations depending on the process, a transition
occurs between the P-channel and the N-channel differential pair, impacting the input offset voltage (see
Figure 11. Input offset voltage vs. common mode voltage at VCC = 5 V TSB711A, TSB712A and Figure 12. Input
offset voltage vs. common mode voltage at VCC = 36 V TSB711A, TSB712A). As a consequence, CMRR can be
degraded around this transition region. In order to achieve the best possible performance, this operating point
should be avoided.
Please also notice that the input bias current polarity depends on the operation of NPN or PNP input stage. This
transition is visible in figures Figure 15. Input bias current vs. common mode voltage at VCC = 5 V and
Figure 16. Input bias current vs. common mode voltage at VCC = 36 V.

5.4 Input offset voltage drift over the temperature

The maximum input voltage drift variation over temperature is defined as the offset variation related to the offset
value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and
the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be
compensated during the production at application level. The maximum input voltage drift overtemperature enables
the system designer to anticipate the effect of temperature variations. The maximum input voltage drift
overtemperature is computed using the following formula:

ΔVio Vio T − Vio 25°C

ΔT = max T − 25°C (1)
T = − 40 °C and T = 125 °C
The datasheet maximum value is guaranteed by a measurement on a representative sample size ensuring a Cpk
(process capability index) greater than 1.3.

DS12487 - Rev 7 page 16/32

 TSB711, TSB711A, TSB712, TSB712A
Long term input offset voltage drift

5.5 Long term input offset voltage drift

To evaluate product reliability, two types of stress acceleration are used:
• Voltage acceleration, by changing the applied voltage.
• Temperature acceleration, by changing the die temperature (below the maximum junction temperature
allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using:

(2)
AFV = еβ.(VS - VU)
Where:
AFV is the voltage acceleration factor
β is the voltage acceleration coefficient in 1/V, constant technology parameter (β = 1)
VS is the stress voltage used for the accelerated test
VU is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined as follows:

(3)
Ea 1 1
AFT = e k . TU − TS .
Where:
AFT is the temperature acceleration factor
Ea is the activation energy of the technology based on the failure rate
k is the Boltzmann constant (8.6173 x 10-5 eV.K-1)
TU is the temperature of the die when VU is used (K)
TS is the temperature of the die under temperature stress (K)
The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and the temperature
acceleration factor.

(4)
AF = AFT . AFV
AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can
then be used in Equation 5 to calculate the number of months of use equivalent to 1000 hours of reliable stress
duration.

(5)
Months = AF × 1000 h × 12 months / (24 h × 365.25 days)
To evaluate the op-amp reliability, a follower stress condition is used where VCC is defined as a function of the
maximum operating voltage and the absolute maximum ratings (as recommended by JEDEC rules). Vio drift (in
µV) of the product after 1000 h of stress is tracked with parameters at different measurement conditions.

(6)
VCC = max(VOP) with Vicm = VCC/2

The long term drift parameter ΔVio (in µV.month-1/2), estimating the reliability performance of the product, is
obtained using the ratio of the Vio (input offset voltage value) drift over the square root of the calculated number of
months.

(7)
Viodrift
∆ Vio = montℎs

Where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration.

DS12487 - Rev 7 page 17/32

 TSB711, TSB711A, TSB712, TSB712A
EMI rejection

The Vio final drift, in µV, to be measured on the device in real operation conditions can be computed from:

(8)
Ea 1 1
β . VCC − VCC nom
Vio final drift top, Top, VCC = ∆ Vio, 25°C . top . e . e k . 297 − Top
Where:
ΔVio is the long term drift parameter in µV.month-1/2
top is the operating time seen by the device, in months
Top is the operating temperature
VCC is the power supply during operating time
VCC nom is the nominal VCC at which the ΔVio is computed (36 V for the TSB712A).
Ea is the activation energy of the technology (here 0.7 eV).

5.6 EMI rejection

The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many op-amps is a change in the offset voltage as a result of RF
signal rectification. EMIRR is defined as follows:

Vin pp
EMIRR = 20.log ΔVio (9)

The TSB711, TSB711A, TSB712, TSB712A have been specially designed to minimize susceptibility to EMIRR
and shows a low sensitivity. As visible on figure below, EMI rejection ratio has been measured on both inputs and
outputs, from 400 MHz to 2.4 GHz.

Figure 43. EMIRR on In+, In- and out pins

EMIRR performance might be improved by adding small capacitances (in the pF range) on the inputs, power
supply and output pins. These capacitances help in minimizing the impedance of these nodes at high frequencies.

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 TSB711, TSB711A, TSB712, TSB712A
Maximum power dissipation

5.7 Maximum power dissipation

The usable output load current drive is limited by the maximum power dissipation allowed by the device package.
The absolute maximum junction temperature for the TSB711, TSB711A, TSB712, TSB712A is 150 °C. The
junction temperature can be estimated as follows:

T J = PD × Rtℎ − ja + TA (10)
TJ is the die junction temperature
PD is the power dissipated in the package
Rth-ja is the junction to ambient thermal resistance of the package
TA is the ambient temperature
The power dissipated in the package PD is the sum of the quiescent power dissipated and the power dissipated
by the output stage transistor. It is calculated as follows:

PD = VCC × ICC + VCC + − VOUT × ILoad (11)

when the op-amp sources the current

PD = VCC × ICC + VOUT − VCC− × ILoad (12)

when the op-amp is sinks the current.

Do not exceed the 150 °C maximum junction temperature for the device. Exceeding the junction temperature limit
can cause degradation in the parametric performance or even destroy the device.

5.8 Capacitive load and stability

Stability analysis must be performed for large capacitive loads over 100 pF. Increasing the load capacitance to
high values produces gain peaking in the frequency response, with overshoot and ringing in the step response.
Generally, unity gain configuration is the worst situation for stability and the ability to drive large capacitive loads.
For additional capacitive load drive capability in unity-gain configuration, stability can be improved by inserting a
small resistor RISO (10 Ω to 30 Ω) in series with the output. This resistor significantly reduces ringing while
maintaining DC performance for purely capacitive loads. However, if there is a resistive load in parallel with the
capacitive load, a voltage divider is created introducing a gain error on the output and slightly reducing the output
swing. The error introduced is proportional to the ratio RISO / RL. RISO modifies the maximum capacitive load
acceptable from a stability point-of-view as described in the following figure:

Figure 44. Stability criteria with a serial resistor at different capacitive loads

Unstable

DS12487 - Rev 7 page 19/32

 TSB711, TSB711A, TSB712, TSB712A
Capacitive load and stability

Figure 45. Test configuration for RISO

Please note that RISO = 30 Ω is sufficient to make the TSB711, TSB711A, TSB712, TSB712A stable whatever the
capacitive load.

DS12487 - Rev 7 page 20/32

 TSB711, TSB711A, TSB712, TSB712A
PCB layout recommendations

5.9 PCB layout recommendations

Particular attention must be paid to the layout of the PCB tracks connected to the amplifier, load, and power
supply. The power and ground traces are critical as they must provide adequate energy and grounding for all
circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic
inductance. In addition, to minimize parasitic impedance over the entire surface, a multi-via technique that
connects the bottom and top layer ground planes together in many locations is often used. The copper traces
connecting the output pins to the load and supply pins should be as wide as possible to minimize trace resistance.

5.10 Decoupling capacitor

In order to ensure op-amp full functionality, it is mandatory to place a decoupling capacitor of at least 22 nF as
close as possible to the op-amp supply pin. A good decoupling helps to reduce electromagnetic interference
impact.

DS12487 - Rev 7 page 21/32

 TSB711, TSB711A, TSB712, TSB712A
Typical applications

6 Typical applications

6.1 Low-side current sensing

Power management mechanisms are found in most electronic systems. Current sensing is useful to protect
applications. The low-side current sensing method consists of placing a sense resistor between the load and the
circuit ground. The resulting voltage drop is amplified using the TSB711A and the TSB712A (see the following
figure).

Figure 46. Low-side current sensing schematic

C1

Rg1 Rf1

I 5V
In
Rshunt - +
Vout
+ -
Ip TSB711A
Rg2
TSB712A

Rf2

Vout can be expressed as follows:

Rg2 Rf1 Rg2.Rf2 Rf1

VOUT = Rsℎunt.I 1 − Rg2 + Rf2 . 1− Rg1 + Ip. Rg2 + Rf2 . 1+ Rg1 − In.Rf1 (13)
Rf1
− Vio. 1 − Rg1

Assuming that Rf2 = Rf1 = Rf and Rg2 = Rg1 = Rg, can be simplified in the following manner:

Rf Rf
VOUT = Rsℎunt.I . Rg − Vio. 1 + Rg + Rf.Iio (14)

The main advantage of using the TSB711A and the TSB712A for a low-side current sensing relies on its low Vio,
compared to general purpose operational amplifiers. For the same current and targeted accuracy, the shunt
resistor can be chosen with a lower value, resulting in lower power dissipation, lower drop in the ground path, and
lower cost. Particular attention must be paid to the matching and precision of Rg1, Rg2, Rf1, and Rf2, to maximize
the accuracy of the measurement.

DS12487 - Rev 7 page 22/32

 TSB711, TSB711A, TSB712, TSB712A
Package information

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

DS12487 - Rev 7 page 23/32

 TSB711, TSB711A, TSB712, TSB712A
SOT23-5 package information

7.1 SOT23-5 package information

Figure 47. SOT23-5 package outline

Table 7. SOT23-5 mechanical data

Dimensions

Ref. Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 0.90 1.20 1.45 0.035 0.047 0.057

A1 0.15 0.006
A2 0.90 1.05 1.30 0.035 0.041 0.051
B 0.35 0.40 0.50 0.014 0.016 0.020
C 0.09 0.15 0.20 0.004 0.006 0.008
D 2.80 2.90 3.00 0.110 0.114 0.118
D1 1.90 0.075
e 0.95 0.037
E 2.60 2.80 3.00 0.102 0.110 0.118
F 1.50 1.60 1.75 0.059 0.063 0.069
L 0.10 0.35 0.60 0.004 0.014 0.024
K 0 degrees 10 degrees 0 degrees 10 degrees

DS12487 - Rev 7 page 24/32

 TSB711, TSB711A, TSB712, TSB712A
MiniSO8 package information

7.2 MiniSO8 package information

Figure 48. MiniSO8 package outline

Table 8. MiniSO8 package mechanical data

mm Inches
Dim
Min. Typ. Max. Min. Typ. Max.

A 1.1 0.043
A1 0 0.15 0 0.006
A2 0.75 0.85 0.95 0.03 0.033 0.037
b 0.22 0.4 0.009 0.016
c 0.08 0.23 0.003 0.009
D 2.8 3 3.2 0.11 0.118 0.126
E 4.65 4.9 5.15 0.183 0.193 0.203
E1 2.8 3 3.1 0.11 0.118 0.122
e 0.65 0.026
L 0.4 0.6 0.8 0.016 0.024 0.031
L1 0.95 0.037
L2 0.25 0.01
k 0° 8° 0° 8°
ccc 0.1 0.004

DS12487 - Rev 7 page 25/32

 TSB711, TSB711A, TSB712, TSB712A
SO8 package information

7.3 SO8 package information

Figure 49. SO8 package outline

Table 9. SO8 mechanical data

mm Inches
Dim.
Min. Typ. Max. Min. Typ. Max.

A 1.75 0.069
A1 0.1 0.25 0.004 0.01
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.01
D 4.8 4.9 5 0.189 0.193 0.197
E 5.8 6 6.2 0.228 0.236 0.244
E1 3.8 3.9 4 0.15 0.154 0.157
e 1.27 0.05
h 0.25 0.5 0.01 0.02
L 0.4 1.27 0.016 0.05
L1 1.04 0.04
k 0 8° 1° 8°
ccc 0.1 0.004

DS12487 - Rev 7 page 26/32

 TSB711, TSB711A, TSB712, TSB712A
Ordering information

8 Ordering information

Table 10. Order code

Order code Temperature range Package Packing Marking

TSB711AILT SOT23-5 K223

-40° to +125 °C
TSB711ILT SOT23-5 K219
TSB711AIYLT SOT23-5 K225
-40 °C to +125 °C automotive grade (1)
TSB711IYLT SOT23-5 K221
TSB712AIST MiniSO8 K214
TSB712AIDT SO8 TSB712AI
-40° to +125 °C Tape and reel
TSB712IDT SO8 TSB712I
TSB712IST MiniSO8 712S
TSB712AIYDT SO8 712AIY
TSB712AIYST MiniSO8 712Y
-40 to 125 °C automotive grade (1)
TSB712IYDT SO8 712IY
TSB712IYST MiniSO8 K215

1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001
and Q002 or equivalent.

DS12487 - Rev 7 page 27/32

 TSB711, TSB711A, TSB712, TSB712A

Revision history
Table 11. Document revision history

Date Revision Changes

23-Apr-2018 1 Initial release.

Added the TSB712 as root part number; cover page has been updated accordingly.
Updated Section 3 Electrical characteristics, Section 4 Typical performance characteristics,
17-Sep-2018 2
Section 5 Application information and Table 7. Order code.
Added Section 7.2 SO8 package information.
Updated Table 3. Electrical characteristics at VCC = 36 V, VICM = VOUT = VCC / 2, Tamb =
25 °C and RL connected to VCC / 2 (unless otherwise specified) and Table 4. Electrical
29-Nov-2018 3
characteristics at VCC = 5 V, VICM = VOUT = VCC / 2, Tamb = 25 °C and RL connected to
VCC / 2 (unless otherwise specified).
18-Feb-2019 4 Updated Figure 44. Stability criteria with a serial resistor at different capacitive loads.
Added the root part numbers TSB711 and TSB711A, therefore the whole document has
11-Jun-2019 5
been updated accordingly.
Added new part numbers in Table 13. Order code, new Section 7.4 SO14 package
28-Oct-2020 6
information and Section 7.5 TSSOP14 package information.
Updated figure on the cover page and Table 10. Order code.
19-Oct-2023 7
Removed TSSOP14 and SO14 package and package informations.

DS12487 - Rev 7 page 28/32

 TSB711, TSB711A, TSB712, TSB712A
Contents

Contents
1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.1 Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 Input pin voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Rail-to-rail input stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 Input offset voltage drift over the temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5 Long term input offset voltage drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.6 EMI rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7 Maximum power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.8 Capacitive load and stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.9 PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.10 Decoupling capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6.1 Low-side current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7.1 SOT23-5 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2 MiniSO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.3 SO8 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

DS12487 - Rev 7 page 29/32

 TSB711, TSB711A, TSB712, TSB712A
List of tables

List of tables
Table 1. TSB711 pin description (SOT23-5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. TSB712 pin description (miniSO8/SO8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 4. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 5. Electrical characteristics at VCC = 36 V, VICM = VOUT = VCC / 2, Tamb = 25 °C and RL connected to VCC / 2 (unless
otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 6. Electrical characteristics at VCC = 5 V, VICM = VOUT = VCC / 2, Tamb = 25 °C and RL connected to VCC / 2 (unless
otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 7. SOT23-5 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. MiniSO8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 9. SO8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10. Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

DS12487 - Rev 7 page 30/32

 TSB711, TSB711A, TSB712, TSB712A
List of figures

List of figures
Figure 1. TSB711 pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. TSB712 pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 3. Supply current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Input offset voltage distribution at VCC = 5 V TSB711A, TSB712A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Input offset voltage distribution at VCC = 36 V TSB711A, TSB712A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Input offset voltage vs. temperature at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Input offset voltage vs. temperature at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Input offset voltage thermal coefficient distribution at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9. Channel separation vs. frequency at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10. Input offset voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 11. Input offset voltage vs. common mode voltage at VCC = 5 V TSB711A, TSB712A . . . . . . . . . . . . . . . . . . . . . . 9
Figure 12. Input offset voltage vs. common mode voltage at VCC = 36 V TSB711A, TSB712A . . . . . . . . . . . . . . . . . . . . . 9
Figure 13. Input bias current vs. temperature at VICM = VCC / 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 14. Output current vs. output voltage at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 15. Input bias current vs. common mode voltage at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 16. Input bias current vs. common mode voltage at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 17. Output current vs. output voltage at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 18. Output voltage (VOH) vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 19. Output voltage (VOL) vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 20. Positive slew rate at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 21. Negative slew rate at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 22. Bode diagram at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 23. Bode diagram at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 24. Phase margin vs. output current at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 25. Phase margin vs. output current at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 26. Phase margin vs. capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 27. Overshoot vs. capacitive load at VCC = 36 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 28. Small step response vs. time at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 29. Desaturation time at low rail at VCC = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 30. Desaturation time at high rail at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 31. Small step response vs. time at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 32. Amplifier behavior close to the low rail at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 33. Amplifier behavior close to the high rail at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 34. Noise vs. frequency at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 35. Noise vs. frequency at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 36. Noise vs. time at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 37. THD+N vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 38. THD+N vs. output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 39. PSRR vs. frequency at VCC = 10 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 40. CMRR vs. frequency at VCC = 10 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 41. Input current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 42. Rail-to-rail input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 43. EMIRR on In+, In- and out pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 44. Stability criteria with a serial resistor at different capacitive loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 45. Test configuration for RISO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 46. Low-side current sensing schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 47. SOT23-5 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 48. MiniSO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 49. SO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

DS12487 - Rev 7 page 31/32

 TSB711, TSB711A, TSB712, TSB712A

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DS12487 - Rev 7 page 32/32