CHAPTER 3 (2) Comp Science Igcse
CHAPTER 3 (2) Comp Science Igcse
CHAPTER 3 (2) Comp Science Igcse
Before 1943 computers like the one above did not store their programs in memory,
instead a series of switches had to be manually turned, or read from a paper
stream. These instructions would then be read one at a time. If you required the
computer to do something else you would then have to manually turn all pf the
switches into another combination.
This situation was far from ideal, time consuming and prone to mistakes.
In 1943 a mathematician named Von Neuman came up with the idea of storing these
program instructions and the data used into the same memory.
This is the basis of the Von Neuman concept - That program instructions and data
can be stored on the same memory.
The process that was designed is known as the FETCH - EXECUTE - CYCLE
These three operations are constantly repeated by the CPU as the computer is
running this allows the CPU to quickly and efficiently work through new instructions
as they are required.
Decode
Once the CPU has fetched the
instructions and data it will
then translate them into
instructions understandable by
the CPU
Execute
The CPU will then execute
the instructions in a logical
sequence
The CPU is commonly referred to as the brain of the computer and this is a fair
comparison. THE CPU is responsible for all processing and calculations within a
computer.
The above diagram should illustrate the fact that the CPU sits firmly at the center of
a computer connecting and managing all components as they interact with each
other.
• Control Unit
• Program Counter
Addition
The CIR contains the instruction currently being executed, Subtraction
the PC contains the address if the next instruction. Multiplication
Division
The CU will fetch an instruction from main memory Logical Comparisons e.g. Is A =
(address found in the PC)and then pass it on to the other B, Is 3 > 5
CPU parts to execute it effectively.
REGISTER SUMMARY
PC (Program counter)
Contains the address of the next instruction to be fetched
ACC (Accumulator)
Contains the results of any calculations performed in the ALU
Coming Together
As you can see there are a lot of different parts within the CPU, all of which have to
operate under the Fetch - Decode - Execute Cycle concept. Luckily a system has
been developed where by all parts work in perfect harmony to maintain the
cycle. Follow the diagram below to fully understand the process in more detail.
Buses
Within the computer system and within the CPU itself there are many different
components that have to work together. In order to communicate with each other
there needs to be some sort of connection between them that will allow for data
transmission.
This connection comes in the form of buses. A bus is a set of parallel wires that
connect two more components within a computer system.
The bus can be broken down into three different wires, these are:
Address bus - This carries signals that relate to addresses between the processor
and memory. It is Uni-directional which means that data will only travel in one
direction.
Control bus - This carries signals that relate to control e.g. an instruction to read
data. This can be uni-directional or Bi-directional.
Data Bus - This will carry actual data between components and devices. It is bi-
directional which means data can travel in both directions.
CPU CORES
In the CPU a core is essentially a processor unit that is capable of fetching, decoding and
executing instructions independently. In the past, CPUs would only contain one core,
however, in recent years CPU manufacturers have managed to create CPUs containing
between 2 and 32 cores.
What this means is that the modern CPU will contain between 2 and 32 processors... but why
would we want this?
Having multiple cores in a CPU makes it capable of completing multiple tasks at the same
time (Multitasking). This drastically increases the performance of the CPU as more tasks can
be complete in less time.
Each CPU core contains its own ALU, Control Unit and Registers thus allowing it to work on
tasks independently.
Well each time you add a new core to the CPU it increases the channels of communication
and the amount of coordination that needs to take place between them.
CLOCK SPEED
As you can see above, the CPU pictured has 8 - 16 cores. This detail is closely followed by a
"Clock speed" of 3.80 GHZ.
The CPU will process a large amount of low level instructions every second. The clock
speed, (generally) referred to as GHz (gigahertz) measures how many cycles your CPU can
execute per second.
The actual unit used to describe a processors speed will of course depend on how many
instruction cycles it can carry out per second. The units used are detailed in the table below:
This means that the core clock speed in our pictured CPU allows for 3.8 billion cycles per
second.
In General you can assume that the higher the clock speed the faster the performance of
the CPU will be.
CPU CACHE
Modern CPUs are fast, so fast in fact that their processing speeds can often out pace the speed
of RAM. This causes the CPU to slow down as it deals with the speed bottle neck.
To try and combat this a small but extremely fast piece of memory is built into the CPU
called the cache.
Cache Levels
There are three levels of cache within a CPU, each with differing speed size and
responsibility. The three levels are referred to as L1, L2 and L3 Cache.
L1 Cache - This is the fastest of all three caches and it stores the data that the CPU is most
likely to use whilst completing current tasks. It is very fast but also very small in size.
Typical L! caches will be between 2 and 64 KiB.
L2 Cache - This is slightly slower than the L1 cache but it does have a larger storage
capacity. L2 cache size can vary between 256KiB and 8MiB. Although the L2 cache is
slower than the L1 cache it is still approximately 25 times faster than RAM.
All cores in a CPU will have access to their own individual L1 and L2 caches. This is
illustrated in the diagram above.
L3 Cache - This cache is slower than the L1 and L2 caches, however it is still much faster
than RAM. L3 caches are shared between all CPU cores as illustrated in the above diagram.
The storage capacity of L3 cache is far superior to that of L1 and L2. Most decent CPUs
these days will offer L3 cache with a capacity of between 32 and 64 MiB.
Typically each core within a CPU will have its own cache to store data that it will process.
The larger the CPU cache the better it can perform as more data can be quickly
accessed from the ultrafast memory.
INSTRUCTION SETS
In a CPU, the instruction set refers to the different types of operations that a CPU is
capable of performing.
When we talk about instruction sets we are referring to the low level machine code
instructions that a CPU is built to handle.
Low level operations are split into an opcode and an operand.
Opcode - Represents the machine instruction i.e. what it has to do - ADD, LOAD,
STORE or SUBTRACT
Operand - This is either the value to be operated on OR the address that holds the
value to be operated on.
Each CPU only has a limited number of opcodes available to them and the available
opcodes is what is referred to as the instruction set.
Interesting Point
The available operations are hard coded into each CPU and the consist of electronic
circuitry and transistors. Different instructions will allow the CPU to enable / switch
on relevant transistors to perform the required tasks.
INSTRUCTIONS
ach CPU has a limited number of instructions that it is capable of performing. As
the instructions are hard coded with transistors it is obviously not possible to add
more with a software update. Some example instructions include:
Operation Purpose
ADD Add two numbers
IN Allow input from a device
SUB Subtract one number from another
DIV Divide one number by another
STORE Store a value in a given location
MUL Multiply 2 numbers
HALT Stop operations