03 Building Custom Socs

Generating and Simulating
SoCs in
Jerry Zhao
[email protected]
1
UC Berkeley
Tutorial Outline
1. Generate RTL for a simple SoC
2. Compile simple RISC-V baremetal software
3. Simulate Simple SoC running bare-metal software
4. Generate RTL for a large complex SoC
5. Simulate Complex SoC running bare-metal software
2
Chipyard Directory Structure
chipyard-morning/
generators/ Our library of Chisel generators
chipyard/
sha3/
sims/ Utilities for simulating SoCs
verilator/
firesim/
fpga/ Utilities for FPGA prototyping
software/ Utilities for building RISC-V software
vlsi/ HAMMER VLSI Flow

toolchains/ RISC-V Toolchain
3
> ls $MCYDIR
4
> tmux new –s buildrtl
> tmux a -t buildrtl
5
> cd $MCYDIR/generators/chipyard
> cd src/main/scala/config
> vim TutorialConfigs.scala
6
Designing a SoC Config
• Look for TutorialLeanGemminiConfig (line 121)
• A Config is composed of Config “fragments”
• “fragments” set/override/adjust/clear keys in the Config
object
• Generators query this “Config” object at runtime to figure
out what to do
• Try it yourself –
• Set use_dedicated_tl_port=false
• Change the number of BOOM/Rocket cores
• Change the number of L2 banks (try 1/2/4)
7
Config Fragments In Depth
This fragment changes the BankedL2Key to set its

nBanks field to the desired number of banks.
8
Config Fragments In Depth
This fragment changes the

BuildRoCC key to return a function
that generates a Gemmini instance
9
> cd $MCYDIR/sims/xcelium
> make CONFIG=TutorialLeanGemminiConfig
...
> ls generated-src
> cd generated-src/ … LeanGemminiConfig/
> ls
10
Looking at what is generated
• <CONFIG>.dts
• Device tree string - describes to
software what’s on the SoC
• <CONFIG>.fir
• FIRRTL intermediate
representation
• gen-collateral/
• Directory containing output
verilog files, harness files, etc.
11
> cd gen-collateral/
> ls *.cc
> ls *.sv
> less ChipTop.sv
> less TestHarness.sv
12
ChipTop and TestHarness
ChipTop.sv TestHarness.sv
• Contains definition of the • Contains definition of the
ChipTop TestHarness
• ChipTop defines a single die • TestHarness instantiates a
and its top-level IO ChipTop
• This would get passed to VLSI • Also instantiates simulation
tools as the target module models of I/O devices
• This is the DUT for FireSim as • Ex: model of off-chip DRAM
well
13
Compiling Software
Three common approaches
• bare-metal
• No virtual memory
• No system calls
• Fast … minimal overhead before your main starts
• proxy-kernel
• Compile RISC-V application as you would for Linux
• PK “proxies” syscalls to the x86 host
• Virtual memory
• Slow, and only supports a subset of OS capabilities
• linux
• User binary run as a normal program under OS
14 • Run on FPGA prototypes or FireSim
> cd $MCYDIR/tests
> make
> spike hello.riscv
> spike mt-hello.riscv
> spike –p4 mt-hello.riscv
15
RoCC Software
• RoCC instructions are typically inserted as inline-
assembly in a C program
• For Gemmini, the gemmini.h header encapsulates all
the inline-assembly, and presents a simple C interface to
higher-level software
• Spike ISA simulator extensions can add functional
models for new RoCC instructions to spike
16
RoCC Accelerators
• Send necessary information to the accelerator
• Source(s), Destination, and what function to run
• Accelerator accesses memory, performs SHA3
cmd.valid
cmd.ready
cmd.bits.inst.funct[1:0]
cmd.bits.rs1[63:0]
BOOM/Rocket Gemmini Ctrl
cmd.bits.rs2[63:0]
cmd.bits.inst.rd[4:0]
busy
opcode rd rs1 rs2 funct

asm volatile ("custom2 x0, %[msg_addr], %[hash_addr], 0"
:: [msg_addr] "r" (&input), [hash_addr] "r" (&output));
17
> cd $MCYDIR/tests
> spike mt-gemmini.riscv
> spike –-extension=gemmini mt-gemmini.riscv
> spike --extension=gemmini –p4 mt-gemmini.riscv
18
Running tests on RTL simulators
• Chipyard uses make targets to invoke RTL simulators
• run-binary - Runs a binary
• run-binary-debug - Runs a binary with waveforms
• run-binary-hex - Runs a binary with fast loadmem
• run-binary-hex-debug - Runs a binary with fast loadmem + waves
• Make variables specify simulation options
• CONFIG - What config to build
• BINARY - Run this binary
• timeout_cycles - Terminate simulation after this many cycles
19
> make CONFIG=TutorialLeanGemminiConfig \
BINARY=$MCYDIR/tests/hello.riscv \
run-binary-hex

BINARY=$MCYDIR/tests/mt-hello.riscv \
run-binary-hex

BINARY=$MCYDIR/tests/mt-gemmini.riscv \
run-binary-hex
20
Building Giant SoCs
New in Chipyard 1.9.0 - improved support for
very large designs
• CIRCT - up to 20x faster FIRRTL compilation
• CloneTiles - instantiate a Tile once, then stamp
out many copies
• Constellation - scalable network-on-chip
interconnect generator
21
> cd $MCYDIR/generators/chipyard
> cd src/main/scala/config
> vim TutorialConfigs.scala
22
TutorialManyCoreNoCConfig
• 6 x 4 mesh NoC
Sonic DRAM DRAM DRAM DRAM Sonic
BOOM Channel Channel Channel Channel BOOM • 4 x Rocket + Gemmini
Accelerator Tiles
• 16 x Rocket Cores
Rocket Rocket Rocket Rocket • 8 x 10-wide SonicBoom
Sonic Rocket Rocket Rocket Rocket Sonic Tiles
BOOM BOOM
L2 Bank L2 Bank L2 Bank L2 Bank • 8 x Banks of L2 cache
Rocket Rocket Rocket Rocket • Total 28 coherent cores

Sonic Rocket Rocket Rocket Rocket Sonic
BOOM BOOM
L2 Bank L2 Bank L2 Bank L2 Bank
Rocket Rocket Rocket Rocket

Sonic Sonic
BOOM Gemmini Gemmini Gemmini Gemmini BOOM
23
> make CONFIG=TutorialManyCoreNoCConfig
> make CONFIG=TutorialManyCoreNoCConfig \

run-binary-hex \
BINARY=../../tests/mt-hello.riscv
24
Configuring the NoC Topology
Request that
the System Bus
(SBus) should
be a NoC
25
Map agents
onto physical
on the NoC
26
Specify topology/routing
of NoC
27
> make CONFIG=TutorialManyCoreNoCConfig
> make CONFIG=TutorialManyCoreNoCConfig \

run-binary-hex \
BINARY=../../tests/mt-hello.riscv
28
Lots more to try in Chipyard as well
• Chipyard reduces the complexity of SoC design-space-
exploration
• Try different core/accelerator/memory-system/configurations
• New in Chipyard 1.9.0: Config discovery
• Lists most of the available Config options across all Chipyard
packages
• make find-config-fragments
29
> make find-config-fragments
30

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Generating and Simulating

software/ Utilities for building RISC-V software

vlsi/ HAMMER VLSI Flow

> tmux a -t buildrtl

This fragment changes the BankedL2Key to set its

This fragment changes the

opcode rd rs1 rs2 funct

> make CONFIG=TutorialLeanGemminiConfig \

> make CONFIG=TutorialLeanGemminiConfig \

Rocket Rocket Rocket Rocket • Total 28 coherent cores

Rocket Rocket Rocket Rocket

> make CONFIG=TutorialManyCoreNoCConfig \

> make CONFIG=TutorialManyCoreNoCConfig \

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