Atmel 8051 Microcontroller Family - Product Selection Guide

Device 89C1051 89C1051U 89C2051 89C4051 89C51 89C52 89C55 89S8252 89S53 Max speed depends on Vcc voltage. Frequencies and Currents listed are for
Vcc= 5.0V & T=25c
ON-CHIP MEMORY
Flash (Bytes) 1K 1K 2K 4K 4K 8K 20K 8K 12K **Low voltage operation = 2.7-6.0V Operation
EEPROM (Bytes) 0 0 0 0 0 0 0 2K 0
Key
SRAM (Bytes) 64 64 128 128 128 256 256 256 256
SRAM - Static RAM
In-System Programmable (ISP) NO NO NO NO NO NO NO YES YES
ISP - In-System Programmable
HARDWARE FEATURES
I/O Pins 15 15 3 5 32 32 20 20 32 I/O - Input/Output

Enhanced LED I/O Drivers YES YES YES YES NO NO NO NO NO ADC - Analogue to Digital Convertor
SPI Port NO NO NO NO NO NO NO YES YES SPI - Serial Peripheral Interface
Full Duplex Serial UART NO YES YES YES YES YES YES YES YES PWM - Pulse Width Modulation
Watchdog Timer NO NO NO NO NO NO NO YES YES PAR - Parallel programming mode
Timer/Counters 1 2 2 2 2 3 3 3 3 FLASH - Reprogrammable Code Memory
Analogue Comparator 1 1 1 1 1 NO NO NO NO EEPROM - Parallel programming mode
IDLE and Power Down modes YES YES YES YES YES YES YES YES YES
Dual Data Pointer NO NO NO NO NO NO NO YES YES
Interrupt sources 3 6 6 6 6 8 8 9 9
MISCELLANEOUS
On-chip RC Oscillator NO NO NO NO NO NO NO NO NO
Max External Clock Frequency 24MHz 24MHz 24MHz 24MHz 24MHz 24MHz 24MHz 24MHz 24MHz
VCC Voltage Range (V) 2.7-6.0 2.7-6.0 2.7-6.0 2.7-6.0 4.0-6.0 4.0-6.0 4.0-6.0 4.0-6.0 4.0-6.0
Brown-out protection NO NO NO YES NO NO NO NO NO
EQUINOX SUPPORT TOOLS Farnell Order Code Equinox Order Code
Micro-ISP Series III Programmer NO NO NO NO NO NO NO ISP only ISP onlyNO 111-776 EQ-8051-ST1 (UK)
Micro-ISP Series IV Programmer NO NO NO NO NO NO NO ISP only ISP only 302-2365 AVR-DV1 (UK)
Micro-ISP Series IV LV Programmer NO NO NO NO NO NO NO ISP only ISP only 302-2298 UISP-S4
Micro-Pro Device Programmer PAR PAR PAR PAR PAR PAR PAR PAR PAR 111-715 UISP-LV4
8051 Starter System PAR PAR PAR PAR NO NO NO ISP/PAR ISP/PAR 111-806 MPW-PLUS (UK)
Equinox Guide to C & the 8051 - - - - - - - - - 302-2328 BK-C51-1
EQ-89S-ST1 NO NO NO NO NO NO NO ISP only ISP only 302-2237 EQ-89S-ST1
PK51-2K YES YES YES NO NO NO NO NO NO 121-058 PK51-2K
PK51-8K-UPG YES YES YES YES YES YES NO YES NO 302-2262 PK51-8K-UPG
AllWriter Universal Programmer NO NO NO NO YES YES YES YES NO 302-2225 SG-ALLWRITER

For further information please contact Equinox Technologies UK Ltd on Tel: +44 (0) 1204 529000 Fax: +44 (0) 1204 535555 E-mail: [email protected]
Disclaimer: Whilst information is supplied in good faith, we are not liable for any errors or omissions. Please consult the relevant Atmel datasheet. E&OE
 Atmel 8051 Microcontroller Family - Product Selection Guide
Continued....
Device 89C1051 89C1051U 89C2051 89C4051 89C51 89C52 89C55 89S8252 89S53 Farnell Order Code Equinox Order Code
EQUINOX SUPPORT TOOLS
SS-89S-DIL40 NO NO NO NO NO NO NO Fitted NO 795-252 EQ-8051-ST1 (UK)
SS-89S-PLCC44 NO NO NO NO NO NO NO Fitted NO 795-264 AVR-DV1 (UK)
SS-89S-20P NO NO NO NO NO NO NO Fitted NO 120-996 UISP-S4
AD-PLCC44-A NO NO NO NO YES YES YES YES YES 701-040 AD-PLCC44-A
AD-SOIC20-A YES YES YES YES NO NO NO NO NO 701-051 AD-SOIC20-A
PACKAGE TYPES (Farnell Codes)
20P3 (24PC) 701-063 123-893 701-087 120-911 - - - - -
20S (24SC) 701-075 120-900 - 120-923 - - - - -
40P6 (24PC) - - - - 700-988 701-014 302-2341 795-392 120-935
44J (24JC) - - - - 795-355 795-367 302-2353 795-409 120-947
44A (24JC) - - - - - - - - -

For further information please contact Equinox Technologies UK Ltd on Tel: +44 (0) 1204 529000 Fax: +44 (0) 1204 535555 E-mail: [email protected]
Disclaimer: Whilst information is supplied in good faith, we are not liable for any errors or omissions. Please consult the relevant Atmel datasheet. E&OE
 AT89C55

Features
• Compatible with MCS-51™ Products
• 20K Bytes of In-System Reprogrammable Flash Memory
– Endurance: 1,000 Write/Erase Cycles
• Fully Static Operation: 0 Hz to 33 MHz
• Three-Level Program Memory Lock
• 256 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Three 16-bit Timer/Counters
• Eight Interrupt Sources
• Low Power Idle and Power Down Modes 8-Bit
Description Microcontroller
The AT89C55 is a low-power, high-performance CMOS 8-bit microcomputer with 20K
bytes of Flash programmable and erasable read only memory. The device is manu- with 20K Bytes
factured using Atmel’s high density nonvolatile memory technology and is compatible
with the industry standard 80C51 instruction set and pinout. The on-chip Flash allows Flash
the program memory to be reprogrammed in-system or by a conventional nonvolatile
memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic
chip, the Atmel AT89C55 is a powerful microcomputer which provides a highly flexible
and cost effective solution to many embedded control applications.
AT89C55
(continued)

Pin Configurations PDIP

PQFP/TQFP PLCC

0580D-A–12/97

4-169
Block Diagram

P0.0 - P0.7 P2.0 - P2.7

VCC
PORT 0 DRIVERS PORT 2 DRIVERS

GND

RAM ADDR. RAM PORT 0 PORT 2

REGISTER LATCH FLASH
LATCH

PROGRAM
B STACK
ACC ADDRESS
REGISTER POINTER
REGISTER

BUFFER
TMP2 TMP1

PC
ALU INCREMENTER

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

PROGRAM
PSW COUNTER

PSEN
ALE/PROG TIMING INSTRUCTION
AND DPTR
EA / VPP REGISTER
CONTROL
RST

PORT 1 PORT 3
LATCH LATCH

OSC
PORT 1 DRIVERS PORT 3 DRIVERS

P1.0 - P1.7 P3.0 - P3.7

4-170 AT89C55
 AT89C55

The AT89C55 provides the following standard features: Port 2

20K bytes of Flash, 256-bytes of RAM, 32 I/O lines, three Port 2 is an 8-bit bidirectional I/O port with internal pullups.
16-bit timer/counters, a six-vector two-level interrupt archi- The Port 2 output buffers can sink/source four TTL inputs.
tecture, a full duplex serial port, on-chip oscillator, and When 1s are written to Port 2 pins, they are pulled high by
clock circuitry. In addition, the AT89C55 is designed with the internal pullups and can be used as inputs. As inputs,
static logic for operation down to zero frequency and sup- Port 2 pins that are externally being pulled low will source
ports two software selectable power saving modes. The current (IIL) because of the internal pullups.
Idle Mode stops the CPU while allowing the RAM, Port 2 emits the high-order address byte during fetches
timer/counters, serial port, and interrupt system to continue from external program memory and during accesses to
functioning. The Power Down Mode saves the RAM con- external data memory that use 16-bit addresses (MOVX @
tents but freezes the oscillator, disabling all other chip func- DPTR). In this application, Port 2 uses strong internal pul-
tions until the next hardware reset. The low-voltage option lups when emitting 1s. During accesses to external data
saves power and operates with a 2.7-volt power supply. memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.
Pin Description Port 2 also receives the high-order address bits and some
VCC control signals during Flash programming and verification.
Supply voltage. Port 3
GND Port 3 is an 8-bit bidirectional I/O port with internal pullups.
Ground. The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins, they are pulled high by
Port 0 the internal pullups and can be used as inputs. As inputs,
Port 0 is an 8-bit open drain bidirectional I/O port. As an Port 3 pins that are externally being pulled low will source
output port, each pin can sink eight TTL inputs. When 1s current (IIL) because of the pullups.
are written to port 0 pins, the pins can be used as high-
Port 3 also serves the functions of various special features
impedance inputs.
of the AT89C55, as shown in the following table.
Port 0 can also be configured to be the multiplexed low-
order address/data bus during accesses to external pro- Port Pin Alternate Functions
gram and data memory. In this mode, P0 has internal pul- P3.0 RXD (serial input port)
lups.
Port 0 also receives the code bytes during Flash program- P3.1 TXD (serial output port)
ming and outputs the code bytes during program verifica- P3.2 INT0 (external interrupt 0)
tion. External pullups are required during program verifica-
tion. P3.3 INT1 (external interrupt 1)

Port 1 P3.4 T0 (timer 0 external input)

Port 1 is an 8-bit bidirectional I/O port with internal pullups. P3.5 T1 (timer 1 external input)
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins, they are pulled high by P3.6 WR (external data memory write strobe)
the internal pullups and can be used as inputs. As inputs, P3.7 RD (external data memory read strobe)
Port 1 pins that are externally being pulled low will source
current (IIL) because of the internal pullups. Port 3 also receives the highest-order address bit and
In addition, P1.0 and P1.1 can be configured to be the some control signals for Flash programming and verifica-
timer/counter 2 external count input (P1.0/T2) and the tion.
timer/counter 2 trigger input (P1.1/T2EX), respectively, as
RST
shown in the following table.
Reset input. A high on this pin for two machine cycles while
Port Pin Alternate Functions the oscillator is running resets the device.
T2 (external count input to Timer/Counter 2),
P1.0
clock-out
T2EX (Timer/Counter 2 capture/reload
P1.1
trigger and direction control)

Port 1 also receives the low-order address bytes during

Flash programming and verification.

4-171
ALE/PROG User software should not write 1s to these unlisted loca-
Address Latch Enable is an output pulse for latching the tions, since they may be used in future products to invoke
low byte of the address during accesses to external mem- new features. In that case, the reset or inactive values of
ory. This pin is also the program pulse input (PROG) dur- the new bits will always be 0.
ing Flash programming. Timer 2 Registers Control and status bits are contained in
In normal operation, ALE is emitted at a constant rate of registers T2CON (shown in Table 2) and T2MOD (shown
1/6 the oscillator frequency and may be used for external in Table 4) for Timer 2. The register pair (RCAP2H,
timing or clocking purposes. Note, however, that one ALE RCAP2L) are the Capture/Reload registers for Timer 2 in
pulse is skipped during each access to external data mem- 16 bit capture mode or 16-bit auto-reload mode.
ory. Interrupt Registers The individual interrupt enable bits are
If desired, ALE operation can be disabled by setting bit 0 of in the IE register. Two priorities can be set for each of the
SFR location 8EH. With the bit set, ALE is active only dur- six interrupt sources in the IP register.
ing a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no Data Memory
effect if the microcontroller is in external execution mode.
The AT89C55 implements 256-bytes of on-chip RAM. The
PSEN upper 128-bytes occupy a parallel address space to the
Program Store Enable is the read strobe to external pro- Special Function Registers. That means the upper 128-
gram memory. bytes have the same addresses as the SFR space but are
When the AT89C55 is executing code from external pro- physically separate from SFR space.
gram memory, PSEN is activated twice each machine When an instruction accesses an internal location above
cycle, except that two PSEN activations are skipped during address 7FH, the address mode used in the instruction
each access to external data memory. specifies whether the CPU accesses the upper 128-bytes
EA/VPP of RAM or the SFR space. Instructions that use direct
External Access Enable. EA must be strapped to GND in addressing access SFR space.
order to enable the device to fetch code from external pro- For example, the following direct addressing instruction
gram memory locations starting at 0000H up to FFFFH. accesses the SFR at location 0A0H (which is P2).
Note, however, that if lock bit 1 is programmed, EA will be MOV 0A0H, #data
internally latched on reset.
Instructions that use indirect addressing access the upper
EA should be strapped to VCC for internal program execu- 128-bytes of RAM. For example, the following indirect
tions. addressing instruction, where R0 contains 0A0H, accesses
This pin also receives the 12-volt programming enable volt- the data byte at address 0A0H, rather than P2 (whose
age (VPP) during 12-volt Flash programming. address is 0A0H).
MOV @R0, #data
XTAL1
Input to the inverting oscillator amplifier and input to the Note that stack operations are examples of indirect
internal clock operating circuit. addressing, so the upper 128-bytes of data RAM are avail-
able as stack space.
XTAL2
Output from the inverting oscillator amplifier.

Special Function Registers

A map of the on-chip memory area called the Special
Function Register (SFR) space is shown in Table 1.
Note that not all of the addresses are occupied, and unoc-
cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi-
nate effect.

4-172 AT89C55
 AT89C55

Table 1. AT89C55 SFR Map and Reset Values

0F8H 0FFH

B
0F0H 0F7H
00000000

0E8H 0EFH

ACC
0E0H 0E7H
00000000

0D8H 0DFH

PSW
0D0H 0D7H
00000000

T2CON T2MOD RCAP2L RCAP2H TL2 TH2

0C8H 0CFH
00000000 XXXXXX00 00000000 00000000 00000000 00000000

0C0H 0C7H

IP
0B8H 0BFH
XX000000

P3
0B0H 0B7H
11111111

IE
0A8H 0AFH
0X000000

P2
0A0H 0A7H
11111111

SCON SBUF
98H 9FH
00000000 XXXXXXXX

P1
90H 97H
11111111

TCON TMOD TL0 TL1 TH0 TH1

88H 8FH
00000000 00000000 00000000 00000000 00000000 00000000

P0 SP DPL DPH PCON

80H 87H
11111111 00000111 00000000 00000000 0XXX0000

4-173
Table 2. T2CON—Timer/Counter 2 Control Register
T2CON Address = 0C8H Reset Value = 0000 0000B
Bit Addressable
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
Bit 7 6 5 4 3 2 1 0

Symbol Function
TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK
= 1 or TCLK = 1.
EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must
be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port
Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial
port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if
Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2 Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge
triggered).
CP/RL2 Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 =
0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1.
When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

4-174 AT89C55
 AT89C55

Timer 0 and 1 show a high in one cycle and a low in the next cycle, the
count is incremented. The new count value appears in the
Timer 0 and Timer 1 in the AT89C55 operate the same way
register during S3P1 of the cycle following the one in which
as Timer) and Timer 1 in the AT89C51 and AT89C52. For
the transition was detected. Since two machine cycles (24
further information, see the Microcontroller Data Book, sec-
oscillator periods) are required to recognize a 1-to-0 transi-
tion titled, “Timer/Counters.”
tion, the maximum count rate is 1/24 of the oscillator fre-
quency. To ensure that a given level is sampled at least
Timer 2 once before it changes, the level should be held for at least
Timer 2 is a 16 bit Timer/Counter that can operate as either one full machine cycle.
a timer or an event counter. The type of operation is Capture Mode
selected by bit C/T2 in the SFR T2CON (shown in Table 2).
In the capture mode, two options are selected by bit
Timer 2 has three operating modes: capture, auto-reload
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16 bit timer
(up or down counting), and baud rate generator. The
or counter which upon overflow sets bit TF2 in T2CON.
modes are selected by bits in T2CON, as shown in Table 3.
This bit can then be used to generate an interrupt. If
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the EXEN2 = 1, Timer 2 performs the same operation, but a 1-
Timer function, the TL2 register is incremented every to-0 transition at external input T2EX also causes the cur-
machine cycle. Since a machine cycle consists of 12 oscil- rent value in TH2 and TL2 to be captured into RCAP2H and
lator periods, the count rate is 1/12 of the oscillator fre- RCAP2L, respectively. In addition, the transition at T2EX
quency. causes bit EXF2 in T2CON to be set. The EXF2 bit, like
In the Counter function, the register is incremented in TF2, can generate an interrupt. The capture mode is illus-
response to a 1-to-0 transition at its corresponding external trated in Figure 1.
input pin, T2. In this function, the external input is sampled
during S5P2 of every machine cycle. When the samples
Auto-Reload (Up or Down Counter)
Timer 2 can be programmed to count up or down when
Table 3. Timer 2 Operating Modes configured in its 16-bit auto-reload mode. This feature is
invoked by the DCEN (Down Counter Enable) bit located in
RCLK + TCLK CP/RL2 TR2 MODE the SFR T2MOD (see Table 4). Upon reset, the DCEN bit
0 0 1 16 bit Auto-Reload is set to 0 so that timer 2 will default to count up. When
DCEN is set, Timer 2 can count up or down, depending on
0 1 1 16 bit Capture the value of the T2EX pin.
1 X 1 Baud Rate Generator Figure 2 shows Timer 2 automatically counting up when
X X 0 (Off) DCEN = 0. In this mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to
0FFFFH and then sets the TF2 bit upon overflow. The over-
flow also causes the timer registers to be reloaded with the
16 bit value in RCAP2H and RCAP2L. The values in
RCAP2H and RCAP2L are preset by software. If EXEN2 =
Figure 1. Timer 2 in Capture Mode

4-175
1, a 16 bit reload can be triggered either by an overflow or RCAP2H and RCAP2L to be reloaded into the timer regis-
by a 1-to-0 transition at external input T2EX. This transition ters, TH2 and TL2, respectively.
also sets the EXF2 bit. Both the TF2 and EXF2 bits can A logic 0 at T2EX makes Timer 2 count down. The timer
generate an interrupt if enabled. underflows when TH2 and TL2 equal the values stored in
Setting the DCEN bit enables Timer 2 to count up or down, RCAP2H and RCAP2L. The underflow sets the TF2 bit and
as shown in Figure 3. In this mode, the T2EX pin controls causes 0FFFFH to be reloaded into the timer registers.
the direction of the count. A logic 1 at T2EX makes Timer 2 The EXF2 bit toggles whenever Timer 2 overflows or
count up. The timer will overflow at 0FFFFH and set the underflows and can be used as a 17th bit of resolution. In
TF2 bit. This overflow also causes the 16 bit value in this operating mode, EXF2 does not flag an interrupt.

Figure 2. Timer 2 Auto Reload Mode (DCEN = 0)

Table 4. T2MOD—Timer 2 Mode Control Register

T2MOD Address = 0C9H Reset Value = XXXX XX00B
Not Bit Addressable
— — — — — — T20E DCEN

Bit 7 6 5 4 3 2 1 0

Symbol Function
— Not implemented, reserved for future use.
T20E Timer 2 Output Enable bit.
DCEN When set, this bit allows Timer 2 to be configured as an up/down counter.

4-176 AT89C55
 AT89C55

Figure 3. Timer 2 Auto Reload Mode (DCEN = 1)

(DOWN COUNTING RELOAD VALUE) TOGGLE

0FFH 0FFH
EXF2

OSC ÷12 OVERFLOW

C/T2 = 0

TH2 TL2 TF2

CONTROL
TR2
C/T2 = 1 TIMER 2
INTERRUPT
T2 PIN
RCAP2H RCAP2L
COUNT
(UP COUNTING RELOAD VALUE) DIRECTION
1=UP
0=DOWN

T2EX PIN

Figure 4. Timer 2 in Baud Rate Generator Mode

4-177
Baud Rate Generator
Timer 2 is selected as the baud rate generator by setting
TCLK and/or RCLK in T2CON (Table 2). Note that the baud Modes 1 and 3 Oscillator Frequency
--------------------------------------- = --------------------------------------------------------------------------------------------------
rates for transmit and receive can be different if Timer 2 is Baud Rate 32 × [ 655536 – ( RCAP2H,RCAP2L ) ]
used for the receiver or transmitter and Timer 1 is used for
the other function. Setting RCLK and/or TCLK puts Timer 2 where (RCAP2H, RCAP2L) is the content of RCAP2H and
into its baud rate generator mode, as shown in Figure 4. RCAP2L taken as a 16 bit unsigned integer.
The baud rate generator mode is similar to the auto-reload Timer 2 as a baud rate generator is shown in Figure 4. This
mode, in that a rollover in TH2 causes the Timer 2 registers figure is valid only if RCLK or TCLK = 1 in T2CON. Note
to be reloaded with the 16 bit value in registers RCAP2H that a rollover in TH2 does not set TF2 and will not gener-
and RCAP2L, which are preset by software. ate an interrupt. Note too, that if EXEN2 is set, a 1-to-0
The baud rates in Modes 1 and 3 are determined by Timer transition in T2EX will set EXF2 but will not cause a reload
2’s overflow rate according to the following equation. from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer
2 is in use as a baud rate generator, T2EX can be used as
Timer 2 Overflow Rate an extra external interrupt.
Modes 1 and 3 Baud Rates = ------------------------------------------------------------
16 Note that when Timer 2 is running (TR2 = 1) as a timer in
the baud rate generator mode, TH2 or TL2 should not be
The Timer can be configured for either timer or counter read from or written to. Under these conditions, the Timer is
operation. In most applications, it is configured for timer incremented every state time, and the results of a read or
operation (CP/T2 = 0). The timer operation is different for write may not be accurate. The RCAP2 registers may be
Timer 2 when it is used as a baud rate generator. Normally, read but should not be written to, because a write might
as a timer, it increments every machine cycle (at 1/12 the overlap a reload and cause write and/or reload errors. The
oscillator frequency). As a baud rate generator, however, it timer should be turned off (clear TR2) before accessing the
increments every state time (at 1/2 the oscillator fre- Timer 2 or RCAP2 registers.
quency). The baud rate formula is given below.

Figure 5. Timer 2 in Clock-Out Mode

4-178 AT89C55
 AT89C55

Programmable Clock Out

A 50% duty cycle clock can be programmed to come out on Table 5. Interrupt Enable (IE) Register
P1.0, as shown in Figure 5. This pin, besides being a regu-
(MSB) (LSB)
lar I/O pin, has two alternate functions. It can be pro-
grammed to input the external clock for Timer/Counter 2 or EA — ET2 ES ET1 EX1 ET0 EX0
to output a 50% duty cycle clock ranging from 61 Hz to 4
Enable Bit = 1 enables the interrupt.
MHz at a 16 MHz operating frequency.
To configure the Timer/Counter 2 as a clock generator, bit Enable Bit = 0 disables the interrupt.
C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1)
must be set. Bit TR2 (T2CON.2) starts and stops the timer. Symbol Position Function
The clock-out frequency depends on the oscillator fre- Disables all interrupts. If EA = 0, no
quency and the reload value of Timer 2 capture registers interrupt is acknowledged. If EA =
(RCAP2H, TCAP2L), as shown in the following equation: EA IE.7 1, each interrupt source is
individually enabled or disabled by
setting or clearing its enable bit.
Oscillator Frequency
Clock-Out Frequency = ---------------------------------------------------------------------------------------------- — IE.6 Reserved.
4 × [ 655536 – ( RCAP2H,RCAP2L) ]
ET2 IE.5 Timer 2 interrupt enable bit.
In the clock-out mode, Timer 2 roll-overs will not generate
ES IE.4 Serial Port interrupt enable bit.
an interrupt. This behavior is similar to when Timer 2 is
used as a baud-rate generator. It is possible to use Timer 2 ET1 IE.3 Timer 1 interrupt enable bit.
as a baud-rate generator and a clock generator simulta- EX1 IE.2 External interrupt 1 enable bit.
neously. Note, however, that the baud-rate and clock-out
frequencies cannot be determined independently from one ET0 IE.1 Timer 0 interrupt enable bit.
another since they both use RCAP2H and RCAP2L. EX0 IE.0 External interrupt 0 enable bit.
User software should never write 1s to unimplemented bits,
UART because they may be used in future AT89 products.
The UART in the AT89C55 operates the same way as the
UART in the AT89C51 and AT89C52. For further informa- Figure 6. Interrupt Sources
tion, see the Microcontroller Data Book, section titled,
“Serial Interface.”

Interrupts
The AT89C55 has a total of six interrupt vectors: two exter-
nal interrupts (INT0 and INT1), three timer interrupts (Tim-
ers 0, 1, and 2), and the serial port interrupt. These inter-
rupts are all shown in Figure 6.
Each of these interrupt sources can be individually enabled
or disabled by setting or clearing a bit in Special Function
Register IE. IE also contains a global disable bit, EA, which
disables all interrupts at once.
Note that Table 5 shows that bit position IE.6 is unimple-
mented. In the AT89C51 and AT89LV51, bit position IE.5 is
also unimplemented. User software should not write 1s to
these bit positions, since they may be used in future AT89
products.
Timer 2 interrupt is generated by the logical OR of bits TF2
and EXF2 in register T2CON. Neither of these flags is
cleared by hardware when the service routine is vectored
to. In fact, the service routine may have to determine
whether it was TF2 or EXF2 that generated the interrupt, The Timer 0 and Timer 1 flags, TF0 and TF1, are set at
and that bit will have to be cleared in software. S5P2 of the cycle in which the timers overflow. The values
are then polled by the circuitry in the next cycle. However,

4-179
the Timer 2 flag, TF2, is set at S2P2 and is polled in the Figure 7. Oscillator Connections
same cycle in which the timer overflows. For further infor-
mation, see the Microcontroller Data Book, section titled
“Interrupts.”

Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier that can be configured for use as
an on-chip oscillator, as shown in Figure 7. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven, as shown in Figure 8.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi-
mum voltage high and low time specifications must be Note: C1,C2 = ± 30 pF for Crystals
observed. = ± 40 pF for Ceramic Resonators

Figure 8. External Clock Drive Configuration

Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe-
cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
Note that when idle mode is terminated by a hardware
reset, the device normally resumes program execution
from where it left off, up to two machine cycles before the
internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when idle mode is termi-
nated by a reset, the instruction following the one that
invokes idle mode should not write to a port pin or to exter-
nal memory.

Status of External Pins During Idle and Power Down Modes

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power Down Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data

4-180 AT89C55
 AT89C55

Power Down Mode Program Memory Lock Bits

In the power down mode, the oscillator is stopped, and the The AT89C55 has three lock bits that can be left unpro-
instruction that invokes power down is the last instruction grammed (U) or can be programmed (P) to obtain the addi-
executed. The on-chip RAM and Special Function Regis- tional features listed in the following table.
ters retain their values until the power down mode is termi- When lock bit 1 is programmed, the logic level at the EA pin
nated. The only exit from power down is a hardware reset. is sampled and latched during reset. If the device is pow-
Reset redefines the SFRs but does not change the on-chip ered up without a reset, the latch initializes to a random
RAM. The reset should not be activated before V CC is value and holds that value until reset is activated. The
restored to its normal operating level and must be held latched value of EA must agree with the current logic level
active long enough to allow the oscillator to restart and sta- at that pin in order for the device to function properly.
bilize.

Lock Bit Protection Modes

Program Lock Bits
LB1 LB2 LB3 Protection Type
1 U U U No program lock features.
MOVC instructions executed from external program memory are disabled from fetching code bytes
2 P U U from internal memory, EA is sampled and latched on reset, and further programming of the Flash
memory is disabled.
3 P P U Same as mode 2, but verify is also disabled.
4 P P P Same as mode 3, but external execution is also disabled.

Programming the Flash The AT89C55 code memory array is programmed byte-by-
byte in either programming mode. To program any non-
The AT89C55 is normally shipped with the on-chip Flash
blank byte in the on-chip Flash Memory, the entire memory
memory array in the erased state (that is, contents = FFH)
must be erased using the Chip Erase Mode.
and ready to be programmed. The programming interface
accepts either a high-voltage (12-volt) or a low-voltage Programming Algorithm: Before programming the
(VCC) program enable signal. The low voltage programming AT89C55, the address, data and control signals should be
mode provides a convenient way to program the AT89C55 set up according to the Flash programming mode table and
inside the user’s system, while the high-voltage program- Figures 9 and 10. To program the AT89C55, take the fol-
ming mode is compatible with conventional third party lowing steps:
Flash or EPROM programmers. 1. Input the desired memory location on the address lines.
The AT89C55 is shipped with either the high-voltage or 2. Input the appropriate data byte on the data lines.
low-voltage programming mode enabled. The respective 3. Activate the correct combination of control signals.
top-side marking and device signature codes are listed in
4. Raise EA/VPP to 12V for the high-voltage programming
following table.
mode.
VPP = 12V VPP = 5V 5. Pulse ALE/PROG once to program a byte in the Flash
AT89C55 AT89C55 array or the lock bits. The byte-write cycle is self-timed
and typically takes no more than 1.5 ms. Repeat steps
Top-Side Mark xxxx xxxx-5 1 through 5, changing the address and data for the
yyww yyww entire array or until the end of the object file is reached.
(030H) = 1EH (030H) = 1EH
Signature (031H) = 55H (031H) = 55H
(032H) = FFH (032H) = 05H

4-181
Data Polling: The AT89C55 features Data Polling to indi- Reading the Signature Bytes: The signature bytes are
cate the end of a write cycle. During a write cycle, an read by the same procedure as a normal verification of
attempted read of the last byte written will result in the com- locations 030H, 031H, and 032H, except that P3.6 and
plement of the written data on PO.7. Once the write cycle P3.7 must be pulled to a logic low. The values returned are
has been completed, true data is valid on all outputs, and as follows.
the next cycle may begin. Data Polling may begin any time (030H) = 1EH indicates manufactured by Atmel
after a write cycle has been initiated. (031H) = 55H indicates 89C55
Ready/Busy: The progress of byte programming can also (032H) = FFH indicates 12V programming
be monitored by the RDY/BSY output signal. P3.4 is pulled (032H) = 05H indicates 5V programming
low after ALE goes high during programming to indicate
BUSY. P3.4 is pulled high again when programming is
done to indicate READY.
Programming Interface
Every code byte in the Flash array can be written, and the
Program Verify: If lock bits LB1 and LB2 have not been
entire array can be erased, by using the appropriate combi-
programmed, the programmed code data can be read back
nation of control signals. The write operation cycle is self-
via the address and data lines for verification. The lock bits
timed and once initiated, will automatically time itself to
cannot be verified directly. Verification of the lock bits is
completion.
achieved by observing that their features are enabled.
All major programming vendors offer worldwide support for
Chip Erase: The entire Flash array is erased electrically
the Atmel microcontroller series. Please contact your local
by using the proper combination of control signals and by
programming vendor for the appropriate software revision.
holding ALE/PROG low for 10 ms. The code array is written
with all 1s. The chip erase operation must be executed
before the code memory can be reprogrammed.

Figure 9. Programming the Flash Memory Figure 10. Verifying the Flash Memory
+5V +5V
AT89C55 AT89C55
A0 - A7 VCC A0 - A7 VCC
ADDR. P1 ADDR. P1
0000H/4FFFH PGM 0000H/4FFFH PGM DATA
P2.0 - P2.5 P0 DATA P2.0 - P2.5 P0 (USE 10K
A8 - A13 A8 - A13 PULLUPS)
A14* P3.0 A14* P3.0
P2.6 P2.6
ALE PROG ALE
SEE FLASH P2.7 SEE FLASH P2.7
PROGRAMMING PROGRAMMING
P3.6 P3.6
MODES TABLE MODES TABLE VI H
P3.7 P3.7
XTAL2 EA VI H/VPP XTAL 2 EA

3-33 MHz 3-33 MHz

XTAL 1 RST VI H XTAL 1 RST VI H

GND PSEN GND PSEN

*Programming address line A14 (P3.0) is not the same as the external
memory address line A14 (P2.6)

4-182 AT89C55
 AT89C55

Flash Programming Modes

Mode RST PSEN ALE/PROG EA/VPP P2.6 P2.7 P3.6 P3.7

Write Code Data H L H/12V L H H H

Read Code Data H L H H L L H H

Bit-1
Write Lock H L H/12V H H H H

Bit-2
H L H/12V H H L L

Bit-3
H L H/12V H L H L

Chip Erase (1)

H L H/12V H L L L

Read Signature Byte H L H H L L L L

Note: 1. Chip Erase requires a 10-ms PROG pulse.

4-183
Flash Programming and Verification Characteristics
TA = 0°C to 70°C, VCC = 5.0V ± 10%
Symbol Parameter Min Max Units
VPP(1) Programming Enable Voltage 11.5 12.5 V
IPP (1) Programming Enable Current 1.0 mA
1/tCLCL Oscillator Frequency 3 33 MHz
tAVGL Address Setup to PROG Low 48tCLCL
tGHAX Address Hold After PROG 48tCLCL
tDVGL Data Setup to PROG Low 48tCLCL
tGHDX Data Hold After PROG 48tCLCL
tEHSH P2.7 (ENABLE) High to VPP 48tCLCL
tSHGL VPP Setup to PROG Low 10 µs
tGHSL (1) VPP Hold After PROG 10 µs
tGLGH PROG Width 1 110 µs
tAVQV Address to Data Valid 48tCLCL
tELQV ENABLE Low to Data Valid 48tCLCL
tEHQZ Data Float After ENABLE 0 48tCLCL
tGHBL PROG High to BUSY Low 1.0 µs
tWC Byte Write Cycle Time 2.0 ms
Note: 1. Only used in 12-volt programming mode.

4-184 AT89C55
 AT89C55

Flash Programming and Verification Waveforms - High Voltage Mode (VPP = 12V)

Flash Programming and Verification Waveforms - Low Voltage Mode (VPP = 5V)

4-185
Absolute Maximum Ratings*
Operating Temperature ................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
Voltage on Any Pin other conditions beyond those indicated in the
with Respect to Ground .....................................-1.0V to +7.0V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Maximum Operating Voltage............................................. 6.6V conditions for extended periods may affect device
reliability.
DC Output Current...................................................... 15.0 mA

DC Characteristics
The values shown in this table are valid for TA = -40°C to 85°C and VCC = 5.0V ± 20%, unless otherwise noted.

Symbol Parameter Condition Min Max Units

VIL Input Low Voltage (Except EA) -0.5 0.2 VCC - 0.1 V

VIL1 Input Low Voltage (EA) -0.5 0.2 VCC - 0.3 V

VIH Input High Voltage (Except XTAL1, RST) 0.2 VCC + 0.9 VCC + 0.5 V

VIH1 Input High Voltage (XTAL1, RST) 0.7 VCC VCC + 0.5 V

Output Low Voltage(1)

VOL IOL = 1.6 mA 0.45 V
(Ports 1, 2, 3)

Output Low Voltage(1)

VOL1 IOL = 3.2 mA 0.45 V
(Port 0, ALE, PSEN)

IOH = -60 µA, VCC = 5V ± 10% 2.4 V

Output High Voltage
VOH IOH = -25 µA 0.75 VCC V
(Ports 1, 2, 3, ALE, PSEN)
IOH = -10 µA 0.9 VCC V

IOH = -800 µA, VCC = 5V ± 10% 2.4 V

Output High Voltage
VOH1 IOH = -300 µA 0.75 VCC V
(Port 0 in External Bus Mode)
IOH = -80 µA 0.9 VCC V

Logical 0 Input Current

IIL VIN = 0.45V -50 µA
(Ports 1, 2, 3)

ITL Logical 1 to 0 Transition Current (Ports 1, 2, 3) VIN = 2V, VCC = 5V ± 10% -650 µA

Input Leakage Current

ILI 0.45 < VIN < VCC ±10 µA
(Port 0, EA)

RRST Reset Pulldown Resistor 50 300 kΩ

CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF

Active Mode, 12 MHz 25 mA

Power Supply Current
Idle Mode, 12 MHz 6.5 mA
ICC
VCC = 6V 100 µA
Power Down Mode(2)
VCC = 3V 40 µA

Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA.
Maximum IOL per 8-bit port: Port 0: 26 mA, Ports 1, 2, 3: 15 mA. Maximum total IOL for all output pins: 71 mA. If IOL exceeds
the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
2. Minimum VCC for Power Down is 2V.

4-186 AT89C55
 AT89C55

AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF.

External Program and Data Memory Characteristics

Symbol Parameter Variable Oscillator Units
Min Max
1/tCLCL Oscillator Frequency 0 33 MHz
tLHLL ALE Pulse Width 2tCLCL - 40 ns
tAVLL Address Valid to ALE Low tCLCL - 13 ns
tLLAX Address Hold After ALE Low tCLCL - 20 ns
tLLIV ALE Low to Valid Instruction In 4tCLCL - 65 ns
tLLPL ALE Low to PSEN Low tCLCL - 13 ns
tPLPH PSEN Pulse Width 3tCLCL - 20 ns
tPLIV PSEN Low to Valid Instruction In 3tCLCL - 45 ns
tPXIX Input Instruction Hold After PSEN 0 ns
tPXIZ Input Instruction Float After PSEN tCLCL - 10 ns
tPXAV PSEN to Address Valid tCLCL - 8 ns
tAVIV Address to Valid Instruction In 5tCLCL - 55 ns
tPLAZ PSEN Low to Address Float 10 ns
tRLRH RD Pulse Width 6tCLCL - 100 ns
tWLWH WR Pulse Width 6tCLCL - 100 ns
tRLDV RD Low to Valid Data In 5tCLCL - 90 ns
tRHDX Data Hold After RD 0 ns
tRHDZ Data Float After RD 2tCLCL - 28 ns
tLLDV ALE Low to Valid Data In 8tCLCL - 150 ns
tAVDV Address to Valid Data In 9tCLCL - 165 ns
tLLWL ALE Low to RD or WR Low 3tCLCL - 50 3tCLCL + 50 ns
tAVWL Address to RD or WR Low 4tCLCL - 75 ns
tQVWX Data Valid to WR Transition tCLCL - 20 ns
tQVWH Data Valid to WR High 7tCLCL - 120 ns
tWHQX Data Hold After WR tCLCL - 20 ns
tRLAZ RD Low to Address Float 0 ns
tWHLH RD or WR High to ALE High tCLCL - 20 tCLCL + 25 ns

4-187
External Program Memory Read Cycle

External Data Memory Read Cycle

4-188 AT89C55
 AT89C55

External Data Memory Write Cycle

External Clock Drive Waveforms

External Clock Drive

Symbol Parameter Min Max Units
1/tCLCL Oscillator Frequency 0 33 MHz
tCLCL Clock Period 30 ns
tCHCX High Time 12 ns
tCLCX Low Time 12 ns
tCLCH Rise Time 20 ns
tCHCL Fall Time 20 ns

4-189
Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 5.0V ± 20% and Load Capacitance = 80 pF.
Symbol Parameter Min Max Units
tXLXL Serial Port Clock Cycle Time 12tCLCL ns
tQVXH Output Data Setup to Clock Rising Edge 10tCLCL - 133 ns
tXHQX Output Data Hold After Clock Rising Edge 2tCLCL - 117 ns
tXHDX Input Data Hold After Clock Rising Edge 0 ns
tXHDV Clock Rising Edge to Input Data Valid 10tCLCL - 133 ns

Shift Register Mode Timing Waveforms

AC Testing Input/Output Waveforms(1) Float Waveforms(1)

Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a Note: 1. For timing purposes, a port pin is no longer
logic 1 and 0.45V for a logic 0. Timing measurements floating when a 100 mV change from load volt-
are made at VIH min. for a logic 1 and VIL max. for a age occurs. A port pin begins to float when a
logic 0. 100 mV change from the loaded VOH/VOL level
occurs.

4-190 AT89C55
 AT89C55

Notes: 1. XTAL1 tied to GND for ICC (power down)

2. Lock bits programmed

4-191
Ordering Information
Speed Power
(MHz) Supply Ordering Code Package Operation Range
16 5V ± 20% AT89C55-16AA 44A Automotive
AT89C55-16JA 44J (-40°C to 105°C)
AT89C55-16PA 40P6
AT89C55-16QA 44Q
24 5V ± 20% AT89C55-24AC 44A Commercial
AT89C55-24JC 44J (0°C to 70°C)
AT89C55-24PC 40P6
AT89C55-24QC 44Q
AT89C55-24AI 44A Industrial
AT89C55-24JI 44J (-40°C to 85°C)
AT89C55-24PI 40P6
AT89C55-24QI 44Q
33 5V ± 10% AT89C55-33AC 44A Commercial
AT89C55-33JC 44J (0°C to 70°C)
AT89C55-33PC 40P6
AT89C55-33QC 44Q

Package Type
44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC)
40P6 40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
44Q 44 Lead, Plastic Gull Wing Quad Flatpack (PQFP)

4-192 AT89C55